General verification system, device and method suitable for function performance of FPGA type device

Abstract

The application discloses a general verification system, device and method suitable for the function and performance of FPGA devices, relates to the test technical field of FPGA devices, and comprises verification hardware, verification software, verification auxiliary instruments and environmental equipment, and the specific verification steps are as follows: step one, chip logic function verification; step two, common interface function verification; step three, software and hardware adaptability function verification; step four, comprehensive performance function verification; step five, dynamic power consumption test; step six, common IP function verification; step seven, correlation parameter test; step eight, system adaptability; and step nine, environmental adaptability.The general verification system is suitable for the verification of serial interface function, multi-path IO compatibility test function, development software platform adaptability, simulator adaptability, configuration mode, configuration start time, signal processing function and official IP support, and is suitable for the functions of high-speed interface protocol, Aurora protocol, DDR protocol, IIC protocol and SPI protocol.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of FPGA device testing, in particular to a general verification system, device and method suitable for the functional performance of FPGA devices. BACKGROUND

[0002] An FPGA is composed of many programmable logic elements (such as logic gates, registers and memory cells), which can be combined into complex digital circuits. The design of an FPGA can be completed through a hardware description language (such as Verilog and VHDL), and then the function can be programmably implemented by synthesis and downloading to an FPGA chip.

[0003] FPGAs are widely used in many application fields, including digital signal processing, image processing, communication and control systems, etc. Due to its flexibility and programmability, FPGA is widely used in the field of fast prototyping and reconfigurable electronic systems.

[0004] With the continuous expansion of the scale of FPGA, the requirements for fault detection and reliability verification are also increasing. The programmability of FPGA brings many challenges to the complete and comprehensive testing of FPGA itself. FPGA testing must consider various fault models to fully detect these devices and the fault tolerance of device defects. Logic resources must be tested in different operating modes, which in turn requires multiple reconfigurations of the logic resources being tested in the FPGA.

[0005] FPGA is the core device of circuit (system) such as signal processing, which has powerful performance, high working rate, rich and large number of interface types, complex working circuit, and can realize various complex and high-performance functions through user programming. The peripheral circuits necessary for the working circuit of FPGA include memory, configuration PROM or FLASH, clock, power supply, etc. According to the use of different users, it also includes network interface, DDR, high-speed data interface, AD / DA chip data interface, I2C or SPI memory, asynchronous serial interface, etc. FPGA internally includes various hardware units such as BRAM, CRM and various software IP core functions, which itself has very powerful functions and very complex internal structure.

[0006] At the same time, with the increase in the number of FPGA interfaces and the increase in transmission rate, the difficulty of these tests will become more and more prominent in ATE testing, gradually increasing the requirements for ATE hardware and software control, and increasing the testing cost. At present, the performance test of the same type of FPGA requires multiple Layout test board hardware to split the performance into several parts for testing, resulting in an increase in testing time and cost.

[0007] Currently, due to the limitation of the vector storage depth of the automatic test system itself, the detection of different resources and fault coverage of the FPGA needs repeated configuration, and the corresponding configuration bit stream is long, the configuration file is multiple, and the automatic test system is difficult to load all the configuration files into the memory of the test system at one time, so it has to be loaded multiple times, which leads to the test time to be doubled. At the same time, the automatic test equipment (ATE) is mainly for the direct current parameters, alternating current parameters and part of the function test, in order to repeatedly verify the function of the FPGA, different Layout test boards need to be designed according to different test function items to mobilize the automatic test equipment (ATE) resources, and the test boards are frequently replaced for testing.

[0008] The use of the automatic test equipment (ATE) specifically includes the following disadvantages:

[0009] 1. Repeated configuration and replacement of Layout test boards lead to long test time;

[0010] 2. Different Layout test boards are designed for different functions, leading to increased cost;

[0011] 3. Due to the large size and weight of the automatic test equipment (ATE), it is difficult to carry out high and low temperature tests through the heat flow meter close to the test board, and it is difficult to carry out vibration environment, low pressure environment tests and other special environments through external equipment;

[0012] 4. The test items do not meet the actual environmental application, and the verification of serial interface function, multi-channel IO compatibility test function, development software platform adaptability, emulator adaptability, configuration mode, configuration start time, signal processing function and official IP supportability is not applicable to high-speed interface protocol, Aurora protocol, DDR protocol, IIC protocol, SPI protocol, etc. SUMMARY

[0013] In view of the deficiencies of the prior art, the present application provides a general verification system, device and method suitable for the function and performance of FPGA devices, which solves the problems raised in the above background art.

[0014] To achieve the above purpose, the present application is implemented by the following technical scheme: a general verification method suitable for the function and performance of FPGA devices, comprising the following verification steps:

[0015] Step one: in-chip logic function verification, the specific content is as follows:

[0016] (1) I2C communication: closed-loop test mode in the board, write and read operation is carried out on the E2PROM of I2C interface through FPGA program, and the written data and read data are sent to the host computer, and the host computer compares whether the data is consistent to judge whether the function is normal;

[0017] (2) SPI communication: the closed loop test mode in the board, the E2PROM of the SPI interface is written and read by the FPGA program, the written data and the read data are sent to the host computer, the host computer compares whether the data is consistent, and judges whether the function is normal;

[0018] (3) In-chip memory read and write: the closed loop test mode in the board, the FPGA internal memory is written and read by the FPGA program, the written data and the read data are sent to the host computer, the host computer compares whether the data is consistent, and judges whether the function is normal;

[0019] (4) Multiplier: the closed loop test mode in the board, the multiplier IP is called, the bit width of the multiplicand A and the multiplier B is 4 bits, the output product P width is 8 bits; the value of A and B is 1-15 increment, a total of 225 groups, the multiplier and the product value are sent to the host computer, and the host computer verifies the calculation result;

[0020] (5) Serial communication: the host computer sends a self-check command, and the FPGA returns a self-check success information to the host computer after successful analysis;

[0021] (6) Ethernet communication: the host computer sends a self-check command, and the FPGA returns a self-check success information to the host computer after successful analysis;

[0022] Step two: common interface function verification, the specific content is as follows:

[0023] (1) Debugging interface function: through the JTAG burner, the FPGA device is scanned, and the software is burned into the FPGA, and the on-line debugging and running are carried out after burning;

[0024] (2) High-speed serial interface function: the closed loop test mode in the board, the optical fiber communication is realized through the Aurora protocol, the optical loopback mode is used for testing, the sending data and the receiving data are sent to the host computer, the host computer compares whether the data is consistent, and judges whether the function is normal;

[0025] Step three: software and hardware adaptability function verification, the specific content is as follows:

[0026] Development software platform adaptability function: through the FPGA development software platform, the FPGA is compiled, burned, entered into the debugging mode, and on-line debugging is carried out, and the running state of the FPGA is viewed in real time;

[0027] Step four: comprehensive performance function verification, the specific content is as follows:

[0028] (1) Configuration mode: change the configuration mode of the code switch to change the different configuration mode of the FPGA, turn on the power, the start indicator light DONE of the FPGA changes from off to on, which is normal, otherwise it is abnormal;

[0029] (2) Configuration start time: measure the time difference from the VCCO of the FPGA rising to 90% to the DONE signal jumping to "high level", which is the configuration start time;

[0030] (3) Signal processing function: the FPGA calls the FFT IP, configures a 50M clock, inputs a set of pre-stored single tone data into the FFT IP, and then sends the real and imaginary part data output by the IP to the host computer. The host computer processes the data into a phase-frequency curve to determine whether it is normal;

[0031] Step five: dynamic power consumption test, the specific content is as follows:

[0032] VCCINT working current and voltage: a micro-resistance large power precision resistor is designed on the input path of the FPGA core voltage of the verification board, and a current monitoring chip is used to test the current and voltage of the resistor in real time. The test results are displayed through the host computer software;

[0033] Step six: common IP function verification, the specific content is as follows:

[0034] (1) DDR: closed loop test mode in the board, write and read operations are performed on the DDR memory through the FPGA program, and the written data and read data are sent to the host computer. The host computer compares whether the data is consistent to determine whether the function is normal;

[0035] (2) Clock generator: the FPGA calls the internal PLL, and the clock after the PLL is monitored by the oscilloscope and should be 50MHz;

[0036] (3) FIFO: closed loop test mode in the board, write and read operations are performed on the internal FIFO memory through the FPGA program, and the written data and read data are sent to the host computer. The host computer compares whether the data is consistent to determine whether the function is normal;

[0037] Step seven: correlation parameter test, the specific content is as follows:

[0038] VCCINT working current and FPGA resource utilization rate change correlation parameter test: design FPGA application programs with resource utilization rates of 10%, 20%, 30%, 40%, 50%, 60%, and 70%, respectively, burn them after running, record the corresponding VCCINT working current, and form a correlation curve of dynamic current and resource utilization rate;

[0039] Step eight: system adaptability, the specific content is as follows:

[0040] Core voltage pull: the verification board uses a DC / DC chip designed for core voltage with different configuration resistors, selects different resistors through a DIP switch, controls the output core voltage to be normal, up and down, and adjusts the core voltage to be normal, up and down through the DIP switch during the test, realizes core voltage pull, and tests various functions of the FPGA under the pull condition;

[0041] Step nine: environmental adaptability, the specific content is as follows:

[0042] According to the environmental test conditions, environmental stress is applied, during which the in-chip logic, high-speed serial interface, signal processing, and common IP function test are carried out, after the test, the temperature is restored to normal, and the final test is carried out; including high and low temperature working test, high and low temperature impact test, high and low temperature storage test, mechanical vibration test, mechanical impact test, low pressure working test.

[0043] A system of a general verification method suitable for the function and performance of FPGA devices, comprising verification hardware, verification software, verification auxiliary instruments, and environmental equipment, specifically including FPGA verification board, host computer, auxiliary instruments, and environmental test equipment;

[0044] Among them,

[0045] The host computer is composed of automatic test software and FPGA software platform.

[0046] The automatic test software is used for controlling the test process, recording the test results and data.

[0047] Optionally, the auxiliary instruments include a direct current power supply, a digital oscilloscope, and a multimeter.

[0048] Optionally, the environmental test equipment includes temperature, mechanical, and low pressure environmental test equipment.

[0049] A device of a general verification system suitable for the function and performance of FPGA devices, comprising a verification board, the verification board comprising a FPGA chip, power supply, clock, configuration start, debugging interface, serial port circuit, network port circuit, high-speed interface, and memory.

[0050] Optionally, the verification board is designed in the form of a whole board, that is, all circuits of the whole verification board include the verified FPGA device, serial port chip, FLASH chip, EEPROM chip, DDR chip, optical module, and power supply.

[0051] Optionally, the power supply includes normal power supply, pull, and current monitoring.

[0052] Optionally, the high-speed interface selects optical fiber communication.

[0053] The application provides a universal verification system, device and method suitable for the function performance of FPGA devices, and has the following beneficial effects:

[0054] The universal verification system suitable for the function performance of FPGA devices realizes data transmission in a self-loop mode in the board, simultaneously verifies the sending and receiving functions of the transmitted data, shortens the test time, verifies multiple projects simultaneously in the board mode, reduces the types of verification boards and the cost, and puts the board environment test into a test box to monitor the signals through a cable, makes up for the lack of test projects, and is closest to the actual use mode of the device, the signals between the verified device and the processor are completed in a PCB, the signal path is short, no cable or connector is needed for switching, the signal integrity is good, the device is not easily disturbed by the outside world, the interface device performance test is more stable and reliable, and is more suitable for high-speed interface protocol verification.

[0055] The universal verification device suitable for the function performance of FPGA devices fully utilizes the advantages of the board mode, adopts the data transmission mode in the self-loop mode in the board, stably and reliably realizes the function performance test of the high-speed interface protocol, and flexibly realizes the limit performance test of the power supply pull of the FPGA device, the timing pull, the resource occupation rate and power consumption, and the highlights of the power supply pull circuit, the current collection circuit and the data transmission mode in the self-loop mode in the board are exemplified.

[0056] Power supply pull: the core power V CCINT The voltage is small and the current is large, and there is a strong timing relationship with other groups of power supply, clock, reset and other signals of the FPGA, if the external DC power supply is used to supply power to the FPGA and pull, due to the small absolute value of the voltage, the narrow allowed pull range, the large working current, the large transmission loss, the easy fluctuation of the external DC power supply pull out of the allowed range, the damage of the FPGA, the insecurity, and the failure to meet the timing requirements. The method in the application is to design a pull circuit in the verification board card, to design configuration resistors with different pull values in the periphery of the DC / DC chip for power supply in the board, to select different pull voltages by using the board dial switch mode, to have the characteristics of high pull precision, no influence on the FPGA start timing, easy operation, safety and stability.

[0057] Circuit collection circuit: real-time safe and accurate measurement of FPGA working current, precise resistance and current monitoring circuit are used, the working current can be measured in real time and accurately without affecting the FPGA operation, compared with the conventional method of measuring by using a multimeter, the method is safer and will not cause damage due to improper operation, and the method is more suitable for current test in temperature, mechanics and low pressure test environments.

[0058] The data transmission mode in the self-loop mode in the board: the various verification functions of the FPGA mostly adopt the verification mode of the self-loop in the board, which reduces the demand for test devices and instruments. Meanwhile, the integrity and high-speed transmission of the high-speed signal are ensured, and the error of the test result is avoided.

[0059] The universal verification method suitable for the function and performance of the FPGA device has the following beneficial effects:

[0060] Verification of the process assembly adaptability of the device under test (DUT): the verification board is designed according to the device manual and the assembly process standard of the application industry, the PCB packaging design and layout design of the device are performed, the verification board is manufactured, the welding work is carried out according to the assembly process standard, and the assembly adaptability of the device is verified.

[0061] Verification of the function and performance index of the device under test (DUT): the verification board is placed in the verification system, and the on-chip logic, communication function, on-chip memory read-write function, online debugging function, memory interface function, high-speed serial interface function, IO compatibility test function, development software platform adaptability, emulator adaptability, configuration mode, configuration startup time, signal processing function and official IP support of the DUT are verified under the typical or special working circuit.

[0062] Board-level environmental adaptability and working stability: the verification board is placed in a temperature environment, a mechanical environment and a low-pressure environment, and the function and performance of the device under test (DUT) are tested online.

[0063] When verifying the signal processing function and performance, a self-loop test is adopted, the main idea is that the FPGA device transmits data through a transceiver chip, and then the FPGA receives the signal, error rate analysis is performed, the use of auxiliary devices and cables is reduced, and external instrument monitoring is reduced, thereby greatly reducing the hardware cost.

[0064] The PCB of the verification board adopts a design of partitioning the verified device and the auxiliary functional device, the FPGA verified device is concentrated in the middle area, and the auxiliary functional device is arranged around the FPGA verified device, thereby improving the maintainability of the verification board, as shown in Figure 2 .

[0065] At present, the test system is suitable for the function and performance verification of 5-series and 7-series FPGA devices, and has successfully verified the on-chip logic, communication function, on-chip memory read-write function, online debugging function, memory interface function, high-speed serial interface function, IO compatibility test function, development software platform adaptability, emulator adaptability, configuration mode, configuration startup time, signal processing function and official IP support.

[0066] The whole board verification mode of the scheme is closer to the real application environment of the device, and the verification result is closer to the real application environment; meanwhile, the scheme makes up for the insufficient ATE test project, and can carry out targeted environmental stress test according to the industry requirements;

[0067] Through the PCB partition layout design, the auxiliary device can be protected in an external way under the same environmental stress test, so as to work normally under thermal stress and mechanical stress, thereby reducing the use level of the auxiliary device and the cost of the verification board;

[0068] The hardware adopts a general design scheme, improves the universality of the PCB, and reduces the design and use cost;

[0069] The self-loop test mode is selected, the use of cables and connectors is reduced, signal transmission interference, attenuation, poor contact and other problems are avoided, high-speed and high-quality signal transmission is ensured, and the number of auxiliary instruments is reduced, thereby reducing the design and use cost. BRIEF DESCRIPTION OF DRAWINGS

[0070] Figure 1 The figure is the overall test system architecture diagram in the scheme;

[0071] Figure 2 The figure is the general PCB structure schematic diagram in the scheme. DETAILED DESCRIPTION

[0072] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments.

[0073] In the description of the present application, unless otherwise specified, the meaning of "multiple" is two or more; the terms "upper", "lower", "left", "right", "inner", "outer", "front end", "rear end", "head", "tail" and the like indicate the orientation or positional relationship shown in the drawings, which is only for the purpose of facilitating the description of the present application and simplifying the description, and does not indicate or imply that the device or element must have a particular orientation, be constructed and operated in a particular orientation, therefore it cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" and the like are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0074] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "connected", "connected" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0075] Embodiment one: a general verification method suitable for the function and performance of FPGA type device, including the following verification steps:

[0076] Step one: on-chip logic function verification, the specific content is as follows:

[0077] (1) I2C communication: board closed-loop test mode, through the FPGA program to write and read the operation of E2PROM of I2C interface, write data and read data to the host computer, the host computer compares the data to determine whether the function is normal;

[0078] (2) SPI communication: board closed-loop test mode, through the FPGA program to write and read the operation of E2PROM of SPI interface, write data and read data to the host computer, the host computer compares the data to determine whether the function is normal;

[0079] (3) on-chip memory read and write: board closed-loop test mode, through the FPGA program to write and read the operation of FPGA internal memory, write data and read data to the host computer, the host computer compares the data to determine whether the function is normal;

[0080] (4) multiplier: board closed-loop test mode, call multiplier IP, the bit width of the multiplicand A and the multiplier B is 4bit, the output product P width is 8bit; A and B value is 1-15 increment, a total of 225 groups, the multiplier and the product value are sent to the host computer, and the host computer verifies the calculation result;

[0081] (5) serial communication: the host computer sends a self-check command, and the FPGA returns a self-check success information to the host computer after successful analysis;

[0082] (6) Ethernet communication: the host computer sends a self-check command, and the FPGA returns a self-check success information to the host computer after successful analysis;

[0083] Step two: common interface function verification, the specific content is as follows:

[0084] (1) debugging interface function: through JTAG burner, scan FPGA device, and burn software to FPGA, after burning, online debugging and running;

[0085] (2) High-speed serial interface function: closed-loop test method inside the board, optical fiber communication is realized through Aurora protocol, and optical port loopback method is used for testing. The sending data and receiving data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal.

[0086] Step 3: Verify the adaptability of software and hardware. The specific contents are as follows:

[0087] Development software platform adaptability function: compile, burn, enter debugging mode through the FPGA development software platform, debug the FPGA online, and view the FPGA operation status in real time;

[0088] Step 4: Comprehensive performance function verification, the specific contents are as follows:

[0089] (1) Configuration mode: Change the configuration mode of the FPGA to a different configuration mode by turning on the configuration mode dial switch. If the FPGA startup indicator DONE indicator changes from off to on, it is normal. Otherwise, it is abnormal.

[0090] (2) Configuration startup time: The time difference from when the FPGA's VCCO rises to 90% to when the DONE signal jumps to a "high level" is measured, which is the configuration startup time;

[0091] (3) Signal processing function: FPGA calls FFTIP, configures 50M clock, inputs a set of pre-stored single-tone data into FFTIP, and then sends the real and imaginary data output by IP to the host computer, which processes the data into a phase-frequency curve to determine whether it is normal;

[0092] Step 5: Dynamic power consumption test, the details are as follows:

[0093] VCCINT working current and voltage: The verification board designs a high-power precision resistor with a small resistance value on the core voltage input path of the FPGA, and uses the current monitoring chip to perform real-time testing of the current and voltage of the resistor. For the design circuit, see Figure 2 , the test results are displayed through the host computer software;

[0094] Step 6: Verify common IP functions. The details are as follows:

[0095] (1) DDR: In-board closed-loop test mode, the DDR memory is written and read through the FPGA program, and the written data and read data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal.

[0096] (2) Clock generator: FPGA calls the internal PLL. The clock after monitoring the PLL through an oscilloscope should be 50MHz.

[0097] (3) FIFO: Inboard closed-loop test mode, through the FPGA program to write and read the internal FIFO memory, write data and read data sent to the host computer, host computer to compare data consistency, determine whether the function is normal;

[0098] Step seven: correlation parameter test, the specific content is as follows:

[0099] VCCINT working current and FPGA resource utilization rate change correlation parameter test: respectively design 10%, 20%, 30%, 40%, 50%, 60%, 70% resource utilization rate of FPGA application program, after burning into the running, record the corresponding VCCINT working current, form the dynamic current and resource utilization rate correlation curve;

[0100] Step eight: system adaptability, the specific content is as follows:

[0101] Core voltage pull bias: verify the board using the DC / DC chip of different configuration resistance of the core voltage, through the selection of different resistance of the DIP switch, control its output core voltage in normal, up, down three different amplitude; When testing, through the DIP switch, adjust the core voltage to normal, up, down, realize the core voltage pull bias, under the condition of pull bias, test the above various functions of FPGA;

[0102] Step nine: environmental adaptability, the specific content is as follows:

[0103] According to the environmental test conditions, the environmental stress is applied, during the test, the on-chip logic, high-speed serial interface, signal processing, common IP function test, after the test, restore to normal temperature conditions, carry out the final test; Including high and low temperature working test, high and low temperature impact test, high and low temperature storage test, mechanical vibration test, mechanical impact test, low pressure working test.

[0104] Example two: general verification system suitable for FPGA class device function performance, including verification hardware, verification software, verification auxiliary instrument, environmental equipment, specific for FPGA verification board, host computer, auxiliary instrument, environmental test equipment;

[0105] Among them,

[0106] The host computer is composed of automatic test software and FPGA software platform;

[0107] Automatic test software, used for controlling test process, recording test results and data;

[0108] Auxiliary instrument includes direct current power supply, digital oscilloscope, multimeter;

[0109] The environmental test equipment includes temperature, mechanics, low pressure environmental test equipment.

[0110] Embodiment three: the general verification device suitable for the function and performance of FPGA type device, including verification board card, the verification board card includes FPGA chip, power supply, clock, configuration start, debugging interface, serial port circuit, network port circuit, high speed interface, memory;

[0111] The verification board card adopts the whole board design verification board card, that is, all circuits of the whole verification board card include the verified FPGA device, serial port chip, FLASH chip, EEPROM chip, DDR chip, optical module, power supply;

[0112] Among them,

[0113] The power supply includes normal power supply, pull bias, current monitoring;

[0114] The high speed interface selects optical fiber communication.

[0115] The above is only the preferred specific embodiment of the present application, but the protection scope of the present application is not limited to this, any skilled person in the art in the technical range disclosed by the present application, according to the technical scheme and the invention concept of the present application, equivalent replacement or change, should be covered in the protection scope of the present application.

Claims

1. A general verification method for the functional performance of FPGA devices, characterized by: The verification steps include: Step 1: Verify the on-chip logic function. The specific contents are as follows: (1) I2C communication: closed-loop test mode within the board, write and read operations on the E2PROM of the I2C interface through the FPGA program, send the written data and read data to the host computer, and the host computer compares the data to see if they are consistent and determines whether the function is normal; (2) SPI communication: In-board closed-loop test mode, the FPGA program is used to write and read the E2PROM of the SPI interface, and the written data and read data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal. (3) On-chip memory reading and writing: closed-loop test method on the board, write and read operations are performed on the FPGA internal memory through the FPGA program, and the written data and read data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal; (4) Multiplier: In the closed-loop test mode, the multiplier IP is called, the bit width of the multiplicand A and the multiplier B is set to 4 bits, and the output product P is 8 bits wide; the values ​​of A and B increase from 1 to 15, a total of 225 groups, and the multiplied number and product value are sent to the host computer, which verifies the calculation result; (5) Serial communication: The host computer sends a self-test command, and after the FPGA successfully parses it, it returns the self-test success information to the host computer; (6) Ethernet communication: The host computer sends a self-test command, and after the FPGA successfully parses it, it returns the self-test success information to the host computer; Step 2: Verify common interface functions. The specific contents are as follows: (1) Debug interface function: Scan FPGA devices through JTAG burner and burn software to FPGA. After burning, debug and run online; (2) High-speed serial interface function: closed-loop test method inside the board, optical fiber communication is realized through Aurora protocol, and optical port loopback method is used for testing. The sending data and receiving data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal. Step 3: Verify the adaptability of software and hardware. The specific contents are as follows: Development software platform adaptability function: compile, burn, enter debugging mode through the FPGA development software platform, perform online debugging of the FPGA, and view the FPGA operation status in real time; Step 4: Comprehensive performance function verification, the specific contents are as follows: (1) Configuration mode: Change the configuration mode of the FPGA to a different configuration mode by turning on the configuration mode dial switch. If the FPGA startup indicator DONE indicator turns from off to on, it is normal. Otherwise, it is abnormal. (2) Configuration startup time: The time difference from when the FPGA's VCCO rises to 90% to when the DONE signal jumps to a "high level" is measured, which is the configuration startup time; (3) Signal processing function: FPGA calls FFTIP, configures 50M clock, inputs a set of pre-stored single-tone data into FFTIP, and then sends the real and imaginary data output by IP to the host computer, which processes the data into a phase-frequency curve to determine whether it is normal; Step 5: Dynamic power consumption test, the details are as follows: VCCINT operating current and voltage: This test verifies that a low-resistance, high-power precision resistor is designed on the FPGA's core voltage input path. The current and voltage of the resistor are tested in real time using a current monitoring chip. The test results are displayed on the host computer software. Step 6: Verify common IP functions. The details are as follows: (1) DDR: In-board closed-loop test mode, the DDR memory is written and read through the FPGA program, and the written data and read data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal. (2) Clock generator: FPGA calls the internal PLL. The clock after monitoring the PLL through an oscilloscope should be 50MHz. (3) FIFO: In-board closed-loop test mode, the internal FIFO memory is written and read through the FPGA program, and the written data and read data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal. Step 7: Associated parameter test, the specific contents are as follows: Parameter test on correlation between VCCINT operating current and FPGA resource utilization: Design FPGA applications with resource utilization rates of 10%, 20%, 30%, 40%, 50%, 60%, and 70%, respectively. After burning in and running, record the corresponding VCCINT operating current to form a correlation curve between dynamic current and resource utilization. Step 8: System adaptability, the specific contents are as follows: Core voltage deviation: The verification board uses different resistor configurations for the DC / DC chip designed for the core voltage. Using the DIP switch to select different resistors, the output core voltage is controlled to be between normal, over-deviation, and under-deviation. During the test, the DIP switch is used to adjust the core voltage to normal, over-deviation, and under-deviation to achieve core voltage deviation. Under these deviation conditions, the aforementioned FPGA functions are tested. Step 9: Environmental adaptability, the specific contents are as follows: Environmental stress is applied according to environmental test conditions, during which on-chip logic, high-speed serial interface, signal processing, and common IP function tests are carried out. After the test, the temperature is restored to normal conditions for the final test; including high and low temperature working tests, high and low temperature shock tests, high and low temperature storage tests, mechanical vibration tests, mechanical shock tests, and low pressure working tests.

2. A system for the universal verification method for functional performance of FPGA devices as claimed in claim 1, characterized in that: Including verification hardware, verification software, verification auxiliary instruments, and environmental equipment, specifically divided into FPGA verification board, host computer, auxiliary instruments, and environmental test equipment; in, The host computer consists of automatic test software and FPGA software platform; Automatic testing software used to control the test process and record test results and data.

3. The system according to claim 2, characterized in that: The auxiliary instruments include a DC power supply, a digital oscilloscope, and a multimeter.

4. The system according to claim 2, wherein: The environmental testing equipment includes temperature, mechanics and low pressure environmental testing equipment.

5. A general verification device for the functional performance of FPGA devices, using the system according to any one of claims 2 to 4, characterized in that: It includes a verification board, which includes an FPGA chip, power supply, clock, configuration startup, debugging interface, serial port circuit, network port circuit, high-speed interface, and memory.

6. The device according to claim 5, characterized in that: The verification board is designed in a whole-board manner, that is, all circuits of the entire verification board include the verified FPGA device, serial port chip, FLASH chip, EEPROM chip, DDR chip, optical module, and power supply.

7. The device according to claim 5, characterized in that: The power supply includes normal power supply, bias pulling and current monitoring.

8. The device according to claim 5, characterized in that: The high-speed interface uses optical fiber communication.

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