An on-chip integrated power beam splitter of a metasurface

Abstract

The application discloses a power beam splitter integrated with a super-structured surface on a chip, which is prepared by a semiconductor planarization process on a substrate surface of a back-emission vertical cavity surface emitting laser (VCSEL) to realize the function of power beam splitting. Laser emitted by the VCSEL is split into two beams after passing through the super-structured surface, and the two beams are projected on adjacent diffraction orders, and the energy ratio of the adjacent diffraction orders is adjustable. The proposed power beam splitter integrated on the chip can not only effectively reduce the volume of an optical device, but also realize accurate alignment of the beam splitter and the laser, and ensure the correctness of a beam projection angle.

Description

Technical Field

[0001] The present invention relates to the field of optoelectronics, and mainly designs a power beam splitter with an on-chip integrated metasurface for VCSEL light sources. Background Art

[0002] Beam splitters are key components in many optical systems for distributing and combining light beam paths. They can split a light beam into two or more beams and are widely used in interferometers, spectrometers, and optical communications. However, traditional beam splitters are bulky and heavy, limiting their further application in compact optical systems.

[0003] Metasurfaces have received widespread attention in many application fields, such as holography, polarization optical devices, superlenses, etc. A metasurface is an artificial optical surface composed of two-dimensional subwavelength units that can flexibly manipulate electromagnetic waves of different dimensions, such as amplitude, phase, and polarization. Its ultra-thin thickness and control flexibility make it more suitable for photonic integrated systems than traditional optical devices. In recent years, optical beam splitters based on metasurfaces have been continuously proposed, but this type of beam splitter currently has two problems: 1) The current metasurface beam splitters all use a structure in which the light source and the metasurface are separated. The overall optical path is long and is not suitable for photonic integrated systems. 2) Separate metasurface optical beam splitters often require manual alignment, which can easily lead to large measurement errors. Summary of the Invention

[0004] Currently, the manufacturing of miniaturized devices is gradually becoming the mainstream trend, but traditional separated metasurface beam splitters require external light sources for illumination. The optical path is long and not compact enough, and the precise alignment of the light source and the beam splitter cannot be guaranteed.

[0005] The technical solution employed in this invention is a power beam splitter with an on-chip integrated metasurface. Standard semiconductor planar processing techniques are used to successfully fabricate a dielectric metasurface on the back-emitting VCSEL substrate. From bottom to top, the power beam splitter comprises: a P-face electrode 8, a benzocyclobutene (BCB) layer 7, a P-face distributed Bragg reflector 6, an oxide hole 5, an N-face distributed Bragg reflector 4, a gallium arsenide substrate 3, an N-face electrode 2, and a metasurface 1. Light emitted from the active region passes through the metasurface on the VCSEL substrate and is split into two beams, projected onto the 0th and -1th orders, or the -1st and -2th orders, respectively. The energy ratio between adjacent orders is tunable.

[0006] Furthermore, the energy control of different diffraction orders can be achieved by removing the total phase gradient limitation of 2π.

[0007] Furthermore, the phase profile function of the metasurface is determined by formula (1):

[0008]

[0009] where θ t , n t represents the projection angle and the refractive index of the projection medium, respectively; θ and n represent the incident angle and the refractive index of the incident medium, respectively. λ is the wavelength of the laser, △ is the super unit of the metasurface, and N is the function factor.

[0010] Furthermore, when the projection medium is air, n t =1, θ = 0°, n = the refractive index of the GaAs medium of 3.52, the laser wavelength of 980nm, the lattice constant of the metaatom of 300nm, the height of 700nm, and the size of a supercell of 2.7μm consisting of 9 metaatoms. The phase coverage of the metaatom as a whole is 2π, and the average transmittance is above 80%.

[0011] Furthermore, a standard semiconductor planar process is used to fabricate a back-emitting VCSEL and process cylindrical nanostructures on its substrate. Laser light emitted from the active region passes through the metasurface and is projected onto adjacent diffraction orders 0, -1 or -1, -2. The energy ratio between adjacent diffraction orders is tunable. The specific process steps are as follows:

[0012] (1) A 500 nm thick SiO2 etching barrier layer was grown on the P side of the epitaxial wafer using plasma enhanced chemical vapor deposition (PECVD) at a growth rate of 15 Å / s.

[0013] (2) Photolithography was performed using the designed layout. The photoresist selected was AZ5214, with a spin coating thickness of 1.4 μm at 4000 rpm. After photolithography, the photoresist was cured and the SiO2 outside the frustum was removed by wet etching. The etching solution used was BOE solution with an etching rate of 50 nm / s. The epitaxial wafer with the large frustum SiO2 mask was cleaned and dried using the pretreatment cleaning method. The P-side DBR layer not covered with SiO2 was etched using inductively coupled plasma etching (ICP). The etching depth was the depth from the P-side surface to the peroxide restriction layer. The depth was greater than 4.8 μm and less than 7 μm. A step profiler was used to confirm whether the etching reached the predetermined depth.

[0014] (3) Clean the epitaxial wafer after ICP etching, use BOE solution to etch and remove the SiO2 mask layer, and use a step meter to confirm whether its thickness meets the standard.

[0015] (4) The device was oxidized using a wet oxidation process. Nitrogen gas was introduced at a flow rate of 1 sccm / min through a 100°C constant temperature water area into a constant temperature chamber set at 400°C. The oxidation rate of the back-emitting VCSEL epitaxial structure used was 0.97 μm / min.

[0016] (5) The oxidized laser epitaxial wafer is cleaned again and dried, and a SiO2 passivation layer with a thickness of 500 nm is grown on the epitaxial wafer using PECVD to achieve the purpose of sidewall electrical insulation.

[0017] (6) The surface was flattened and BCB was spin-coated at a spin coating parameter of 3000 rpm and a thickness of 2 μm. The BCB was dried at a preset step-type curing temperature of 250°C.

[0018] (7) Use reactive ion etching (RIE) technology to etch the BCB on the mesa to expose the SiO2 passivation layer.

[0019] (8) Use the designed layout for photolithography, select ARN-4340 reverse glue as the mask, and after photolithography, perform post-baking and use low-power oxygen plasma to glue to ensure the steepness of the edges of the photolithographic pattern. Use BOE solution to etch away the SiO2 in the electrode holes.

[0020] (9) The designed layout was used for the third photolithography, the inversion characteristics of AZ5214 were used for photolithography, and the Ti / AuP surface electrode was prepared using magnetron sputtering and lift-off process.

[0021] (10) The fourth photolithography was performed using the designed layout 4, and the N-side AuGeNi / Au electrode was prepared by magnetron sputtering and lift-off process. After sputtering the electrode, the chip was subjected to rapid thermal annealing at 320°C for 35 seconds.

[0022] (11) A layer of hydrogen silsesquioxane (HSQ) is spin-coated on the VCSEL substrate and exposed using electron beam direct writing to transfer the metasurface pattern onto the HSQ. Subsequently, ICP etching is performed to form circular nanopillars and remove the remaining HSQ resist.

[0023] It can be seen from the above technical solution that the present invention has the following beneficial effects:

[0024] 1. Integrating a metasurface on the substrate of a back-emitting VCSEL can effectively shorten the optical path and achieve precise alignment, with an alignment accuracy that is unmatched by the manual alignment of traditional splitter beamsplitters.

[0025] 2. The metasurface is integrated outside the VCSEL resonant cavity without affecting the laser's emission characteristics.

[0026] 3. Gallium arsenide nanocylinders have high energy conversion efficiency at a wavelength of 980nm, and the isotropic nature of the circular nanocylinders can maintain the original polarization state of the laser. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 In the figure, (a) is the corresponding relationship between the nanopillar radius and the phase; (b) is the corresponding relationship between the nanopillar radius and the transmittance.

[0028] Figure 2 Arrangement of a single supercell nanopillar.

[0029] Figure 3 Schematic diagram of the on-chip integrated power splitter structure. DETAILED DESCRIPTION

[0030] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific implementation examples and with reference to the accompanying drawings.

[0031] A power beam splitter with an on-chip integrated metasurface is proposed. The metasurface design differs from the traditional metasurface design based on the generalized Snell's law. Energy control of different diffraction orders is achieved by removing the 2π total phase gradient restriction. The phase profile function of the metasurface is determined by formula (1):

[0032]

[0033] where θ t , n t represents the projection angle and the refractive index of the projection medium, respectively; θ and n represent the incident angle and the refractive index of the incident medium, respectively. λ is the wavelength of the laser, △ is the super unit of the metasurface, and N is the function factor.

[0034] In this example, n t The refractive index of air is 1, θ is 0°, n is the refractive index of gallium arsenide medium is 3.52, the laser wavelength is 980nm, the lattice constant of the superatom is 300nm, the height is 700nm, and 9 superatoms are selected to form a super unit of 2.7μm. Figure 1 (a) and (b) show the relationship between the radius, phase, and transmittance of different meta-atoms, respectively. The phase of the meta-atom as a whole can cover 2π, with an average transmittance exceeding 80%. Figure 2 It shows supercells composed of superatoms of different radii. There are four rows from top to bottom, and the function factor N of each supercell is different.

[0035] Subsequently, a dielectric metasurface was successfully fabricated on the back-emitting VCSEL substrate using standard semiconductor planar processing technology. The schematic diagram of the overall device is shown in the figure. Figure 3As shown, from bottom to top, they are: P-face electrode 8, benzocyclobutene (BCB) 7, P-face distributed Bragg reflector 6, oxide hole 5, N-face distributed Bragg reflector 4, GaAs substrate 3, N-face electrode 2, and metasurface 1. Light emitted from the active region passes through the metasurface on the VCSEL substrate and is split into two beams, projected onto the 0, -1 order or the -1, -2 order, respectively. The energy ratio of adjacent orders is tunable.

[0036] In an exemplary embodiment of this invention, a chip-integrated power beam splitter design is disclosed. Standard semiconductor planar processes are used to fabricate a back-emitting VCSEL and to fabricate cylindrical nanostructures on its substrate. Laser light emitted from the active region passes through the metasurface, projecting onto adjacent diffraction orders 0, -1, or -1, -2. The energy ratio between adjacent diffraction orders is tunable. The specific process steps are as follows:

[0037] (12) A 500 nm thick silicon dioxide (SiO2) etch barrier layer is grown on the P-side of the epitaxial wafer using plasma-enhanced chemical vapor deposition (PECVD) at a growth rate of 15 Å / s.

[0038] (13) The designed layout was used for photolithography. The photoresist selected was AZ5214. At 4000 rpm, its spin coating thickness was about 1.4 μm, which was more suitable for the preparation of the device. After the photolithography, the photoresist was cured and the SiO2 outside the frustum was removed by wet etching. The etching solution used was BOE solution with an etching rate of 50 nm / s. The epitaxial wafer with the large mesa SiO2 mask was cleaned and dried using the above-mentioned pretreatment cleaning method. The P-side DBR layer not covered with SiO2 was etched using inductively coupled plasma (ICP). The etching depth was the depth from the P-side surface to the peroxide restriction layer. The depth was greater than 4.8 μm and less than 7 μm. A step profiler was used to confirm whether the etching reached the predetermined depth.

[0039] (14) Clean the epitaxial wafer after ICP etching, use BOE solution to etch and remove the SiO2 mask layer, and use a step meter to confirm whether its thickness meets the standard

[0040] (15) The device was oxidized using a wet oxidation process. Nitrogen gas was introduced at a flow rate of 1 sccm / min through a 100°C constant temperature water area into a constant temperature chamber set at 400°C. The oxidation rate of the back-emitting VCSEL epitaxial structure we used was approximately 0.97 μm / min.

[0041] (16) The oxidized laser epitaxial wafer is cleaned again and dried according to the above method, and a SiO2 passivation layer with a thickness of 500 nm is grown on the epitaxial wafer using PECVD to achieve the purpose of electrical insulation of the device sidewall.

[0042] (17) The device surface was planarized and BCB was spin-coated at a spin coating parameter of 3000 rpm and a thickness of about 2 μm. The BCB was dried using a preset step-type curing temperature method with a maximum temperature of 250 °C.

[0043] (18) Reactive ion etching (RIE) is used to etch the BCB on the mesa to expose the SiO2 passivation layer.

[0044] (19) The designed layout was used for photolithography, and ARN-4340 reverse resin was selected as the mask. After photolithography, the pattern was post-baked and low-power oxygen plasma was used for photoresist to ensure the steepness of the edges of the photolithographic pattern. BOE solution was used to etch away the SiO2 in the electrode holes.

[0045] (20) The designed layout was used for the third photolithography, and the inversion characteristics of AZ5214 were used for photolithography. The Ti / Au (50nm / 300nm) P-side electrode was prepared using magnetron sputtering and lift-off process.

[0046] (21) Using the designed layout 4, the fourth photolithography was performed, and N-side AuGeNi / Au (15nm / 300nm) electrodes were prepared by magnetron sputtering and lift-off process. After sputtering the electrodes, the chip was subjected to rapid thermal annealing at 320°C for 35 seconds.

[0047] (22) A layer of hydrogen silsesquioxane (HSQ) is spin-coated on the VCSEL substrate and exposed using electron beam direct writing to transfer the metasurface pattern onto the HSQ. Subsequently, ICP etching is performed to form circular nanopillars and remove the remaining HSQ resist.

[0048] Example

[0049] A power beam splitter with an on-chip integrated metasurface is fabricated directly onto the back-emitting VCSEL substrate using a semiconductor planarization process. Because the metasurface is fabricated outside the resonant cavity, it does not degrade the laser's performance. The metaatoms within the dielectric metasurface effectively manipulate the emitted laser's wavefront without affecting its polarization, thereby achieving power beam splitting.

[0050] Breaking the 2π phase limitation of traditional metasurface structures, incomplete phase gradients are used to design metasurfaces to achieve the purpose of energy regulation of adjacent diffraction orders.

[0051] Gallium arsenide nanocylinders of different diameters are used for phase control. The high refractive index and high transmittance of gallium arsenide materials are very suitable for laser beam shaping. The isotropy of circular nanocylinders can maintain the original polarization state of the laser beam.

[0052] The reflectivity of the bottom Bragg reflector is lower than that of the top Bragg reflector, so the laser beam can be emitted from the bottom and the 3-micron oxidation hole diameter ensures the fundamental mode emission of the laser.

[0053] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A power beam splitter with an on-chip integrated metasurface, characterized in that: A dielectric metasurface is fabricated on the back-emitting VCSEL substrate using semiconductor standard planar processing technology; the power beam splitter comprises, from bottom to top, a P-surface electrode (8), benzocyclobutene (7), a P-surface distributed Bragg reflector (6), an oxide hole (5), an N-surface distributed Bragg reflector (4), a gallium arsenide substrate (3), an N-surface electrode (2), and a metasurface (1); light emitted from the active region passes through the metasurface on the VCSEL substrate and is split into two beams, which are projected onto the 0, -1 order or the -1, -2 order, respectively, and the energy ratio of adjacent orders is tunable; The phase profile function of the metasurface is determined by formula (1): (1) where θ t , n t Represent the projection angle and the refractive index of the projection medium, respectively; θ and n represent the incident angle and the refractive index of the incident medium, respectively; λ is the wavelength of the laser, △ is the super unit length of the metasurface, and N is the function factor; When the projection medium is air, n t is 1, θ is 0°, n is the refractive index of GaAs medium 3.52, the laser wavelength is 980nm, the lattice constant of the superatom is 300nm, the height is 700nm, and 9 superatoms are selected to form a super unit with a length of 2.7μm; The overall phase coverage of the metaatom is 2π, and the average transmittance is above 80%.

2. The on-chip integrated metasurface power beam splitter according to claim 1, characterized in that: A standard semiconductor planar process is used to fabricate a back-emitting VCSEL and process cylindrical nanostructures on its substrate. Laser light emitted from the active region passes through the metasurface and is projected onto adjacent diffraction orders 0, -1 or -1, -2. The energy ratio of adjacent diffraction orders is tunable. The specific process steps are as follows: A 500 nm thick SiO2 etch barrier layer was grown on the P-side of the epitaxial wafer using plasma-enhanced chemical vapor deposition (PECVD) at a growth rate of 15 Å / s. The designed layout was used for photolithography, using AZ5214 photoresist, which was spin-coated to a thickness of 1.4µm at 4000 rpm. After curing the resist after photolithography, the SiO2 outside the frustum was removed by wet etching using BOE solution at an etching rate of 50 nm / s. The epitaxial wafer with the large mesa SiO2 mask was cleaned using the pretreatment cleaning method and then dried. The P-side DBR layer not covered with SiO2 is etched using inductively coupled plasma etching (ICP). The etching depth is the depth from the P-side surface to the over-oxidation restriction layer, which is greater than 4.8 μm and less than 7 μm. A step profiler is used to confirm whether the etching reaches the predetermined depth. Clean the epitaxial wafer after ICP etching, use BOE solution to etch and remove the SiO2 mask layer, and use a step profiler to confirm whether its thickness meets the standard; The device was oxidized using a wet oxidation process, with nitrogen flowing at a flow rate of 1 sccm / min through a 100°C constant-temperature water area into a constant-temperature chamber set at 400°C. The back-emitting VCSEL epitaxial structure used had an oxidation rate of 0.97µm / min. The oxidized laser epitaxial wafer is cleaned again and dried, and a 500nm thick SiO2 passivation layer is grown on the epitaxial wafer using PECVD to achieve the purpose of sidewall electrical insulation; The surface was planarized and spin-coated with benzocyclobutene at 3000 rpm to a thickness of 2 µm. The benzocyclobutene was then dried at a preset step-wise curing temperature of 250°C. The benzocyclobutene on the mesa is etched using reactive ion etching (RIE) technology to expose the SiO2 passivation layer; The designed layout was used for photolithography, and ARN-4340 reverse resin was selected as the mask. After photolithography, it was post-baked and low-power oxygen plasma was used for photoresist to ensure the steepness of the edges of the photolithographic pattern. BOE solution was used to etch away the SiO2 in the electrode holes. The designed layout was used for the third photolithography, and the inversion characteristics of AZ5214 were used for photolithography. The Ti / AuP surface electrode was prepared using magnetron sputtering and lift-off processes. The fourth photolithography was performed using the designed layout 4, and the N-side AuGeNi / Au electrode was prepared by magnetron sputtering and lift-off process. After sputtering the electrode, the chip was subjected to rapid thermal annealing at 320°C for 35 seconds. A layer of hydrogen silsesquioxane (HSQ) is spin-coated on the VCSEL substrate, and electron beam direct writing is used for exposure to transfer the metasurface pattern onto the HSQ. Subsequently, ICP etching is performed to form circular nanopillars and remove the residual HSQ resist.

3. The on-chip integrated metasurface power beam splitter according to claim 1, characterized in that: A dielectric metasurface is directly processed on the back-emitting VCSEL substrate through a semiconductor planarization process. The metasurface is directly prepared outside the resonant cavity without damaging the performance of the laser. The metaatoms in the dielectric metasurface effectively control the wavefront of the emitted laser without affecting the polarization characteristics of the emitted laser, thereby realizing the function of power splitting.

4. The on-chip integrated metasurface power beam splitter according to claim 1, characterized in that: Breaking the 2π phase limitation of the metasurface structure, using incomplete phase gradient to design the metasurface to achieve energy control of adjacent diffraction orders.

5. The on-chip integrated metasurface power beam splitter according to claim 1, characterized in that: Gallium arsenide nanocylinders of different diameters are used for phase control. The high refractive index and high transmittance of gallium arsenide materials are very suitable for laser beam shaping. The isotropy of circular nanocylinders does not change the original polarization state of the laser beam.

6. The on-chip integrated metasurface power beam splitter according to claim 1, characterized in that: The reflectivity of the Bragg reflector at the bottom of the back-emitting VCSEL is lower than that of the Bragg reflector at the top, so the laser beam can be emitted from the bottom and the 3-micron oxidation hole diameter ensures the fundamental mode emission of the laser.

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