Method, device, and medium for overlay accuracy compensation

Abstract

Embodiments according to the present disclosure provide a method, an apparatus, and a medium for overlay accuracy compensation. In this method, an overlay accuracy map characterizing the overlay accuracy distribution of a certain batch of wafers before exposure is obtained. Based on the optimal compensation value used for this batch of wafers, a plurality of overlay accuracy feedback values corresponding to a plurality of candidate weight values for this batch of wafers are determined. Subsequently, based on the overlay accuracy feedback value corresponding to this batch of wafers and the overlay accuracy map, a target weight value of the feedback weight is determined. In this way, the optimal feedback weight under the current process characteristics can be determined. Further, a more accurate overlay accuracy compensation value can be determined by using the optimal feedback weight value, thereby improving the wafer production quality.

Description

Technical Field

[0001] Embodiments of the present disclosure mainly relate to the field of integrated circuits, and more particularly, to methods, devices, and media for overlay accuracy compensation. Background Art

[0002] With the rapid development of integrated circuit manufacturing technology, the process nodes of traditional integrated circuits are gradually reduced, and the sizes of integrated circuit devices are continuously shrinking. The wafer manufacturing process transfers the patterns of different layers on the layout or mask of each layer to the wafer accurately at a certain reduction ratio through the photolithography process. Specifically, the devices and structures of the chip can be formed layer by layer through the manufacturing process. During the wafer manufacturing process, the requirements for the overlay accuracy between different stacked (stack) layers (also called different film layers) are also getting higher and higher. If the patterns in the current layer are not aligned with the patterns in the previous layer or the alignment accuracy is poor, it will affect the normal operation of the integrated circuit chip, and in severe cases, it may even lead to the scrapping of the integrated circuit chip. Summary of the Invention

[0003] In a first aspect of the present disclosure, a method for overlay accuracy compensation is provided. In this method, a first overlay accuracy map corresponding to a first batch of wafers is obtained; based on a plurality of candidate weight values of the compensation optimal value and feedback weights for the first batch of wafers, a plurality of overlay accuracy feedback values for the first batch of wafers are determined; and based on the plurality of overlay accuracy feedback values and the first overlay accuracy map, a target weight value of the feedback weight is determined for use in overlay accuracy compensation of subsequent batches of wafers for the first batch of wafers.

[0004] In a second aspect of the present disclosure, an electronic device is provided. The electronic device includes a processor and a memory coupled to the processor. The memory has instructions stored therein, and when the instructions are executed by the processor, the electronic device executes the method for generating an overlay mark pattern according to the first aspect of the present disclosure.

[0005] In a third aspect of the present disclosure, a computer-readable storage medium is provided. A computer program is stored on the computer-readable storage medium. When the computer program is executed by the processor, the method for generating an overlay mark pattern according to the first aspect of the present disclosure is implemented.

[0006] According to some embodiments of the present disclosure, an overlay accuracy map characterizing the overlay accuracy distribution of a certain batch of wafers before exposure is obtained. Based on the optimal compensation values used for this batch of wafers, a plurality of overlay accuracy feedback values corresponding to a plurality of candidate weight values for this batch of wafers are determined. Subsequently, based on the overlay accuracy feedback values corresponding to this batch of wafers and the overlay accuracy map, the feedback weights are optimized. In this way, the optimal feedback weights under the current process characteristics can be determined. Further, using the optimal feedback weight values, more accurate overlay accuracy compensation values can be determined, thereby improving the wafer production quality.

[0007] It should be understood that the content described in the present invention content section is not intended to limit the key features or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In conjunction with the accompanying drawings and with reference to the following detailed description, the above and other features, advantages, and aspects of the embodiments of the present disclosure will become more apparent. In the drawings, the same or similar reference numerals denote the same or similar elements, where:

[0009] Figure 1 A schematic diagram showing an example environment in which the embodiments of the present disclosure can be implemented;

[0010] Figure 2 A schematic diagram showing a first example process for overlay accuracy compensation according to some embodiments of the present disclosure;

[0011] Figure 3 A schematic diagram showing the measurement results of overlay accuracy according to some embodiments of the present disclosure;

[0012] Figure 4 A schematic diagram showing a first overlay accuracy map according to some embodiments of the present disclosure;

[0013] Figure 5 A schematic diagram showing a second difference according to an embodiment of the present disclosure;

[0014] Figure 6 A schematic diagram showing a second example process for overlay accuracy compensation according to some embodiments of the present disclosure; and

[0015] Figure 7 A block diagram of an electronic device in which one or more embodiments of the present disclosure can be implemented. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Instead, these embodiments are provided to more thoroughly and completely understand the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not used to limit the protection scope of the present disclosure.

[0017] In the description of the embodiments of the present disclosure, the term "including" and its similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. There may also be other explicit and implicit definitions hereinafter.

[0018] With the rapid development of integrated circuit manufacturing technology, the process nodes of traditional integrated circuits are gradually reduced, and the sizes of integrated circuit devices are continuously shrinking. During the integrated circuit manufacturing process, the requirements for the overlay accuracy between different stacked layers (also referred to as different film layers) are also getting higher and higher. Specifically, the devices and structures of the chip can be formed layer by layer through the manufacturing process. The wafer manufacturing process is to accurately transfer the patterns of different layers on the layout or mask of different layers to the wafer through photolithography with a certain reduction ratio. During the wafer manufacturing process, the requirements for the overlay accuracy between different stacked layers (also referred to as different film layers) are also getting higher and higher. If the patterns in the current layer are not aligned with the patterns in the previous layer or the alignment accuracy is poor, it will affect the normal operation of the integrated circuit chip, and in severe cases, it may even lead to the scrapping of the integrated circuit chip. Therefore, how to improve the overlay accuracy is a problem worthy of attention.

[0019] Currently, most methods calculate the errors of the process related to wafer manufacturing based on the overlay measurement results of the wafer patterns, and feed back the errors to the Advanced Process Control (APC) system to determine the overlay compensation value, so as to improve the overlay accuracy. However, this method cannot adapt to the changes in process characteristics (such as layout displacement, expansion, and rotational deformation) during the process. If the process changes, this method will not be able to determine the accurate overlay compensation value.

[0020] To this end, embodiments of the present disclosure propose a method for layout marking. According to embodiments of the present disclosure, based on corresponding measurement results of the overlay accuracy of the first batch of wafers, a first overlay accuracy map corresponding to the first batch of wafers is determined. Based on the overlay accuracy compensation information related to multiple batches of wafers and multiple candidate weight values of feedback weights, multiple overlay accuracy feedback values for the first batch of wafers are determined, where the multiple batches of wafers include the first batch of wafers and the previous batch of wafers of the first batch of wafers. Based on the multiple overlay accuracy feedback values and the first overlay accuracy map, a target weight value of the feedback weight is determined for use in overlay accuracy compensation for subsequent batches of wafers of the first batch of wafers.

[0021] According to the solution of the present disclosure, an overlay accuracy map characterizing the overlay accuracy distribution of a certain batch of wafers before exposure is obtained. Based on the optimal compensation value used for this batch of wafers, multiple overlay accuracy feedback values corresponding to multiple candidate weight values for this batch of wafers are determined. Subsequently, based on the overlay accuracy feedback values corresponding to this batch of wafers and the overlay accuracy map, the feedback weight is optimized. In this way, the optimal feedback weight under the current process characteristics can be determined. Further, using the optimal feedback weight, a more accurate overlay accuracy compensation value can be determined, thereby improving the wafer production quality.

[0022] Various example implementations of this solution will be described in detail below with reference to the accompanying drawings.

[0023] Figure 1 FIG. shows a schematic diagram of an example environment 100 in which embodiments of the present disclosure can be implemented. The example environment 100 generally may include a layout processing device 110. In some embodiments, the layout processing device 110 may be a computing device such as a personal computer, a workstation, a server, etc. The scope of the present disclosure is not limited in this regard.

[0024] The layout processing device 110 obtains measurement results regarding wafers as input. As an example, the layout processing device 110 may obtain a first measurement result 120 of a first wafer as input. The first measurement result 120 may be a cross-sectional measurement diagram of a first stack or a lower stack of the first wafer. The first stack is a semiconductor material layer after lithography. The layout corresponding to the first stack or the lower stack is also referred to as the first layout. The first layout includes an overlay mark pattern. In an example where the first layout is the layout corresponding to the lower stack, the overlay mark pattern in the first layout is also referred to as the "lower overlay mark pattern". The first measurement result 120 may include measurement results regarding the overlay mark pattern in the first layout. The first measurement result 120 may indicate one or more geometric parameters in the first layout corresponding to the first stack of the first wafer.

[0025] Alternatively, the first measurement result 120 may also include measurement results regarding the second stack or the upper stack of the first wafer. The first measurement result 120 may alternatively also include measurement results of the upper photoresist (PR). The first stack and the second stack in the first wafer are semiconductor layers respectively.

[0026] As an example, the first measurement result 120 may be measurement results collected by devices such as SEM, transmission electron microscope (TEM), atomic force microscope (AFM), etc. The manner of measuring the alignment marks on the wafer may be any existing or future possible measurement manner. The embodiments of the present disclosure are not limited in this regard.

[0027] The layout processing device 110 processes the first measurement result 120 to obtain a second layout 130 corresponding to the second stack or the upper stack of the first wafer. The second layout 130 includes an alignment mark pattern. Herein, the layout corresponding to the second stack or the upper stack is also referred to as the second layout. In an example where the second layout is the layout corresponding to the upper stack, the alignment mark pattern in the second layout is also referred to as the "upper alignment mark pattern". Alternatively, in some embodiments, the layout processing device 110 may also determine an alignment mark pattern for the first layout based on the first measurement result 120, such as a lower alignment mark pattern.

[0028] It should be understood that Figure 1 and the shapes, sizes, and numbers of the respective stacks, layouts, masks, and alignment mark patterns shown in the various figures listed below are merely exemplary and not restrictive. The scope of the present disclosure is not limited in this regard.

[0029] Will be further described in detail below in conjunction with Figures 2 to 6 Several examples of generating alignment mark patterns in a layout.

[0030] Figure 2 A schematic diagram of a first example process 200 for alignment accuracy compensation according to some embodiments of the present disclosure is shown. In some embodiments, the process 200 may be implemented or included in a layout processing device 110 as shown in Figure 1 It should be understood that the process 200 may also include additional blocks not shown and / or certain (or some) of the shown blocks may be omitted. The scope of the present disclosure is not limited in this regard.

[0031] Figure 3 A schematic diagram of an alignment accuracy measurement result 300 according to some embodiments of the present disclosure is shown. As shown in Figure 3As shown, the layout processing device 110 determines a first overlay accuracy map 220 corresponding to the first batch of wafers based on the overlay accuracy measurement results 310 of the first batch of wafers. The first batch of wafers can be any batch of wafers in the wafer production process. The layout processing device 110 determines the overlay accuracy compensation value of the subsequent batch of wafers according to the overlay accuracy compensation value and the measurement results of this batch of wafers, so as to improve the quality of the subsequent batch of wafers.

[0032] The first batch of wafers can include multiple wafers. Correspondingly, multiple wafer patterns can be obtained for the first batch of wafers during the lithography process. In some embodiments, the measurement results 210 of the overlay accuracy for the first batch of wafers can include multiple measurement results corresponding to the multiple wafer patterns respectively. Correspondingly, there can be multiple first overlay accuracy maps corresponding to the first batch of wafers. The first overlay accuracy map corresponding to each wafer can be determined based on multiple different measurement results. In some embodiments, the measurement results 210 of the overlay accuracy for the first batch of wafers can be the average value of the multiple measurement results 210 corresponding to the multiple wafer patterns. Based on the average value of the multiple measurement results 210 of the first batch of wafers, a first overlay accuracy map corresponding to all the wafer patterns included in the first batch of wafers is determined. In this solution, taking a certain wafer in the first batch of wafers as an example, the process 200 is described.

[0033] The first overlay accuracy map 220 characterizes the overlay accuracy distribution of the first batch of wafers before exposure. Figure 4 The schematic diagram of the first overlay accuracy map 220 according to some embodiments of the present disclosure is shown. As Figure 4 shown, the first overlay accuracy map 220 includes the offset vectors of each measurement point in the wafer. For the image after exposure of a certain wafer in the first batch of wafers, the overlay accuracy measurement results 210 of each measurement point on the wafer are obtained. Subsequently, based on the overlay accuracy measurement results 210 and the mask pattern of the wafer, the overlay accuracy measurement feature map corresponding to the wafer is determined. Subsequently, reduction calculations are performed on the multiple overlay accuracy measurement feature maps respectively generated for the first batch of wafers to determine the first overlay accuracy map 220. The calculation formula for the reduction calculation can be:

[0034] ;

[0035] where represents the first overlay accuracy map 220, represents the one used for the first batch of wafers, represents the overlay accuracy measurement results 210 corresponding to the first batch of wafers, the matrix P(⋱) represents the measurement coordinates of the overlay accuracy, and the matrix represents the first process parameter in the wafer production process, and the matrix represents the second process parameter in the wafer production process.

[0036] In some embodiments, if the overlay accuracy measurement result 210 is the average of the measurement results of each wafer in the first batch of wafers, the first overlay accuracy map 220 is determined only based on the overlay accuracy measurement result 210.

[0037] Continue Figure 2 , the layout processing device 110 may determine an overlay accuracy feedback value based on the compensation information of the first batch of wafers to provide data support for the update of the feedback weight. Exemplarily, for the compensation optimal value of the first batch of wafers and multiple candidate weight values of the feedback weight, multiple overlay accuracy feedback values for the first batch of wafers are determined. Exemplarily, for each candidate value of the feedback weight, an overlay accuracy feedback value for the first batch of wafers is determined based on the candidate weight value and the compensation optimal value.

[0038] In some embodiments, the overlay accuracy feedback value may be determined based on the compensation information of multiple historical batches of wafers. The multiple historical batches of wafers may include the above-mentioned first batch of wafers and the wafers of the previous batches of the first batch of wafers. Exemplarily, first, multiple overlay accuracy feedback values for the previous batches of wafers may be determined based on the compensation optimal values of the previous batches of wafers of the first batch of wafers. Subsequently, for the candidate weight value among the multiple candidate weight values, an overlay accuracy feedback value corresponding to the candidate weight value is determined based on the compensation optimal value, the historical overlay accuracy feedback value, and the candidate weight value, and used as one of the multiple overlay accuracy feedback values. The historical overlay accuracy feedback value may include multiple overlay accuracy feedback values corresponding to multiple batches of wafers respectively. For the sake of convenience of description, hereinafter, the compensation optimal value of the first batch of wafers and the multiple overlay accuracy feedback values corresponding to the previous batches of wafers of the first batch of wafers are collectively referred to as overlay accuracy compensation information.

[0039] Based on the overlay accuracy compensation information related to multiple batches of wafers and multiple candidate weight values of the feedback weight, multiple overlay accuracy feedback values for the first batch of wafers are determined. The calculation formula of the overlay accuracy feedback value may be:

[0040] ;

[0041] where represents the compensation optimal value of the th batch of wafers, represents the feedback weight, represents the overlay accuracy feedback value.

[0042] The compensation optimal value of the th batch of wafers

[0043] ;

[0044] wherein represents the unloading compensation value used for the batch of wafers, represents the measurement compensation value corresponding to the batch of wafers, represents a coefficient, .

[0045] For a certain wafer, the optimal compensation value 230 may include the optimal compensation values corresponding to different points on the wafer (i.e., the overlay accuracy compensation value that makes the overlay accuracy of the wafer optimal). In some embodiments, the optimal compensation value 230 may be determined based on the overlay accuracy compensation value and the overlay accuracy measurement result 210 used in manufacturing the first batch of wafers. Exemplarily, when the compensation value used in manufacturing the first batch of wafers is 5, the overlay accuracy measurement result 210 (i.e., the alignment error) is 4. When the compensation value used is 3, the overlay accuracy measurement result 210 (i.e., the alignment error) is 2, then the optimal compensation value 230 for the first batch of wafers can be determined to be 1. In some embodiments, the exponential weighted moving average (EWMA) method may be used to determine the optimal compensation value 230 for each batch of wafers. Exemplarily, for a certain batch of wafers, first determine the historical measurement data of this batch of wafers (including the overlay accuracy measurement result and the corresponding overlay compensation value). Based on the determined historical measurement data, determine the alignment error at each time point (each wafer or each batch). Use the EWMA formula to calculate the EWMA value at each time point, thereby determining the optimal compensation value 230 for this batch of wafers.

[0046] In some embodiments, for a certain candidate weight value among multiple candidate weight values, the overlay accuracy feedback value corresponding to this candidate weight value may be determined based on the overlay accuracy compensation information and this candidate weight value, as one of the multiple overlay accuracy feedback values. In this way, the overlay accuracy feedback values corresponding to different selected feedback weights 240 are determined, so as to determine the influence of different feedback weights 240 on the overlay accuracy. The candidate weight value may be a value pre-determined based on historical process parameters. For example, if the weight values corresponding to the historical process parameters include 2, 4, 6, 8, then these values are used as candidate weight values. The candidate weight value may be a randomly determined value. In some embodiments, the estimated value range of the feedback weight 240 may be determined based on historical process parameters, and then the candidate weight value is determined from the estimated value range. Exemplarily, if the estimated value range of the feedback weight 240 is in the interval of 0 to 1, then the candidate weight value is randomly determined from this interval.

[0047] In some embodiments, the layout processing device 110 determines a target weight value 260 of the feedback weight 240 based on a plurality of overlay accuracy feedback values and the first overlay accuracy map 220 for subsequent wafer batches of the first batch of wafers for overlay accuracy compensation. The first overlay accuracy map 220 represents the actual measurement results of the overlay accuracy. The plurality of overlay accuracy feedback values can represent the simulation results of the plurality of overlay accuracies. In some embodiments, the feedback weight 240 that minimizes the difference between the simulated overlay accuracy and the actual overlay accuracy can be determined based on the difference between the simulation result of the overlay accuracy and the actual result of the overlay accuracy. Further, the overlay accuracy compensation for subsequent wafer batches determined based on the feedback weight 240 is made more accurate.

[0048] In some embodiments, the target weight value can be determined from a plurality of candidate weight values based on a second difference determined respectively for the plurality of candidate weight values. The second difference represents the difference between the simulated overlay accuracy corresponding to each candidate weight value and the overlay accuracy corresponding to the target batch of wafers. The target batch of wafers can include the first batch of wafers and the previous batch of wafers of the first batch of wafers. Exemplarily, for a certain batch of wafers, based on the compensation optimal value and the candidate weight value of this batch of wafers, an overlay accuracy feedback value corresponding to this batch of wafers is determined, and the overlay accuracy feedback value represents the simulated overlay accuracy of this batch of wafers. Based on the measurement information of this batch of wafers, a first overlay accuracy map corresponding to this batch of wafers is determined, and the first overlay accuracy map represents the overlay accuracy distribution of this batch of wafers before exposure. Subsequently, based on the difference between the simulated overlay accuracy corresponding to this batch of wafers and the overlay accuracy distribution, a first difference corresponding to this batch of wafers is determined. In some embodiments, for each candidate weight value among the plurality of candidate values, first, a target overlay accuracy feedback value corresponding to this candidate weight value (i.e., the overlay accuracy feedback value determined using this candidate weight value) is determined from the plurality of overlay accuracy feedback values. Subsequently, based on the overlay accuracy feedback value corresponding to this candidate value weight among the plurality of overlay accuracy feedback values and the first overlay accuracy map 220, a first difference is determined. The first difference represents the difference between the simulated overlay accuracy and the overlay accuracy distribution. The simulated overlay accuracy is determined based on the overlay accuracy feedback value corresponding to this candidate value. Exemplarily, for a certain candidate weight value, first, an overlay accuracy feedback value 250 corresponding to this candidate weight value is determined. Subsequently, the simulated overlay accuracy corresponding to this overlay accuracy feedback value 250 is determined. Based on the difference between the simulated overlay accuracy and the overlay accuracy distribution, using a loss function, a first difference corresponding to this candidate weight value is determined. The first difference can be calculated by the following formula:

[0049] ;

[0050] where represents the first difference, represents the The feedback value of the overlay accuracy for the batch is 250, matrix represents the third process parameter in the wafer production process. In some embodiments, based on the wafer pattern and the overlay accuracy feedback value 250, a second overlay accuracy map can be determined. The second overlay accuracy map indicates the distribution of the simulated overlay accuracy on the wafer, including the simulated overlay accuracy vectors at various points on the wafer. Subsequently, based on the difference between the second overlay accuracy map and the first overlay accuracy map 220, a first difference is determined.

[0051] Subsequently, based on the first difference and the historical difference information, a second difference corresponding to the candidate weight value can be determined. The second difference can be calculated by the following formula:

[0052] ;

[0053] where SR is the second difference, represents the batch of the wafer, represents the batch number of the current wafer, represents for the first difference obtained for the batch of wafers.

[0054] The historical difference information characterizes the first difference obtained based on the previous batch of wafers of the first batch of wafers. Based on the first difference corresponding to the first batch of wafers and the first difference corresponding to the previous batch of wafers, the second difference between the simulated overlay accuracy and the actual overlay accuracy corresponding to different feedback weights 240 is determined. Subsequently, based on the multiple second differences respectively determined for multiple candidate weight values. Figure 5 shows a schematic diagram of the second difference 500 according to an embodiment of the present disclosure. As Figure 5 shown, for different candidate weight values, different second differences can be determined. For multiple different feedback weights 240, the candidate weight value corresponding to the smallest second difference will be used as the target weight value 260 of the feedback weight 240.

[0055] In some embodiments, at least one weight value can be determined from multiple candidate weight values based on the second differences respectively determined for the multiple candidate weight values and a preset condition. The preset condition can be that the second difference is less than a difference threshold, or the second difference corresponding to a certain candidate weight value is less than the second differences corresponding to other candidate weight values, which is not limited herein. In some embodiments, the target weight value 260 can be determined based on the change trend of at least one weight value. In some embodiments, the target weight value 260 can be determined from the candidate weight values, or a value other than the candidate weight values can be determined as the target weight value based on the change trend of the weight values. Exemplarily, if there are three candidate weight values that meet the preset condition (i.e., the first candidate weight value, the second candidate weight value, and the third candidate weight value) and these three candidate weight values increase in sequence, the second differences corresponding to these three candidate weight values are determined respectively. If the second difference corresponding to the first candidate weight value is greater than the second difference corresponding to the second candidate weight value, and the second difference corresponding to the second candidate weight value is less than the second difference corresponding to the third candidate weight value, then it can be determined that the change trend of the second differences corresponding to the candidate weight values first decreases and then increases, so as to determine that the target weight value 260 is between the first weight value and the third weight value.

[0056] In some embodiments, due to process limitations or the existence of multiple weight values with the same second difference, it may not be possible to use the weight value corresponding to the smallest second difference as the feedback weight 240. In this case, the target weight value 260 can be determined based on the user's selection. Exemplarily, the change trend of at least one weight value can be presented to the user in an interaction interface. Subsequently, the selection of a weight value from the at least one weight value is received, and the selected weight value is determined as the target weight value 260. As Figure 5 shown, the second differences determined in the cases where the weight value is 0.2 and the weight value is 0.8 are the smallest, so the weight value 0.2 can be selected as the target weight value 260.

[0057] In some embodiments, based on the target weight value 260 of the feedback weight 240 and the compensation optimal value 230 for the first batch of wafers, a feedback calculation model can be used to determine the target overlay accuracy feedback value 250 for the first batch of wafers. Based on the target overlay accuracy feedback value, an overlay accuracy compensation value to be used for manufacturing the second batch of wafers is determined, where the second batch of wafers is a subsequent batch of the first batch of wafers. Exemplarily, the compensation optimal value 230 corresponding to the first batch of wafers (i.e., the offload value used for the first batch of wafers) and the determined target weight are provided to the feedback calculation model (such as an overlay process model, etc.). The feedback calculation model is used to determine the overlay accuracy feedback value 250 for the first batch of wafers, thereby determining the overlay accuracy compensation value to be used for manufacturing the second batch of wafers. In this way, through an accurate feedback weight value, based on the historical compensation optimal value, an optimal compensation value that maximizes the overlay accuracy of the second batch of wafers is determined. Thus, by continuously repeating the above process, the overlay accuracy of subsequent batches of wafers is ensured, preventing the situation where the overlay accuracy decreases due to process parameter changes, and improving the wafer production quality.

[0058] Figure 6 FIG. shows a schematic diagram of a second example process 600 for overlay accuracy compensation according to some embodiments of the present disclosure. Process 600 can be implemented at the layout processing device 110. The following refers to Figure 1 to describe process 600.

[0059] As Figure 6 shown, at block 610, a first overlay accuracy map corresponding to the first batch of wafers is obtained.

[0060] In some embodiments, the first overlay accuracy map is determined by: for a target wafer in the first batch of wafers, determining a measurement result corresponding to the target wafer; based on the measurement result and the wafer pattern on the target wafer, generating a target overlay accuracy map corresponding to the target wafer; and based on the target overlay accuracy maps respectively generated for the first batch of wafers, determining the first overlay accuracy map.

[0061] At block 620, based on the compensation optimal value for the first batch of wafers and multiple candidate weight values of the feedback weight, multiple overlay accuracy feedback values for the first batch of wafers are determined.

[0062] In some embodiments, determining multiple overlay accuracy feedback values includes: for a candidate weight value among the multiple candidate weight values, based on the compensation optimal value and the candidate weight value, determining an overlay accuracy feedback value corresponding to the candidate weight value as one of the multiple overlay accuracy feedback values.

[0063] In some embodiments, determining a plurality of overlay accuracy feedback values includes: determining historical overlay accuracy feedback values for wafers of a previous lot of the first lot of wafers; for a candidate weight value among a plurality of candidate weight values, determining an overlay accuracy feedback value corresponding to the candidate weight value based on a compensation optimal value, the historical overlay accuracy feedback values, and the candidate weight value, as one of the plurality of overlay accuracy feedback values.

[0064] In some embodiments, the compensation optimal value is determined by: determining the compensation optimal value based on the overlay accuracy compensation value and the measurement result used in manufacturing the first lot of wafers.

[0065] In block 630, based on the plurality of overlay accuracy feedback values and the first overlay accuracy map, determine a target weight value of the feedback weight for overlay accuracy compensation of subsequent lots of wafers of the first lot of wafers.

[0066] In some embodiments, determining the target weight value of the feedback weight includes: for each candidate weight value among the plurality of candidate values, based on the overlay accuracy feedback value corresponding to the candidate value weight among the plurality of overlay accuracy feedback values and the first overlay accuracy map, determining a first difference, where the first difference characterizes the difference between the simulated overlay accuracy and the overlay accuracy distribution, and the simulated overlay accuracy is determined based on the overlay accuracy feedback value corresponding to the candidate value; based on the first difference and the historical difference information corresponding to the wafers of the previous lot of the first lot of wafers, determining a second difference corresponding to the candidate weight value, where the historical difference information characterizes the difference between the simulated overlay accuracy corresponding to the previous lot of wafers and the overlay accuracy distribution corresponding to the previous lot of wafers; and based on the second differences respectively determined for the plurality of candidate weight values, determining the target weight value from the plurality of candidate weight values.

[0067] In some embodiments, determining the target weight value from the plurality of candidate weight values includes: determining at least one weight value from the plurality of candidate weight values based on the second differences respectively determined for the plurality of candidate weight values and a preset condition; and determining the target weight value based on the change trend of the at least one weight value.

[0068] In some embodiments, determining the target weight value includes: presenting the change trend of the at least one weight value; receiving a selection of a weight value among the at least one weight value; and determining the selected weight value as the target weight value.

[0069] In some embodiments, determining the first difference includes: based on the overlay accuracy feedback value, determining a second overlay accuracy map that simulates the distribution of the overlay accuracy on the wafer; and determining the first difference based on the difference between the first overlay accuracy map and the second overlay accuracy map.

[0070] In some embodiments, process 600 further includes: determining a target overlay accuracy feedback value for the first batch of wafers by using a feedback calculation model based on a target weight value of a feedback weight and a compensation optimal value for the first batch of wafers; and determining an overlay accuracy compensation value to be used for manufacturing a second batch of wafers based on the target overlay accuracy feedback value, where the second batch of wafers is a subsequent batch of the first batch of wafers.

[0071] Figure 7 A block diagram of an electronic device 700 in which one or more embodiments of the present disclosure may be implemented is shown. The electronic device 700 may be used, for example, to implement a layout processing device 110 as shown in Figure 1 It should be understood that Figure 7 The electronic device 700 shown is merely exemplary and should not constitute any limitation on the functions and scopes of the embodiments described herein.

[0072] As Figure 7 shown, the electronic device 700 is in the form of a general-purpose electronic device. The components of the electronic device 700 may include, but are not limited to, one or more processors 710 or processing units, a memory 720, a storage device 730, one or more communication units 740, one or more input devices 750, and one or more output devices 760. The processing unit may be an actual or virtual processor and is capable of performing various processes according to programs stored in the memory 720. In a multi-processor system, multiple processing units execute computer-executable instructions in parallel to improve the parallel processing ability of the electronic device 700.

[0073] The electronic device 700 generally includes multiple computer storage media. Such media may be any accessible media available to the electronic device 700, including but not limited to volatile and non-volatile media, removable and non-removable media. The memory 720 may be a volatile memory (such as registers, caches, random access memory (RAM)), a non-volatile memory (such as read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. The storage device 730 may be a removable or non-removable medium and may include a machine-readable medium, such as a flash drive, a magnetic disk, or any other medium that can be used to store information and / or data (such as training data for training) and can be accessed within the electronic device 700.

[0074] The electronic device 700 may further include additional removable / non-removable, volatile / non-volatile storage media. Although not shown in Figure 7As shown, a disk drive for reading from and writing to a removable, non-volatile disk (e.g., a "floppy disk") and an optical disk drive for reading from and writing to a removable, non-volatile optical disk can be provided. In these cases, each drive can be connected to a bus (not shown) by one or more data medium interfaces. Memory 720 may include a computer program product 725 having one or more program modules configured to execute the various methods or actions of the various embodiments of the present disclosure.

[0075] Communication unit 740 enables communication with other electronic devices via a communication medium. Additionally, the functions of the components of electronic device 700 can be implemented in a single computing cluster or multiple computer machines that are capable of communicating via a communication connection. Thus, electronic device 700 can operate in a networked environment using a logical connection to one or more other servers, network personal computers (PCs), or another network node.

[0076] Input device 750 can be one or more input devices, such as a mouse, keyboard, trackball, etc. Output device 760 can be one or more output devices, such as a display, speaker, printer, etc. Electronic device 700 can also communicate with one or more external devices (not shown) as needed via communication unit 740, such as storage devices, display devices, etc., communicate with one or more devices that enable a user to interact with electronic device 700, or communicate with any device that enables electronic device 700 to communicate with one or more other electronic devices (e.g., a network card, a modem, etc.). Such communication can be performed via an input / output (I / O) interface (not shown).

[0077] According to an exemplary implementation of the present disclosure, a computer-readable storage medium is provided, on which one or more computer instructions are stored, and the one or more computer instructions are executed by a processor to implement the method described above.

[0078] Aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and the combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0079] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine such that the instructions, when executed by the processing unit of the computer or other programmable data processing apparatus, result in an apparatus that implements the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that causes a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer-readable medium storing the instructions comprises a manufacture including instructions that implement various aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0080] The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device, such that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0081] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various implementations of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a segment of code, or a portion of an instruction, and the module, segment of code, or portion of an instruction includes one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two consecutive blocks may in fact be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or by a combination of dedicated hardware and computer instructions.

[0082] The implementations of the present disclosure have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed implementations. Many modifications and variations will be apparent to those of ordinary skill in the art in the field without departing from the scope and spirit of the described implementations. The choice of terms used herein is intended to best explain the principles of the implementations, the practical application, or the improvement of the technology in the market, or to enable other ordinary skilled persons in the art in the field to understand the implementations disclosed herein.

Claims

1. A method for overlay accuracy compensation, comprising: Acquire a first overlay accuracy map corresponding to the first batch of wafers, wherein the first overlay accuracy map represents the overlay accuracy distribution of the first batch of wafers before exposure, and the first batch of wafers is not the first batch of wafers; Determining a plurality of overlay accuracy feedback values ​​for the first batch of wafers based on the compensation optimal value for the first batch of wafers and a plurality of candidate weight values ​​of the feedback weight; For each candidate weight value among the plurality of candidate weight values, Determine a first difference based on the overlay accuracy feedback value corresponding to the candidate weight value among the multiple overlay accuracy feedback values ​​and the first overlay accuracy map; Determining a second difference corresponding to the candidate weight value based on the first difference and historical difference information corresponding to a previous batch of wafers of the first batch of wafers; as well as Based on the second difference, a target weight value is determined from the plurality of candidate weight values ​​for use in overlay accuracy compensation for subsequent batches of wafers of the first batch of wafers.

2. The method according to claim 1, characterized in that Determining the multiple overlay accuracy feedback values ​​includes: For a candidate weight value among the multiple candidate weight values, based on the compensation optimal value and the candidate weight value, an overlay accuracy feedback value corresponding to the candidate weight value is determined as one of the multiple overlay accuracy feedback values.

3. The method according to claim 1, characterized in that Determining the target weight value from the plurality of candidate weight values ​​comprises: determining a plurality of weight values ​​from the plurality of candidate weight values ​​based on the second differences and preset conditions respectively determined for the plurality of candidate weight values; and The target weight value is determined based on the change trends of the multiple weight values.

4. The method according to claim 1, characterized in that: The first set of engraving accuracy maps is determined by: For a target wafer in the first batch of wafers, determining a measurement result corresponding to the target wafer; Based on the measurement result and the wafer pattern on the target wafer, generating a target overlay accuracy map corresponding to the target wafer; as well as The first overlay accuracy map is determined based on the target overlay accuracy maps generated for the first batch of wafers.

5. The method according to claim 1, characterized in that The method further comprises: Determining a target overlay accuracy feedback value for the first batch of wafers using a feedback calculation model based on the target weight value of the feedback weight and the optimal compensation value for the first batch of wafers; and Based on the target overlay accuracy feedback value, an overlay accuracy compensation value to be used in manufacturing a second batch of wafers is determined, where the second batch of wafers is a subsequent batch of the first batch of wafers.

6. The method according to claim 1, characterized in that Determining the first difference includes: Based on the overlay accuracy feedback value, determining a second overlay accuracy map, wherein the second overlay accuracy map simulates the distribution of overlay accuracy on the wafer; and The first difference is determined based on a difference between the first overlay accuracy map and the second overlay accuracy map.

7. The method according to claim 1, characterized in that The optimal compensation value is determined as follows: The optimal compensation value is determined based on the overlay accuracy compensation value used in manufacturing the first batch of wafers and the measurement result of the overlay accuracy of the first batch of wafers.

8. The method according to claim 3, characterized in that Determining the target weight value includes: presenting the change trend of the multiple weight values; receiving a selection of a weight value from the plurality of weight values; and The selected weight value is determined as the target weight value.

9. The method according to claim 1, characterized in that Determining the multiple overlay accuracy feedback values ​​includes: Determining a historical overlay accuracy feedback value for a preceding batch of wafers of the first batch of wafers; and For the candidate weight value, based on the optimal compensation value, the historical overlay accuracy feedback value and the candidate weight value, an overlay accuracy feedback value corresponding to the candidate weight value is determined as one of the multiple overlay accuracy feedback values.

10. An electronic device comprising: processor; as well as A memory coupled to the processor, the memory having instructions stored therein, the instructions causing the device to perform the method according to any one of claims 1 to 9 when executed by the processor.

11. A computer-readable storage medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the method according to any one of claims 1 to 9.

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