A Low Dropout Linear Regulator Based on Damping Coefficient Control

Abstract

The present invention discloses a low dropout linear regulator based on damping coefficient control, belonging to the technical field of linear regulators. The low dropout linear regulator includes a first-stage amplifier circuit, a second-stage amplifier circuit, a power stage circuit, and a damping coefficient control circuit. By adding a damping control circuit between the second-stage amplifier circuit and the power stage circuit to adjust the damping factor, the linear regulator can obtain good stability and transient characteristics. In addition, this structure can be used for both the structure without an external capacitor and the structure with an external capacitor. External capacitor structure External capacitor structure External capacitor structure External capacitor structure External capacitor structure.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly relates to a low dropout linear regulator based on damping coefficient control. Background Art

[0002] The low dropout linear regulator is a core module in the power management chip, which is widely integrated on the system-on-chip to supply power to its core modules and provide a stable voltage. Its performance indicators such as power consumption, noise, transient response, and efficiency are very important and play a crucial role in the entire chip system.

[0003] In traditional low dropout linear regulators, a large microfarad-level capacitor is externally connected to the chip output terminal, and this capacitor can improve the stability and transient performance of the system. However, with the improvement of the device integration level, it is desired to remove this externally connected large capacitor, which requires facing the challenges of poor stability and poor transient characteristics of the capacitorless low dropout linear regulator.

[0004] In view of this, how to solve the problems of poor stability and poor transient characteristics of the capacitorless low dropout linear regulator is a major technical problem in this field. Summary of the Invention

[0005] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a low dropout linear regulator based on damping coefficient control.

[0006] The purpose of the present invention is achieved by the following technical solutions:

[0007] A low dropout linear regulator based on damping coefficient control includes a first-stage amplifier circuit, a second-stage amplifier circuit, a damping coefficient control circuit, and a power stage circuit connected in sequence;

[0008] The first-stage amplifier circuit is used to provide high gain and output a stable voltage value;

[0009] The second-stage amplifier circuit is used to increase the gain and swing of the amplifier, and uses push-pull output to enhance the slew rate;

[0010] The power stage circuit is connected to the second-stage amplifier circuit and is used to bear a large current load and output a stable voltage;

[0011] The damping coefficient control circuit is used to control the damping coefficient of the circuit.

[0012] Further, the first-stage amplification circuit includes: a first PMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh NMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, a twenty-second PMOS transistor, a twenty-fifth NMOS transistor, and a twenty-sixth NMOS transistor; where:

[0013] The gate of the first PMOS transistor is connected to the supply voltage Vref3, and the drain of the first PMOS transistor is connected to the drains of the second NMOS transistor, the gates of the fourth NMOS transistor, the fifth NMOS transistor, the fifteenth NMOS transistor, the twenty-fifth NMOS transistor, and the twenty-sixth NMOS transistor;

[0014] The gate of the second NMOS transistor is connected to the gates of the third NMOS transistor, the tenth NMOS transistor, the drain of the tenth NMOS transistor, the gate of the fourteenth NMOS transistor, the gates of the twenty-third NMOS transistor and the twenty-fourth NMOS transistor, and the source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor;

[0015] The drain of the third NMOS transistor is connected to the gates of the sixth PMOS transistor, the seventh PMOS transistor, the drain of the eighth PMOS transistor, the gate of the sixteenth PMOS transistor, the gate of the nineteenth PMOS transistor, and the gate of the twentieth PMOS transistor, and the source of the third NMOS transistor is connected to the drain of the fifth NMOS transistor;

[0016] The drain of the sixth PMOS transistor is connected to the source of the eighth PMOS transistor;

[0017] The drain of the seventh PMOS transistor is connected to the source of the ninth PMOS transistor;

[0018] The gate of the eighth PMOS transistor is connected to the gates of the ninth PMOS transistor, the thirteenth PMOS transistor, the drain of the thirteenth PMOS transistor, the gate of the twenty-first PMOS transistor, and the gate of the twenty-second PMOS transistor;

[0019] The drain of the ninth PMOS transistor is connected to the drain and the gate of the tenth NMOS transistor;

[0020] The source of the tenth PMOS transistor is connected to the drain and the gate of the eleventh NMOS transistor;

[0021] The gate of the twelfth PMOS transistor is connected to the drain of the twelfth PMOS transistor and the source of the thirteenth PMOS transistor;

[0022] The drain of the thirteenth PMOS transistor is connected to the drain of the fourteenth NMOS transistor;

[0023] The source of the fourteenth NMOS transistor is connected to the drain of the fifteenth NMOS transistor;

[0024] The drain of the sixteenth PMOS transistor is connected to the sources of the seventeenth PMOS transistor and the eighteenth PMOS transistor;

[0025] The drain of the seventeenth PMOS transistor is connected to the source of the twenty-third NMOS transistor and the drain of the twenty-fifth NMOS transistor;

[0026] The gate of the eighteenth PMOS transistor is connected to the supply voltage Vref1, and the drain of the eighteenth PMOS transistor is connected to the source of the twenty-fourth NMOS transistor and the drain of the twenty-sixth NMOS transistor;

[0027] The drain of the nineteenth PMOS transistor is connected to the source of the twenty-first PMOS transistor;

[0028] The drain of the twentieth PMOS transistor is connected to the source of the twenty-second PMOS transistor;

[0029] The drain of the twenty-first PMOS transistor is connected to the drain of the twenty-third NMOS transistor;

[0030] The drain of the twenty-second PMOS transistor is connected to the drain of the twenty-fourth NMOS transistor;

[0031] The sources of the first PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the twelfth PMOS transistor, the sixteenth PMOS transistor, the nineteenth PMOS transistor, and the twentieth PMOS transistor are all connected to the supply power VDD;

[0032] The sources of the fourth NMOS transistor, the fifth NMOS transistor, the eleventh NMOS transistor, the fifteenth NMOS transistor, the twenty-fifth NMOS transistor, and the twenty-sixth NMOS transistor are all connected to ground.

[0033] Furthermore, the second-stage amplifier circuit includes a twenty-seventh PMOS transistor, a twenty-eighth NMOS transistor, a twenty-ninth NMOS transistor, a thirtieth NMOS transistor, a thirty-first NMOS transistor, a thirty-second PMOS transistor, and a thirty-third PMOS transistor, wherein:

[0034] The gate of the twenty-seventh PMOS transistor is connected to the drain of the third NMOS transistor in the first-stage amplifier circuit, and the drain of the twenty-seventh PMOS transistor is connected to the drains of the twenty-eighth NMOS transistor, the twenty-ninth NMOS transistor, the gate of the twenty-ninth NMOS transistor, and the gate of the thirty-first NMOS transistor;

[0035] The gate of the twenty-eighth NMOS transistor is connected to the gate of the thirtieth NMOS transistor and the drain of the twenty-second PMOS transistor in the first-stage amplifier circuit;

[0036] The drain of the thirtieth PMOS transistor is connected to the drain of the thirty-second PMOS transistor, and the gate of the thirty-second PMOS transistor is connected to the gate of the thirty-third PMOS transistor;

[0037] The drain of the thirty-first NMOS transistor is connected to the drain of the thirty-third PMOS transistor;

[0038] The sources of the twenty-eighth NMOS transistor, the twenty-ninth NMOS transistor, the thirtieth NMOS transistor, and the thirty-first NMOS transistor are connected to ground;

[0039] The sources of the twenty-seventh PMOS transistor, the thirty-second PMOS transistor, and the thirty-third PMOS transistor are connected to the power supply VDD.

[0040] Further, the power stage circuit includes: a thirty-fourth PMOS transistor, a first resistor, a second resistor, a first capacitor, and a second capacitor;

[0041] The source of the thirty-fourth PMOS transistor is connected to the power supply VDD, the gate of the thirty-fourth PMOS transistor is connected to the drain of the thirty-first NMOS transistor, and the drain of the thirty-fourth PMOS transistor is connected to one end of the first capacitor, one end of the first resistor, and one end of the second capacitor;

[0042] The other end of the first capacitor is connected to the drain of the twenty-sixth NMOS transistor in the first-stage amplifier circuit;

[0043] The first resistor and the second resistor are connected in series, the second capacitor is connected in parallel with the first resistor, and the other end of the second resistor is connected to ground;

[0044] The other end of the second capacitor is connected to the gate of the seventeenth NMOS transistor in the first-stage amplifier circuit.

[0045] Further, the damping factor control circuit includes a thirty-fifth PMOS transistor, a thirty-sixth PMOS transistor, a thirty-seventh NMOS transistor, a thirty-eighth NMOS transistor, a thirty-ninth NMOS transistor, a fortieth NMOS transistor, a forty-first NMOS transistor, a forty-second PMOS transistor, a forty-third PMOS transistor, a forty-fourth PMOS transistor, a forty-fifth PMOS transistor, and a third capacitor, where:

[0046] The gate of the thirty-fifth PMOS transistor is connected to the gate of the thirty-sixth PMOS transistor, the drain of the thirty-sixth PMOS transistor, the drain of the thirty-seventh NMOS transistor, and the gate of the forty-fifth PMOS transistor. The drain of the thirty-fifth PMOS transistor is connected to the drain of the thirty-ninth NMOS transistor, the gate of the thirty-ninth NMOS transistor, and the gate of the fortieth NMOS transistor.

[0047] The source of the thirty-seventh NMOS transistor is connected to the drain of the forty-first NMOIS transistor and the source of the thirty-eighth NMOS transistor. The gate of the thirty-seventh NMOS transistor is connected to one end of the third capacitor, the drain of the forty-fourth NMOS transistor, and the drain of the forty-fifth PMOS transistor.

[0048] The gate of the thirty-eighth NMOS transistor is connected to the supply voltage Vref2. The drain of the thirty-eighth NMOS transistor is connected to the drain of the forty-second PMOS transistor, and the gates of the forty-second PMOS transistor and the forty-third PMOS transistor.

[0049] The drain of the fortieth NMOS transistor is connected to the drain of the forty-third PMOS transistor.

[0050] The gate of the forty-first NMOS transistor is connected to the drain of the first PMOS transistor in the first-stage amplifier circuit.

[0051] The gate of the forty-fourth PMOS transistor is connected to the other end of the third capacitor and the drain of the thirty-first NMOS transistor in the second-stage amplifier circuit.

[0052] The sources of the thirty-fifth PMOS transistor, the thirty-sixth PMOS transistor, the forty-second PMOS transistor, the forty-third PMOS transistor, and the forty-fifth PMOS transistor are connected to the power supply VDD.

[0053] The sources of the thirty-ninth NMOS transistor, the fortieth NMOS transistor, the forty-first NMOS transistor, and the forty-fourth PMOS transistor are connected to ground.

[0054] The beneficial effects of the present invention are:

[0055] 1) By using Cascode frequency compensation, the influence of the feedforward path is blocked, the zero point in the right half plane caused by Miller capacitance compensation is eliminated, making the entire circuit easier to compensate, with better stability. And compared with Miller compensation, the compensation capacitor used in Cascode frequency compensation is smaller, saving chip area and tape-out cost.

[0056] 2) A symmetric amplifier with smaller mismatch is adopted to clamp the input voltage at a fixed voltage, approximately compensating for a zero point in the low-frequency left half-plane of the circuit to stabilize the circuit. In addition, through the design of transistor parameters, the damping factor coefficient of the circuit system can be set. When the damping factor coefficient is about 0.7, the transient response of the circuit system reaches the best.

[0057] 3) The second-stage amplifier adopts a push-pull output and transconductance boosting technology. By designing the width-to-length ratio of the MOS transistors, the slew rate of the output can be increased, that is, the input of the power stage can respond faster to load changes, and the circuit can obtain better transient response performance.

[0058] 4) The current mirror adopts a Cascode common-source and common-gate form to eliminate the channel length modulation effect. Description of the Drawings

[0059] Figure 1 This is the system circuit diagram of the low-dropout linear regulator based on damping coefficient control provided by the present invention;

[0060] Figure 2 This is the circuit schematic diagram of the low-dropout linear regulator based on damping coefficient control provided by an embodiment of the present invention. Detailed Embodiments

[0061] Next, the technical solutions of the present invention will be clearly and completely described in conjunction with the embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0062] Refer to Figure 1 - Figure 2 The present invention provides a technical solution:

[0063] As Figure 1 A low-dropout linear regulator based on damping coefficient control includes a first-stage amplifier circuit, a second-stage amplifier circuit, a damping coefficient control circuit, and a power stage circuit connected in sequence;

[0064] The first-stage amplifier circuit is used to provide high gain and output a stable voltage value;

[0065] The second-stage amplifier circuit is used to increase the gain and swing of the amplifier, and adopts a push-pull output to enhance the slew rate; when the output voltage jumps, the resistor network samples the jump voltage and feeds it back to the positive port of the first-stage amplifier circuit. Through the feedback control of the overall circuit, a stable voltage is output.

[0066] The power stage circuit is connected to the second-stage amplifier circuit and is used to bear a large current load and output a stable voltage;

[0067] The damping coefficient control circuit is used to control the damping coefficient of the circuit.

[0068] In one embodiment, as Figure 2 shown, the first-stage amplification circuit includes: a first PMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh NMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, a twenty-second PMOS transistor, a twenty-fifth NMOS transistor, and a twenty-sixth NMOS transistor; where:

[0069] The gate of the first PMOS transistor is connected to the supply voltage Vref3, and the drain of the first PMOS transistor is connected to the drains of the second NMOS transistor, the gates of the fourth NMOS transistor, the fifth NMOS transistor, the fifteenth NMOS transistor, the twenty-fifth NMOS transistor, and the twenty-sixth NMOS transistor.

[0070] The gate of the second NMOS transistor is connected to the gates of the third NMOS transistor, the tenth NMOS transistor, the drain of the tenth NMOS transistor, the gate of the fourteenth NMOS transistor, the gates of the twenty-third NMOS transistor and the twenty-fourth NMOS transistor, and the source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor.

[0071] The drain of the third NMOS transistor is connected to the gates of the sixth PMOS transistor, the seventh PMOS transistor, the drain of the eighth PMOS transistor, the gate of the sixteenth PMOS transistor, the gate of the nineteenth PMOS transistor, and the gate of the twentieth PMOS transistor, and the source of the third NMOS transistor is connected to the drain of the fifth NMOS transistor.

[0072] The drain of the sixth PMOS transistor is connected to the source of the eighth PMOS transistor.

[0073] The drain of the seventh PMOS transistor is connected to the source of the ninth PMOS transistor.

[0074] The gate of the eighth PMOS transistor is connected to the gates of the ninth PMOS transistor, the thirteenth PMOS transistor, the drain of the thirteenth PMOS transistor, the gate of the twenty-first PMOS transistor, and the gate of the twenty-second PMOS transistor.

[0075] The drain of the ninth PMOS transistor is connected to the drain and the gate of the tenth NMOS transistor.

[0076] The source of the tenth PMOS transistor is connected to the drain and the gate of the eleventh NMOS transistor;

[0077] The gate of the twelfth PMOS transistor is connected to the drain of the twelfth PMOS transistor and the source of the thirteenth PMOS transistor;

[0078] The drain of the thirteenth PMOS transistor is connected to the drain of the fourteenth NMOS transistor;

[0079] The source of the fourteenth NMOS transistor is connected to the drain of the fifteenth NMOS transistor;

[0080] The drain of the sixteenth PMOS transistor is connected to the sources of the seventeenth PMOS transistor and the eighteenth PMOS transistor;

[0081] The drain of the seventeenth PMOS transistor is connected to the source of the twenty-third NMOS transistor and the drain of the twenty-fifth NMOS transistor;

[0082] The gate of the eighteenth PMOS transistor is connected to the supply voltage Vref1, and the drain of the eighteenth PMOS transistor is connected to the source of the twenty-fourth NMOS transistor and the drain of the twenty-sixth NMOS transistor;

[0083] The drain of the nineteenth PMOS transistor is connected to the source of the twenty-first PMOS transistor;

[0084] The drain of the twentieth PMOS transistor is connected to the source of the twenty-second PMOS transistor;

[0085] The drain of the twenty-first PMOS transistor is connected to the drain of the twenty-third NMOS transistor;

[0086] The drain of the twenty-second PMOS transistor is connected to the drain of the twenty-fourth NMOS transistor;

[0087] The sources of the first PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the twelfth PMOS transistor, the sixteenth PMOS transistor, the nineteenth PMOS transistor, and the twentieth PMOS transistor are all connected to the supply power VDD;

[0088] The sources of the fourth NMOS transistor, the fifth NMOS transistor, the eleventh NMOS transistor, the fifteenth NMOS transistor, the twenty-fifth NMOS transistor, and the twenty-sixth NMOS transistor are all connected to ground.

[0089] In one embodiment, as Figure 2 shown, the second-stage amplifier circuit includes a twenty-seventh PMOS transistor, a twenty-eighth NMOS transistor, a twenty-ninth NMOS transistor, a thirtieth NMOS transistor, a thirty-first NMOS transistor, a thirty-second PMOS transistor, and a thirty-third PMOS transistor, wherein:

[0090] The gate of the twenty-seventh PMOS transistor is connected to the drain of the third NMOS transistor in the first-stage amplifier circuit. The drain of the twenty-seventh PMOS transistor is connected to the drains of the twenty-eighth NMOS transistor, the twenty-ninth NMOS transistor, the gate of the twenty-ninth NMOS transistor, and the gate of the thirty-first NMOS transistor.

[0091] The gates of the twenty-eighth NMOS transistor and the thirtieth NMOS transistor, and the drain of the twenty-second PMOS transistor in the first-stage amplifier circuit are connected.

[0092] The drain of the thirtieth PMOS transistor is connected to the drains of the thirty-second PMOS transistor, the gate of the thirty-second PMOS transistor, and the gate of the thirty-third PMOS transistor.

[0093] The drain of the thirty-first NMOS transistor is connected to the drain of the thirty-third PMOS transistor.

[0094] The sources of the twenty-eighth NMOS transistor, the twenty-ninth NMOS transistor, the thirtieth NMOS transistor, and the thirty-first NMOS transistor are connected to ground.

[0095] The sources of the twenty-seventh PMOS transistor, the thirty-second PMOS transistor, and the thirty-third PMOS transistor are connected to the power supply VDD.

[0096] In one embodiment, as Figure 2 shown, the power stage circuit includes: a thirty-fourth PMOS transistor, a first resistor, a second resistor, a first capacitor, and a second capacitor.

[0097] The source of the thirty-fourth PMOS transistor is connected to the power supply VDD. The gate of the thirty-fourth PMOS transistor is connected to the drain of the thirty-first NMOS transistor. The drain of the thirty-fourth PMOS transistor is connected to one end of the first capacitor, one end of the first resistor, and one end of the second capacitor.

[0098] The other end of the first capacitor is connected to the drain of the twenty-sixth NMOS transistor in the first-stage amplifier circuit.

[0099] The first resistor and the second resistor are connected in series. The second capacitor is connected in parallel with the first resistor. The other end of the second resistor is connected to ground.

[0100] The other end of the second capacitor is connected to the gate of the seventeenth NMOS transistor in the first-stage amplifier circuit.

[0101] In one embodiment, as Figure 2As shown, the damping coefficient control circuit includes the thirty-fifth PMOS transistor, the thirty-sixth PMOS transistor, the thirty-seventh NMOS transistor, the thirty-eighth NMOS transistor, the thirty-ninth NMOS transistor, the fortieth NMOS transistor, the forty-first NMOS transistor, the forty-second PMOS transistor, the forty-third PMOS transistor, the forty-fourth PMOS transistor, the forty-fifth PMOS transistor and the third capacitor, where:

[0102] The gate of the thirty-fifth PMOS transistor is connected to the gate of the thirty-sixth PMOS transistor, the drain of the thirty-sixth PMOS transistor, the drain of the thirty-seventh NMOS transistor and the gate of the forty-fifth PMOS transistor. The drain of the thirty-fifth PMOS transistor is connected to the drain of the thirty-ninth NMOS transistor, the gate of the thirty-ninth NMOS transistor and the gate of the fortieth NMOS transistor;

[0103] The source of the thirty-seventh NMOS transistor is connected to the drain of the forty-first NMOIS transistor and the source of the thirty-eighth NMOS transistor. The gate of the thirty-seventh NMOS transistor is connected to one end of the third capacitor, the drain of the forty-fourth NMOS transistor and the drain of the forty-fifth PMOS transistor;

[0104] The gate of the thirty-eighth NMOS transistor is connected to the supply voltage Vref2. The drain of the thirty-eighth NMOS transistor is connected to the drain of the forty-second PMOS transistor, and the gates of the forty-second PMOS transistor and the forty-third PMOS transistor;

[0105] The drain of the fortieth NMOS transistor is connected to the drain of the forty-third PMOS transistor;

[0106] The gate of the forty-first NMOS transistor is connected to the drain of the first PMOS transistor in the first-stage amplifier circuit;

[0107] The gate of the forty-fourth PMOS transistor is connected to the other end of the third capacitor and the drain of the thirty-first NMOS transistor in the second-stage amplifier circuit;

[0108] The sources of the thirty-fifth PMOS transistor, the thirty-sixth PMOS transistor, the forty-second PMOS transistor, the forty-third PMOS transistor and the forty-fifth PMOS transistor are connected to the power supply VDD;

[0109] The sources of the thirty-ninth NMOS transistor, the fortieth NMOS transistor, the forty-first NMOS transistor and the forty-fourth PMOS transistor are connected to ground.

[0110] The damping coefficient control circuit is between the second-stage amplifier circuit and the power stage. Its principle is approximately to introduce a low-frequency zero point into the circuit to compensate for the influence of the secondary pole, ensuring the stability of the circuit. In addition, through the design of transistor parameters, the damping factor coefficient of the circuit system can be set. When the damping factor coefficient is about 0.7, the second-order circuit system is in an underdamped state. At this time, the circuit response speed is fast, and the circuit response oscillation is not serious. The transient response of the circuit system reaches the best.

[0111] In the present invention, by adding a damping control circuit between the second-stage amplifier circuit and the power-stage circuit and adjusting the damping factor, the linear voltage regulator can obtain good stability and transient characteristics. In addition, this structure can be used for both the structure without off-chip capacitors and the structure with off-chip capacitors. Off-chip capacitor structure Off-chip capacitor structure Off-chip capacitor structure Off-chip capacitor structure Off-chip capacitor structure.

[0112] Among them, Cascode frequency compensation is adopted to block the influence of the feedforward path, eliminate the zero point in the right half plane brought by Miller capacitance compensation, making the whole circuit easier to compensate and having better stability. Moreover, compared with Miller compensation, the compensation capacitor used in Cascode frequency compensation is smaller, saving chip area and tape-out cost. The current mirror adopts the Cascode cascode form to eliminate the channel length modulation effect. The present invention uses a symmetric amplifier with smaller mismatch to clamp the input voltage at a fixed voltage, approximately compensating a low-frequency zero point in the left half plane of the circuit to make the circuit stable. In addition, through the design of transistor parameters, the damping factor coefficient of the circuit system can be set. When the damping factor coefficient is about 0.7, the transient response of the circuit system reaches the best. The second-stage amplifier adopts a push-pull output and a transconductance boosting technique to design the aspect ratio of the MOS transistor, which can improve the slew rate of the output, that is, the input of the power stage can respond faster to the load change, and the circuit can obtain better transient response performance.

[0113] [[ID=⑨]]The above are only the preferred embodiments of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be changed within the scope of the concept described herein through the above teachings or the techniques or knowledge in related fields. And the changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention should fall within the protection scope of the appended claims of the present invention.

Claims

1. A low dropout linear regulator based on damping coefficient control, characterized in that: It includes a first-stage amplifier circuit, a second-stage amplifier circuit, a damping factor control circuit, and a power stage circuit that are connected in sequence; The first-stage amplifier circuit is used to provide high gain and output a stable voltage value; The second-stage amplifier circuit is used to increase the gain and swing of the amplifier, and uses push-pull output to enhance the slew rate; The power stage circuit is connected to the second-stage amplifier circuit and is used to bear a large current load and output a stable voltage; The damping factor control circuit is used to control the damping factor of the circuit; The low-dropout linear regulator based on damping factor control uses Cascode frequency compensation to block the influence of the feedforward path, eliminate the right-half plane zero caused by Miller capacitance compensation, and at the same time uses a symmetric amplifier to clamp the input voltage at a fixed voltage, approximately compensating a low-frequency left-half plane zero for the circuit to make the circuit stable; The first-stage amplifier circuit includes: a first PMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh NMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, a twenty-second PMOS transistor, a twenty-fifth NMOS transistor, a twenty-sixth NMOS transistor; where: The gate of the first PMOS transistor is connected to the supply voltage Vref3, and the drain of the first PMOS transistor is connected to the drains of the second NMOS transistor, the gates of the fourth NMOS transistor, the fifth NMOS transistor, the fifteenth NMOS transistor, the twenty-fifth NMOS transistor, and the twenty-sixth NMOS transistor; The gate of the second NMOS transistor is connected to the gates of the third NMOS transistor, the tenth NMOS transistor, the drain of the tenth NMOS transistor, the gate of the fourteenth NMOS transistor, the gate of the twenty-third NMOS transistor, and the gate of the twenty-fourth NMOS transistor. The source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor; The drain of the third NMOS transistor is connected to the gates of the sixth PMOS transistor, the seventh PMOS transistor, the drain of the eighth PMOS transistor, the gate of the sixteenth PMOS transistor, the gate of the nineteenth PMOS transistor, and the gate of the twentieth PMOS transistor. The source of the third NMOS transistor is connected to the drain of the fifth NMOS transistor; The drain of the sixth PMOS transistor is connected to the source of the eighth PMOS transistor; The drain of the seventh PMOS transistor is connected to the source of the ninth PMOS transistor; The gate of the eighth PMOS transistor is connected to the gates of the ninth PMOS transistor, the thirteenth PMOS transistor, the drain of the thirteenth PMOS transistor, the gate of the twenty-first PMOS transistor, and the gate of the twenty-second PMOS transistor; The drain of the ninth PMOS transistor is connected to the drain and gate of the tenth NMOS transistor; The source of the tenth PMOS transistor is connected to the drain and gate of the eleventh NMOS transistor; The gate of the twelfth PMOS transistor is connected to the drain of the twelfth PMOS transistor and the source of the thirteenth PMOS transistor; The drain of the thirteenth PMOS transistor is connected to the drain of the fourteenth NMOS transistor; The source of the fourteenth NMOS transistor is connected to the drain of the fifteenth NMOS transistor; The drain of the sixteenth PMOS transistor is connected to the source of the seventeenth PMOS transistor and the source of the eighteenth PMOS transistor; The drain of the seventeenth PMOS transistor is connected to the source of the twenty-third NMOS transistor and the drain of the twenty-fifth NMOS transistor; The gate of the eighteenth PMOS transistor is connected to the supply voltage Vref1, and the drain of the eighteenth PMOS transistor is connected to the source of the twenty-fourth NMOS transistor and the drain of the twenty-sixth NMOS transistor; The drain of the nineteenth PMOS transistor is connected to the source of the twenty-first PMOS transistor; The drain of the twentieth PMOS transistor is connected to the source of the twenty-second PMOS transistor; The drain of the twenty-first PMOS transistor is connected to the drain of the twenty-third NMOS transistor; The drain of the twenty-second PMOS transistor is connected to the drain of the twenty-fourth NMOS transistor; The sources of the first PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the twelfth PMOS transistor, the sixteenth PMOS transistor, the nineteenth PMOS transistor and the twentieth PMOS transistor are all connected to the supply power VDD; The sources of the fourth NMOS transistor, the fifth NMOS transistor, the eleventh NMOS transistor, the fifteenth NMOS transistor, the twenty-fifth NMOS transistor and the twenty-sixth NMOS transistor are all connected to ground; The second-stage amplifier circuit includes a twenty-seventh PMOS transistor, a twenty-eighth NMOS transistor, a twenty-ninth NMOS transistor, a thirtieth NMOS transistor, a thirty-first NMOS transistor, a thirty-second PMOS transistor and a thirty-third PMOS transistor, where: The gate of the twenty-seventh PMOS transistor is connected to the drain of the third NMOS transistor in the first-stage amplifier circuit, and the drain of the twenty-seventh PMOS transistor is connected to the drain of the twenty-eighth NMOS transistor, the drain of the twenty-ninth NMOS transistor, the gate of the twenty-ninth NMOS transistor and the gate of the thirty-first NMOS transistor; The gates of the twenty-eighth NMOS transistor and the thirtieth NMOS transistor and the drain of the twenty-second PMOS transistor in the first-stage amplifier circuit are connected; The drain of the thirtieth PMOS transistor is connected to the drain of the thirty-second PMOS transistor, the gate of the thirty-second PMOS transistor and the gate of the thirty-third PMOS transistor; The drain of the thirty-first NMOS transistor is connected to the drain of the thirty-third PMOS transistor; The sources of the twenty-eighth NMOS transistor, the twenty-ninth NMOS transistor, the thirtieth NMOS transistor and the thirty-first NMOS transistor are connected to ground; The sources of the twenty-seventh PMOS transistor, the thirty-second PMOS transistor and the thirty-third PMOS transistor are connected to the supply power VDD; The power stage circuit includes: a thirty-fourth PMOS transistor, a first resistor, a second resistor, a first capacitor and a second capacitor; The source of the thirty-fourth PMOS transistor is connected to the power supply VDD. The gate of the thirty-fourth PMOS transistor is connected to the drain of the thirty-first NMOS transistor. The drain of the thirty-fourth PMOS transistor is connected to one end of the first capacitor, one end of the first resistor, and one end of the second capacitor. The other end of the first capacitor is connected to the drain of the twenty-sixth NMOS transistor in the first-stage amplifier circuit. The first resistor and the second resistor are connected in series. The second capacitor is connected in parallel with the first resistor. The other end of the second resistor is connected to ground. The other end of the second capacitor is connected to the gate of the seventeenth NMOS transistor in the first-stage amplifier circuit. The damping coefficient control circuit includes a thirty-fifth PMOS transistor, a thirty-sixth PMOS transistor, a thirty-seventh NMOS transistor, a thirty-eighth NMOS transistor, a thirty-ninth NMOS transistor, a fortieth NMOS transistor, a forty-first NMOS transistor, a forty-second PMOS transistor, a forty-third PMOS transistor, a forty-fourth PMOS transistor, a forty-fifth PMOS transistor, and a third capacitor, where: The gate of the thirty-fifth PMOS transistor is connected to the gate of the thirty-sixth PMOS transistor, the drain of the thirty-sixth PMOS transistor, the drain of the thirty-seventh NMOS transistor, and the gate of the forty-fifth PMOS transistor. The drain of the thirty-fifth PMOS transistor is connected to the drain of the thirty-ninth NMOS transistor, the gate of the thirty-ninth NMOS transistor, and the gate of the fortieth NMOS transistor. The source of the thirty-seventh NMOS transistor is connected to the drain of the forty-first NMOS transistor and the source of the thirty-eighth NMOS transistor. The gate of the thirty-seventh NMOS transistor is connected to one end of the third capacitor, the drain of the forty-fourth NMOS transistor, and the drain of the forty-fifth PMOS transistor. The gate of the thirty-eighth NMOS transistor is connected to the supply voltage Vref2. The drain of the thirty-eighth NMOS transistor is connected to the drain of the forty-second PMOS transistor. The gate of the forty-second PMOS transistor is the same as the gate of the forty-third PMOS transistor. The drain of the fortieth NMOS transistor is connected to the drain of the forty-third PMOS transistor. The gate of the forty-first NMOS transistor is connected to the drain of the first PMOS transistor in the first-stage amplifier circuit. The gate of the forty-fourth PMOS transistor is connected to the other end of the third capacitor and the drain of the thirty-first NMOS transistor in the second-stage amplifier circuit. The sources of the thirty-fifth PMOS transistor, the thirty-sixth PMOS transistor, the forty-second PMOS transistor, the forty-third PMOS transistor, and the forty-fifth PMOS transistor are connected to the power supply VDD. The sources of the thirty-ninth NMOS transistor, the fortieth NMOS transistor, the forty-first NMOS transistor, and the forty-fourth PMOS transistor are connected to ground.

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