Method and apparatus for accelerating critical path instructions

Abstract

The present disclosure relates to a method and apparatus for accelerating critical path instructions, the method comprising: performing a critical path analysis on a program using a profile-guided optimization (PGO) tool to identify critical path instructions; the recognized key path instruction is recompiled into a self-defined key instruction with key prompt information through a compiler tool, an operation code of the self-defined key instruction is an operation code reserved for the self-defined instruction by an RISC-V instruction set architecture, and the operation code is used for indicating that the instruction is a key instruction of a specific type; and the RISC-V processor realizes accelerated execution of the custom key instruction based on the operation code and / or the key prompt information of the custom key instruction.

Description

Technical Field

[0001] The present disclosure relates to the field of computers, and more particularly, to a method and apparatus for accelerating critical path instructions in a fifth-generation reduced instruction set computer (RISC-V) processor. Background Art

[0002] Out-of-order execution is a key technology in modern processor architectures. The processor core executes instructions based on data dependencies in the program. If there is no dependency between instructions, they can be executed in parallel to hide delays. At this time, the instructions with the longest execution time (for example, load operations that miss all caches) form the critical path and ultimately determine the overall execution time of the program. Any delay in executing these instructions will affect the performance of the entire system. Conversely, the system can tolerate delays in non-critical path instructions as long as such delays do not result in the generation of new critical path instructions. Therefore, identifying critical path instructions in the program and designing specific microarchitecture algorithms to accelerate them are crucial to developing high-performance processors. Summary of the invention

[0003] According to an embodiment of the present disclosure, a method for accelerating critical path instructions in a RISC-V processor is provided, the method comprising: performing critical path analysis on a program using a profile guided optimization (PGO) tool to identify critical path instructions; recompiling the identified critical path instructions into custom critical instructions with critical hint information using a compiler tool, wherein an opcode of the custom critical instruction is an opcode reserved for the custom instruction by a RISC-V instruction set architecture, and wherein the opcode is used to indicate that the instruction is a critical instruction of a specific type; and accelerating execution of the custom critical instruction by the RISC-V processor based on the opcode and / or critical hint information of the custom critical instruction.

[0004] According to an embodiment of the present disclosure, a device for accelerating critical path instructions in a RISC-V processor is provided, the device comprising means for executing the steps of the above method.

[0005] According to an embodiment of the present disclosure, a computer-readable storage medium is provided, on which executable codes are stored, wherein when the executable codes are executed by a processing circuit, the processing circuit executes the method according to the above embodiment.

[0006] According to an embodiment of the present disclosure, a computer program product is provided, comprising executable codes, wherein when the instructions are executed by a processing circuit, the processing circuit executes the method according to the above embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments of the present disclosure will be described by way of example and not limitation with reference to the figures of the accompanying drawings in which like reference numerals refer to like elements and in which: Figure 1 Illustrated is a block diagram of an example processor and / or SoC 100 that may have one or more cores and with an integrated memory controller.

[0008] Figure 2 A flowchart of a method for accelerating critical path instructions in a RISC-V processor according to an embodiment of the present disclosure is shown.

[0009] Figure 3 An exemplary schematic diagram of an event dependency graph according to an embodiment of the present invention is shown.

[0010] Figure 4 A schematic diagram showing existing instruction encoding of RISC-V.

[0011] Figure 5 A schematic diagram of a flow chart of a BPU predicting a custom critical branch instruction according to an embodiment of the present disclosure is shown.

[0012] Figure 6 A schematic diagram of a flow chart of a hardware cache prefetcher predicting a load instruction according to an embodiment of the present disclosure is shown.

[0013] Figure 7 is a block diagram illustrating components capable of reading instructions from a machine-readable or computer-readable medium (eg, a non-transitory machine-readable storage medium) and performing any one or more of the methods discussed herein, according to some example embodiments. DETAILED DESCRIPTION

[0014] The features and exemplary embodiments of various aspects of the application will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the application. However, it is obvious to those skilled in the art that the application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the application by illustrating the example of the application. The application is by no means limited to any specific configuration proposed below, but covers any modification, replacement and improvement of elements, parts and algorithms without departing from the spirit of the application. In the accompanying drawings and the following description, known structures and technologies are not shown to avoid causing unnecessary ambiguity to the application.

[0015] Furthermore, various operations will be described as multiple discrete operations in a manner that is most helpful for understanding the illustrative embodiments; however, the order of description should not be construed as implying that these operations are necessarily order dependent. In particular, these operations do not need to be performed in the order presented.

[0016] The phrases "in an embodiment," "in one embodiment," and "in some embodiments" are used repeatedly herein. The phrase generally does not refer to the same embodiment; however, it may. The terms "comprising," "having," and "including" are synonymous unless the context dictates otherwise. The phrases "A or B" and "A / B" mean "(A), (B) or (A and B)."

[0017] Figure 1 A block diagram of an example processor and / or SoC 100 is illustrated, which may have one or more cores and have an integrated memory controller. The processor 100 illustrated by the solid line box has a single core 102(A), a system agent unit circuit 110, and a set of one or more interface controller unit circuits 116, while the optionally added dashed line box illustrates an alternative processor 100 as having multiple cores 102(A)-(N), a set of one or more integrated memory control unit circuits 114 in the system agent unit circuit 110, dedicated logic 108, and a set of one or more interface controller unit circuits 116.

[0018] Different implementations of processor 100 may include: 1) a CPU, where dedicated logic 108 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores, not shown), and cores 102 (A)-(N) are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, or a combination of the two); 2) a coprocessor, where cores 102 (A)-(N) are a large number of dedicated cores primarily for graphics and / or scientific (throughput) purposes; and 3) a coprocessor, where cores 102 (A)-(N) are a large number of general-purpose in-order cores. Thus, processor 100 may be a general-purpose processor, a coprocessor, or a dedicated processor, such as a network or communication processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput many-in-one (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor may be implemented on one or more chips. Processor 100 may be part of and / or may be implemented on one or more substrates using any of a variety of process technologies, such as complementary metal oxide semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal oxide semiconductor (PMOS), or N-type metal oxide semiconductor (NMOS).

[0019] The memory hierarchy includes one or more levels of cache unit circuits 104(A)-(N) within the cores 102(A)-(N), a set of one or more shared cache unit circuits 106, and external memory (not shown) coupled to the set of integrated memory controller unit circuits 114. The set of one or more shared cache unit circuits 106 may include one or more intermediate level caches, such as level 2 (L2), level 3 (L3), level 4 (4), or other levels of cache, such as last level cache (LLC), and / or combinations thereof. While in some examples an interface network circuit 112 (e.g., a ring interconnect) provides an interface to the dedicated logic 108 (e.g., integrated graphics logic), the set of shared cache unit circuits 106, and the system agent unit circuit 110, alternative examples use any number of well-known techniques to provide interfaces to these units. In some examples, coherency is maintained between one or more circuits in the shared cache unit circuits 106 and the cores 102(A)-(N). In some examples, interface controller unit circuitry 116 couples the cores to one or more other devices 118 , such as one or more I / O devices, storage, one or more communication devices (eg, wireless network, wired network, etc.), and the like.

[0020] In some examples, one or more of the cores 102(A)-(N) have multi-threading capabilities. The system agent unit circuit 110 includes those components that coordinate and operate the cores 102(A)-(N). The system agent unit circuit 110 may include, for example, a power control unit (PCU) circuit and / or a display unit circuit (not shown). The PCU may be (or may include) logic and components required to adjust the power state of the cores 102(A)-(N) and / or the dedicated logic 108 (e.g., integrated graphics logic). The display unit circuit is used to drive one or more externally connected displays.

[0021] The cores 102(A)-(N) may be homogeneous with respect to instruction set architecture (ISA). Alternatively, the cores 102(A)-(N) may be heterogeneous with respect to ISA; that is, a subset of the cores 102(A)-(N) may be capable of executing one ISA, while other cores may be capable of executing only a subset of the ISA or may be capable of executing another ISA. In one embodiment, the processor cores 102(A)-(N) may employ the RISC-V instruction set architecture in whole or in part.

[0022] Existing solutions for identifying and accelerating critical path instructions mainly focus on predicting the criticality of load (LOAD) instructions and using prefetching techniques to accelerate load instructions identified as critical. However, existing solutions are limited to identifying and accelerating a single type of critical path instructions (i.e., load instructions only), while other types of critical path instructions are not effectively processed. In addition, existing solutions lack a unified framework for identifying and accelerating critical path instructions.

[0023] In view of this, the present disclosure provides a software-hardware co-design framework that can realize free identification and acceleration of critical path instructions. Specifically, in the software-hardware co-design framework provided by the present disclosure, the software part can be used to: (1) use PGO technology to identify critical path instructions in the critical path; (2) use the characteristics of the RISC-V instruction set architecture to establish instruction extensions for indicating the criticality of instructions; and (3) use criticality hints to recompile the identified critical path instructions to obtain different types of custom critical instructions. In the hardware part, different microarchitectures can adopt various strategies to process instructions marked as critical (recompiled custom critical instructions). Specifically, prediction components (e.g., branch prediction components (BPUs), prefetchers, etc.) can accurately predict custom critical instructions and prepare the required data for custom critical instructions in advance. Buffer components (e.g., arithmetic logic units (ALUs)) and computing components can ensure the availability of hardware resources for custom critical instructions and prioritize the allocation of hardware resources for custom critical instructions.

[0024] The disclosed hardware-software co-design framework is highly versatile and flexible, and can recognize not only load instructions, but also all other types of critical instructions, and supports the implementation of various algorithms or strategies customized for accelerating these instructions. By comprehensively accelerating all types of critical instructions, the disclosed framework can significantly improve system performance compared to previous solutions that only focus on load instructions.

[0025] Figure 2 A flow chart of a method for accelerating critical path instructions in a RISC-V processor according to an embodiment of the present disclosure is shown. Method 200 may include steps S202, S204, and S206. However, in some embodiments, method 200 may include more or fewer different steps, which is not limited by the present disclosure.

[0026] In step S202, a critical path analysis is performed on the program using a PGO tool to identify critical path instructions; In step S204, using a compiler tool, the identified critical path instruction is recompiled into a custom critical instruction with critical hint information, wherein the opcode of the custom critical instruction is an opcode reserved for the custom instruction by the RISC-V instruction set architecture, and wherein the opcode is used to indicate that the instruction is a critical instruction of a specific type; and In step S206, the RISC-V processor implements accelerated execution of the custom key instruction based on the opcode and / or critical prompt information of the custom key instruction.

[0027] In an embodiment of the present disclosure, the method 200 may further include: identifying a critical path and a critical event on the critical path based on an event dependency graph (DEG); and determining a critical path instruction that generates a critical event based on the identified critical event. Figure 3 FIG. 2 shows an exemplary schematic diagram of an event dependency graph according to an embodiment of the present disclosure. DEG is widely used to determine which CPU events are the main causes of cycle loss during the entire micro-execution process. Figure 3 As shown, for example, a D cache miss may be a critical event that contributes 100 cycles to the micro-execution. The events that form DEG come from the execution of instructions. Therefore, by searching for critical events in DEG, we can identify which instructions are critical. These instructions can have one or more critical events in DEG.

[0028] In an embodiment of the present disclosure, different opcodes reserved by the RISC-V instruction set architecture for custom instructions are used to indicate different types of custom key instructions. In the existing instruction encoding of RISC-V, some opcodes are reserved for custom instructions. Figure 4 FIG. 1 is a schematic diagram showing the existing instruction encoding of RISC-V. Figure 4 As shown, four custom instruction types custom-0, custom-1, custom-2, and custom-3 are reserved in the RISC-V instruction architecture, and their opcodes can use the opcodes corresponding to custom-0, custom-1, custom-2, and custom-3 in the table.

[0029] In one embodiment of the present disclosure, the opcode 0001011 of custom-0 can be used to compile a custom key branch instruction; the opcode 0101011 of custom-1 can be used to compile a custom key load instruction; the opcode 1011011 of custom-2 can be used to compile a custom key multiply-add instruction; and the opcode 1111011 of custom-3 can be used to compile a custom key multiply-subtract instruction. In another embodiment of the present disclosure, the opcodes of custom-0, custom-1, custom-2, and custom-3 can be used to compile various other types of custom key instructions, respectively. In yet another embodiment of the present disclosure, any other reserved opcode in the RISC-V instruction architecture can be used to compile various types of custom key instructions, and the present disclosure does not specifically limit this.

[0030] In an embodiment of the present disclosure, the critical prompt information of the custom key instruction can be encoded in the Funct3 field of the custom key instruction, for example, using 3 bits in the Funct3 field. In an embodiment of the present disclosure, the critical prompt information of the custom key instruction can be used to indicate whether the instruction is a regular instruction or a critical instruction. In an embodiment of the present disclosure, the critical prompt information of the custom key instruction can also be used to indicate the stability of the critical instruction.

[0031] In one embodiment, the criticality hint information of the custom key branch instruction is used to indicate that the instruction is one of the following items: a regular instruction; a key instruction for stable jump; a key instruction for stable non-jump; or a key instruction for unstable jump. For example, in the Funct3 field of the custom key branch instruction: 000 may indicate that the instruction is a regular instruction; 001 may indicate that the instruction is a key instruction for stable jump; 010 may indicate that the instruction is a key instruction for stable non-jump; 011 may indicate that the instruction is a key instruction for unstable jump.

[0032] In one embodiment, the criticality hint information of a custom key instruction such as a custom load key instruction, a custom multiply-add key instruction, or a custom multiply-subtract key instruction is used to indicate that the instruction is one of the following: a regular instruction; or a critical instruction. For example, in the Funct3 field of the above instruction: 000 may indicate that the instruction is a regular instruction; 001 may indicate that the instruction is a critical instruction.

[0033] It should be understood that the encoding format of the Funct3 field of the above-mentioned custom key instruction is only for illustrative purposes. The present disclosure does not specifically limit the encoding format of the Funct3 field. On the contrary, the present invention is intended to cover all possible changes and modifications, as long as they fall within the technical scope of the present invention.

[0034] In an embodiment of the present disclosure, the accelerated execution of a custom key instruction by a RISC-V processor based on the opcode and / or critical hint information of the custom key instruction may include: a prediction component of the RISC-V processor predicting the control flow and / or data flow of the custom key instruction based on the opcode and / or critical hint information of the custom key instruction.

[0035] In an embodiment of the present disclosure, the prediction component of the RISC-V processor may include, for example, a branch prediction unit (BPU) and an instruction cache prefetcher for predicting the control flow of custom key instructions, and a data cache prefetcher for predicting the data flow of custom key instructions, and the like.

[0036] Figure 5 FIG. 2 shows a flow chart of a BPU predicting a custom key branch instruction according to an embodiment of the present disclosure. Figure 5 As shown, the BPU component is configured to directly predict the branch direction of the key branch instruction based on the hint information compiled in the key instruction when it is determined that the branch instruction is a key instruction with a stable hint based on the key hint information of the entered custom key instruction, without executing the conventional process of the BPU component for predicting the direction of the branch instruction. The BPU component is also configured to execute the conventional process for predicting the direction of the branch instruction on the branch instruction when it is determined that the branch instruction is a key instruction or a conventional instruction with an unstable hint based on the key hint information of the entered custom key instruction. In one embodiment, in the BPU history table of the BPU component, compared with conventional branch instructions, key instructions with unstable hints can be assigned a higher replacement age (or lower replacement priority), and a higher replacement age means that the entry of the instruction will be kept in the history table for a longer time and is not easily replaced by a new entry. For branch instructions with unstable hints, keeping their prediction information in the history table for a long time helps to improve the accuracy of the prediction.

[0037] In an embodiment of the present disclosure, the hardware cache prefetcher is configured to prefetch corresponding data blocks or instructions only for critical instructions. In one embodiment, the cache prefetcher may include a training data filter for filtering instructions without criticality hints, such as conventional load instructions. In another embodiment, the training data filter may be set before the cache prefetcher. Figure 6 FIG. 2 shows a flow chart of a hardware cache prefetcher predicting a load instruction according to an embodiment of the present disclosure. Figure 6As shown, before entering the cache prefetcher 620, the instruction first enters the training data filter 610, which is used to filter any memory access requests of instructions without critical hints. Only critical memory accesses from critical instructions are used to train the cache prefetcher 620 and trigger prefetch requests. It should be understood that although Figure 6 Only load instructions are shown in FIG. 1 , but the cache prefetcher according to an embodiment of the present disclosure may be used for any type of critical instructions that may utilize the cache prefetcher.

[0038] In an embodiment of the present disclosure, the accelerated execution of custom key instructions by a RISC-V processor based on the opcode and / or critical prompt information of the custom key instructions may include: the hardware buffer component and / or hardware computing component of the RISC-V processor preferentially prepares corresponding hardware resources for the custom key instructions.

[0039] In one embodiment, the buffer component is configured to prioritize resource allocation for custom critical instructions with criticality hints and reduce the possibility of them being replaced. In other words, when critical instructions arrive at the buffer component (such as renaming register stack, instruction queue, etc.), if the critical instructions and ordinary instructions request hardware resources at the same time, the buffer component will prioritize the resource requirements of the critical instructions. In one embodiment of the present disclosure, the buffer component is configured to prioritize replacing entries inserted by non-critical instructions rather than entries inserted by critical instructions when a replacement operation needs to be performed.

[0040] In one embodiment, the computing component of the processor is configured to prioritize the allocation of computing resources to custom critical instructions to ensure that the critical instructions can be executed as quickly and efficiently as possible.

[0041] The disclosed hardware-software co-design framework is highly versatile and flexible, and can recognize not only load instructions, but also all other types of critical instructions, and supports the implementation of various algorithms or strategies customized for accelerating these instructions. By comprehensively accelerating all types of critical instructions, the disclosed framework can significantly improve system performance compared to previous solutions that only focus on load instructions.

[0042] Figure 7 is a block diagram illustrating components capable of reading instructions or executable code from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium) and performing any one or more of the methods discussed herein according to some example embodiments. Specifically, Figure 7A schematic diagram of hardware resources 700 is shown, which includes one or more processors (or processor cores) 710, one or more memory / storage devices 720, and one or more communication resources 730, wherein each of these processors, memory / storage devices, and communication resources can be communicatively coupled via a bus 740 or other interface circuits. For embodiments utilizing node virtualization (e.g., network function virtualization (NFV)), a hypervisor 702 can be executed to provide an execution environment for one or more network slices / sub-slices to utilize hardware resources 700.

[0043] Processor 710 may include, for example, processor 712 and processor 714. Processor 710 may be, for example, a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP) such as a baseband processor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a radio frequency integrated circuit (RFIC), another processor (including those discussed herein), or any suitable combination thereof.

[0044] The memory / storage device 720 may include a main memory, a disk storage device, or any suitable combination thereof. The memory / storage device 720 may include, but is not limited to, any type of volatile, non-volatile, or semi-volatile memory, such as, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), flash memory, solid-state memory, etc.

[0045] The communication resources 730 may include an interconnect or network interface controller, component, or other suitable device to communicate with one or more peripheral devices 704 or one or more databases 706 or other network elements via the network 708. For example, the communication resources 730 may include a wired communication component (e.g., for coupling via USB, Ethernet, etc.), a cellular communication component, a near field communication (NFC) component, a Bluetooth® (or Bluetooth® low energy) component, a Wi-Fi® component, and other communication components.

[0046] The instructions 750 may include software, a program, an application, an applet, an application, or other executable code for causing at least any one of the processors 710 to perform any one or more of the methods discussed herein. The instructions 750 may reside in whole or in part in at least one of the processors 710 (e.g., in a cache of the processor), the memory / storage device 720, or any suitable combination thereof. In addition, any portion of the instructions 750 may be transmitted to the hardware resources 700 from any combination of the peripheral device 704 or the database 706. Therefore, the memory of the processor 710, the memory / storage device 720, the peripheral device 704, and the database 706 are examples of computer-readable and machine-readable media.

[0047] Some examples may be implemented using or as an article of manufacture or at least one computer-readable medium. The computer-readable medium may include a non-transitory storage medium to store logic. In some examples, the non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, and the like. In some examples, logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, processes, software interfaces, APIs, instruction sets, computing codes, computer codes, code segments, computer code segments, words, values, symbols, or any combination of these.

[0048] According to some examples, a computer-readable medium may include a non-transitory storage medium to store or maintain instructions that, when executed by a machine, a computing device, or a system, cause the machine, the computing device, or the system to perform methods and / or operations according to the described examples. The instructions may include any appropriate type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. The instructions may be implemented according to a predetermined computer language, manner, or syntax to instruct a machine, a computing device, or a system to perform a specific function. The instructions may be implemented using any appropriate high-level, low-level, object-oriented, visual, compiled, and / or interpreted programming language.

[0049] One or more aspects of at least one example may be implemented by representative instructions stored on at least one machine-readable medium representing various logic within the processor, which when read by a machine, computing device or system causes the machine, computing device or system to fabricate logic to perform the techniques described herein. Such representations, known as "IP cores", may be stored on a tangible machine-readable medium and provided to various customers or manufacturing facilities to load into fabrication machines that actually fabricate the logic or processor.

[0050] The appearance of the phrase "an example" or "an example" does not necessarily refer to the same example or embodiment. Any aspect described herein may be combined with any other aspect or similar aspect described herein, whether or not these aspects are described with respect to the same figure or element. The division, omission or inclusion of block functions depicted in the figures does not infer that the hardware components, circuits, software and / or elements used to implement these functions will necessarily be divided, omitted or included in the embodiments.

[0051] Some examples may be described using the expressions "coupled" and "connected," and their derivatives. These terms are not necessarily intended to be synonymous with each other. For example, descriptions using the terms "connected" and / or "coupled" may indicate that two or more elements are in direct physical or electrical contact with each other. However, the term "coupled" may also refer to two or more elements that are not in direct contact with each other, but still cooperate or interact with each other.

[0052] The terms "first", "second" and the like do not represent any order, quantity or importance in this article, but are used to distinguish one element from another element. The term "one" herein does not represent a limitation on quantity, but rather represents the presence of at least one item mentioned. The term "assertion" used when referring to a signal herein refers to a state of the signal, in which the signal is valid, and the state can be achieved by applying any logic level (whether logic 0 or logic 1) to the signal. The term "subsequently" or "afterwards" may refer to immediately following or following some or some other event. According to alternative embodiments, other step sequences may also be performed. In addition, depending on the specific application, additional steps may be added or removed. Any combination of variations may be used, and those of ordinary skill in the art who benefit from the present disclosure will understand its many variations, modifications and alternative embodiments.

[0053] Unless specifically stated otherwise, disjunctive language such as the phrase "at least one of X, Y, or Z" is understood within the context to be generally used to state that an item, term, etc. can be X, Y, or Z, or any combination thereof (e.g., X, Y, and / or Z). Thus, such disjunctive language is generally not intended to, and should not, imply that certain embodiments require the presence of each of at least one X, at least one Y, or at least one Z. Furthermore, unless specifically stated otherwise, conjunctive language such as the phrase "at least one of X, Y, and Z" should also be understood to refer to X, Y, Z, or any combination thereof, including "X, Y, and / or Z."

Claims

1. A method for accelerating critical path instructions in a RISC-V processor, comprising: Perform critical path analysis on the program using the profile guided optimization (PGO) tool to identify critical path instructions; Recompiling the identified critical path instruction into a custom critical instruction with critical hint information using a compiler tool, wherein an opcode of the custom critical instruction is an opcode reserved for custom instructions by the RISC-V instruction set architecture, and wherein the opcode is used to indicate that the instruction is a critical instruction of a specific type; and The RISC-V processor implements accelerated execution of the custom key instruction based on the opcode and / or critical prompt information of the custom key instruction.

2. The method according to claim 1, wherein: The different opcodes reserved by the RISC-V instruction set architecture for custom instructions are used to compile different types of custom key instructions.

3. The method according to claim 1, wherein: Using the PGO tool to perform critical path analysis on a program to identify critical path instructions includes: Identifying a critical path and key events on the critical path based on the event dependency graph; and A critical path instruction that generates the critical event is determined based on the identified critical event.

4. The method according to claim 1, wherein: The Funct3 field of the custom key instruction is used to indicate the key prompt information.

5. The method according to any one of claims 1 to 4, wherein: The custom critical instruction is a custom critical branch instruction.

6. The method according to claim 5, wherein: The key prompt information of the custom key branch instruction is used to indicate that the instruction is one of the following items: General instructions; Key instructions for stable jumps; Critical instructions that are stable and do not jump; or Jump to unstable critical instructions.

7. The method according to any one of claims 1 to 4, wherein: The custom critical instruction is any one of the following: a custom load critical instruction, a custom multiply-add critical instruction, or a custom multiply-subtract critical instruction.

8. The method according to claim 7, wherein the key prompt information of the custom key instruction is used to indicate that the instruction is one of the following items: a standing order; or Key instructions.

9. The method according to any one of claims 1 to 4, wherein: Implementing accelerated execution of the custom key instruction by the RISC-V processor based on the opcode and / or critical prompt information of the custom key instruction includes: Predicting, by a prediction component of the RISC-V processor, a control flow and / or a data flow of the custom key instruction based on an opcode and / or critical hint information of the custom key instruction; and The buffer component and / or computing component of the RISC-V processor preferentially prepares corresponding hardware resources for the custom key instructions.

10. An apparatus for accelerating critical path instructions in a RISC-V processor, comprising means for performing the steps of the method according to any one of claims 1-9.

11. A computer-readable storage medium having executable codes stored thereon, wherein the instructions, when executed by a processing circuit, cause the processing circuit to perform the method according to any one of claims 1 to 9.

12. A computer program product comprising executable code, wherein the instructions, when executed by a processing circuit, cause the processing circuit to perform the method according to any one of claims 1 to 9.

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