Branch prediction method and apparatus, electronic device, storage medium and processor

Abstract

Embodiments of the present disclosure provide a branch prediction method and device, electronic equipment, storage medium and processor. The branch prediction method comprises: obtaining address information of a target instruction to be predicted; querying whether the address information of the target instruction to be predicted hits a branch target buffer; and in response to the address information of the target instruction to be predicted hitting a first entry of the branch target buffer, updating a low address part of the address information of the target instruction to be predicted with a target prediction address in the first entry to obtain an updated target prediction address. The branch prediction method saves more timing resources by reducing the number of fan-outs of the branch target buffer at the hardware level, thereby expanding the capacity of the branch target buffer and enabling the branch target buffer to be compatible with more branch types.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a branch prediction method and apparatus, an electronic device, a storage medium, and a processor. Background Art

[0002] The development trend of high-performance commercial processors is toward ever-faster clock frequencies and deeper pipelines. The requirement for branch prediction (BP) is to improve both accuracy and speed. For example, a multi-level branch target buffer (BTB) structure can be used to implement branch prediction. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a branch prediction method, which includes: obtaining address information of a target instruction to be predicted; querying whether the address information of the target instruction to be predicted hits a branch target buffer, wherein the branch target buffer includes multiple entries, each entry includes a first field and a second field, the first field is used to record an address tag, and the second field is used to record a target prediction address corresponding to the address tag; and in response to the address information of the target instruction to be predicted hitting the first entry of the branch target buffer, using the target prediction address in the first entry to update the low-order address portion of the address information of the target instruction to be predicted, so as to obtain an updated target address to be predicted, wherein the low-order address portion includes the lowest m bits of the address information of the target instruction to be predicted, where m is an integer greater than or equal to 1.

[0004] For example, the branch prediction method provided by at least one embodiment of the present disclosure further includes: in response to the address information of the target to-be-predicted instruction not hitting the branch target buffer, using the next sequential address of the target to-be-predicted instruction in the instruction sequence as the updated target to-be-predicted address.

[0005] For example, the branch prediction method provided by at least one embodiment of the present disclosure further includes: using the updated target address to be predicted to perform the next round of branch prediction operations.

[0006] For example, in the branch prediction method provided in at least one embodiment of the present disclosure, the address information includes an address identifier, which is the lowest n bits of the address information of the target instruction to be predicted, where n is an integer greater than or equal to 1, and each entry also includes a third field for recording the validity of the corresponding entry; and querying whether the address information of the target instruction to be predicted hits the branch target buffer, including: in response to the address identifier of the target instruction to be predicted matching the address tag in the first entry, and the first entry is in a valid state, determining that the address information of the target instruction to be predicted hits the first entry of the branch target buffer.

[0007] For example, in the branch prediction method provided by at least one of the embodiments of the present disclosure, the branch target buffer is shared by multiple threads of the multi-thread processor, the multiple threads at least include a first thread and a second thread, and before the address information of the target to-be-predicted instruction is acquired, the branch prediction method further includes: selecting a first to-be-predicted instruction corresponding to the first thread or a second to-be-predicted instruction corresponding to the second thread as the target to-be-predicted instruction.

[0008] For example, the branch prediction method provided by at least one of the embodiments of the present disclosure further includes: in response to selecting the first to-be-predicted instruction corresponding to the first thread as the target to-be-predicted instruction and the address information of the first to-be-predicted instruction hitting the first entry of the branch target buffer, updating a low address part of the address information of the first to-be-predicted instruction by using the target prediction address in the first entry to obtain an updated target to-be-predicted address corresponding to the first to-be-predicted instruction.

[0009] For example, the branch prediction method provided by at least one of the embodiments of the present disclosure further includes: selecting the updated target to-be-predicted address of the first to-be-predicted instruction or the address information of the second to-be-predicted instruction for a next round of branch prediction operation.

[0010] For example, in the branch prediction method provided by at least one of the embodiments of the present disclosure, the branch target buffer is a multi-level branch target buffer, the multi-level branch target buffer at least includes a first-level branch target buffer and a second-level branch target buffer, and the query of whether the address information of the target to-be-predicted instruction hits the branch target buffer includes: a query of whether the address information of the target to-be-predicted instruction hits the first-level branch target buffer and / or the second-level branch target buffer.

[0011] At least one of the embodiments of the present disclosure further provides a branch prediction device, which includes: an acquisition module configured to acquire address information of a target to-be-predicted instruction; a query module including a branch target buffer and configured to query whether the address information of the target to-be-predicted instruction hits the branch target buffer, wherein the branch target buffer includes multiple entries, each entry includes a first field and a second field, the first field is used to record an address tag, and the second field is used to record a target prediction address corresponding to the address tag; and an update module configured to, in response to the address information of the target to-be-predicted instruction hitting a first entry of the branch target buffer, update a low address part of the address information of the target to-be-predicted instruction by using the target prediction address in the first entry, so as to obtain an updated target to-be-predicted address, wherein the low address part includes the lowest m bits of the address information of the target to-be-predicted instruction, and m is an integer greater than or equal to 1.

[0012] For example, the branch prediction device provided by at least one embodiment of the present disclosure also includes a first multiplexer, which is coupled to the query module, the branch target buffer and the update module, and is configured to at least receive the next sequential address of the target instruction to be predicted in the instruction sequence, and read the target prediction address corresponding to the first entry hit during the query process from the branch target buffer; wherein, the query module is also configured to generate a first control signal in response to the address information of the target instruction to be predicted hitting the first entry of the branch target buffer, so as to control the first multiplexer to output the target prediction address in the first entry to the update module.

[0013] For example, in the branch prediction device provided by at least one embodiment of the present disclosure, the query module is also configured to generate a second control signal in response to the address information of the target instruction to be predicted not hitting the branch target buffer, so as to control the first multiplexer to output the next sequential address of the target instruction to be predicted in the instruction sequence to the update module.

[0014] For example, in the branch prediction device provided in at least one embodiment of the present disclosure, the branch target buffer is shared by multiple threads of a multi-threaded processor, the multiple threads include at least a first thread and a second thread, and the branch prediction device also includes a second multiplexer, which is configured to select a first to-be-predicted instruction corresponding to the first thread or a second to-be-predicted instruction corresponding to the second thread as the target to-be-predicted instruction.

[0015] At least one embodiment of the present disclosure also provides an electronic device, which includes at least one storage unit and at least one processing unit; wherein, at least one storage unit stores computer-readable instructions; at least one processing unit executes the computer-readable instructions stored in at least one storage unit to implement the branch prediction method provided in any of the above embodiments.

[0016] At least one embodiment of the present disclosure further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-readable instructions. When a processor executes the computer-readable instructions, the branch prediction method provided in any of the above embodiments is implemented.

[0017] At least one embodiment of the present disclosure further provides a processor, which includes the branch prediction device provided by any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0019] Figure 1A A flowchart of branch instruction jump prediction in a CPU pipeline;

[0020] Figure 1B A schematic diagram showing an exemplary method of using a three-level branch target buffer for branch prediction is shown;

[0021] Figure 2 A schematic diagram showing an exemplary branch prediction based on a zero-delay branch target buffer is shown;

[0022] Figure 3 A branch prediction method provided by at least one embodiment of the present disclosure is shown;

[0023] Figure 4 A schematic diagram illustrating branch prediction based on a zero-delay branch target buffer provided by at least one embodiment of the present disclosure is shown;

[0024] Figure 5 A schematic diagram illustrating a multi-threaded processor performing a branch prediction operation according to at least one embodiment of the present disclosure is shown;

[0025] Figure 6 A schematic block diagram of a branch prediction device provided by at least one embodiment of the present disclosure is shown; and

[0026] Figure 7 A schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0027] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0028] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0029] The processor cores (e.g., CPU cores) of single-core or multi-core processors use pipelining technology to improve instruction-level parallelism. The processor core internally includes multiple pipeline stages. For example, after the pipeline feeds program counters from various sources and the multiplexer (Mux) selects the next program counter (PC), the instruction corresponding to that PC undergoes branch prediction, instruction fetch, instruction decoding, instruction dispatch and renaming, instruction execution, and instruction retirement.

[0030] Branch prediction technology (BP technology) is a technology that predicts the branch jump instruction from the jump target location in advance. Based on the historical information of the instruction, it uses tools including but not limited to BTB (Branch Target Buffer) and TAGE (Tagged Geometric History Branch Predictor) for branch instruction prediction to predict the most likely jump location of the current branch instruction.

[0031] Figure 1A This is a flow chart of branch instruction jump prediction in a CPU pipeline. Figure 1AAs shown, the entire branch instruction jump prediction process is divided into the frontend and the backend. In the backend, a series of steps including instruction decoding, instruction caching, instruction distribution, instruction execution, and data write-back are performed in sequence, and information such as historical jump results of instructions is collected and sent to the branch prediction unit (BPU) in the frontend. The BPU predicts the most likely jump position of the current branch in advance based on the historical branch instruction jump information, and then sends the prediction result to the branch target queue (Fetch Target Queue, FTQ) in the backend for temporary storage. The prediction result is then sent to the instruction fetch unit (IFU). The IFU starts to fetch instructions from the memory or cache according to the predicted instruction fetch position in the branch target queue and passes them backward to avoid blocking of the CPU pipeline.

[0032] The function of the branch prediction unit (BPU) is to perform target address prediction for branch instructions, but there is a certain probability of prediction error; the branch target queue (FTQ) is a buffer queue between the BPU and the IFU, which is used to temporarily store the instruction fetch targets predicted by the branch prediction unit and send instruction fetch requests to the instruction fetch unit based on these instruction fetch targets; the instruction fetch unit (IFU) is used to read instruction data from memory or cache and pass it backward for operations such as decoding the read instructions.

[0033] As previously mentioned, the branch target buffer (BTB) may implement branch prediction using a multi-level branch target buffer structure.

[0034] Figure 1B A schematic diagram showing an exemplary implementation of a three-level branch target buffer for branch prediction is shown.

[0035] like Figure 1BAs shown, the three-level branch target buffer includes a zero-delay branch target buffer (ZBTB), a first-level branch target buffer (L1BTB), and a second-level branch target buffer (L2BTB). The capacity of the ZBTB is relatively small and is used to store branch instructions that appear more frequently and their corresponding target prediction addresses. The prediction delay of the ZBTB is 0 clock cycles, that is, the branch prediction operation can be completed in the current clock cycle. The capacity of the L1BTB is larger than that of the ZBTB, and the prediction delay of the L1BTB is generally 1 to 2 clock cycles. The capacity of the L2BTB is very large. For example, a static random access memory (SRAM) can generally be used, and the prediction delay of the L2BTB is generally 3 to 4 clock cycles. The L1BTB and L2BTB are generally used to store branch instructions that appear less frequently and their corresponding target prediction addresses. The "target prediction address" here is the address of the instruction corresponding to the branch process executed in the historical execution process of the branch instruction.

[0036] like Figure 1B As shown, when performing a branch prediction operation, the address information of the target instruction to be predicted (i.e., the branch instruction) is first input into the multi-level BTB, and the address information of the target instruction to be predicted is queried to see whether it hits the ZBTB, L1ZBTB, or L2BTB. When querying whether it hits the ZBTB, the "address information" can be the linear address of the target instruction to be predicted or at least part of the linear address. When querying whether it hits the L1ZBTB or L2BTB, the "address information" can be the hash value obtained by converting the linear address based on, for example, a hash algorithm ( Figure 1B If the address information hits the ZBTB, L1ZBTB or L2BTB, the corresponding target prediction address is read from the hit ZBTB, L1ZBTB or L2BTB (for example, Figure 1B The "ZBTB Target," "L1BTB Target," or "L2BTB Target" in the BTB is used to update the address information (e.g., linear address) of the target instruction to be predicted, obtaining an updated target address to be predicted. If no BTB level hits, the next sequential address of the target instruction to be predicted in the instruction sequence is used as the updated target address to be predicted. The updated target address to be predicted is used as input for the next round of branch prediction, and a query is performed to determine whether the updated target address to be predicted hits the multi-level BTB.

[0037] like Figure 1BAs shown, the query for whether the ZBTB hits can be completed within the current clock cycle, cycle 0, meaning the ZBTB prediction latency is 0 clock cycles. The branch prediction operation based on the L1BTB requires two clock cycles (cycle 0 to cycle 1). In cycle 0, the linear address of the branch instruction is converted into a hash value using a hash algorithm. In cycle 1, the hash value is used to query whether the L1ZBTB hits. This means the L1BTB prediction latency is 1 clock cycle. The branch prediction operation based on the L2BTB requires four clock cycles (cycle 0 to cycle 3). In cycles 0 to 1, the L1ZBTB hit is queried. If the L1ZBTB does not hit, the converted hash value is used to query whether the L2ZBTB hits in cycles 2 to 3. This means the L2BTB prediction latency is 3 clock cycles.

[0038] Figure 2 A schematic diagram of an exemplary branch prediction based on a zero-delay branch target buffer is shown.

[0039] like Figure 2As shown, the zero-delay branch target buffer (ZBTB) includes 16 entries (e.g., entry0 to entry15). When performing branch prediction on a target instruction to be predicted, the ZBTB is first checked based on the address identifier LA[21:0] of the target instruction to be predicted (the low-order address portion of the address information of the target instruction to be predicted). If the address identifier LA[21:0] hits entry 1 and entry 1 is valid, that is, the address identifier LA[21:0] is equal to the address tag Tag1 of entry 1, and the field Val of entry 1 indicates valid, then the ZBTB outputs the target predicted address Tgt1[19:0] recorded in entry 1 (recorded in the field Target1 of entry 1) and generates a control signal ZCorrect to control the output operation of the multiplexer MUX. In order to achieve the zero-latency feature of the ZBTB, the ZBTB cannot store the complete target prediction address. That is, the target prediction address recorded in the field Target1 of entry 1 is a portion of the complete target prediction address (e.g., Tgt1[63:0]), such as the low-order address portion Tgt1[19:0]. Therefore, after the ZBTB outputs Tgt1[19:0], the high-order address portion (e.g., LA[63:20]) of the address information of the target instruction to be predicted is used to concatenate with Tgt1[19:0] to obtain the complete target prediction address Tgt[63:0] (i.e., the updated target prediction address) and provide it to the multiplexer MUX. Based on the received control signal ZCorrect, the multiplexer MUX selects to output Tgt[63:0] to register 201 to update the address information of the target instruction to be predicted stored in register 201.

[0040] like Figure 2As shown, the multiplexer MUX also receives predicted addresses RedirectTgt[63:0], L2Tgt[63:0], L1Tgt[63:0], and SeqTgt[63:0]. RedirectTgt[63:0] is the redirect address, that is, the actual target address to which the instruction needs to be redirected when a branch prediction error is detected during the execution phase. L2Tgt[63:0] and L2Tgt[63:0] represent the target predicted addresses output by the first-level branch target buffer (L1BTB) and the second-level branch target buffer (L2BTB), respectively. SeqTgt[63:0] represents the next sequential address of the target predicted instruction in the instruction sequence. The predicted addresses RedirectTgt[63:0], L2Tgt[63:0], L1Tgt[63:0], and SeqTgt[63:0] correspond one-to-one to the control signals Redirect, L2Correct, L1Correct, and SeqCorrect. The control signals (Redirect, L2Correct, L1Correct, ZCorrect, and SeqCorrect) jointly control the output operation of the multiplexer MUX, and the priorities of these control signals from high to low are Redirect, L2Correct, L1Correct, ZCorrect, and SeqCorrect.

[0041] like Figure 2 As shown, since the address information of the target instruction to be predicted includes 64-bit data, for example, register 201 includes 64 D flip-flops (DFFs), each DFF stores 1 bit of address information, when using Tgt[63:0] to update the address information in register 201, 64 D flip-flops need to be updated in sequence, and the fan-out number of ZBTB at the hardware level (i.e., the number of DFFs to be driven by ZBTB) is 64.

[0042] The inventors of this disclosure noted that to achieve the zero-latency feature of the ZBTB, the number of entries in the ZBTB is relatively small and limited by the frequency of the processor's internal clock signal. In other words, increasing the number of entries in the ZBTB increases the complexity of the sequential logic, making it impossible for the ZBTB to perform branch prediction within a single clock cycle. Consequently, the current ZBTB has a small capacity and cannot accommodate all branch types, processing only simpler branch types.

[0043] One or more embodiments of the present disclosure provide a branch prediction method and apparatus, an electronic device, a computer-readable storage medium, and a processor.

[0044] The branch prediction method includes: obtaining address information of a target instruction to be predicted; querying whether the address information of the target instruction to be predicted hits a branch target buffer, wherein the branch target buffer includes multiple entries, each entry includes a first field and a second field, the first field is used to record an address tag, and the second field is used to record a target prediction address corresponding to the address tag; and in response to the address information of the target instruction to be predicted hitting the first entry of the branch target buffer, using the target prediction address in the first entry to update the low-order address portion of the address information of the target instruction to be predicted, so as to obtain an updated target address to be predicted, wherein the low-order address portion includes the lowest m bits of the address information of the target instruction to be predicted, where m is an integer greater than or equal to 1.

[0045] This branch prediction method directly uses the target prediction address to update the low-order address part of the address information of the target instruction to be predicted. That is, by reducing the fanout number of the branch target buffer at the hardware level (that is, the number of storage devices to be driven by the branch target buffer), more timing resources can be saved. The saved timing resources can be used to expand the capacity of the branch target buffer, so that the branch target buffer can be compatible with more branch types.

[0046] The present disclosure is described below using several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numeral in each drawing.

[0047] Some embodiments and examples of the present disclosure are described in detail below with reference to the accompanying drawings.

[0048] Figure 3 The branch prediction method provided by at least one embodiment of the present disclosure includes steps S301 to S303.

[0049] Step S301: Obtain address information of a target instruction to be predicted.

[0050] Step S302: Query whether the address information of the target to-be-predicted instruction hits the branch target buffer.

[0051] Step S303: In response to the address information of the target to-be-predicted instruction hitting the first entry of the branch target buffer, the target predicted address in the first entry is used to update the low-order address portion of the address information of the target to-be-predicted instruction to obtain an updated target to-be-predicted address.

[0052] For example, the target instruction to be predicted may be a branch instruction. The address information may be a linear address of the target instruction to be predicted (e.g., "LA[63:0]" indicating that the address information has 64 bits), or a hash value obtained by converting the linear address based on, for example, a hash algorithm, and the present disclosure does not impose any restrictions on this.

[0053] For example, the low-order address portion of the address information includes the lowest m bits of the address information of the target instruction to be predicted, where m is an integer greater than or equal to 1. For example, the low-order address portion of the address information can be recorded as "LA[m-1:0]".

[0054] It should be noted that the branch target buffer in at least one embodiment of the present disclosure is a branch target buffer with a zero-delay characteristic, or is a multi-level branch target buffer including a zero-delay branch target buffer (ZBTB). For example, the branch target buffer includes at least a first-level branch target buffer and a second-level branch target buffer, wherein the first-level branch target buffer is a branch target buffer with a zero-delay characteristic (e.g., a ZBTB).

[0055] For example, the branch target buffer includes multiple entries, each entry includes a first field and a second field, the first field is used to record an address tag, and the second field is used to record a target prediction address corresponding to the address tag. Here, the address tag (Tag) is used to identify each entry to ensure that the entry hit by the address information of the target to-be-predicted instruction can be accurately found when retrieving (or querying) the branch target buffer, thereby improving the accuracy and performance of branch prediction. The target prediction address refers to the address of the next instruction to which the program jumps when executing the target to-be-predicted instruction in the historical execution process of the target to-be-predicted instruction, that is, the prediction result obtained by performing branch prediction on the target to-be-predicted instruction.

[0056] For example, each entry may also include a third field (e.g., "Val") to record the validity of the corresponding entry. That is, the third field is used to record whether the data in the corresponding entry is valid data, so that corresponding access control can be performed based on the validity of the entry. For example, Val = 1 indicates that the entry is valid, and Val = 0 indicates that the entry is invalid.

[0057] For the branch target buffer with zero latency characteristic, the branch target buffer cannot save the complete target prediction address, and also cannot compare the address tag in the entry and the address information of the target predicted instruction completely (i.e., compare each data in the address tag and the address information), otherwise the storage requirement and access delay will be increased. Therefore, the target prediction address recorded in the second field is the low address part of the complete target prediction address, and directly updates (or replaces) the low address part of the address information of the target predicted instruction in the subsequent process. The number of bits of the low address part of the complete target prediction address (e.g., Tgt[m-1:0]) is equal to the number of bits of the low address part of the address information (e.g., LA[m-1:0]), and m is an integer greater than or equal to 1.

[0058] For example, when performing the above step S302 (querying whether the address information of the target predicted instruction hits the branch target buffer with zero latency characteristic), it can be realized by comparing the address identification in the address information and the address tag of each entry. Here, the address identification is the lowest n bits of the address information of the target predicted instruction, and n is an integer greater than or equal to 1. For example, the address identification can be the lowest 22 bits of the address information, which can be denoted as "LA[21:0]".

[0059] For example, the above step S302 can include: in response to the address identification of the target predicted instruction matching the address tag in the first entry, and the first entry being in the valid state, determining that the address information of the target predicted instruction hits the first entry of the branch target buffer.

[0060] For example, in response to the address identification of the target predicted instruction being equal to the address tag in the first entry, and the third field Val of the first entry being equal to 1 (indicating that the first entry is valid), it indicates that the address information of the target predicted instruction hits the first entry of the branch target buffer.

[0061] For example, in the case that the branch target buffer is a multi-level branch target buffer (i.e., including a first-level branch target buffer and a second-level branch target buffer), the above step S302 can include: querying whether the address information of the target predicted instruction hits the first-level branch target buffer and / or the second-level branch target buffer. The first-level branch target buffer can be a ZBTB, and the second-level branch target buffer can be a L1ZBTB. The address information of the target predicted instruction can hit the ZBTB, hit the L1BTB, or hit both the ZBTB and the L1BTB. When hitting the ZBTB or the L1BTB, the subsequent operation can refer to the description of the foregoing Figure 1B , which will not be described here. The following describes the case that the address information of the target predicted instruction hits both the ZBTB and the L1BTB through an example.

[0062] In an example, the predicted latency of the ZBTB is 0 clock cycles, the predicted latency of the L1BTB is 1 clock cycle, hitting the ZBTB is determined in clock cycle cycle0, and hitting the L1BTB is determined in clock cycle cycle1 next to clock cycle cycle0.

[0063] In clock cycle cycle0, it is determined that the address information LA[63:0] of the target instruction to be predicted hits entry0 of the ZBTB, for example, and the target prediction address Tgt0[19:0] recorded in entry0 is used to update the low-order address part of the address information LA[63:0] (for example, LA[19:0]) to obtain the updated target address to be predicted (recorded as "LA_0[63:0]"). In the next clock cycle cycle1 of the clock cycle0, it is determined that the address information LA[63:0] of the target instruction to be predicted hits the entry 1 of the L1BTB. If the target predicted address Tgt1[19:0] recorded in the entry 1 is equal to Tgt0[19:0], the low-order address part (for example, LA_0[19:0]) of LA_0[63:0] obtained in cycle0 is not updated; if Tgt1[19:0] is not equal to Tgt0[19:0], Tgt1[19:0] is used to update the low-order address part LA_0[63:0] LA_0[19:0] to obtain a new updated target address to be predicted (recorded as "LA_1[63:0]").

[0064] It should be noted that in clock cycle 1, when querying whether the target to-be-predicted instruction address LA[63:0] hits the L1BTB, the updated target to-be-predicted address LA_0[63:0] is also queried to see if it hits the ZBTB. If it is determined that LA[63:0] hits the L1BTB and Tgt1[19:0] is not equal to Tgt0[19:0], the query result of whether LA_0[63:0] hits the ZBTB in clock cycle 1 is flushed.

[0065] The branch prediction method provided by at least one embodiment of the present disclosure may further include step S304.

[0066] Step S304: In response to the address information of the target to-be-predicted instruction not hitting the branch target buffer, the next sequential address of the target to-be-predicted instruction in the instruction sequence is used as an updated target to-be-predicted address.

[0067] For example, when the branch target buffer is a multi-level branch target buffer, the above-mentioned step S304 may include: in response to the address information of the target to-be-predicted instruction not hitting the branch target buffers at each level in the multi-level branch target buffer, using the next sequential address of the target to-be-predicted instruction in the instruction sequence as the updated target to-be-predicted address.

[0068] At least one embodiment of the present disclosure provides a branch prediction method further comprising step S305:

[0069] Step S305: Use the updated target address to be predicted to perform the next round of branch prediction operation.

[0070] Figure 4 A schematic diagram of branch prediction based on a zero-delay branch target buffer provided by at least one embodiment of the present disclosure is shown.

[0071] Figure 4 The zero-delay branch target buffer ZBTB shown includes 16 entries (for example, denoted as "entry0 to entry15"), and the output of the ZBTB is directly coupled to an input of the multiplexer. Assuming that the address information of the target instruction to be predicted is 64 bits (denoted as "LA[63:0]"), the register 401 is used to store the address information LA[63:0] of the target instruction to be predicted, and the register 401 includes 64 D flip-flops (DFFs), and each DFF stores 1 bit of address information. The structure and function of the multiplexer MUX, as well as other predicted addresses (such as RedirectTgt[63:0], L2Tgt[63:0], L1Tgt[63:0] and SeqTgt[63:0]) and control signals (such as ZCorrect, etc.) received by the multiplexer MUX can refer to the above description. Figure 2 The description is not repeated here.

[0072] like Figure 4As shown, when performing branch prediction based on the zero-delay branch target buffer, the address information LA[63:0] of the target instruction to be predicted is first obtained from register 401. Then, based on the address identifier LA[21:0] included in the address information LA[63:0], a query is made to determine whether the address information of the target instruction to be predicted hits the branch target buffer. For example, the address tags Tag0 to Tag15 of all entries in the ZBTB are traversed to determine whether there is an address tag that matches (i.e., is equal to) the address identifier LA[21:0]. In response to the fact that the address tag Tag1 matches the address identifier LA[21:0] and the entry entry1 corresponding to the address tag Tag1 is in a valid state, it is determined that the address information LA[63:0] of the target instruction to be predicted hits the entry entry1 in the ZBTB. Then, the ZBTB outputs the target prediction address (e.g., Tgt[19:0]) recorded in the field Target1 of the entry entry1 to the multiplexer MUX, and the ZBTB generates a control signal ZCorrect. The control signal ZCorrect controls the multiplexer MUX to provide the received target prediction address Tgt[19:0] to the corresponding 20 D flip-flops in the register 401 to update the lowest 20 bits of the address information LA[63:0] (i.e., LA[19:0]), thereby obtaining an updated target to-be-predicted address (e.g., "LA_0[63:0]"). The instruction corresponding to the updated target to-be-predicted address LA_0[63:0] serves as the target to-be-predicted instruction for the next round of branch prefetch operations. The updated target to-be-predicted address LA_0[63:0] is used as the address information for the next round of branch prefetch operations. The lowest 22 bits of the updated target to-be-predicted address LA_0[63:0] serve as the address identifier (i.e., LA_0[21:0]) to query whether the ZBTB is hit.

[0073] At least one embodiment of the present disclosure provides a branch prediction method that omits the address splicing operation (see Figure 2 ), directly use the target predicted address Tgt[19:0] to update the lowest 20 bits of the address information LA[63:0] (i.e. LA[19:0]), that is, it is necessary to update the 20 D flip-flops corresponding to the lowest 20 bits of LA[63:0] in sequence. The fan-out number of ZBTB at the hardware level (i.e., the number of D flip-flops to be driven by ZBTB) is 20, which is less than Figure 2 The fan-out number of the ZBTB shown at the hardware level is 64, which reduces the timing resources required to update the address information of the target to-be-predicted instruction (or update register 401). The saved timing resources can then be used to expand the capacity of the branch target buffer, making the branch target buffer compatible with more branch types.

[0074] In the branch prediction method provided in at least one embodiment of the present disclosure, a branch target buffer can be shared by multiple threads of a multi-threaded processor, where the multiple threads include at least a first thread and a second thread. The multi-threaded processor allows multiple threads to execute concurrently at the same time, so each thread has its own instruction sequence and state information (including address information).

[0075] For example, the branch prediction method provided in at least one embodiment of the present disclosure further includes: before obtaining the address information of the target instruction to be predicted, selecting a first instruction to be predicted corresponding to the first thread or a second instruction to be predicted corresponding to the second thread as the target instruction to be predicted. This branch prediction method maximizes hardware resource utilization and reduces hardware complexity and cost by enabling multiple threads in a multi-threaded processor to share the same branch target buffer.

[0076] For example, before obtaining the address information of the target instruction to be predicted, a thread to be scheduled is first determined from multiple threads. For example, the thread to be scheduled can be determined based on the arbitration result of a thread arbiter, or a thread arbitration policy can be set as needed to determine the thread to be scheduled. This is not limited in this disclosure. After the thread to be scheduled is determined, the instruction to be predicted corresponding to the thread to be scheduled is used as the target instruction to be predicted. The remaining branch prediction process can refer to steps S301 to S305 above and will not be repeated here.

[0077] For example, the branch prediction method provided by at least one embodiment of the present disclosure also includes: in response to selecting the first to-be-predicted instruction corresponding to the first thread as the target to-be-predicted instruction (that is, the thread to be scheduled is the first thread), and the address information of the first to-be-predicted instruction hits the first entry of the branch target buffer, using the target prediction address in the first entry to update the low-order address part of the address information of the first to-be-predicted instruction to obtain an updated target to-be-predicted address corresponding to the first to-be-predicted instruction.

[0078] For example, the branch prediction method provided in at least one embodiment of the present disclosure further includes: selecting to use the updated target address to be predicted of the first instruction to be predicted or the address information of the second instruction to be predicted for the next round of branch prediction operations. Before performing the next round of branch prediction operations, it is necessary to first determine the thread for which the next round of branch prediction operations are to be performed, that is, to redetermine the thread to be scheduled from the multiple threads.

[0079] For example, Figure 5 A schematic diagram illustrating a multi-threaded processor performing a branch prediction operation according to at least one embodiment of the present disclosure is shown.

[0080] exist Figure 5In the example shown, the address information of the target instruction to be predicted is 64 bits, which can be recorded as "LA[63:0]". The first thread T1 and the second thread T2 of the multi-threaded processor share the same branch target buffer. The branch target buffer is a three-level branch target buffer, including a zero-delay branch target buffer (recorded as "ZBTB"), a first-level branch target buffer (recorded as "L1BTB", Figure 5 Not shown) and the second level branch target buffer (denoted as "L2BTB" Figure 5 (Not shown). The capacity of L1BTB and L2BTB is large. The entries in L1BTB and L2BTB can record the complete target prediction address (i.e., 64-bit target prediction address). The target prediction addresses output by L1BTB and L2BTB are recorded as "L1Tgt[63:0]" and "L2Tgt[63:0]" respectively. In addition, Figure 5 The structure and function of the ZBTB, the predicted address RedirectTgt[63:0], the sequential address SeqTgt[63:0], the control signals (Redirect, L2Correct, L1Correct, ZCorrect and SeqCorrect), the priority of the control signals, etc. can be referred to above. Figure 2 The description is not repeated here.

[0081] For example, the multiplexer Thread_MUX is configured to determine the threads to be scheduled from the first thread T1 and the second thread T2 according to the thread arbitration result. The thread arbitration result can be obtained directly from the thread arbitrator or based on a preset thread arbitration strategy. The multiplexer T1_MUX and register 501 are used for the first thread T1, and the multiplexer T2_MUX and register 502 are used for the second thread T2. The multiplexers T1_MUX and T2_MUX can refer to Figure 4 The structure and function of the multiplexer MUX, register 501 and register 502 can be referred to Figure 4 The register 401 in will not be described in detail here.

[0082] For example, register 503 includes 64 D flip-flops (DDF_0 to DFF_63), and register 503 is used to store the address information Pred_LA[63:0] of the target predicted instruction corresponding to the thread to be scheduled. The address information Pred_LA[63:0] in register 503 can be directly used for the next round of branch prediction operations.

[0083] For example, during the a-th round of branch prediction operations (a is an integer greater than or equal to 1), the address identifier Pred[21:0] of the address information Pred_LA[63:0] in register 503 is first input into the ZBTB to query whether the address information Pred_LA[63:0] hits the ZBTB. In response to the address identifier Pred[21:0] being equal to the address tag Tag1 and the entry entry1 corresponding to the address tag Tag1 being in a valid state, it is determined that the address information Pred_LA[63:0] hits the ZBTB, and the ZBTB generates a control signal ZCorrect and provides it to the multiplexer T1_MUX. Because the first thread T1 has been determined as the thread to be scheduled based on the thread arbitration result before the a-th round of branch prediction operations, that is, in the previous round of branch prediction operations, the ZBTB provides the target predicted address Tgt[19:0] recorded in the entry entry1 to the input of the multiplexer T1_MUX. Then, the multiplexer T1_MUX provides the target prediction address T1_Tgt[19:0] to the register 501 and the input terminal of the multiplexer Thread_MUX based on the control signal ZCorrect. Here, the target prediction address T1_Tgt[19:0] output by the multiplexer T1_MUX is the same as the target prediction address Tgt[19:0] received by the multiplexer T1_MUX, and "T1_Tgt[19:0]" is only used to distinguish "T2_Tgt[19:0]" output by the multiplexer T2_MUX.

[0084] Specifically, the multiplexer T1_MUX provides the target prediction address T1_Tgt[19:0] to the corresponding 20 D flip-flops (e.g., DDF_0 to DFF_19) in register 501. Under the control of the timing logic, the 20 bits of the target prediction address T1_Tgt[19:0] are sequentially written into the corresponding D flip-flops in register 501 to obtain the updated target prediction address T1_LA[63:0] corresponding to the first thread T1. For example, the least significant bit of T1_Tgt[19:0] is written into D flip-flop DDF_0 in register 501. After the multiplexer Thread_MUX receives the target prediction address T1_Tgt[19:0], in response to the second thread T2 being the thread corresponding to the (a+1)th round of branch prediction operation, the multiplexer Thread_MUX selects T2_Tgt[19:0] from the target prediction addresses T1_Tgt[19:0] and T2_Tgt[19:0] and outputs T2_Tgt[19:0] to register 503 to update the corresponding 20 D flip-flops of register 503 to obtain the updated target predicted address Pred_LA_(a+1)[63:0].

[0085] It should be noted that the target predicted address T2_Tgt[19:0] is obtained before the a-th round of branch prediction operations, for example, when the address information of the target to-be-predicted instruction corresponding to the second thread T2 hits the ZBTB during the (a-3)-th round of branch prediction operations. The method for updating register 503 can be referred to the description of updating register 501 above and will not be repeated here.

[0086] Continuing with the above example, during the (a+1)th round of branch prediction operation, the address identifier Pred_LA_(a+1)[21:0] of the updated target to-be-predicted address Pred_LA_(a+1)[63:0] in register 503 is input into the ZBTB to query whether Pred_LA_(a+1)[63:0] hits the ZBTB. If the entry 15 of the ZBTB is hit, since the second thread T2 is the thread corresponding to the (a+1)th round of branch prediction operation, the target prediction address recorded in the field Target15 in the entry 15 is provided to the multiplexer T2_MUX (e.g., Figure 5 The remaining branch prediction round (a+1) (e.g., operations of multiplexer T2_MUX, multiplexer Thread_MUX, and registers 502 and 503) can be referred to the above description of the branch prediction round a, and will not be repeated here.

[0087] like Figure 5 As shown, for a branch target buffer supporting a two-thread microarchitecture, when the branch prediction method provided by the embodiment of the present disclosure is adopted, the fan-out number of the ZBTB in the branch target buffer at the hardware level is 60 (3×20), that is, the ZBTB needs to drive 20 D flip-flops in register 501, 20 D flip-flops in register 502, and 20 D flip-flops in register 501. Accordingly, when the branch prediction method provided by the embodiment of the present disclosure is adopted and the number of bits of the target prediction address recorded by the entry in the ZBTB is 20 bits, the fan-out number of the ZBTB in the branch target buffer supporting a four-thread microarchitecture at the hardware level is 100, and the fan-out number of the ZBTB in the branch target buffer supporting an N-thread microarchitecture at the hardware level is (N+1)×20.

[0088] If adopted Figure 2The branch prediction method shown in the figure supports a ZBTB fan-out number of 192 (3×64) at the hardware level for a branch target buffer in a two-thread microarchitecture, and a ZBTB fan-out number of 320 (5×64) at the hardware level for a branch target buffer in a four-thread microarchitecture. Therefore, for a multi-threaded processor using the branch prediction method provided by the embodiment of the present disclosure, the more threads there are, the greater the reduction in the fan-out number of the ZBTB at the hardware level, and the more timing resources are saved.

[0089] With the branch prediction method according to at least one embodiment of the present disclosure (such as Figure 3 Correspondingly, at least one embodiment of the present disclosure further provides a branch prediction device.

[0090] The branch prediction device provided in the embodiments of the present disclosure can execute the branch prediction method provided in any embodiment of the present disclosure, and has the corresponding functional modules and beneficial effects of the execution method.

[0091] For example, Figure 6 A schematic block diagram of a branch prediction device provided by at least one embodiment of the present disclosure is shown.

[0092] like Figure 6 As shown, the branch prediction device 600 includes an acquisition module 610, a query module 620 and an update module 630. The acquisition module 610 is configured to acquire the address information of the target instruction to be predicted. The query module 620 includes a branch target buffer 621 and is configured to query whether the address information of the target instruction to be predicted hits the branch target buffer 621. The branch target buffer 621 includes a plurality of entries, each entry includes a first field and a second field, the first field is used to record the address tag, and the second field is used to record the target predicted address corresponding to the address tag. The update module 630 is configured to update the low-order address portion of the address information of the target instruction to be predicted using the target predicted address in the first entry in response to the address information of the target instruction to be predicted hitting the first entry of the branch target buffer 621, so as to obtain the updated target address to be predicted. The low-order address portion includes the lowest m bits of the address information of the target instruction to be predicted, where m is an integer greater than or equal to 1.

[0093] For example, the branch prediction apparatus 600 is further configured to use the updated target to-be-predicted address to perform the next round of branch prediction operations.

[0094] For example, the branch prediction device 600 further includes a first multiplexer ( Figure 6 Not shown, please refer to Figure 5The first multiplexer is coupled to the branch target buffer 621 and the update module 630 in the query module 620. The first multiplexer is configured to receive at least the next sequential address of the target instruction to be predicted in the instruction sequence and read the target predicted address corresponding to the first entry hit during the query from the branch target buffer 621. The query module 620 is further configured to, in response to the address information of the target instruction to be predicted hitting the first entry in the branch target buffer 621, generate a first control signal to control the first multiplexer to output the target predicted address in the first entry to the update module 630.

[0095] For example, the query module 620 is also configured to generate a second control signal (such as SeqCorrect above) in response to the address information of the target to-be-predicted instruction not hitting the branch target buffer 621, so as to control the multiplexer to output the next sequential address of the target to-be-predicted instruction in the instruction sequence to the update module 630.

[0096] For example, the branch target buffer 621 in the branch prediction device 600 may be shared by multiple threads of a multi-threaded processor, where the multiple threads include at least a first thread and a second thread. The branch prediction device 600 further includes a second multiplexer ( Figure 6 Not shown, please refer to Figure 5 The second multiplexer is configured to select a first to-be-predicted instruction corresponding to the first thread or a second to-be-predicted instruction corresponding to the second thread as a target to-be-predicted instruction.

[0097] For example, the update module 630 is configured to, in response to selecting the first to-be-predicted instruction corresponding to the first thread as the target to-be-predicted instruction and the address information of the first to-be-predicted instruction hitting the first entry of the branch target buffer 621, use the target predicted address in the first entry to update the low-order address part of the address information of the first to-be-predicted instruction to obtain an updated target to-be-predicted address corresponding to the first to-be-predicted instruction.

[0098] For example, the branch prediction apparatus 600 is further configured to selectively use the updated target to-be-predicted address of the first to-be-predicted instruction or the address information of the second to-be-predicted instruction to perform the next round of branch prediction operations.

[0099] For example, the branch target buffer 621 is a multi-level branch target buffer, which includes at least a first-level branch target buffer and a second-level branch target buffer. The query module 620 is configured to query whether the address information of the target instruction to be predicted hits the first-level branch target buffer and / or the second-level branch target buffer.

[0100] It is worth noting that the various units and modules included in the above-mentioned branch prediction device are only divided according to functional logic, but are not limited to the above-mentioned division, as long as the corresponding functions can be achieved; in addition, the specific names of the functional units are only for the convenience of distinguishing each other, and are not used to limit the protection scope of the embodiments of the present disclosure.

[0101] At least one embodiment of the present disclosure further provides an electronic device. The electronic device includes at least one storage unit and at least one processing unit. The at least one storage unit stores computer-readable instructions. The at least one processing unit executes the computer-readable instructions stored in the at least one storage unit to implement the branch prediction method provided in any embodiment of the present disclosure. The processing unit can be any circuit unit with instruction execution capability, such as a microcontroller, and the embodiments of the present disclosure are not limited thereto.

[0102] The electronic device provided by the embodiment of the present disclosure and the branch prediction method provided by the above embodiment belong to the same inventive concept. For technical details not fully described in this embodiment, please refer to the embodiments related to the above branch prediction method, and this embodiment has the same beneficial effects as the above embodiment.

[0103] At least one embodiment of the present disclosure further provides a processor (CPU), the processor including an instruction processing pipeline, the pipeline including a branch predictor, the branch predictor including a branch prediction device according to any of the above embodiments. For example, the pipeline of the processor also includes a value acquisition unit, a decoding unit, an execution unit, etc., which is not limited by the embodiments of the present disclosure. For example, the processor can be a single-core processor or a multi-core processor, and can be based on, for example, an X86 microarchitecture, an ARM microarchitecture, a RISC-V microarchitecture, etc., which is not limited by the embodiments of the present disclosure.

[0104] At least one embodiment of the present disclosure further provides a computer-readable storage medium having computer-readable instructions stored therein, which, when executed by a processor, implements the branch prediction method provided in any embodiment of the present disclosure.

[0105] For example, the computer-readable storage medium may include a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a compact disc read-only memory (CD-ROM), a flash memory, or any combination of the foregoing computer-readable storage media, or other applicable storage media.

[0106] At least some embodiments of the present disclosure further provide an electronic device, which includes the processor provided by any of the above embodiments. Figure 7A schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0107] The electronic devices in the embodiments of the present disclosure can be implemented as but not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., as well as fixed terminals such as digital TVs, desktop computers, etc.

[0108] Figure 7 The electronic device 700 shown is merely an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0109] For example, Figure 7 As shown, in some examples, the electronic device 700 includes a processor 701, which may include the processor of any of the above-mentioned embodiments, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 702 or the program loaded from the storage device 708 into the random access memory (RAM) 703. Various programs and data required for the operation of the computer system are also stored in the RAM 703. The processor 701, ROM 702, and RAM 703 are connected to each other via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0110] For example, the following components can be connected to the I / O interface 705: an input device 706 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 707 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 708 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 709 which can also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 709 can allow the electronic device 700 to communicate with other devices wirelessly or by wire to exchange data, and perform communication processing via a network such as the Internet. The drive 710 is also connected to the I / O interface 705 as needed. Removable media 711, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 710 as needed so that the computer program read therefrom can be installed into the storage device 708 as needed. Although Figure 7 The electronic device 700 is shown as including various devices, but it should be understood that it is not required to implement or include all of the devices shown. More or fewer devices may be implemented or included instead.

[0111] For example, the electronic device 700 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 709 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communications may use any of a variety of communication standards, protocols, and technologies, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0112] At least one embodiment of the present disclosure further provides a processor, which includes the branch prediction device provided by any embodiment of the present disclosure.

[0113] In addition to the above exemplary explanations, the following points should be explained:

[0114] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0115] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0116] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.

Claims

1. A branch prediction method, comprising: Obtain the address information of the target instruction to be predicted; querying whether the address information of the target to-be-predicted instruction hits a branch target buffer, wherein the branch target buffer includes a plurality of entries, each entry includes a first field and a second field, the first field is used to record an address tag, and the second field is used to record a target predicted address corresponding to the address tag; and In response to the address information of the target to-be-predicted instruction hitting a first entry of the branch target buffer, updating a low-order address portion of the address information of the target to-be-predicted instruction using the target predicted address in the first entry to obtain an updated target to-be-predicted address, The low-order address portion includes the lowest m bits of the address information of the target instruction to be predicted, where m is an integer greater than or equal to 1.

2. The branch prediction method according to claim 1 , further comprising: In response to the address information of the target instruction to be predicted not hitting the branch target buffer, the next sequential address of the target instruction to be predicted in the instruction sequence is used as the updated target address to be predicted.

3. The branch prediction method according to claim 1 , further comprising: The updated target to-be-predicted address is used to perform the next round of branch prediction operation.

4. The branch prediction method according to claim 1, wherein: The address information includes an address identifier, where the address identifier is the lowest n bits of the address information of the target instruction to be predicted, where n is an integer greater than or equal to 1, and each entry further includes a third field for recording the validity of the corresponding entry; as well as Querying whether the address information of the target to-be-predicted instruction hits the branch target buffer includes: In response to the address identifier of the target to-be-predicted instruction matching the address tag in the first entry, and the first entry being in a valid state, it is determined that the address information of the target to-be-predicted instruction hits the first entry of the branch target buffer.

5. The branch prediction method according to claim 1, wherein: The branch target buffer is shared by multiple threads of a multi-threaded processor, the multiple threads including at least a first thread and a second thread. Before obtaining address information of the target instruction to be predicted, the branch prediction method further includes: A first instruction to be predicted corresponding to the first thread or a second instruction to be predicted corresponding to the second thread is selected as the target instruction to be predicted.

6. The branch prediction method according to claim 5 , further comprising: In response to selecting the first to-be-predicted instruction corresponding to the first thread as the target to-be-predicted instruction and the address information of the first to-be-predicted instruction hitting the first entry of the branch target buffer, the target predicted address in the first entry is used to update the low-order address portion of the address information of the first to-be-predicted instruction to obtain the updated target to-be-predicted address corresponding to the first to-be-predicted instruction.

7. The branch prediction method according to claim 6, further comprising: The updated target address to be predicted of the first instruction to be predicted or the address information of the second instruction to be predicted is selected for use in performing the next round of branch prediction operation.

8. The branch prediction method according to claim 1, wherein: The branch target buffer is a multi-level branch target buffer, and the multi-level branch target buffer includes at least a first-level branch target buffer and a second-level branch target buffer. Querying whether the address information of the target to-be-predicted instruction hits the branch target buffer includes: Query whether the address information of the target to-be-predicted instruction hits the first-level branch target buffer and / or the second-level branch target buffer.

9. A branch prediction device, comprising: An acquisition module configured to acquire address information of a target instruction to be predicted; a query module, comprising a branch target buffer, and configured to query whether the address information of the target to-be-predicted instruction hits the branch target buffer, wherein the branch target buffer comprises a plurality of entries, each entry comprises a first field and a second field, the first field being used to record an address tag, and the second field being used to record a target predicted address corresponding to the address tag; and an updating module configured to, in response to the address information of the target to-be-predicted instruction hitting a first entry of the branch target buffer, update a low-order address portion of the address information of the target to-be-predicted instruction using the target predicted address in the first entry to obtain an updated target to-be-predicted address; The low-order address portion includes the lowest m bits of the address information of the target instruction to be predicted, where m is an integer greater than or equal to 1.

10. The branch prediction apparatus according to claim 9, further comprising: a first multiplexer coupled to the query module, the branch target buffer, and the update module, and configured to receive at least a next sequential address of the target to-be-predicted instruction in the instruction sequence, and read from the branch target buffer a target predicted address corresponding to the first entry hit during the query; The query module is further configured to generate a first control signal in response to the address information of the target to-be-predicted instruction hitting the first entry of the branch target buffer to control the first multiplexer to output the target predicted address in the first entry to the update module.

11. The branch prediction device according to claim 10, wherein: The query module is also configured to, in response to the address information of the target instruction to be predicted not hitting the branch target buffer, generate a second control signal to control the first multiplexer to output the next sequential address of the target instruction to be predicted in the instruction sequence to the update module.

12. The branch prediction apparatus according to claim 9, wherein: The branch target buffer is shared by a plurality of threads of a multi-threaded processor, the plurality of threads including at least a first thread and a second thread, The branch prediction apparatus further includes a second multiplexer configured to select a first instruction to be predicted corresponding to the first thread or a second instruction to be predicted corresponding to the second thread as the target instruction to be predicted.

13. An electronic device comprising: at least one storage unit and at least one processing unit; wherein the at least one storage unit stores computer-readable instructions; The at least one processing unit executes the computer-readable instructions stored in the at least one storage unit to implement the branch prediction method according to any one of claims 1 to 8.

14. A computer-readable storage medium, wherein: The computer-readable storage medium stores computer-readable instructions. When a processor executes the computer-readable instructions, the branch prediction method according to any one of claims 1 to 8 is implemented.

15. A processor comprising the branch prediction device according to any one of claims 9 to 12.

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