Response method and device for interrupt signal of virtual machine, terminal and storage medium

Abstract

The embodiment of the invention discloses a response method and device for an interrupt signal of a virtual machine, a terminal and a storage medium. The method comprises the following steps: in response to a target trigger operation of external equipment of a virtual machine, obtaining target interrupt information matched with the target trigger operation from a pre-configured interrupt information set, and determining a target virtual processor for processing the target trigger operation; sending a target interrupt signal to the target virtual processor according to the target interrupt information through a target message interrupt controller matched with the target virtual processor; the target interrupt signal has a corresponding first physical address. And determining a second physical address matched with the first physical address according to pre-configured address mapping, and executing the target interrupt signal based on the second physical address through the physical processor to complete interrupt response of the target trigger operation. Through the embodiment of the invention, frequent operation of the virtual machine monitor is avoided, the system overhead is reduced, and the operation efficiency of the virtual machine is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of computer virtualization, and in particular to a method, device, terminal and storage medium for responding to an interrupt signal of a virtual machine. Background Art

[0002] Interrupt virtualization is a technology for effectively handling interrupts in a virtualized environment. It refers to reporting interrupts in independent spaces to ensure that task scheduling between virtual functions (VFs) is not interfered with.

[0003] In the related art, when virtualizing an external interrupt of a virtual machine, the external interrupt signal is first processed by a virtual machine monitor, and then the processed external interrupt signal is injected into the virtual machine for processing by the virtual machine.

[0004] In the process of injecting external interrupts into a virtual machine, the virtual machine monitor will be trapped. It is necessary to suspend the operation of the virtual machine first, and resume the operation of the virtual machine after the injection is completed. Multiple virtual machine monitor traps will increase system overhead and affect the operating efficiency of the virtual machine. Summary of the invention

[0005] The embodiment of the present application provides a method, device, terminal and storage medium for responding to an interrupt signal of a virtual machine, which can avoid frequent trapping of the virtual machine monitor, reduce system overhead and improve the operation efficiency of the virtual machine. The technical solution is as follows:

[0006] In a first aspect, a method for responding to an interrupt signal of a virtual machine is provided, the method comprising:

[0007] In response to a target trigger operation of an external device of the virtual machine, target interrupt information matching the target trigger operation is obtained from a pre-configured interrupt information set, and a target virtual processor for processing the target trigger operation is determined; the interrupt information set includes interrupt information matching each trigger operation, and the interrupt information represents parameters required when executing a message signal interrupt;

[0008] Sending a target interrupt signal to the target virtual processor according to the target interrupt information through a target message interrupt controller matched with the target virtual processor; the target interrupt signal has a corresponding first physical address;

[0009] According to the pre-configured address mapping, a second physical address matching the first physical address is determined, and the target interrupt signal is executed by the physical processor based on the second physical address to complete the interrupt response of the target trigger operation; the address mapping is used to characterize the correspondence between the physical address of the virtual processor and the physical address of the physical processor.

[0010] In a second aspect, a device for responding to an interrupt signal of a virtual machine is provided, the device comprising:

[0011] Platform interrupt control module: used to respond to the target trigger operation of the external device of the virtual machine, obtain the target interrupt information matching the target trigger operation from the pre-configured interrupt information set, and determine the target virtual processor to process the target trigger operation; the interrupt information set includes the interrupt information matched by each trigger operation, and the interrupt information represents the parameters required when executing the message signal interrupt

[0012] A message interrupt control module: used for sending a target interrupt signal to the target virtual processor according to the target interrupt information through a target message interrupt controller matching the target virtual processor; the target interrupt signal has a corresponding first physical address;

[0013] Execution module: used to determine a second physical address matching the first physical address according to a pre-configured address mapping, and execute the target interrupt signal based on the second physical address through a physical processor to complete the interrupt response of the target trigger operation; the address mapping is used to characterize the correspondence between the physical address of the virtual processor and the physical address of the physical processor.

[0014] According to a third aspect, an electronic terminal is provided, comprising: a memory and a processor, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the method according to any one of the first aspects is performed.

[0015] In a fourth aspect, a computer-readable storage medium is provided, characterized in that the computer-readable storage medium includes a stored program, wherein when the program is running, the terminal where the computer-readable storage medium is located is controlled to execute any method described in the first aspect.

[0016] In an embodiment of the present invention, an interrupt signal is transmitted to a virtual machine through a message interrupt controller, so that the interrupt responses generated by the triggering operation are all converted into message signal interrupt responses, thereby changing the way the interrupt signal enters the virtual machine, avoiding the frequent trapping of the virtual machine monitor required for the interrupt signal to enter the virtual machine in the related art, greatly reducing the cumbersome calling process, allowing the virtual machine to respond to the interrupt generated by the triggering operation more quickly, and improving the operating efficiency of the virtual machine; adopting the corresponding method of the interrupt signal of the virtual machine provided by the present invention can not only reduce the processing overhead of the entire system, but also reduce the time delay caused by the trapping of the virtual machine monitor, so that the response of the interrupt signal is more timely, the efficiency of the virtual machine in processing interrupts is improved, and the overall performance of the virtual machine is improved.

[0017] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 It is a flowchart of the steps of a method for responding to an interrupt signal of a virtual machine provided by an embodiment of the present invention;

[0020] Figure 2 It is a flowchart of the steps of another method for responding to an interrupt signal of a virtual machine provided by an embodiment of the present invention;

[0021] Figure 3 It is a block diagram of a device for responding to an interrupt signal of a virtual machine provided by an embodiment of the present invention;

[0022] Figure 4 is a block diagram of an electronic terminal provided by an embodiment of the present invention;

[0023] Figure 5 is a block diagram of another electronic terminal provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0025] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally a class, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three kinds of relationships can exist, for example, A and / or B can be represented: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the front and back associated objects are a kind of "or" relationship. In the embodiment of the present application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0026] The embodiment of the present invention can be based on the fifth-generation Reduced Instruction Set Computer-V (RISC-V) architecture. The RISC-V architecture is an open source architecture, and its original interrupt response is implemented based on a platform interrupt controller (Platform Level Interrupt Controller, PLIC). The platform interrupt controller does not support virtualization and has insufficient support for message signal interrupts. When using PLIC to implement the interrupt response of a virtual machine, it is necessary to go through cumbersome calling operations, wherein it is necessary to frequently execute operations of falling into a virtual machine monitor. When falling into a virtual machine monitor, the virtual machine monitor will suspend the operation of the virtual machine, and resume the operation of the virtual machine after the virtual machine monitor completes processing the interrupt signal and injects it into the virtual machine. Frequent falling into a virtual machine monitor will increase the overhead of the computer system, generate time delays that are difficult to ignore, and affect the efficiency of the virtual machine in processing interrupts.

[0027] In order to solve the problem in the related art that the operating efficiency of a virtual machine is reduced due to frequent trapping in a virtual machine monitor, an embodiment of the present invention provides a method for responding to an interrupt signal of a virtual machine, and the method is as follows:

[0028] refer to Figure 1 , is a flowchart of a method for responding to an interrupt signal of a virtual machine provided by an embodiment of the present invention, the method comprising:

[0029] Step 101: In response to a target trigger operation of an external device of a virtual machine, target interrupt information matching the target trigger operation is obtained from a pre-configured interrupt information set, and a target virtual processor for processing the target trigger operation is determined; the interrupt information set includes interrupt information matched by each trigger operation, and the interrupt information represents parameters required for executing a message signal interrupt;

[0030] In the embodiment provided by the present invention, an Advanced Platform Level Interrupt Controller (APLIC) receives an interrupt signal of an external device, that is, an external interrupt, which can be generated by a trigger operation of a user; the interrupt signal of an external device can be an electrical signal such as a high level, a low level, a rising edge, a falling edge, etc.; after receiving the interrupt signal generated by a target trigger operation, the Advanced Platform Interrupt Controller selects a target virtual processor (Virtual Central Processing Unit, vCPU) that needs to process the interrupt signal according to a preset configuration, converts the interrupt signal of the external device into target interrupt information, the target interrupt information includes the parameters required for executing a message signal interrupt (Message Signal Interrupt, MSI) corresponding to the target trigger operation, and sends the target interrupt information in the form of an electrical signal to an incoming message signal interrupt controller (IMSIC) to perform a message signal interrupt.

[0031] Step 102: Send the target interrupt signal to the target virtual processor according to the target interrupt information through a target message interrupt controller that matches the target virtual processor; the target interrupt signal has a corresponding first physical address.

[0032] When the message interrupt controller receives the target interrupt information from the advanced platform interrupt controller, it will generate a target interrupt signal and send the target interrupt signal into the virtual machine; the process of the message interrupt controller receiving the target interrupt information, generating the target interrupt signal and sending the target interrupt signal into the virtual machine not only transmits the interrupt signal of the external interrupt into the virtual machine, but also avoids falling into the operation of the virtual machine monitor, and reduces the time consumption required for the interrupt signal to be transmitted into the virtual machine; the target interrupt signal sent by the interrupt signal controller will be responded to inside the virtual machine, and the responding process will occupy the first physical address inside the virtual machine.

[0033] Step 103: According to the pre-configured address mapping, determine a second physical address that matches the first physical address, and execute the target interrupt signal based on the second physical address through the physical processor to complete the interrupt response of the target trigger operation; the address mapping is used to characterize the correspondence between the physical address of the virtual processor and the physical address of the physical processor.

[0034] After the interrupt signal is transmitted into the virtual machine, it will be responded to by the process inside the virtual machine. The first physical address occupied by the process is reflected to the second physical address outside the virtual machine, that is, the actual physical address, according to the pre-configured address mapping. The physical processor executes the target interrupt signal based on the second physical address, which is equivalent to the target virtual processor executing the target interrupt signal and completing the interrupt response of the target trigger operation; the pre-configured address mapping refers to the mapping between the physical address inside the virtual machine and the actual physical address outside the virtual machine. In step 103, it includes the mapping relationship between the physical address of the virtual processor and the physical address of the physical processor.

[0035] In an embodiment of the present invention, an interrupt signal is transmitted to a virtual machine through a message interrupt controller, so that the interrupt responses generated by the triggering operation are all converted into message signal interrupt responses, thereby changing the way the interrupt signal enters the virtual machine, avoiding the frequent trapping of the virtual machine monitor required for the interrupt signal to enter the virtual machine in the related art, greatly reducing the cumbersome calling process, allowing the virtual machine to respond to the interrupt generated by the triggering operation more quickly, and improving the operating efficiency of the virtual machine; adopting the corresponding method of the interrupt signal of the virtual machine provided by the present invention can not only reduce the processing overhead of the entire system, but also reduce the time delay caused by the trapping of the virtual machine monitor, so that the response of the interrupt signal is more timely, the efficiency of the virtual machine in processing interrupts is improved, and the overall performance of the virtual machine is improved.

[0036] refer to Figure 2 , is another method for responding to an interrupt signal of a virtual machine provided by an embodiment of the present invention, the method comprising:

[0037] Step 201: During the startup of the virtual machine, in response to a page fault exception triggered by an advanced platform interrupt controller, suspend the operation of the virtual machine through a virtual machine monitor; the page fault exception is caused by the fact that a physical address in the virtual machine is not mapped to an actual physical address.

[0038] When the virtual machine is started, the interrupt control initialization is performed, including configuring the hardware and software related to the virtual machine in the entire system to prepare for the interrupt response of the virtual machine.

[0039] When the virtual machine starts, it will access the address space of the advanced platform interrupt controller, but at this time, the advanced platform interrupt controller does not provide support for the virtual machine, so the address in the address space of the advanced platform interrupt controller is not mapped to the actual physical address, which triggers a page fault exception. After the page fault exception is captured, the virtual machine will be trapped and the operation of the virtual machine will be suspended.

[0040] Step 202: configure the interrupt information set in the advanced platform interrupt controller through the virtual machine monitor.

[0041] After the operation of the virtual machine is suspended, the virtual machine monitor will start to configure the advanced platform interrupt controller. One of the steps of configuring the advanced platform interrupt controller is to configure the interrupt information set in the advanced platform interrupt controller through the virtual machine monitor; through the interrupt information set, the advanced platform interrupt controller can obtain the necessary parameters in the message signal interrupt process corresponding to the target trigger operation.

[0042] Optionally, step 202 may include:

[0043] Sub-step 2021: Obtain the permission status of the target virtual processor to read and write addresses in the address space of the advanced platform interrupt controller.

[0044] Sub-step 2022: When the permission status indicates that the target virtual processor has the permission to read and write addresses in the address space, write interrupt information to the advanced platform interrupt controller to obtain the interrupt information set; the interrupt information includes the instruction data and address that triggers the page fault exception.

[0045] Specifically, the interrupt information set includes the interrupt information matched by each triggering operation, and each interrupt information includes the address and instruction data that triggers the page fault exception; after the instruction data and address that triggers the page fault exception are submitted to the virtual machine monitor, it is determined whether the virtual processor that executes the interrupt signal sent by the triggering operation has the authority to read and write the address. If it is determined that the virtual processor has the authority to read and write addresses within the address space of the advanced platform interrupt controller, the address and instruction data that triggers the page fault exception are written into the advanced platform interrupt controller to obtain the interrupt information set.

[0046] Step 203: Preset the delivery mode of the advanced platform interrupt controller to a message signal interrupt mode.

[0047] One of the steps in configuring the advanced platform interrupt controller is to preset the delivery mode of the advanced platform interrupt controller; all devices can be connected to the advanced platform interrupt controller through an interrupt line, and the interrupt signal generated by the device can be delivered to the virtual machine in the advanced platform interrupt controller through a wired interrupt or a message signal interrupt; in an embodiment of the present invention, the delivery mode of the interrupt signal is set to the message signal interrupt mode to ensure that the interrupt signal generated by the trigger operation is processed in the form of a message signal.

[0048] Step 204: assign a corresponding interrupt number to each trigger operation according to the type of the trigger operation, and different types of trigger operations are assigned different interrupt numbers; and assign a specified virtual processor to each interrupt number.

[0049] Another step in configuring the advanced platform interrupt controller is to assign an interrupt number to the interrupt signal and assign a virtual processor in the virtual machine to the interrupt number. For example, the interrupt signal generated by the trigger operation of pressing the q key on the keyboard is assigned the interrupt number 10, and then vCPU0 among the multiple virtual processors in the virtual machine is designated to receive and process the interrupt signal with the interrupt number 10; after the configuration is completed, pressing the q key on the keyboard will trigger an interrupt signal with the interrupt number 10, and the interrupt signal will be sent to the virtual machine in the form of a message signal interrupt. Under the control of vCPU0, the virtual machine receives the interrupt number 10 from the keyboard, enters the corresponding interrupt processing function, reads the receiving buffer of the Universal Asynchronous Receiver Transmitter (UART) serial port, parses the pressed character as q, and prints the character q on the virtual machine console.

[0050] Step 205: After completing the configuration of the interruption information set, resume the operation of the virtual machine.

[0051] After the address and instruction data that trigger the page fault exception are written into the advanced platform interrupt controller, it can be considered that the interrupt information set has been configured; if other configuration steps have been completed, that is, the configuration of the advanced interrupt controller has been completed, the operation of the virtual machine can be restored through the virtual machine monitor.

[0052] Step 206: During the startup of the virtual machine, according to the number of the virtual processors corresponding to each physical processor, obtain the arrangement format of the interrupt file; and establish an address mapping between the physical address of the virtual processor and the physical address of the physical processor according to the arrangement format.

[0053] When the virtual machine monitor initializes and starts the virtual machine, it is also necessary to configure the address mapping of the interrupt file during the message signal interrupt process; each virtual processor has a matching interrupt file, which is used to respond to write operations and trigger the message signal interrupt of the virtual processor matching the interrupt file, that is, writing to the interrupt file is equivalent to the interruption of the virtual processor matching the interrupt file; after the address mapping of the interrupt file is configured, the writing of the specified address of the interrupt file can be mapped to the writing of the physical processor to the actual physical address, which is equivalent to establishing a mapping relationship between the physical address of the virtual processor and the physical address of the physical processor. During the virtual machine startup process, the virtual machine monitor accesses the pre-configured device tree, which records the number of physical processors and virtual processors, and calibrates the corresponding relationship between the number of physical processors and virtual processors. By accessing the device tree, the virtual machine monitor will establish the address mapping of the interrupt file in the virtual machine, that is, the mapping between the virtual physical address of the interrupt file and the actual physical address.

[0054] It should be noted that the above configuration steps are only performed when the virtual machine is started. In the subsequent triggering operations before the virtual machine is shut down, steps 201-206 will not be entered. In steps 201-205, only one trap to the virtual machine monitor is performed, and in subsequent steps, the virtual machine monitor will no longer be trapped to process interrupt signals.

[0055] Step 207: In response to a target trigger operation of an external device of the virtual machine, target interrupt information matching the target trigger operation is obtained from a pre-configured interrupt information set.

[0056] This step refers to step 101 and will not be described in detail here.

[0057] Step 208: Determine a target virtual processor for processing the target trigger operation.

[0058] This step refers to step 101 and will not be described in detail here.

[0059] Optionally, step 208 may include:

[0060] Sub-step 2081: acquiring an interrupt number matching the target trigger operation according to a preset correspondence between the trigger operation and the interrupt number;

[0061] Sub-step 2082: According to the preset correspondence between the interrupt number and the virtual processor, determine the virtual processor that matches the interrupt number of the target trigger operation as the target virtual processor.

[0062] According to the configuration of the advanced platform interrupt controller in step 204, step 208 can be subdivided into sub-step 2081 and sub-step 2082. For example, the target trigger operation is: press the q key on the keyboard, according to the preset correspondence between the trigger operation and the interrupt number, obtain the interrupt number 10 that matches the target trigger operation, according to the preset correspondence between the interrupt number and the virtual processor, select the virtual processor vCPU0 that matches the interrupt number 10, and use vCPU0 as the target virtual processor.

[0063] Step 209: Send a target interrupt signal to the target virtual processor according to the target interrupt information through a target message interrupt controller that matches the target virtual processor; the target interrupt signal has a corresponding first physical address.

[0064] This step refers to step 102 and will not be described in detail here.

[0065] Optionally, step 209 may include:

[0066] Sub-step 2091: Control the message interrupt controller to write the target instruction data in the target interrupt information to the interrupt file matching the target virtual processor according to the target address in the target interrupt information, wherein the interrupt file is used to respond to the write operation and trigger the message signal interrupt of the virtual processor matching the interrupt file; the target address is an address in the physical address space of the interrupt file.

[0067] After the message interrupt controller receives the target interrupt information from the advanced platform interrupt controller, the message interrupt controller implements the interrupt of the target virtual processor according to the parameters required for executing the message signal interrupt contained in the target interrupt information; the above parameters include a target address and target instruction data, the target address is a specific address in the interrupt file matching the target virtual processor, and the target instruction data is specific instruction data representing the message signal interrupt. The message signal interrupt controller can send the target interrupt signal to the target virtual processor by maintaining the interrupt file matching the target virtual processor; specifically, the message interrupt controller writes the target instruction data in the target interrupt information to the interrupt file matching the target virtual processor according to the target address in the target interrupt information, and by writing to the specific address of the interrupt file, the target interrupt signal is able to enter the virtual machine and be processed by the target virtual processor.

[0068] Step 210: determine a second physical address matching the first physical address according to the preconfigured address mapping, and execute the target interrupt information signal based on the second physical address through a physical processor to complete an interrupt response of the target trigger operation.

[0069] This step refers to step 103 and will not be described in detail here.

[0070] The embodiment of the present application can also implement inter-core interruption, and the steps of inter-core interruption are as follows:

[0071] Step 211: In response to a task trigger instruction of the first virtual processor of the virtual machine, determine a second virtual processor that responds to the interrupt, and send inter-core interrupt information to a message interrupt controller of the second virtual processor through the first virtual processor.

[0072] When a task executed by the first virtual processor requires sending an inter-core interrupt to the second virtual processor during a task trigger instruction, the first virtual processor will send inter-core interrupt information to the message interrupt controller of the second virtual processor. The inter-core interrupt information includes the parameters required for the second virtual processor to execute the message signal interrupt.

[0073] Step 212: Send an inter-core interrupt signal to the second virtual processor according to the inter-core interrupt information through a message interrupt controller matched with the second virtual processor; the inter-core interrupt signal has a corresponding first physical address.

[0074] When the message interrupt controller receives the inter-core interrupt information from the first virtual processor, the message interrupt controller will send an inter-core interrupt signal to the second virtual processor. Referring to sub-step 2091, sending the inter-core interrupt signal is still achieved by maintaining the interrupt file that matches the second virtual processor: the parameters in the inter-core interrupt information include a specific address in the interrupt file that matches the second virtual processor and specific instruction data that characterizes the message signal interrupt. The specific instruction data is written to the specific address in the interrupt file that matches the second virtual processor to enable the second virtual processor to receive the inter-core interrupt signal.

[0075] Step 213: According to the pre-configured address mapping, determine a second physical address that matches the first physical address, and execute the inter-core interrupt signal based on the second physical address through the physical processor to complete the interrupt response of the task trigger instruction; the address mapping is used to characterize the correspondence between the physical address of the virtual processor and the physical address of the physical processor.

[0076] In the embodiment of the present invention, the inter-core interrupt does not involve the advanced platform interrupt controller, but is related to the message interrupt controller. Since a matching message interrupt controller is set for each virtual processor in the process of implementing the external interrupt, the inter-core interrupt can also be transmitted from the first virtual processor to the second virtual processor in the form of a message signal interrupt, and responded to and processed by the second virtual processor.

[0077] In summary, in the embodiments of the present invention, the interrupt signal is transmitted to the virtual machine through the message interrupt controller, so that the interrupt responses generated by the trigger operation are all converted into message signal interrupt responses, which changes the way the interrupt signal enters the virtual machine, avoids the frequent trapping of the virtual machine monitor required for the interrupt signal to enter the virtual machine in the related technology, greatly reduces the cumbersome calling process, and enables the virtual machine to respond to the interrupt generated by the trigger operation more quickly, thereby improving the operating efficiency of the virtual machine; at the same time, the message signal interrupt is used to realize the inter-core interrupt, unifies the implementation form of the inter-core interrupt and the external interrupt, facilitates the virtual machine to process, avoids the introduction of additional hardware or methods, and reduces the cost of the system; the corresponding method of the interrupt signal of the virtual machine provided by the present invention can not only reduce the processing overhead of the entire system, but also reduce the time delay caused by the trapping of the virtual machine monitor, so that the response of the interrupt signal is more timely, the efficiency of the virtual machine in processing interrupts is improved, and the overall performance of the virtual machine is improved.

[0078] In a second aspect, an embodiment of the present application provides a device 30 for responding to an interrupt signal of a virtual machine, referring to Figure 3 , is a block diagram of a device for responding to an interrupt signal of a virtual machine provided by an embodiment of the present invention, wherein the response device 30 includes:

[0079] The platform interrupt control module 301 is used to respond to the target trigger operation of the external device of the virtual machine, obtain the target interrupt information matching the target trigger operation from the pre-configured interrupt information set, and determine the target virtual processor for processing the target trigger operation; the interrupt information set includes the interrupt information matched by each trigger operation, and the interrupt information represents the parameters required for executing the message signal interrupt

[0080] The message interrupt control module 302 is used to send a target interrupt signal to the target virtual processor according to the target interrupt information through a target message interrupt controller matching the target virtual processor; the target interrupt signal has a corresponding first physical address;

[0081] Execution module 303: used to determine a second physical address matching the first physical address according to a pre-configured address mapping, and execute the target interrupt signal based on the second physical address through a physical processor to complete the interrupt response of the target trigger operation; the address mapping is used to characterize the correspondence between the physical address of the virtual processor and the physical address of the physical processor.

[0082] Optionally, the device 30 may further include:

[0083] an initialization startup module, used for suspending the operation of the virtual machine through a virtual machine monitor in response to a page fault exception triggered by an advanced platform interrupt controller during the startup of the virtual machine; the page fault exception is caused by the physical address in the virtual machine not being mapped to the actual physical address;

[0084] Initialize the execution module and configure the interrupt information set in the advanced platform interrupt controller through the virtual machine monitor;

[0085] The initialization completion module resumes the operation of the virtual machine after completing the configuration of the interruption information set.

[0086] Optionally, the initialization execution module may further include:

[0087] A first allocation submodule: used for allocating a corresponding interrupt number to each trigger operation according to the type of the trigger operation, and different types of trigger operations are allocated different interrupt numbers;

[0088] The second allocation submodule is used to allocate a specified virtual processor to each interrupt number;

[0089] Optionally, the initialization execution module may include:

[0090] The reading submodule is used to obtain the permission status of the target virtual processor to read and write addresses in the address space of the advanced platform interrupt controller;

[0091] Writing submodule: when the permission status indicates that the target virtual processor has the permission to read and write addresses in the address space, write interrupt information into the advanced platform interrupt controller to obtain the interrupt information set; the interrupt information includes the instruction data and address that triggers the page fault exception.

[0092] Optionally, the initialization execution module may further include:

[0093] The delivery mode preset submodule is used to preset the delivery mode of the advanced platform interrupt controller to the message signal interrupt mode.

[0094] Optionally, the interrupt information includes instruction data and an address, and the message interrupt control module 302 includes:

[0095] Message interrupt submodule: used to control the message interrupt controller to write the target instruction data in the target interrupt information to the interrupt file matching the target virtual processor according to the target address in the target interrupt information, the interrupt file is used to respond to the write operation and trigger the message signal interrupt of the virtual processor matching the interrupt file; the target address is an address in the physical address space of the interrupt file.

[0096] Optionally, the response device 30 may further include:

[0097] The address mapping module is used to obtain the arrangement format of the interrupt file according to the number of the virtual processors corresponding to each physical processor during the startup of the virtual machine; and to establish an address mapping between the physical address of the virtual processor and the physical address of the physical processor according to the arrangement format.

[0098] Optionally, the response device 30 may further include:

[0099] The inter-core interrupt startup module is used to respond to the task trigger instruction of the first virtual processor of the virtual machine, determine the second virtual processor that responds to the interrupt, and send the inter-core interrupt information to the message interrupt controller of the second virtual processor through the first virtual processor.

[0100] An inter-core interrupt delivery module is used to deliver an inter-core interrupt signal to the second virtual processor according to the inter-core interrupt information through a message interrupt controller matching the second virtual processor; the inter-core interrupt signal has a corresponding first physical address.

[0101] An inter-core interrupt execution module is used to determine a second physical address that matches the first physical address according to a pre-configured address mapping, and execute the inter-core interrupt signal based on the second physical address through a physical processor to complete the interrupt response of the task trigger instruction; the address mapping is used to characterize the correspondence between the physical address of the virtual processor and the physical address of the physical processor.

[0102] In summary, in the embodiments of the present invention, the interrupt signal is transmitted to the virtual machine through the message interrupt controller, so that the interrupt response generated by the trigger operation is converted into a message signal interrupt response, which changes the way the interrupt signal enters the virtual machine, avoids the frequent trapping of the virtual machine monitor required for the interrupt signal to enter the virtual machine in the related technology, greatly reduces the cumbersome calling process, enables the virtual machine to respond to the interrupt generated by the trigger operation more quickly, and improves the operating efficiency of the virtual machine; the corresponding method of the interrupt signal of the virtual machine provided by the present invention can not only reduce the processing overhead of the entire system, but also reduce the time delay caused by the trapping of the virtual machine monitor, so that the response of the interrupt signal is more timely, improves the efficiency of the virtual machine in processing interrupts, and improves the overall performance of the virtual machine.

[0103] Reference Figure 4The electronic terminal 1700 may include one or more of the following components: a processing component 1702 , a memory 1704 , a power component 1706 , a multimedia component 1708 , an audio component 1710 , an input / output (I / O) interface 1712 , a sensor component 1714 , and a communication component 1716 .

[0104] The processing component 1702 generally controls the overall operation of the electronic terminal 1700, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 1702 may include one or more processors 1720 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 1702 may include one or more modules to facilitate the interaction between the processing component 1702 and other components. For example, the processing component 1702 may include a multimedia module to facilitate the interaction between the multimedia component 1708 and the processing component 1702.

[0105] The memory 1704 is used to store various types of data to support the operation of the electronic terminal 1700. Examples of such data include instructions for any application or method operating on the electronic terminal 1700, contact data, phone book data, messages, pictures, multimedia, etc. The memory 1704 can be implemented by any type of volatile or non-volatile storage terminal or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0106] The power supply component 1706 provides power to various components of the electronic terminal 1700. The power supply component 1706 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic terminal 1700.

[0107] The multimedia component 1708 includes a screen that provides an output interface between the electronic terminal 1700 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, sliding, and gestures on the touch panel. The touch sensor may not only sense the demarcation of the touch or sliding action, but also detect the duration and pressure associated with the touch or sliding operation. In some embodiments, the multimedia component 1708 includes a front camera and / or a rear camera. When the electronic terminal 1700 is in an operating mode, such as a shooting mode or a multimedia mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and the rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0108] The audio component 1710 is used to output and / or input audio signals. For example, the audio component 1710 includes a microphone (MIC), and when the electronic terminal 1700 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is used to receive an external audio signal. The received audio signal can be further stored in the memory 1704 or sent via the communication component 1716. In some embodiments, the audio component 1710 also includes a speaker for outputting audio signals.

[0109] I / O interface 1712 provides an interface between processing component 1702 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, a home button, a volume button, a start button, and a lock button.

[0110] The sensor assembly 1714 includes one or more sensors for providing various aspects of status assessment for the electronic terminal 1700. For example, the sensor assembly 1714 can detect the open / closed state of the electronic terminal 1700, the relative positioning of components, such as the display and keypad of the electronic terminal 1700, and the sensor assembly 1714 can also detect the position change of the electronic terminal 1700 or a component of the electronic terminal 1700, the presence or absence of user contact with the electronic terminal 1700, the orientation or acceleration / deceleration of the electronic terminal 1700, and the temperature change of the electronic terminal 1700. The sensor assembly 1714 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 1714 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 1714 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0111] The communication component 1716 is used to facilitate wired or wireless communication between the electronic terminal 1700 and other terminals. The electronic terminal 1700 can access a wireless network based on a communication standard, such as WiFi, an operator network (such as 2G, 3G, 4G or 5G), or a combination thereof. In an exemplary embodiment, the communication component 1716 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 1716 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0112] In an exemplary embodiment, the electronic terminal 1700 can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing terminals (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components to implement a method for responding to an interrupt signal of a virtual machine provided in an embodiment of the present invention.

[0113] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 1704 including instructions, and the instructions can be executed by a processor 1720 of an electronic terminal 1700 to perform the above method. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage terminal, etc.

[0114] Figure 5 1 is a block diagram of an electronic terminal 1800 shown in an exemplary embodiment. For example, the electronic terminal can be provided as a server. Figure 5 The electronic terminal 1800 includes a processing component 1822, which further includes one or more processors, and a memory resource represented by a memory 1832, for storing instructions that can be executed by the processing component 1822, such as an application. The application stored in the memory 1832 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1822 is configured to execute instructions to execute a method for responding to an interrupt signal of a virtual machine provided in an embodiment of the present invention.

[0115] The electronic terminal 1800 may also include a power supply component 1826 configured to perform power management of the electronic terminal 1800, a wired or wireless network interface 1850 configured to connect the electronic terminal 1800 to a network, and an input / output (I / O) interface 1858. The electronic terminal 1800 may operate based on an operating system stored in the memory 1832, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™ or the like.

[0116] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the claims.

[0117] Those skilled in the art should be aware that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented with hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein the communication media include any media that facilitates the transmission of a computer program from one place to another. The storage medium can be any available medium that a general or special-purpose computer can access.

[0118] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A method for responding to an interrupt signal of a virtual machine, characterized in that: The method comprises: In response to a target trigger operation of an external device of the virtual machine, target interrupt information matching the target trigger operation is obtained from a pre-configured interrupt information set, and a target virtual processor for processing the target trigger operation is determined; the interrupt information set includes interrupt information matching each trigger operation, and the interrupt information represents parameters required when executing a message signal interrupt; Sending a target interrupt signal to the target virtual processor according to the target interrupt information through a target message interrupt controller matched with the target virtual processor; the target interrupt signal has a corresponding first physical address; According to the pre-configured address mapping, a second physical address matching the first physical address is determined, and the target interrupt signal is executed by the physical processor based on the second physical address to complete the interrupt response of the target trigger operation; the address mapping is used to characterize the correspondence between the physical address of the virtual processor and the physical address of the physical processor.

2. The method according to claim 1, characterized in that The method further comprises: During the startup of the virtual machine, in response to a page fault exception triggered by an advanced platform interrupt controller, suspending the operation of the virtual machine through a virtual machine monitor; the page fault exception is caused by a physical address in the virtual machine not being mapped to an actual physical address; configuring the interrupt information set in the advanced platform interrupt controller through the virtual machine monitor; After completing the configuration of the interruption information set, the operation of the virtual machine is resumed.

3. The method according to claim 2, characterized in that After suspending the operation of the virtual machine through the virtual machine monitor in response to the page fault exception triggered by the advanced platform interrupt controller, the method further includes: According to the type of the trigger operation, a corresponding interrupt number is assigned to each trigger operation, and different interrupt numbers are assigned to different types of trigger operations; Allocate a specified virtual processor to each of the interrupt numbers; The determining a target virtual processor for processing the target trigger operation includes: According to the preset correspondence between the trigger operation and the interrupt number, obtaining an interrupt number matching the target trigger operation; According to the preset correspondence between the interrupt number and the virtual processor, a virtual processor matching the interrupt number of the target triggering operation is determined as the target virtual processor.

4. The method according to claim 2, characterized in that The configuring the interrupt information set in the advanced platform interrupt controller through the virtual machine monitor includes: Obtaining the permission status of the target virtual processor to read and write addresses in the address space of the advanced platform interrupt controller; When the permission state indicates that the target virtual processor has permission to read and write addresses in the address space, interrupt information is written into the advanced platform interrupt controller to obtain the interrupt information set; the interrupt information includes instruction data and address that triggers the page fault exception.

5. The method according to claim 2, characterized in that: After suspending the operation of the virtual machine through the virtual machine monitor in response to the page fault exception triggered by the advanced platform interrupt controller, the method further includes: The delivery mode of the advanced platform interrupt controller is preset to be a message signal interrupt mode.

6. The method according to claim 1, wherein the interrupt information includes instruction data and address, The method of sending a target interrupt signal to the target virtual processor according to the target interrupt information through a target message interrupt controller matched with the target virtual processor includes: The message interrupt controller is controlled to write the target instruction data in the target interrupt information to the interrupt file matching the target virtual processor according to the target address in the target interrupt information, wherein the interrupt file is used to respond to the write operation and trigger the message signal interrupt of the virtual processor matching the interrupt file; the target address is an address in the physical address space of the interrupt file.

7. The method according to claim 1, characterized in that Each of the virtual processors has a matching interrupt file, and the interrupt file is used to respond to a write operation and trigger a message signal interrupt of the virtual processor matching the interrupt file; the method further includes: During the startup of the virtual machine, according to the number of the virtual processors corresponding to each physical processor, the arrangement format of the interrupt file is obtained; An address mapping between the physical address of the virtual processor and the physical address of the physical processor is established according to the arrangement format.

8. The method according to claim 1, characterized in that: The method further comprises: In response to a task trigger instruction of a first virtual processor of the virtual machine, determining a second virtual processor that responds to the interrupt, and sending inter-core interrupt information to a message interrupt controller of the second virtual processor through the first virtual processor; Sending an inter-core interrupt signal to the second virtual processor according to the inter-core interrupt information through a message interrupt controller matched with the second virtual processor; the inter-core interrupt signal has a corresponding first physical address; According to the pre-configured address mapping, a second physical address matching the first physical address is determined, and the inter-core interrupt signal is executed by the physical processor based on the second physical address to complete the interrupt response of the task trigger instruction; the address mapping is used to characterize the correspondence between the physical address of the virtual processor and the physical address of the physical processor.

9. A device for responding to an interrupt signal of a virtual machine, characterized in that: The response device comprises: Platform interrupt control module: used to respond to the target trigger operation of the external device of the virtual machine, obtain the target interrupt information matching the target trigger operation from the pre-configured interrupt information set, and determine the target virtual processor to process the target trigger operation; the interrupt information set includes the interrupt information matched by each trigger operation, and the interrupt information represents the parameters required when executing the message signal interrupt A message interrupt control module: used for sending a target interrupt signal to the target virtual processor according to the target interrupt information through a target message interrupt controller matching the target virtual processor; the target interrupt signal has a corresponding first physical address; Execution module: used to determine a second physical address matching the first physical address according to a pre-configured address mapping, and execute the target interrupt signal based on the second physical address through a physical processor to complete the interrupt response of the target trigger operation; the address mapping is used to characterize the correspondence between the physical address of the virtual processor and the physical address of the physical processor.

10. An electronic terminal, characterized in that: include: A memory and a processor, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the method according to any one of claims 1 to 8 is performed.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored program, wherein when the program is executed, the terminal where the computer-readable storage medium is located is controlled to execute the method according to any one of claims 1 to 8.

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