A method for preventing misconnection of GGNMOS in layout

Abstract

The present invention discloses a method for preventing misconnection of GGNMOS in a layout, and relates to the technical field of integrated circuits. The steps include: writing a design rule check file to identify a silicide barrier layer region in the layout; analyzing hierarchical connections according to the written design rule check file to determine whether the silicide barrier layer region is correctly connected to the drain terminal; automatically checking the connection of GGNMOS through layout design verification software to identify misconnection problems in the published drawing; the present invention is used to prevent misconnection of GGNMOS in the integrated circuit layout, accurately identify and verify the position and connection of the silicide barrier layer region, ensure correct electrical connection with the drain terminal, optimize the connection path, improve the accuracy of circuit design, and predict circuit performance through SPICE model simulation, and intuitively display the inspection results through graphical result viewing and analysis tools, thereby reducing errors in manual inspection and improving design efficiency.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to an inspection method for preventing misconnection of a GGNMOS in a layout. Background Art

[0002] In the prior art, there are two main types of ESD protection for NMOS tubes: GGNMOS and GCNMOS. Compared with traditional NMOS tubes, these NMOS tubes used for ESD protection remove the silicide layer and LDD injection, and widen the Drain end to increase the parasitic resistance, thereby providing protection. However, in layout design, since the Source end and Drain end of the MOS tube cannot be distinguished by tools, it is impossible to automatically check whether the processed Drain end or Source end is incorrectly connected to the pad. This usually requires manual visual inspection, which is prone to errors, inefficient, and requires a huge workload when processing large-scale and complex chips. Summary of the invention

[0003] The object of the present invention is to provide an inspection method for preventing misconnection of GGNMOS in a layout, realize automated inspection of GGNMOS layout design, and improve the accuracy and reliability of circuit design.

[0004] The purpose of the present invention can be achieved through the following technical solutions:

[0005] The present application provides a method for preventing misconnection of GGNMOS in a layout, comprising the following steps:

[0006] Write a DRC rule file to identify the Silicide Block Layer area in the layout, where the Silicide Block Layer is used to remove the Silicide layer from the NMOS tube for ESD protection;

[0007] Analyze the hierarchical connection according to the DRC rule file to determine whether the Silicide Block Layer area is correctly connected to the Drain end;

[0008] Automatically check the connection of GGNMOS through Calibre DRC tool to identify misconnection problems in published drawings;

[0009] Among them, after automatically checking the connection status of GGNMOS through the Calibre DRC tool and identifying the misconnection problem in the published drawing, it also includes: using SPICE models for simulation, checking connectivity and electrical performance, and judging the connection status based on actual electrical characteristics;

[0010] Simulations using SPICE models include:

[0011] Extract circuit components and their connection relationships from the layout, and set the electrical characteristic parameters of each component in the SPICE model;

[0012] Configure the SPICE simulation environment, set the simulation type and define the simulation conditions;

[0013] Perform SPICE simulation to obtain circuit response data under different operating conditions;

[0014] Analyze the simulation results, identify whether the circuit performance meets the design specifications, and optimize the circuit design based on the analysis results.

[0015] Furthermore, a DRC rule file is written to identify the Silicide Block Layer area in the layout, including:

[0016] According to the process requirements and design specifications, define DRC rules to describe the geometric features, position requirements, and connection standards with the Drain end of the Silicide Block Layer;

[0017] Loading layout data through the DRC tool, reading layout files in GDSII or other formats, wherein the layout files include detailed geometric information and hierarchical structure of the layout;

[0018] The DRC tool scans the layout data to extract Silicide Block Layer features according to defined rules, including identifying the geometry, size, and relative position on a specific layer;

[0019] Use a pattern matching algorithm to identify areas in the layout that match the Silicide Block Layer definition, including comparing layout elements to the patterns defined in the rule file.

[0020] Furthermore, a pattern matching algorithm is used to identify areas in the layout that meet the definition of the Silicide Block Layer, including using a DRC tool to compare elements in the layout with the Silicide Block Layer patterns predefined in the rule file, including checking whether the geometry, size, relative position and electrical connection in the layout match the features described in the rule file, and then analyzing each element in the layout through the DRC tool to determine whether the element meets the specific parameters and layout requirements for the Silicide Block Layer in the rule file.

[0021] Furthermore, the analysis of hierarchical connections specifically includes:

[0022] Network list generation: The DRC rule file will define the relevant properties of the Silicide Block Layer and the Drain end. By parsing all the connection nodes in the layout, a network list is generated, listing all endpoints and their connection relationships;

[0023] Using the topology analysis algorithm, the connection path between the Silicide Block Layer and the Drain end is identified. The analysis will traverse the network list to detect whether the connection between nodes meets the design rules;

[0024] After the topological analysis, the connection between the Silicide Block Layer area and the Drain end is verified.

[0025] Furthermore, the verification includes:

[0026] Check the connection type to confirm whether the Silicide Block Layer is defined as the Silicide layer of the NMOS tube, and check whether its connection relationship with the Drain end meets the design requirements;

[0027] Electrical rule check: According to the DRC rules, confirm that the Silicide Block Layer is electrically correctly connected to the Drain end, and mark the connection that does not comply with this rule as abnormal.

[0028] Furthermore, based on the network list generated, the Dijkstra algorithm in graph theory is used to find the shortest path from the Silicide Block Layer to the Drain end. The specific contents include:

[0029] Set the node corresponding to the Silicide Block Layer as the starting node of the algorithm, set the distance from the starting node to itself to 0, initialize the distance to all other nodes to infinity, create a priority queue to store the nodes and their distance to the starting node, and sort them according to the distance;

[0030] Select the node with the smallest distance from the priority queue as the current node. For all neighboring nodes of the current node, calculate the distance from the current node to the neighboring node and compare it with the recorded distance. If the newly calculated distance is shorter, update the distance and add the new distance and node back to the priority queue. Then mark the current node as visited until all nodes are visited or the Drain end node is reached.

[0031] While updating the distance, the path information is recorded to track the shortest path from the starting node to each node, starting from the Drain end node, and tracing back to the Silicide Block Layer starting node through the recorded path information to reconstruct the entire shortest path;

[0032] Output the shortest path from the Silicide Block Layer to the Drain end, including all nodes and edges on the path.

[0033] Furthermore, the distance from the current node to the neighboring node is calculated as:

[0034] ,in Indicates the current node Arrival of neighboring nodes The shortest distance, is the set of all nodes in the graph, It is the previous node Arrival of neighboring nodes The weight of .

[0035] Further, optimizing and adjusting the circuit design according to the analysis results also includes: using a local anomaly factor algorithm to analyze the connected data and automatically discover anomalies that do not conform to the normal connection pattern;

[0036] Extract connection data from the layout and select features;

[0037] For each data point, determine the data point Nearest neighbors, and calculate the local density of neighbors, use the local density to calculate the LOF value of each point, and evaluate the density difference between each point and its neighbors;

[0038] According to the calculated LOF value, a threshold is set to identify abnormal points. When the LOF value exceeds the threshold, the data point is considered abnormal and the abnormal point is marked;

[0039] The detected abnormal points are analyzed in detail to determine the causes of the abnormalities and compared with the design specifications. Based on the analysis results, the circuit design is optimized and adjusted.

[0040] Furthermore, the LOF value of each point in the local density calculation is expressed as:

[0041] ,in is the local outlier factor of point p, is the specified number of neighbors, Yes of Neighbor set, is the local density at point p, Yes Every neighbor of The local density of .

[0042] Furthermore, it also includes: generating a misunderstood area report according to the recognition result, and viewing the inspection result using the Calibre RVE tool; wherein the inspection result is displayed graphically.

[0043] The beneficial effects of the present invention are:

[0044] Through automated design rule checking and precise layout analysis, the problems of low efficiency and easy errors in manual inspection in the prior art are solved. By writing a DRC rule file, the geometric features, position requirements and connection standards of the Silicide Block Layer and the Drain end are defined. Based on process requirements and design specifications, the automated verification of the layout design is ensured. The DRC tool is used to load the layout data and scan and extract the Silicide Block Layer features. Then, the pattern matching algorithm is used to identify the areas that meet the definition, so that all Silicide Block Layer areas that meet the definition are efficiently identified, and the precise identification of the Silicide Block Layer area is achieved, which improves the accuracy and reliability of the layout design, reduces the burden and errors of manual inspection, and ensures that the circuit layout meets the design specifications.

[0045] Through hierarchical connection analysis and Dijkstra algorithm, it is ensured that the connection between the Silicide Block Layer area and the Drain end meets both electrical requirements and physical layout standards. By generating a network list and using a topology analysis algorithm to identify the connection path, it is ensured that all connections comply with the design rules. The Dijkstra algorithm is used to find the shortest path from the Silicide Block Layer to the Drain end, which optimizes the connection efficiency and ensures the accuracy and compliance of the path. The SPICE model simulation further verifies the connectivity and electrical performance of the circuit, ensuring that the performance of the circuit design under actual working conditions meets expectations. It can not only identify and correct misconnection problems in the layout, but also predict the performance of the circuit under different working conditions, optimize circuit parameters to meet performance goals, and perform fault analysis;

[0046] Through the misunderstanding area report generated by the Calibre RVE tool, engineers can intuitively see the location of the misconnection and make necessary modifications accordingly, further improving the quality of the layout design and the reliability of the circuit. This method effectively solves the problem of relying on manual inspection mentioned in the background technology and realizes the automation and precision of the layout design. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] For better understanding and implementation, the technical solution of the present application is described in detail below with reference to the accompanying drawings.

[0048] Figure 1 A flowchart of a method for preventing misconnection of GGNMOS in a layout provided in Example 1 of the present application;

[0049] Figure 2 A schematic diagram of a flow chart of a method for preventing misconnection of GGNMOS in a layout provided in Example 1 of the present application to identify a Silicide Block Layer region in the layout;

[0050] Figure 3 A schematic diagram of a flow chart of analyzing hierarchical connections of a method for preventing misconnection of GGNMOS in a layout provided in Example 1 of the present application;

[0051] Figure 4 A flowchart of a method for preventing misconnection of GGNMOS in a layout provided in Example 1 of the present application using a SPICE model for simulation. DETAILED DESCRIPTION

[0052] In order to further explain the technical means and effects taken by the present invention to achieve the predetermined invention purpose, exemplary embodiments will be described in detail here, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are only examples of methods and systems consistent with some aspects of the present application as detailed in the attached claims.

[0053] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0054] The specific implementation methods, features and effects of the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments.

[0055] See also Figure 1-Figure 4 This embodiment provides a method for preventing misconnection of GGNMOS in a layout, realizes automated inspection of GGNMOS layout design, and improves the accuracy and reliability of circuit design.

[0056] The present invention provides a method for preventing misconnection of GGNMOS in a layout, comprising the following steps:

[0057] S1. Write a DRC (design rule check) rule file to identify the Silicide Block Layer area in the layout, where the Silicide Block Layer is the part of the NMOS tube for ESD protection where the Silicide layer is removed;

[0058] Among them, DRC (Design Rule Checking) stands for design rule checking, which is used to automatically verify whether the layout design complies with specific design rules; Silicide Block Layer is a special material layer used in the semiconductor manufacturing process. Its main function is to prevent the formation of silicide (such as titanium silicide or cobalt silicide). In integrated circuit design, especially in the ESD (electrostatic discharge) protection structure of NMOS tubes, the Silicide layer needs to be removed to increase the parasitic resistance of the Drain end, thereby improving the ESD protection capability of the device; in NMOS tubes, the Silicide layer is usually used to reduce the contact resistance of the source (Source) and the drain (Drain). However, in ESD protection design, in order to increase the resistance of the Drain end and prevent the current from flowing directly to the sensitive area during an ESD event, it is necessary to form a Silicide Block Layer at the Drain end to prevent the formation of Silicide. The increased resistance at the Drain end helps to disperse and limit the current when an ESD event occurs, protecting the chip from damage.

[0059] Furthermore, a DRC (Design Rule Check) rule file is written to identify the Silicide BlockLayer area in the layout, including:

[0060] S11. Define DRC rules according to process requirements and design specifications. DRC rules describe the geometric features, location requirements, and connection standards with the Drain end of the Silicide Block Layer. They also include areas that the Silicide Block Layer should avoid, areas that it should connect to, and any specific design constraints.

[0061] S12, loading layout data through a DRC tool, reading a layout file in a GDSII or other format, wherein the layout file includes detailed geometric information and a hierarchical structure of the layout;

[0062] S13, DRC tool scans the layout data to extract Silicide Block Layer features according to defined rules, including identifying the geometry, size and relative position on a specific layer;

[0063] S14. Use a pattern matching algorithm to identify areas in the layout that conform to the Silicide Block Layer definition, including comparing whether the layout elements are consistent with the patterns defined in the rule file.

[0064] Among them, in the process of using the pattern matching algorithm to identify the areas in the layout that meet the definition of Silicide Block Layer, the DRC tool will compare the elements in the layout with the Silicide Block Layer patterns predefined in the rule file, including checking whether the geometry, size, relative position and electrical connection in the layout match the features described in the rule file, thereby identifying the areas that meet the definition of Silicide Block Layer. Specifically, the DRC tool will analyze each element in the layout to determine whether they meet the specific parameters and layout requirements of the Silicide Block Layer in the rule file, such as whether they are located at the correct level, whether they have the correct size and shape, and whether they are correctly connected to the Drain end. Through this automated comparison and matching, the DRC tool can efficiently identify all Silicide Block Layer areas that meet the definition, providing accurate data support for subsequent design verification and correction.

[0065] Specifically, the Silicide Block Layer area in the layout is identified by writing a DRC (Design Rule Check) rule file. First, it involves defining DRC rules according to process requirements and design specifications. These rules describe in detail the geometric features, position requirements, and connection standards with the Drain end of the Silicide Block Layer, ensuring that the identification of the Silicide Block Layer is not limited to its geometric shape and size, but also includes its correct position and electrical connection in the layout. Next, the DRC tool loads a layout file in GDSII or other formats containing detailed geometric information and hierarchical structure of the layout, and then scans the layout data according to these predefined rules to extract the features of the Silicide Block Layer, including identifying the geometric shape, size, and relative position on a specific layer. Finally, using a pattern matching algorithm, the DRC tool compares the layout elements with the patterns defined in the rule file, identifies the areas that meet the Silicide Block Layer definition, and ensures that these areas are consistent with the design rules in terms of electrical and physical properties, thereby achieving accurate identification of the Silicide Block Layer area and providing a basis for subsequent layout design verification and correction.

[0066] S2. Analyze the hierarchical connection according to the DRC rule file to determine whether the Silicide Block Layer area is correctly connected to the Drain end;

[0067] Furthermore, the analysis of hierarchical connections specifically includes:

[0068] S21. Network list generation. The DRC rule file will define the relevant properties of the Silicide Block Layer and the Drain end. By parsing all the connection nodes in the layout (including the Silicide Block Layer and the Drain end), a network list is generated, listing all endpoints and their connection relationships.

[0069] S22. Use the topology analysis algorithm to identify the connection path between the Silicide Block Layer and the Drain end. The analysis will traverse the network list to detect whether the connection between the nodes meets the design rules.

[0070] Among them, in the process of using the topology analysis algorithm to identify the connection path between the Silicide Block Layer and the Drain end, the DRC tool will first build a network diagram containing all relevant nodes and connections in the layout, and then the algorithm will traverse this network diagram, starting from the node of the Silicide Block Layer, and tracing the path to the Drain end along the connection relationship in the network list. During the traversal process, the topology analysis algorithm will check whether the node connection on each path meets the predefined design rules, including the distance, angle, inter-layer relationship between nodes, and whether it avoids the prohibited connection area. Through this systematic check, the algorithm can identify all legal connection paths and verify whether they meet the design specifications, thereby ensuring that the connection between the Silicide Block Layer and the Drain end meets both electrical requirements and physical layout standards.

[0071] S23. After topological analysis, the connection between the Silicide Block Layer area and the Drain end is verified.

[0072] Specifically, the DRC tool can accurately generate a network list containing all endpoints and their connection relationships, and use a topology analysis algorithm to systematically traverse the network diagram to identify and verify whether the connection path between the Silicide Block Layer and the Drain end meets the design rules and electrical requirements, ensuring that the Silicide Block Layer area in the layout is correctly connected to the Drain end, avoiding design errors and manufacturing defects, and improving the accuracy and reliability of the design.

[0073] Furthermore, the verification includes:

[0074] Check the connection type to confirm whether the Silicide Block Layer is defined as the Silicide layer of the NMOS tube, and check whether its connection relationship with the Drain end meets the design requirements;

[0075] Electrical rule check: According to the DRC rules, ensure that the Silicide Block Layer is electrically correctly connected to the Drain end. Any connection that does not comply with this rule will be marked as an exception.

[0076] in,

[0077] Specifically, the verification process first involves a connection type check, in which the DRC tool confirms whether the SilicideBlock Layer in the layout is correctly defined as the Silicide layer of the NMOS tube, and verifies whether its connection relationship with the Drain end meets the preset design requirements. This is followed by an electrical rule check. The DRC tool automatically checks whether the electrical connection between the Silicide Block Layer and the Drain end is compliant according to the provisions in the DRC rule file, including checking the size, spacing, and interlayer relationship of the connection to ensure the correctness of the electrical connection. In this process, any connection that does not comply with the DRC rules will be marked as an exception, allowing designers to quickly identify and correct these potential design problems to ensure the accuracy and reliability of the circuit layout.

[0078] Furthermore, based on the network list generated, the Dijkstra algorithm in graph theory is used to find the shortest path from the Silicide Block Layer to the Drain end. The specific contents include:

[0079] Set the node corresponding to the Silicide Block Layer as the starting node of the algorithm, set the distance from the starting node to itself to 0, initialize the distance to all other nodes to infinity, create a priority queue to store the nodes and their distance to the starting node, and sort them according to the distance;

[0080] Select the node with the smallest distance from the priority queue as the current node. For all neighboring nodes of the current node, calculate the distance from the current node to the neighboring node and compare it with the recorded distance. If the newly calculated distance is shorter, update the distance and add the new distance and node back to the priority queue. Then mark the current node as visited until all nodes are visited or the Drain end node is reached.

[0081] While updating the distance, the path information is recorded so that the shortest path from the starting node to each node can be traced, starting from the Drain end node and tracing back to the Silicide Block Layer starting node through the recorded path information to reconstruct the entire shortest path.

[0082] Output the shortest path from the Silicide Block Layer to the Drain end, including all nodes and edges on the path.

[0083] Specifically, by applying the Dijkstra algorithm, the shortest path search from the Silicide Block Layer to the Drain end can be realized. Specifically, the algorithm first initializes the distance from the starting node to itself to 0, the distance of all other nodes to infinity, and adds all nodes to the priority queue. Then, the algorithm iteratively selects the unvisited node with the smallest distance as the current node, updates the distance of its neighboring nodes, and records the path information. This process continues until all nodes are visited or reach the Drain end node. Finally, by backtracking the path information, the shortest path from the Silicide Block Layer to the Drain end is reconstructed, and all nodes and edges on the path are output, which not only improves the efficiency of network list generation, but also ensures the accuracy and compliance of the path.

[0084] Furthermore, the distance from the current node to the neighboring node is calculated as:

[0085] ,in Indicates the current node Arrival of neighboring nodes The shortest distance, is the set of all nodes in the graph, It is the previous node Arrival of neighboring nodes The weight of .

[0086] S3. Use the Calibre DRC tool to automatically check the connection of GGNMOS and identify the misconnection problem in the published diagram, that is, the Source end is incorrectly connected to the pad;

[0087] The Calibre DRC (Design Rule Checking) tool is an integrated circuit (IC) layout design verification software provided as part of Siemens EDA. It is used to automatically check whether the layout design meets specific manufacturing process requirements and design rules.

[0088] Furthermore, after automatically checking the connection status of GGNMOS through the Calibre DRC tool and identifying the misconnection problem in the published drawing, it also includes: using the SPICE model for simulation, checking the connectivity and electrical performance, and judging the connection status based on the actual electrical characteristics.

[0089] S31, extracting circuit components and their connection relationships from the layout, and setting electrical characteristic parameters of each component in the SPICE model, including transistor parameters, resistor values, capacitor values, etc.;

[0090] S32. Configure the SPICE simulation environment, set the simulation type (such as DC, AC, transient analysis), and define the simulation conditions, such as power supply voltage, signal characteristics, temperature range, etc.;

[0091] S33, perform SPICE simulation to obtain the response data of the circuit under different working conditions, including key electrical performance parameters such as static operating point, frequency response, and transient behavior;

[0092] S34. Analyze the simulation results, identify whether the circuit performance meets the design specifications, and optimize and adjust the circuit design based on the analysis results.

[0093] Specifically, SPICE (Simulation Program with Integrated Circuit Emphasis) is an electronic circuit simulation software tool that uses mathematical models to describe the electrical characteristics of each component in the circuit, allowing designers to predict the performance of the circuit under different operating conditions before actual manufacturing, verify whether the design meets specification requirements, optimize circuit parameters to meet performance goals, and perform fault analysis.

[0094] After automatically checking the connection of GGNMOS and identifying misconnection problems through the Calibre DRC tool, the SPICE model is used for simulation to further ensure the accuracy and reliability of the circuit design. Specifically, the circuit components and their connection relationships are extracted from the layout, the electrical characteristic parameters of each component in the SPICE model are set, and then the simulation environment is configured and the simulation is performed to obtain the response data of the circuit under different conditions. Finally, by analyzing the simulation results, it is possible to identify whether the circuit performance meets the design specifications, and optimize the circuit design as needed to ensure that the circuit connectivity and electrical performance meet the expected requirements, thereby improving the quality and performance of the circuit design.

[0095] Furthermore, optimizing and adjusting the circuit design according to the analysis results also includes: using a local anomaly factor (LOF) algorithm to analyze the connection data and automatically discover abnormal situations that do not conform to the normal connection pattern.

[0096] Extract necessary connection data from the layout, including node geometry, connection properties, and electrical parameters, and select appropriate features, such as node spacing, connection angles, and resistance values, which help distinguish normal and abnormal connections;

[0097] For each data point, determine the data point Nearest neighbors, and calculate the local density of neighbors, use the local density to calculate the LOF value of each point, and evaluate the density difference between each point and its neighbors;

[0098] The LOF value of each point in the local density calculation is expressed as:

[0099] ,in is the local outlier factor of point p, is the specified number of neighbors, Yes of Neighbor set, is the local density at point p, Yes Every neighbor of The local density of .

[0100] According to the calculated LOF value, a threshold is set to identify abnormal points. When the LOF value exceeds the threshold, the data point is considered abnormal and the abnormal point is marked;

[0101] The detected abnormal points are analyzed in detail to determine the causes of the abnormalities and compared with the design specifications. Based on the analysis results, necessary optimization adjustments are made to the circuit design to solve the abnormal problems and improve the overall quality of the layout.

[0102] Among them, the above-mentioned DRC rules and Dijkstra algorithm provide a rule-based approach to verify the compliance of the design and optimize the physical connection path of the circuit; the LOF algorithm provides a data-driven approach to detect and identify anomalies, which can supplement the problems that may be missed by rule checking. On the one hand, the basic compliance of the design is ensured by rules, and on the other hand, more subtle problems are identified and corrected through data-driven methods. This combined approach can more comprehensively ensure the quality and performance of circuit design, reduce design errors and manufacturing defects, and improve the reliability and performance of the circuit.

[0103] Specifically, the LOF algorithm identifies anomalies by evaluating the deviation between the local density of a data point and the local density of neighboring points. It is very useful for detecting local abnormal connections in a layout, especially when the anomaly contrasts significantly with the surrounding environment.

[0104] By applying the local outlier factor algorithm (LOF), the present invention can effectively extract and analyze connection data from the layout, automatically identify abnormal points that do not conform to the normal connection pattern, and these abnormal points are marked and located by comparing with preset thresholds. Then, through detailed analysis of the causes of the abnormalities and comparison with design specifications, the circuit design is guided to make necessary optimization adjustments, ultimately achieving the effect of improving the overall quality of the layout and enhancing the accuracy and reliability of the circuit design.

[0105] S4. Generate a misinterpretation area report based on the identification results, and use the Calibre RVE (Result View) tool to view the inspection results. The inspection results are displayed graphically, allowing engineers to intuitively see the location of the misconnection and make necessary modifications accordingly.

[0106] Among them, Calibre RVE (Result View Environment) is a powerful graphical result viewing and analysis tool, mainly used in the integrated circuit (IC) design verification process, especially after layout versus schematic (Layout Versus Schematic, LVS) and design rule checking (Design Rule Checking, DRC).

[0107] Specifically, the Silicide BlockLayer area in the layout is identified by writing a DRC (Design Rule Check) rule file, and the Calibre DRC tool is used to automatically check the connection of the GGNMOS, thereby identifying whether the Source or Drain end is incorrectly connected to the pad. This method improves the efficiency and accuracy of inspection through automated pattern matching and topology analysis algorithms, reduces the burden and errors of manual inspection, and is not affected by the size and complexity of the chip, ensuring the accuracy and reliability of the layout design.

[0108] This embodiment provides a comprehensive inspection method to prevent misconnection of GGNMOS in the layout. Through automated design rule checking (DRC) and advanced algorithm analysis, it ensures that the key component Silicide Block Layer in the circuit layout is correctly connected to the Drain end to avoid chip failure caused by misconnection. The whole process first involves writing a DRC rule file, which defines in detail the geometric features, position requirements, and connection standards of the Silicide Block Layer with the Drain end. These rules are based on process requirements and design specifications to ensure the accuracy of the identification process. Next, the DRC tool loads the layout data, reads files in GDSII or other formats, extracts detailed geometric information and hierarchical structures in the layout, and then scans the layout data according to predefined rules to identify Silicide Block Layer features on specific layers, including geometric shapes, sizes, and relative positions. The pattern matching algorithm further compares the layout elements with the patterns defined in the rule file, identifies areas that meet the Silicide Block Layer definition, and ensures that these areas are consistent with the design rules in terms of electrical and physical properties;

[0109] In the hierarchical connection analysis phase, the DRC tool generates a network list that lists all endpoints and their connection relationships, and identifies the connection paths between the Silicide Block Layer and the Drain end through a topology analysis algorithm to ensure that these paths comply with the design rules. The Dijkstra algorithm is used to find the shortest path from the Silicide Block Layer to the Drain end to optimize the connection efficiency. In addition, SPICE model simulation is used to check connectivity and electrical performance, and to determine the connection status based on actual electrical characteristics to further verify the accuracy of the design;

[0110] Finally, the connection data is analyzed by the local anomaly factor algorithm (LOF), and anomalies that do not conform to the normal connection pattern are automatically discovered, which is very useful for detecting local abnormal connections in the layout. Through these steps, the present invention not only improves the efficiency of network list generation, but also ensures the accuracy and compliance of the path, and finally generates a misunderstood area report, and uses the Calibre RVE tool to graphically display the inspection results, so that engineers can intuitively see the location of the misconnection and make necessary modifications accordingly. The effect of this method is to significantly improve the accuracy and reliability of circuit design, reduce design errors and manufacturing defects, and thus improve the performance and reliability of the chip.

[0111] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technical personnel in this field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A method for preventing misconnection of GGNMOS in a layout, characterized in that: The steps include: Write a DRC rule file to identify the Silicide Block Layer area in the layout, where the Silicide Block Layer is used to remove the Silicide layer from the NMOS tube for ESD protection; Analyze the hierarchical connection according to the DRC rule file to determine whether the Silicide Block Layer area is correctly connected to the Drain end; Automatically check the connection of GGNMOS through Calibre DRC tool to identify misconnection problems in published drawings; Use SPICE models to simulate, check connectivity and electrical performance, and determine the connection status based on actual electrical characteristics; Among them, simulation using SPICE model includes: Extract circuit components and their connection relationships from the layout, and set the electrical characteristic parameters of each component in the SPICE model; Configure the SPICE simulation environment, set the simulation type and define the simulation conditions; Perform SPICE simulation to obtain circuit response data under different operating conditions; Analyze simulation results, identify whether circuit performance meets design specifications, and optimize circuit design based on analysis results; Wherein, the analysis level connection includes: Network list generation: The DRC rule file will define the relevant properties of the Silicide Block Layer and the Drain end. By parsing all the connection nodes in the layout, a network list is generated, listing all endpoints and their connection relationships; Using the topology analysis algorithm, the connection path between the Silicide Block Layer and the Drain end is identified. The analysis will traverse the network list to detect whether the connection between the nodes meets the design rules; Verify the connection between the Silicide Block Layer area and the Drain end, including: connection type check, confirm whether the Silicide Block Layer is defined as the Silicide layer of the NMOS tube, and check whether its connection relationship with the Drain end meets the design requirements; electrical rule check, according to the DRC rules, confirm that the Silicide Block Layer is electrically correctly connected to the Drain end, and mark the connection that does not meet this rule as abnormal.

2. A method for preventing misconnection of GGNMOS in a layout according to claim 1, characterized in that: Write a DRC rule file to identify the Silicide Block Layer area in the layout, including: According to the process requirements and design specifications, define DRC rules to describe the geometric features, position requirements, and connection standards with the Drain end of the Silicide Block Layer; Loading layout data through a DRC tool, reading a layout file in GDSII or other formats, wherein the layout file includes detailed geometric information and hierarchical structure of the layout; The DRC tool scans the layout data to extract Silicide Block Layer features according to defined rules, including identifying the geometry, size, and relative position on a specific layer; Use a pattern matching algorithm to identify areas in the layout that match the Silicide Block Layer definition, including comparing layout elements to patterns defined in the rule file.

3. A method for preventing misconnection of GGNMOS in a layout according to claim 2, characterized in that: Use a pattern matching algorithm to identify areas in the layout that meet the Silicide Block Layer definition, including using a DRC tool to compare elements in the layout with the Silicide Block Layer patterns predefined in the rule file, including checking whether the geometry, size, relative position, and electrical connections in the layout match the features described in the rule file, and then use the DRC tool to analyze each element in the layout to determine whether the element meets the specific parameters and layout requirements for the Silicide Block Layer in the rule file.

4. The method for preventing misconnection of GGNMOS in a layout according to claim 1, characterized in that: Based on the network list generation, the Dijkstra algorithm in graph theory is used to find the shortest path from the Silicide Block Layer to the Drain end, including: Set the node corresponding to the Silicide Block Layer as the starting node of the algorithm, set the distance from the starting node to itself to 0, initialize the distance to all other nodes to infinity, create a priority queue to store the nodes and their distance to the starting node, and sort them according to the distance; Select the node with the smallest distance from the priority queue as the current node. For all neighboring nodes of the current node, calculate the distance from the current node to the neighboring node and compare it with the recorded distance. If the newly calculated distance is shorter, update the distance and add the new distance and node back to the priority queue. Then mark the current node as visited until all nodes are visited or the Drain end node is reached. While updating the distance, the path information is recorded to track the shortest path from the starting node to each node, starting from the Drain end node, and tracing back to the Silicide Block Layer starting node through the recorded path information to reconstruct the entire shortest path; Output the shortest path from the Silicide Block Layer to the Drain end, including all nodes and edges on the path.

5. A method for preventing misconnection of GGNMOS in a layout according to claim 4, characterized in that: The distance from the current node to the neighboring node is calculated as: ,in Indicates the current node Arrival of neighboring nodes The shortest distance, is the set of all nodes in the graph, It is the previous node Arrival of neighboring nodes The weight of .

6. The method for preventing misconnection of GGNMOS in a layout according to claim 1, characterized in that: Optimizing and adjusting the circuit design based on the analysis results also includes: using a local anomaly factor algorithm to analyze the connected data and automatically discover anomalies that do not conform to the normal connection pattern; Extract connection data from the layout and select features; For each data point, determine the data point Nearest neighbors, and calculate the local density of neighbors, use the local density to calculate the LOF value of each point, and evaluate the density difference between each point and its neighbors; According to the calculated LOF value, a threshold is set to identify abnormal points. When the LOF value exceeds the threshold, the data point is considered abnormal and the abnormal point is marked; The detected abnormal points are analyzed in detail to determine the causes of the abnormalities and compared with the design specifications. Based on the analysis results, the circuit design is optimized and adjusted.

7. A method for preventing misconnection of GGNMOS in a layout according to claim 6, characterized in that: The LOF value of each point in the local density calculation is expressed as: ,in is the local outlier factor of point p, is the specified number of neighbors, Yes of Neighbor set, is the local density at point p, Yes Every neighbor of The local density of .

8. The inspection method for preventing misconnection of GGNMOS in a layout according to claim 1, characterized in that: Also includes: Generate misinterpretation area reports based on identification results and use Calibre RVE tools to review inspection results; The inspection results are displayed graphically.

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