Circuit module with improved time sequence control

Abstract

The invention discloses a circuit module with improved time sequence control. The circuit module comprises a functional circuit, a control circuit, a main auxiliary circuit and an additional auxiliary circuit, the control circuit controls the operation time sequence of the functional circuit according to the response characteristic of a first node. When the main auxiliary circuit is enabled, one or more main conductive paths can be provided between the first node and a base node. When the additional auxiliary circuit is enabled and disabled, one or more additional conductive paths can be provided or not provided between the first node and the base node. When the control circuit controls the operation time sequence of the functional circuit, the main auxiliary circuit is enabled, and the additional auxiliary circuit is disabled or enabled according to a mode signal which is a first mode level or a second mode level.

Description

Technical Field

[0001] The present invention relates to a circuit module with improved timing control, and in particular to a circuit module comprising a control circuit, a functional circuit, a main auxiliary circuit and an additional auxiliary circuit, such as a storage module comprising a storage unit; wherein the control circuit can control the operating timing of the functional circuit according to the response characteristics of a first node (such as the time required for the voltage to change from a certain level to another level), and when the main auxiliary circuit is enabled, one or more main conductive paths can be provided between the first node and a basic node, and when the additional auxiliary circuit is enabled or disabled, one or more additional conductive paths can be provided or not provided between the first node and the basic node; when the control circuit controls the operating timing of the functional circuit, the main auxiliary circuit can be enabled, and the additional auxiliary circuit can be disabled or enabled according to whether a mode signal is a first mode level; the main auxiliary circuit and / or the additional auxiliary circuit can include one or more modified memory cells. Background Art

[0002] Various circuit modules, such as silicon intellectual property or memory modules, are important basic building blocks of integrated circuits. A circuit module has one or more internal functional circuits, and generates one or more internal timing signals under the triggering of a clock to control the operation timing of the one or more functional circuits. Summary of the invention

[0003] In order to balance power consumption and performance, the circuit module of the present invention can switch between different operation modes, such as a high-performance mode with high clock and high voltage and a low-power mode with low clock and low voltage, and dynamically adjust the operation timing of the internal functional circuits in response to different modes.

[0004] One of the purposes of the present invention is to provide a circuit module (eg, 10, Figure 1a or Figure 2 The circuit module may include a functional circuit (eg, 40, Figure 1a or Figure 2 ), a control circuit (e.g. 20, Figure 1a or Figure 2 ), a main auxiliary circuit (such as 210, 310 or 910, Figure 2 , Figure 3a or Fig. 9 ) and an additional auxiliary circuit (e.g., 220, 320, 420 or 820, Figure 2 , Figure 3a , Figure 4a or Figure 8aThe control circuit may be coupled to the functional circuit and a first node (eg, n1, Figure 1a or Figure 2 ), the main auxiliary circuit can be coupled to the first node, and the additional auxiliary circuit can be coupled to the first node and a mode signal (such as dvs_sa_relax, Figure 1a or Figure 2 The control circuit can control the operation timing of the functional circuit according to the response characteristics of the first node. When the main auxiliary circuit is enabled, the first node and a basic node (such as n0, Figure 1a or Figure 2 ) provide one or more main conductive paths between the first node and the base node, and when disabled, the one or more main conductive paths may no longer be provided. When the additional auxiliary circuit is enabled, it can provide one or more additional conductive paths between the first node and the base node, and when disabled, the one or more additional conductive paths may no longer be provided. When the control circuit controls the operating timing of the functional circuit according to the response characteristics of the first node, the main auxiliary circuit is enabled, and the additional auxiliary circuit is a first mode level (e.g., v1, Figure 1b ) or a second mode level (e.g. v0, Figure 1b ) and disable or enable.

[0005] In one embodiment (for example Figure 1a or Figure 2 ), the circuit module may further include one or more word lines (e.g., WL[1] to WL[I]), one or more bit lines (e.g., BL[1] to BL[I'] and BL'[1] to BL'[I']), one or more memory cells (e.g., c[1,1] to c[I,I']), a following word line (e.g., TWL), a following bit line (e.g., TBL), and one or more following memory cells (e.g., tc[1] to tc[I]). Each of the memory cells (e.g., c[i,i']) may be coupled to one of the one or more word lines (e.g., WL[i]) and one of the one or more bit lines (e.g., BL[i']). Each of the following memory cells (e.g., tc[i]) may be coupled to the following bit line and one of the one or more word lines (e.g., WL[i]). The first node may further be coupled to the following bit line. The functional circuit may include one or more sense amplifiers (eg, sa[1] to sa[J]), each of which senses a voltage of one of the one or more bit lines according to the operating timing.

[0006] In one embodiment (for example Figure 3c ), the control circuit can control the operating timing of the functional circuit according to the response characteristics of the first node when the following word line is driven (for example, after tc0).

[0007] In one embodiment (for example Figure 3aand Figure 3b ), the main auxiliary circuit (e.g. 310, Figure 3a ) may include one or more first modified storage units (e.g., h[1,1] to h[K,K']). Each of the first modified storage units (e.g., h[k,k'], Figure 3b ) may include a pass-gate transistor (e.g., gd31[k, k']) and a data transistor (e.g., d31[k, k']). The data transistor may include a data-controlled terminal and two data channel terminals (e.g., a gate, a drain, and a source), and the pass-gate transistor may include a pass-gate controlled terminal and two pass-gate channel terminals (e.g., a gate, a drain, and a source). The two pass-gate channel terminals and the two data channel terminals may be connected in series between the first node and the base node; and one of the pass-gate controlled terminal and the data-controlled terminal may be coupled to the tracking word line, and the other may be coupled to a supply voltage (e.g., Vcc).

[0008] In one embodiment (for example Figure 3a ), the additional auxiliary circuit (e.g. 320, Figure 3a ) may include a front-stage transistor (e.g., L31) and a rear-stage transistor (e.g., L32). The front-stage transistor may include a front-stage controlled terminal and two front-stage channel terminals (e.g., a gate, a drain, and a source), and the rear-stage transistor may include a rear-stage controlled terminal and two rear-stage channel terminals (e.g., a gate, a drain, and a source). The two front-stage channel terminals and the two rear-stage channel terminals may be connected in series between the first node and the base node; one of the front-stage controlled terminal and the rear-stage controlled terminal may be coupled to the mode signal, and the other may be coupled to the tracking word line.

[0009] In one embodiment (for example Figure 3a ), the additional auxiliary circuit may further include an inverter (such as L33, Figure 3a ), one of the front-stage controlled end and the rear-stage controlled end is coupled to the mode signal via the inverter.

[0010] In one embodiment (for example Figure 4a and Figure 4b ), the additional auxiliary circuit (e.g. 420, Figure 4a ) may include one or more second modified storage units (e.g., u[1,1] to u[Q,Q'], Figure 4a ). Each of the second transformed storage units (e.g. u[q,q'], Figure 4b) may include a gate-pass transistor (e.g., gd41[q,q']) and a data transistor (d41[q,q']). The data transistor may include a data-controlled terminal and two data-channel terminals (e.g., a gate, a drain, and a source), and the gate-pass transistor may include a gate-pass controlled terminal and two gate-pass channel terminals (e.g., a gate, a drain, and a source). The two gate-pass channel terminals and the two data channel terminals may be connected in series between the first node and the base node, and one of the gate-pass controlled terminal and the data-controlled terminal may be coupled to the mode signal, and the other may be coupled to the tracking word line.

[0011] In one embodiment (for example Figure 4a and Figure 4b ), the additional auxiliary circuit may further include an inverter (eg, L41), and one of the gate-controlled end and the data-controlled end is coupled to the mode signal via the inverter.

[0012] In one embodiment (for example Figure 5 , Figure 6a or Figure 7a ), the circuit module further includes a calibration load (e.g., 550 or 650, Figure 5 or Figure 6a ) and a calibration switch circuit (e.g., 560, 660, or 760, Figure 5 , Figure 6a or Figure 7a The adjustment switch circuit may be coupled between the adjustment load and the first node, and may control whether to conduct the adjustment load to the first node according to an adjustment control signal (eg, sc1).

[0013] In one embodiment (for example Figure 6a or Figure 7a ), the calibration load may include at least one additional bit line (e.g., ABL) and one or more additional memory cells (e.g., ac[1] to ac[I]). Each of the additional memory cells (e.g., ac[i]) may be coupled to the additional bit line and one of the one or more word lines (e.g., WL[i]), and the calibration switch circuit couples the calibration load to the additional bit line.

[0014] In one embodiment (for example Figure 6a or Figure 7a ), the adjustment switch circuit (e.g., 660 or 760) may include a main switch (e.g., ss1). The main switch may be coupled between the first node and the adjustment load, and include a main switch control terminal (e.g., n8 or n10, Figure 6a or Figure 7a); when the logic value of the main switch control end is a first logic value (e.g., logic 1), the main switch can conduct the calibrated load to the first node; when the logic value of the main switch control end is a second logic value (e.g., logic 0), the main switch does not conduct the calibrated load to the first node.

[0015] In one embodiment (for example Figure 6a or Figure 7a ), the adjustment switch circuit (e.g., 660 or 760) may further include an additional switch (e.g., ss2) coupled between the main switch control terminal, the adjustment load, and a supply voltage (e.g., Vcc). When the logic value of the main switch control terminal is the second logic value, the additional switch may conduct the adjustment load to the supply voltage; when the logic value of the main switch control terminal is the first logic value, the additional switch does not conduct the adjustment load to the supply voltage.

[0016] In one embodiment (for example Figure 7a ), the adjustment switch circuit (e.g., 760) may further include an adjustment logic circuit (e.g., 770). The adjustment logic circuit may include a first logic input terminal (e.g., n1), a second logic input terminal (e.g., n8), and a logic output terminal (e.g., n10), which are respectively coupled to the first node, the adjustment control signal, and the main switch control terminal.

[0017] In one embodiment (for example Figure 7a and Figure 7b ), the adjustment logic circuit can be based on whether the voltage of the first logic input terminal is greater than a adjustment logic trip point level (for example, vp_L72, Figure 7b ) determines whether the logic value of the first logic input terminal is the first logic value or the second logic value, and determines the logic value of the logic output terminal according to the logic values ​​of the first logic input terminal and the second logic input terminal. The control circuit can determine whether the voltage of the first node is greater than a control logic inversion point level (e.g., vp_20, Figure 7b ) determines that the logic value of the first node is the first logic value or the second logic value. And, the adjustment logic reversal point level is different from the control logic reversal point level.

[0018] In one embodiment (for example Figure 7b ), the adjustment logic reversal point level is higher than the control logic reversal point level.

[0019] In one embodiment (for example Figure 7a ), the calibration logic circuit may further include a dual-input NAND gate (eg, L72) and an inverter (eg, L73).

[0020] In one embodiment (for example Figure 7b), the response characteristic of the first node may be related to a period (e.g., Ti3) during which the voltage of the first node changes from an initial level (e.g., v31) to a reference level (e.g., vp_20). There may be an intermediate level (e.g., vp_L72) between the initial level and the reference level. When the tuning switch circuit controls whether to conduct the tuning load to the first node according to the tuning control signal, the tuning switch circuit controls whether to conduct the tuning load to the first node according to whether the tuning control signal is a first logic value (e.g., logic 1) during the period when the voltage of the first node changes from the initial level to the intermediate level (e.g., Ti1). During the period when the voltage of the first node changes from the intermediate level to the reference level (e.g., Ti2), the tuning switch circuit may stop conducting the tuning load to the first node, regardless of whether the tuning control signal is the first logic value.

[0021] In one embodiment (for example Figure 7b ), the response characteristic of the first node may be related to a period (e.g., Ti3) during which the voltage of the first node changes from an initial level (e.g., v31) to a reference level (e.g., vp_20). When the tuning switch circuit controls whether to conduct the tuning load to the first node according to the tuning control signal, the tuning switch circuit controls whether to conduct the tuning load to the first node during a first part (e.g., Ti1) of the period according to whether the tuning control signal is a first logic value. During a second part (e.g., Ti2) of the period, the tuning switch circuit may stop conducting the tuning load to the first node, regardless of whether the tuning control signal is the first logic value.

[0022] In one embodiment (for example Figure 1a and Figure 1b ), the circuit module can be powered by a supply voltage (such as Vcc, Figure 1a ) is used for power supply. When the supply voltage is a first voltage value (e.g., vcc1, Figure 1b ), the mode signal may be the first mode level; when the supply voltage is a second voltage value (eg, vcc0, Figure 1b ), the mode signal may be the second mode level. The first voltage value and the second voltage value may be different; for example, the first voltage value may be lower than the second voltage value.

[0023] In one embodiment (for example Figure 1a and Figure 1b ), the circuit module can be driven by a clock (such as CK1, Figure 1a ) is triggered. When the period of the clock is a first period value (for example, T1, Figure 1b ), the mode signal may be the first mode level; when the period of the clock is a second period value (eg, T0, Figure 1b), the mode signal may be the second mode level, and the first cycle value and the second cycle value may be different; for example, the first cycle value may be greater than the second cycle value.

[0024] In one embodiment (for example Figure 3c ), when the mode signal maintains the first mode level, the time for the voltage of the first node to change from an initial level (e.g., v31) to a reference level (e.g., v30) is a first time value (e.g., T11); when the mode signal maintains the second mode level, the time for the voltage of the first node to change from the initial level to the reference level is a second time value (e.g., T00). The operating timing may be associated with a timing parameter, a tolerance of the timing parameter may include a second tolerance value and a first tolerance value, the second tolerance value may be related (e.g., positively correlated) to the second time value, and the first tolerance value may be related (e.g., positively correlated) to the first time value.

[0025] One of the purposes of the present invention is to provide a circuit module (eg, 10, Figure 1a or Figure 2 ) has a method for improving timing control. The circuit module may include a functional circuit (eg, 40, Figure 1a or Figure 2 ), a control circuit (e.g. 20, Figure 1a or Figure 2 ), a main auxiliary circuit (such as 210, 310 or 910, Figure 2 , Figure 3a or Fig. 9 ) and an additional auxiliary circuit (e.g., 220, 320, 420 or 820, Figure 2 , Figure 3a , Figure 4a or Figure 8a The control circuit may be coupled to the functional circuit and a first node (eg, n1, Figure 1a or Figure 2 ), the main auxiliary circuit can be coupled to the first node, and the additional auxiliary circuit can be coupled to the first node and a mode signal (such as dvs_sa_relax, Figure 1a or Figure 2 When the main auxiliary circuit is enabled, the first node and a basic node (eg, n0, Figure 1a or Figure 2) when enabled, and the one or more main conductive paths may no longer be provided when disabled. The additional auxiliary circuit may provide one or more additional conductive paths between the first node and the base node when enabled, and the one or more additional conductive paths may no longer be provided when disabled. The method may include: enabling the control circuit to control the operating timing of the functional circuit according to the response characteristics of the first node; when enabling the control circuit to control the operating timing of the functional circuit according to the response characteristics of the first node, enabling the main auxiliary circuit, and determining whether the mode signal is a first mode level (e.g., v1, Figure 1b ) disables or enables the additional auxiliary circuit.

[0026] In order to better understand the above and other aspects of the present invention, the following embodiments are specifically described in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1a The circuit module according to one embodiment of the present invention is shown, which may include one or more memory cells, one or more follower memory cells and an auxiliary circuit set, may be powered by a supply voltage, and may receive one or more mode signals and a clock.

[0028] Figure 1b Hint Figure 1a An embodiment of the waveform timing of the clock, supply voltage and mode signal in FIG.

[0029] Figure 1c Hint Figure 1a An embodiment of a storage unit in FIG.

[0030] Figure 1d Hint Figure 1a An embodiment of a following storage unit.

[0031] Figure 2 The auxiliary circuit set according to one embodiment of the present invention can be used to implement Figure 1a The auxiliary circuit set in the device may include two auxiliary circuits.

[0032] Figure 3a The two auxiliary circuits according to one embodiment of the present invention can respectively realize Figure 2 The invention also provides two auxiliary circuits in the invention and may include one or more modified storage units.

[0033] Figure 3b It indicates Figure 3a An embodiment of transforming a storage unit.

[0034] Figure 3c It indicates Figure 3a The waveform timing of the relevant signals in different scenarios.

[0035] Figure 4a The two auxiliary circuits according to one embodiment of the present invention can respectively realize Figure 2 The invention also provides two auxiliary circuits in the invention and may include one or more modified storage units.

[0036] Figure 4b It indicates Figure 4a An embodiment of a storage unit modified in.

[0037] Figure 5 The auxiliary circuit set according to one embodiment of the present invention can be used to implement Figure 1a The auxiliary circuit set may include two auxiliary circuits, a calibration load and a calibration switch circuit.

[0038] Figure 6a The diagram shows that the load adjustment and switch adjustment circuit according to an embodiment of the present invention can respectively implement Figure 5 The calibrated load and the calibrated switch circuit are provided; wherein the calibrated load may include one or more additional storage units.

[0039] Figure 6b It indicates Figure 6a An embodiment of an additional storage unit.

[0040] Figure 6c It indicates Figure 6a The waveform timing of the relevant signals in different scenarios.

[0041] Figure 7a The diagram shows that the load adjustment and switch adjustment circuit according to an embodiment of the present invention can respectively implement Figure 5 The calibrated load and calibrated switch circuit in.

[0042] Figure 7b It indicates Figure 7a The operation of the switching circuit is calibrated.

[0043] Figure 8a The two auxiliary circuits according to one embodiment of the present invention can respectively realize Figure 2 or Figure 5 The invention also provides two auxiliary circuits in the invention and may include one or more modified storage units.

[0044] Figure 8b It indicates Figure 8a An embodiment of a storage unit modified in.

[0045] Fig. 9 The two auxiliary circuits according to one embodiment of the present invention can respectively realize Figure 2 or Figure 5 Two auxiliary circuits in.

[0046] The reference numerals are described as follows:

[0047] 10: Circuit module

[0048] 20: Control circuit

[0049] 30: Peripheral circuit

[0050] 40: Functional Circuit

[0051] 100, 200, 500: Auxiliary circuit set

[0052] 210, 220, 310, 320, 420, 820, 910: Auxiliary circuit

[0053] 550, 650: Adjust the load

[0054] 560, 660, 760: Adjust the switch circuit

[0055] 770: Adjusting logic circuits

[0056] a1[i,i'], a2[i,i'], a3[i,i'], a4[i,i'], b1[i], b2[i], b3[i], b4[i], d31[k,k'],

[0057] d32[k,k'], d33[k,k'], d34[k,k'], d41[q,q'], d42[q,q'], d43[q,q'], d44[q,q'], d61[i],

[0058] d62[i], d63[i], d64[i], d81[q,q'], d82[q,q'], d83[q,q'], d84[q,q'], ga1[i,i'],

[0059] ga2[i,i'], gb1[i], gb2[i], gd31[k,k'], gd32[k,k'], gd41[q,q'], gd42[q,q'], gd61[i],

[0060] gd62[i], gd81[q,q'], gd82[q,q'], L31, L32: transistors

[0061] ABL, ABL': Additional bit lines

[0062] ac[1], ac[i], ac[I]: additional storage units

[0063] BL[1], BL'[1], BL[i'], BL'[i'], BL[I'], BL'[I']: bit lines

[0064] c[1,1], c[1,i'], c[1,I'], c[i,1], c[i,i'], c[i,I'], c[I,1], c[I,i'], c[I,I']: storage unit

[0065] CK1: Clock

[0066] Dt1, Dt2: delay time

[0067] dvs_rawa_assert, dvs_sa_relax, s1: signal

[0068] Gnd: ground voltage

[0069] h[1,1],h[1,k'],h[1,K'],h[k,1],h[k,k'],h[k,K'],h[K,1],h[K,k'],h[K, K'], h[1,q'], h[1,Q'], h[k,q'], h[k,Q'], h[K,q'], h[K,Q'], u[1,1], u[1,q' ],u[1,Q'],u[q,1],u[q,q'],u[q,Q'],u[Q,1],u[Q,q'],u[Q,Q'],z[1,1],z[ 1,q'], z[1,Q'], z[q,1], z[q,q'], z[q,Q'], z[Q,1], z[Q,q'], z[Q,Q']: Modify the memory unit

[0070] hBL[1], hBL[q'], hBL[Q']: connection

[0071] L33, L41, L61, L71, L73, L81, L83: Inverters

[0072] L72, L82: NAND gate

[0073] n0 to n12, n81, n82, n83, na1[i,i'], na2[i,i'], nb1[i], nb2[i], nb3[i], nd31[k,k'], nd32[k,k'], nd33[k,k'], nd34[k,k'], nd35[k,k'], nd36[k,k'], nd41[q,q'], nd42[ q,q'], nd43[q,q'], nd44[q,q'], nd45[q,q'], nd46[q,q'], nd61[i], nd62[i], nd63[ i], nd81[q,q'], nd82[q,q'], nd83[q,q'], nd84[q,q'], nd85[q,q'], nd86[q,q']: nodes

[0074] sa[1], sa[j], sa[J]: sense amplifier

[0075] sc1: Adjust control signal

[0076] ss1: main switch

[0077] ss2: Additional switches

[0078] T: period

[0079] T0, T1: period value

[0080] T00, T01, T10, T11, T00n, T11n: time value

[0081] Ti1, Ti2, Ti3: Period

[0082] Time points: t1 to t9, tb0 to tb6, tc0, td00, td01, td10, td11, tn00, tn11, tx01, tx10, ti1, ti2

[0083] TBL, TBL': Follow the Bit Line

[0084] tc[1], tc[i], tc[I]: follow the storage unit

[0085] TC1: Running Round

[0086] TWL: Follow the Character Line

[0087] v0, v1, v30, v31, vw30, vw31: Level

[0088] vp_20: Control logic reversal point level

[0089] vp_L72: Adjust the logic reversal point level

[0090] Vcc: supply voltage

[0091] vcc0, vcc1: voltage value

[0092] vTBL, vTBL00, vTBL00n, vTBL01, vTBL10, vTBL11, vTBL11n, vTWL: Waveforms

[0093] WL[1], WL[i], WL[I]: word line DETAILED DESCRIPTION

[0094] Figure 1aThe circuit module 10 according to one embodiment of the present invention is shown. For example, the circuit module 10 may be a memory module, such as a static random access memory module embedded in a processor chip. The circuit module 10 may be triggered by a clock CK1, and may be biased between a supply voltage Vcc and a ground voltage Gnd, and powered by the supply voltage Vcc. The circuit module 10 may operate in different modes and receive one or more mode signals related to the operating mode, such as signals dvs_sa_relax and dvs_rawa_assert. In different modes, the period value of the clock CK1 and / or the voltage value of the supply voltage Vcc may be different.

[0095] Figure 1b The waveform timing of the supply voltage Vcc, the clock CK1, and the signals dvs_sa_relax and dvs_rawa_assert are shown in FIG. Figure 1b As shown, during the time period from tb0 to tb1, the period T of the clock CK1 may be a period value T0, the value of the supply voltage Vcc may be a voltage value vcc0, and the signals dvs_sa_relax and dvs_rawa_assert may be a level v0.

[0096] Between time points tb1 and tb2, the period T of the clock CK1 may be switched to another period value T1, and the value of the supply voltage Vcc may be maintained at the voltage value vcc0; wherein the period values ​​T1 and T0 may be different. For example, the period value T1 may be greater than the period value T0; that is, the clock CK1 may be switched from the original higher frequency (1 / T0) to the lower frequency (1 / T1) after time point tb1. Furthermore, between time points tb1 and tb2, the signal dvs_sa_relax may be switched from the level v0 to another different level v1 at time point t1 to t2; after a delay time Dt1, the signal dvs_rawa_assert may be switched from the level v0 to the level v1 at time point t3 to t4. In one embodiment, the levels v0 and v1 may correspond to logic 0 and logic 1, respectively.

[0097] Between time points tb2 and tb3, the period T of clock CK1 can be maintained at period value T1, and the value of supply voltage Vcc can be switched from voltage value vcc0 to another different voltage value vcc1; for example, voltage value vcc1 can be lower than voltage value vcc0. Signals dvs_sa_relax and dvs_rawa_assert can be maintained at level v1.

[0098] Between time points tb3 and tb4, the period T of the clock CK1 can be maintained at period value T1, the supply voltage Vcc can be maintained at voltage value vcc1, and the signals dvs_sa_relax and dvs_rawa_assert can be maintained at level v1. Before time point tb1, the circuit module 10 originally operates at period value T0 and voltage value vcc0 (such as a high-performance mode); after the handover preparation between time points tb1 and tb3, the circuit module 10 can operate at period value T1 and voltage value vcc1 (such as a low-power mode) after time point tb3.

[0099] During the time period from tb4 to tb5, the period T of the clock CK1 can be maintained at the period value T1, the value of the supply voltage Vcc can be switched from the voltage value vcc1 back to vcc0, and the signals dvs_sa_relax and dvs_rawa_assert can be maintained at the level v1.

[0100] Between time points tb5 and tb6, the period T of the clock CK1 can be maintained at period value T1, and the value of the supply voltage Vcc can be maintained at voltage value vcc0. Furthermore, between time points tb5 and tb6, the signal dvs_rawa_assert can be switched from level v1 to level v0 at time points t5 to t6; after a delay time Dt2, the signal dvs_sa_relax can be switched from level v1 to level v0 at time points t7 to t8.

[0101] After time point tb6, the period T of clock CK1 can be switched back to period value T0, the value of supply voltage Vcc can be maintained at voltage value vcc0, and signals dvs_sa_relax and dvs_rawa_assert can be maintained at level v0. Between time point tb3 and tb4, circuit module 10 originally operates at period value T1 and voltage value vcc1; after handover preparation between time point tb4 and tb6, circuit module 10 can switch to operate at period value T0 and voltage value vcc0 after time point tb6. Figure 1b It can be seen that the level switching of the signals dvs_sa_relax and dvs_rawa_assert is related to the operation mode switching of the circuit module 10 .

[0102] Back to Figure 1a ;like Figure 1aAs shown, the circuit module 10 may include I word lines WL[1] to WL[I], I' groups of bit lines BL[1] to BL[I'] and BL'[1] to BL'[I'], I*I' memory cells c[1,1] to c[I,I'], a following word line TWL, a group of following bit lines TBL and TBL', I following memory cells tc[1] to tc[I], J sense amplifiers sa[1] to sa[J], a control circuit 20 and a peripheral circuit 30. The sense amplifiers sa[1] to sa[J] may serve as an internal functional circuit 40 in the circuit module 10. Figure 1a In the embodiment, each number I, I' and J can be an integer constant greater than or equal to one; the number J can be equal to, greater than or less than the number I, and the number I' can be greater than or equal to the number J. Each memory cell c[i, i'] (for subscript i=1 to I, subscript i'=1 to I') can be coupled to the corresponding word line WL[i] and the corresponding bit lines BL[i'] and BL'[i']. Each following memory cell tc[i] (for subscript i=1 to I) can be coupled to the word line WL[i] and the following bit lines TBL and TBL'. The word lines WL[1] to WL[I], the bit lines BL[1] to BL[I'] and BL'[1] to BL'[I'], the following word lines TWL and the sense amplifiers sa[1] to sa[J] can also be coupled to the peripheral circuit 30. The control circuit 20 may be coupled to the clock CK1 , the peripheral circuit 30 , and the functional circuit 40 , and may be coupled to the tracking bit line TBL at a node n1 .

[0103] In order to implement the present invention, the circuit module 10 may further include an auxiliary circuit set 100. The auxiliary circuit set 100 may be coupled to the tracking bit line TBL at the node n1, and may be coupled to the ground voltage Gnd, the tracking word line TWL and the signal dvs_sa_relax at the other three nodes n0, n2 and n3, respectively. The circuit module 10 may further include other circuits, and / or may further input and / or output other signals (such as addresses to be accessed, data to be written and / or data to be read, etc.), but they are not described in detail for the sake of brevity.

[0104] exist Figure 1a In the circuit module 10, each storage cell c[i,i'] can store one bit of data. Figure 1c The figure shows an embodiment of a storage unit c[i,i']. Figure 1cAs shown, the memory cell c[i,i'] may include transistors ga1[i,i'] and ga2[i,i'] (as pass transistors) and transistors a1[i,i'] to a4[i,i'] (as data transistors). The transistors ga1[i,i'], ga2[i,i'], a1[i,i'] and a2[i,i'] may be n-channel metal oxide semiconductor transistors, and the transistors a3[i,i'] and a4[i,i'] may be p-channel metal oxide semiconductor transistors. The transistor ga1[i,i'] may include a controlled terminal and two channel terminals (such as a gate, a drain and a source), which are respectively coupled to the word line WL[i], the bit line BL[i'] and a node na1[i,i']. The transistor ga2[i,i'] may include a controlled end and two channel ends, respectively coupled to the word line WL[i], the bit line BL'[i'] and another node na2[i,i']. The transistor a1[i,i'] may include a controlled end and two channel ends (such as a gate, a drain and a source), respectively coupled to the nodes na2[i,i'], na1[i,i'] and the ground voltage Gnd. The transistor a2[i,i'] may include a controlled end and two channel ends, respectively coupled to the nodes na1[i,i'], na2[i,i'] and the ground voltage Gnd. The transistor a3[i,i'] may include a controlled end and two channel ends (such as a gate, a drain and a source), respectively coupled to the nodes na2[i,i'], na1[i,i'] and the supply voltage Vcc. Transistor a4[i,i'] may include a controlled terminal and two channel terminals, respectively coupled to nodes na1[i,i'], na2[i,i'] and supply voltage Vcc. When word line WL[i] is driven (i.e., when the voltage of word line WL[i] is driven from a level that can make transistors ga1[i,i'] and ga2[i,i'] non-conductive to another level that can make transistors ga1[i,i'] and ga2[i,i'] conductive), pass transistors ga1[i,i'] and ga2[i,i'] will respectively connect nodes na1[i,i'] and na2[i,i'] (which can be regarded as two storage nodes) to bit lines BL[i'] and BL'[i']. When the word line WL[i] is not driven, the pass transistors ga1[i,i'] and ga2[i,i'] do not conduct the nodes na1[i,i'] and na2[i,i'] to the bit lines BL[i'] and BL'[i'].

[0105] Back to Figure 1a ;exist Figure 1a In the circuit module 10, each follower memory cell tc[i] can reflect (follow) the electrical characteristics of each memory cell c[i,i']. Figure 1d The following is an embodiment of the following storage unit tc[i]. Figure 1dAs shown, the following memory cell tc[i] may include transistors gb1[i] and gb2[i] (as pass transistors) and transistors b1[i] to b4[i] (as data transistors). Transistors gb1[i], gb2[i], b1[i] and b2[i] may be n-channel metal oxide semiconductor transistors, and transistors b3[i] and b4[i] may be p-channel metal oxide semiconductor transistors. Transistor gb1[i] may include a controlled terminal and two channel terminals, respectively coupled to the ground voltage Gnd, the following bit line TBL and a node nb3[i]. Transistor gb2[i] may include a controlled terminal and two channel terminals, respectively coupled to the word line WL[i], the following bit line TBL' and another node nb2[i]. Transistor b1[i] may include a controlled terminal and two channel terminals, respectively coupled to nodes nb2[i], nb3[i] and the ground voltage Gnd. Transistor b2[i] may include a controlled terminal and two channel terminals, respectively coupled to nodes nb1[i], nb2[i] and ground voltage Gnd. Transistor b3[i] may include a controlled terminal and two channel terminals, respectively coupled to nodes nb2[i], node nb1[i] and supply voltage Vcc. Transistor b4[i] may include a controlled terminal and two channel terminals, respectively coupled to nodes nb1[i], node nb2[i] and supply voltage Vcc. When word line WL[i] is driven, pass transistor gb2[i] will conduct node nb2[i] to following bit line TBL'. When following word line TWL is not driven, pass transistor gb2[i] will not conduct node nb2[i] to following bit line TBL'.

[0106] exist Figure 1d The following storage unit tc[i] and Figure 1c In the storage unit c[i,i'], Figure 1d Transistors b1[i], b2[i] and Figure 1c The transistors a1[i,i'] and a2[i,i'] may be matched to each other; for example, the dimensions (such as channel length and / or width) of the transistors b1[i], b2[i], a1[i,i'] and a2[i,i'] may be substantially equal, and the doped regions used to form the channels may be formed in the same semiconductor layer. And / or, Figure 1d Transistors b3[i], b4[i] and Figure 1c The transistors a3[i,i'] and a4[i,i'] may be matched to each other; for example, the sizes of the transistors b3[i], b4[i], a3[i,i'] and a4[i,i'] may be substantially equal, and the doped regions for forming the channels may be formed in the same semiconductor layer. And / or, Figure 1d Transistors gb1[i], gb2[i] and Figure 1cThe transistors ga1[i,i'] and ga2[i,i'] may be matched with each other; for example, the sizes of the transistors gb1[i], gb2[i], ga1[i,i'] and ga2[i,i'] may be substantially equal, and the doping regions for forming the channels may be formed in the same semiconductor layer. Due to the above transistor matching arrangement, the load formed by the following memory cells tc[1] to tc[I] on the following bit line TBL may reflect the load formed by the memory cells c[1,i'] to c[I,i'] on the bit lines BL[i'] and BL'[i'].

[0107] Back to Figure 1a ;exist Figure 1a In the circuit module 10, the control circuit 20 can control the internal operation timing of the circuit module 10 according to the clock CK1. For example, when the data stored in a certain memory cell c[i,i'] is to be read, the control circuit 20 can start a read cycle triggered by the rising edge of the clock CK1, and control the peripheral circuit 30, so that the peripheral circuit 30 turns on the corresponding bit lines BL[i'] and BL'[i'] to one of the sense amplifiers sa[1] to sa[J], and drives the following word line TWL, and also drives the word line WL[i]. As the word line WL[i] is driven, the memory cell c[i,i'] can be enabled, that is, the gate transistors ga1[i,i'] and ga2[i,i'] ( Figure 1c ) can respectively conduct the storage nodes na1[i,i'] and na2[i,i'] to the corresponding bit lines BL[i'] and BL'[i']. When the following word line TWL is driven and the word line WL[i] is driven, the control circuit 20 can further provide a signal s1 according to the response characteristics of the node n1 (for example, the time taken for the voltage of the node n1 to change from one level to another) to control the operation timing of the sense amplifiers sa[1] to sa[J] in the functional circuit 40, for example, when to start enabling the sense amplifiers sa[1] to sa[J] for sensing, and when to stop enabling the sense amplifiers sa[1] to sa[J] for stopping sensing. After the memory cell c[i,i'] is enabled, when the control circuit 20 enables the sense amplifiers sa[1] to sa[J] with the signal s1, the sense amplifier sa[j] can sense the data stored in the memory cell c[i,i'] via the bit lines BL[i'] and BL'[i']. There may be a time difference between “the time of driving the word line WL[i] to enable the memory cell c[i,i′]” and “the time of enabling the sensor sa[j]”, and this time difference may be referred to as a memory cell read time.

[0108] To correctly sense the data of the bit lines BL[i'] and BL'[i'], the operation timing (e.g., the time to start enabling and / or the time to stop enabling) of the sense amplifier sa[j] needs to match the response of the memory cell c[i,i'] on the bit lines BL[i'] and BL'[i'] after the word line WL[i] is driven. Under the arrangement of the present invention, the response characteristics of the following bit lines TBL and TBL' after the following word line TWL is driven can reflect the response of the memory cell c[i,i'] on the bit lines BL[i'] and BL'[i'] after the word line WL[i] is driven. Therefore, when the control circuit 20 controls the sense amplifier sa[j] in the functional circuit 40 according to the response characteristics of the node n1, the control circuit 20 can make the operation timing of the sense amplifier sa[j] match the response of the bit lines BL[i'] and BL'[i'].

[0109] However, if Figure 1b As shown in FIG. 1 , the circuit module 10 can operate in different modes; in different modes, the period value of the clock CK1 and / or the voltage value of the supply voltage Vcc are also different. Therefore, the internal operation timing of the circuit module 10 and one or more related timing parameters, such as the aforementioned storage unit read time, should also be dynamically and adaptively adjusted according to the different modes, so that the circuit module 10 can operate correctly in different modes. For example, when the period value of the clock CK1 is shorter and / or the voltage value of the supply voltage Vcc is higher (for example, Figure 1b The memory cell read time can be set to a shorter time. In contrast, when the cycle value of the clock CK1 is longer and / or the voltage value of the supply voltage Vcc is lower (e.g. Figure 1b In the example of the time point tb3 to tb4 in the present invention, the storage unit read time can be set to a longer period of time. Furthermore, the internal operation timing and related timing parameters of the circuit module 10 may also need to be adjusted due to other factors, such as process drift. Figure 1a ), the auxiliary circuit set 100 coupled to the node n1 can change and adjust the response characteristics of the node n1 according to different requirements (e.g., different modes and / or different process drifts, etc.). In this way, when the control circuit 20 controls the operating timing of the functional circuit 40 according to the response characteristics of the node n1, the control circuit 20 can adaptively and dynamically adjust the operating timing and related timing parameters, such as the storage unit read time, according to different requirements.

[0110] Figure 2 The auxiliary circuit set 200 according to one embodiment of the present invention is shown, which can be used to implement Figure 1a The auxiliary circuit set 100 in the circuit module 10. Figure 2As shown, the auxiliary circuit set 200 may include two auxiliary circuits 210 and 220. The auxiliary circuit 210 may be a main auxiliary circuit, and may be coupled to the ground voltage Gnd, the following bit line TBL, and the following word line TWL at nodes n0, n1, and n2, respectively. The auxiliary circuit 220 may be an additional auxiliary circuit, and may be coupled to the ground voltage Gnd, the following bit line TBL, the following word line TWL, and the signal dvs_sa_relax at nodes n0, n1, n2, and n3, respectively.

[0111] In one embodiment, the auxiliary circuit 210 can be enabled when the following word line TWL is driven. When the auxiliary circuit 210 is enabled, one or more parallel main conductive paths can be provided between nodes n1 and n0. When the following word line TWL is driven, if the signal dvs_sa_relax is at level v0 ( Figure 1b ), the auxiliary circuit 220 may be enabled and provide one or more parallel additional conductive paths between the nodes n1 and n0; the one or more additional conductive paths and the one or more main conductive paths provided by the auxiliary circuit 210 may be connected in parallel with each other. On the other hand, when the following word line TWL is driven, if the signal dvs_sa_relax is at the level v1, the auxiliary circuit 220 may be disabled and stop providing the one or more additional conductive paths between the nodes n1 and n0.

[0112] Figure 3a The auxiliary circuits 310 and 320 according to an embodiment of the present invention can respectively implement Figure 2 The auxiliary circuits 210 and 220 in FIG. Figure 3a As shown, the auxiliary circuit 310 may include K*K' modified memory cells h[1,1] to h[K,K'], wherein the number K and K' may be integer constants greater than or equal to 1. Each modified memory cell h[k,k'] (for subscript k=1 to K, subscript k'=1 to K') may be coupled to nodes n0, n1 and n2.

[0113] Figure 3b It indicates Figure 3aAn embodiment of a modified memory cell h[k,k'] in the embodiment. The modified memory cell h[k,k'] may include transistors gd31[k,k'], gd32[k,k'] and transistors d31[k,k'] to d34[k,k']. The transistors gd31[k,k'], gd32[k,k'], d31[k,k'] and d32[k,k'] may be n-channel metal oxide semiconductor transistors, and the transistors d33[k,k'] and d34[k,k'] may be p-channel metal oxide semiconductor transistors. The transistor gd31[k,k'] may be a pass transistor, and may include a controlled terminal and two channel terminals (such as a gate, a drain and a source), which are respectively coupled to a node n2 (following a word line TWL), a node n1 (following a bit line TBL) and a node nd31[k,k']. The transistor gd32[k,k'] may include a controlled terminal and two channel terminals, which are respectively coupled to the three nodes nd35[k,k'], nd36[k,k'] and nd32[k,k']. The transistor d31[k,k'] may be a data transistor, and may include a controlled terminal and two channel terminals (such as a gate, a drain and a source), which are respectively coupled to the supply voltage Vcc, the node nd31[k,k'] and the node n0 (ground voltage Gnd). The transistor d32[k,k'] may include a controlled terminal and two channel terminals, which are respectively coupled to a node nd33[k,k'], the node nd32[k,k'] and the node n0. The transistor d33[k,k'] may include a controlled terminal and two channel terminals (such as a gate, a drain and a source), which are respectively coupled to the supply voltage Vcc, the node nd33[k,k'] and the supply voltage Vcc. The transistor d34[k, k'] may include a controlled terminal and two channel terminals, respectively coupled to the node nd33[k, k'], another node nd34[k, k'] and the supply voltage Vcc. The nodes nd31[k, k'] to nd34[k, k'] may be insulated from each other. In one embodiment, the number I( Figure 1a ) and the number K( Figure 3a ) may be equal, and the node nd35[k, k'] may be coupled to the word line WL[k] for every index k=1 to K. In one embodiment, the node nd36[k, k'] may be floating.

[0114] In the modified memory cell h[k, k'], when the following word line TWL is driven, the transistor gd31[k, k'] can conduct the node n1 to the node nd31[k, k']; since the controlled terminal (gate) of the transistor d31[k, k'] is coupled to the supply voltage Vcc, the transistor d31[k, k'] can conduct the node nd31[k, k'] to the node n0. Therefore, when the following word line TWL is driven, the transistors gd31[k, k'] and d31[k, k'] that are turned on in the modified memory cell h[k, k'] can provide a conductive path between the nodes n1 and n0. In contrast, when the following word line TWL is not driven, the transistor gd31[k, k'] is turned off and is not turned on, and the modified memory cell h[k, k'] does not provide a conductive path between the nodes n1 and n0.

[0115] Based on the operation of each modified memory cell h[k, k'], when the following word line TWL is driven, the auxiliary circuit 310 ( Figure 3a ) can be enabled, and the modified memory cells h[1,1] to h[K,K'] can provide K*K' parallel conductive paths between nodes n1 to n0 as the main conductive paths. When the following word line TWL is not driven, the auxiliary circuit 310 can be disabled and does not provide the K*K' conductive paths between nodes n1 to n0.

[0116] exist Figure 3b Transform storage unit h[k,k'] and Figure 1c In the storage unit c[i,i'], Figure 3b Transistors d31[k,k'], d32[k,k'] and Figure 1c The data transistors a1[i,i'] and a2[i,i'] may be matched with each other; for example, the dimensions (such as channel length and / or width) of the transistors d31[k,k'], d32[k,k'], a1[i,i'] and a2[i,i'] may be substantially equal, and the doped regions used to form the channels may also be formed in the same semiconductor layer. And / or, Figure 3b Transistors d33[k,k'] and d34[k,k'] and Figure 1c Data transistors a3[i,i'] and a4[i,i'] may be matched with each other; for example, the sizes of transistors d33[k,k'], d34[k,k'], a3[i,i'] and a4[i,i'] may be substantially equal, and the doped regions for forming the channel may be formed in the same semiconductor layer. And / or, Figure 3b Transistors gd31[k,k'], gd32[k,k'] and Figure 1cThe pass transistors ga1[i,i'] and ga2[i,i'] can be matched to each other; for example, the sizes of the transistors gd31[k,k'], gd32[k,k'], ga1[i,i'] and ga2[i,i'] can be substantially equal, and the doped regions used to form the channels can be formed in the same semiconductor layer. That is, the transistors included in the modified memory cell h[k,k'] and the transistors included in the memory cell c[i,i'] can be of the same specifications, with the same layout, structure and electronic characteristics. On the other hand, Figure 1c and Figure 3b It can be seen that the internal connections between transistors of the storage cell c[i,i'] and the internal connections between transistors of the modified storage cell h[k,k'] can be different; for example, Figure 1c In the embodiment, the drain of transistor a1[i,i'] can be coupled to the drain of transistor a3[i,i'], and the gate of transistor a1[i,i'] can be insulated from the supply voltage Vcc; Figure 3b In the embodiment, the drain of the transistor d31 [k, k′] may be insulated from the drain of the transistor d33 [k, k′], and the gate of the transistor d31 [k, k′] may be coupled to the supply voltage Vcc.

[0117] Back to Figure 3a ;like Figure 3aAs shown, the auxiliary circuit 320 may include an inverter L33 and two transistors L31 and L32. The transistors L31 and L32 may be n-channel metal oxide semiconductor transistors. The transistor L31 may include a controlled terminal and two channel terminals (such as a gate, a drain and a source), respectively coupled to a node n4, a node n1 (following the bit line TBL) and another node n5. The transistor L32 may include a controlled terminal and two channel terminals, respectively coupled to a node n2 (following the word line TWL), a node n5 and a node n0 (ground voltage Gnd). The inverter L33 may include an input terminal and an output terminal, respectively coupled to nodes n3 and n4. When the following word line TWL is driven, if the signal dvs_sa_relax is at level v0, the transistors L31 and L32 will both be turned on, the auxiliary circuit 320 may be enabled, and a conductive path is provided between nodes n1 and n0 as an additional conductive path. When the following word line TWL is driven, if the signal dvs_sa_relax is at level v1, the transistor L31 is not turned on, and the auxiliary circuit 320 can be disabled and no longer provide a conductive path between the nodes n1 and n0. When the following word line TWL is driven, if the signal dvs_sa_relax is switched from level v0 to level v1, the additional auxiliary circuit 320 can be switched from enabled (providing a conductive path) to disabled (not providing a conductive path). When the following word line TWL is driven, if the signal dvs_sa_relax is switched from level v1 to level v0, the additional auxiliary circuit 320 can be switched from disabled (not providing a conductive path) to enabled (providing a conductive path). When the following word line TWL is not driven, the auxiliary circuit 320 can be disabled.

[0118] In one embodiment of the present invention, the channel doping regions of the transistors L31 and L32 and the transistors d31[k, k'] and d32[k, k'] ( Figure 3b ) can be formed in different semiconductor layers. The transistors d31[k, k'] and d32[k, k'] can be transistors used to form memory cells, and the transistors L31 and L32 can be transistors used to form logic gates.

[0119] Figure 3c It indicates Figure 3a The waveform timing of the relevant signals in FIG. 1 is shown in FIG. 1 ; wherein the waveform vTWL represents the voltage of the following word line TWL, and the waveforms vTBL00, vTBL01, vTBL10 and vTBL11 respectively represent the voltage responses of the following bit line TBL in different scenarios. Figure 3c As shown, in a running round TC1 of the circuit module 10 (for example, a reading round, the length of which can be equal to Figure 1bIn one cycle T of the clock CK1, the voltage of the word line TWL can be driven from a level vw30 to another level vw31 at time tc0, as shown by the waveform vTWL; wherein the level vw31 can be a level that enables the transistor L32 ( Figure 3a ) and gd31[k,k']( Figure 3b ) is turned on, and the level vw30 can be a level that can make the transistor L32 and gd31[k,k'] non-conductive.

[0120] After time point tc0, as the following word line TWL is driven, the voltage of the following bit line TBL at the node n1 starts to change (e.g., decrease) from a level v31. The time taken for the voltage of the following bit line TBL to change from the level v31 to another different level v30 can be regarded as a response parameter of the response characteristic of the node n1, hereinafter referred to as the following bit line discharge time; the level v31 can be regarded as an initial level. After time point tc0, the control circuit 20 can control the operation timing of the functional circuit 40 and / or the circuit module 10 according to the response characteristic of the node n1, so that one or more timing parameters of the operation timing (e.g., the length of the memory cell read time) are related to one or more response parameters of the response characteristic (e.g., the length of the following bit line discharge time). Furthermore, after time tc0, as the following word line TWL is driven, the auxiliary circuit 310 is also enabled after time tc0, and the transformed memory cells h[1,1] to h[K,K'] can provide K*K' conductive paths between nodes n1 and n0 as main conductive paths.

[0121] In a first scenario, after the following word line TWL is driven at time tc0 to enable the auxiliary circuit 310, the signal dvs_sa_relax maintains the level v0 to enable the auxiliary circuit 320. Therefore, after time tc0, not only does the auxiliary circuit 310 provide a main conductive path between nodes n1 and n0, but the transistors L31 and L32 turned on in the auxiliary circuit 320 also provide an additional conductive path between nodes n1 and n0, which is parallel to the main conductive path. Through the main conductive path and the additional conductive path jointly provided by the two auxiliary circuits 310 and 320, the following bit line TBL coupled to the node n1 can start to discharge from the level v31 to the node n0 at time tc0, and change to the level v30 at a time td00, as shown in the waveform vTBL00. In this first scenario, the discharge time of the following bit line is the time value T00 (from time tc0 to td00).

[0122] In a second scenario, when the following word line TWL is driven at time tc0 to enable the auxiliary circuit 310, the signal dvs_sa_relax switches from level v0 to level 1 at a certain time tx01, so that the auxiliary circuit 320 switches from enabling to disabling at time tx01. Therefore, between time tc0 and tx01, both the auxiliary circuits 310 and 320 are enabled; through the main conductive path and the additional conductive path provided by the enabling auxiliary circuits 310 and 320, the following bit line TBL coupled to the node n1 can start to discharge from level v31 to the node n0 at time tc0. After time point tx01, the auxiliary circuit 320 is disabled and no longer provides an additional conductive path, but the auxiliary circuit 310 remains enabled, and the tracking bit line TBL can continue to discharge to the node n0 via the main conductive path provided by the auxiliary circuit 310, and changes to the level v30 at a time point td01, as shown in the waveform vTBL01. In this second scenario, the discharge time of the tracking bit line is the time value T01 (from time point tc0 to td01).

[0123] In a third scenario, after the following word line TWL is driven at time tc0 to enable the auxiliary circuit 310, the signal dvs_sa_relax switches from level v1 to level 0 at a certain time tx10, so that the auxiliary circuit 320 switches from disabled to enabled at time tx10. Therefore, between time tc0 and tx10, the auxiliary circuits 310 and 320 are enabled and disabled respectively; through the main conductive path provided by the enabled auxiliary circuit 310, the following bit line TBL coupled to the node n1 can start to discharge from level v31 to the node n0 at time tc0. After time tx10, the auxiliary circuits 310 and 320 are both enabled, and the following bit line TBL can continue to discharge to the node n0 through the main conductive path and the additional conductive path jointly provided by the auxiliary circuits 310 and 320, and change to level v30 at a time td10, as shown by the waveform vTBL10. In the third scenario, the tracking bit line discharge time is the time value T10 (from time point tc0 to td10).

[0124] In a fourth scenario, after the following word line TWL is driven at time tc0 to enable the auxiliary circuit 310, the signal dvs_sa_relax maintains the level v1 to disable the auxiliary circuit 320. Therefore, after time tc0, the auxiliary circuits 310 and 320 are enabled and disabled respectively; through the main conductive path provided by the enabling auxiliary circuit 310, the following bit line TBL coupled to the node n1 can start to discharge from the level v31 to the node n0 at time tc0, and change to the level v30 at a time td11, as shown in the waveform vTBL11. In this fourth scenario, the discharge time of the following bit line is the time value T11 (from time tc0 to td11).

[0125] like Figure 1b As shown, the level of the signal dvs_sa_relax can reflect the operation mode of the circuit module 10. Therefore, in the first and fourth scenarios, the circuit module 10 is maintained in two different modes in the same operation cycle TC1; in the second and third scenarios, the circuit module 10 switches between different modes in the same operation cycle TC1. Figure 3c It can be seen from the waveforms vTBL00, vTBL01, vTBL10 and vTBL11 (corresponding to the first to fourth scenarios respectively) that in the auxiliary circuits 310 and 320 ( Figure 3a ), the response characteristics of the following bit line TBL (node ​​n1) will change adaptively according to the first to fourth scenarios. For example, the discharge time of the following bit line can be time values ​​T00, T01, T10 and T11 respectively. Figure 1a ) is to control the operation timing of the functional circuit 40 according to the response characteristics of the node n1, so the control circuit 20 can adaptively adjust the operation timing of the functional circuit 40 according to different scenarios (modes), and then adjust the timing parameters of the functional circuit 40 and / or the circuit module 10, such as the memory cell read time. For example, the control circuit 20 can control the time when each sense amplifier sa[j] starts to be enabled according to the discharge time of the tracking bit line, and then control the memory cell read time, for example, to make the memory cell read time positively correlated with the discharge time of the tracking bit line; the longer the discharge time of the tracking bit line, the longer the memory cell read time.

[0126] Furthermore, as mentioned above, each transformed storage unit h[k,k']( Figure 3b ) and each storage unit c[i,i']( Figure 1c ) can have the same structure and characteristics as the transistor a1[i,i'], and the transistor gd31[k,k']( Figure 3b ) and ga1[i,i']( Figure 1c ) can also have the same structure and characteristics. In this arrangement, when each modified memory cell h[k, k'] provides a conductive path at the node n1, the effect of the conductive path on the following bit line TBL can reflect the effect of each memory cell c[i, i']( Figure 1a) on the bit lines BL[i'] and BL'[i']. If the characteristics of each memory cell c[i,i'] are affected by process drift, the effect of each memory cell c[i,i'] on the bit lines BL[i'] and BL'[i'] will also be affected after the word line WL[i] is driven; however, the characteristics of each modified memory cell h[k,k'] will also be affected by process drift. In conjunction, when the following word line TWL is driven, the effect of each modified memory cell h[k,k'] on the following bit line TBL and the response characteristics of the node n1 will also reflect the influence of process drift. When the control circuit 20( Figure 1a ) When the operating timing of each sense amplifier sa[j] in the functional circuit 40 is controlled according to the response characteristics of the node n1, the operating timing and related timing parameters (such as the storage cell read time) will also adaptively reflect the influence of the process drift. In this way, even if each storage cell c[i,i'] is affected by the process drift, each sense amplifier sa[j] can still correctly sense the data stored in each storage cell c[i,i'].

[0127] Moreover, Figure 3c It can also be seen from the waveforms vTBL00, vTBL01, vTBL10 and vTBL11 (corresponding to the first to fourth scenarios respectively) that in the auxiliary circuits 310 and 320 ( Figure 3a ), no matter how the signal dvs_sa_relax changes in the same operation round TC1 (maintaining level v0, maintaining level v1, switching from level v0 to level v1 at any time point, switching from level v1 to level v0 at any time point), the voltage response waveform of the following bit line TBL (node ​​n1) after time point tc0 will be enveloping between the waveforms vTBL00 and vTBL11, and the discharge time of the following bit line will fall between the time values ​​T00 and T11. During the discharge of the following bit line TBL from the level v31 to the level v30, since the following bit line TBL will continue to discharge with more conductive paths (the main conductive path plus the additional conductive path) in the first scenario (the signal dvs_sa_relax maintains the level v0), and will continue to discharge with fewer conductive paths (only the main conductive path) in the fourth scenario (the signal dvs_sa_relax maintains the level v1), the following bit line discharge time in the first scenario is the shortest time value T00, and the following bit line discharge time in the fourth scenario is the longest time value T11; in the second and third scenarios, the following bit line TBL will discharge with more conductive paths for a portion of time and with fewer conductive paths for another portion of time, so the following bit line discharge time (time values ​​T01 and T10) will be between the time values ​​T00 and T11.

[0128] In other words, through the operation arrangement of the auxiliary circuits 310 and 320 of the present invention, in the same operation round TC1, no matter which mode the circuit module 10 maintains or whether it switches modes, the response parameters related to the response characteristics of the node n1 will fall into a clear (well-defined) response parameter range; for example, the discharge time of the tracking bit line will fall between the time values ​​T00 and T11. Corresponding to the clear response parameter range of the response parameter, when the control circuit 20 ( Figure 1a ) When the operation timing of the functional circuit 40 is controlled according to the response characteristics of the node n1, the timing parameters related to the operation timing will also have a clear timing parameter range; for example, the storage unit read time will fall within a clear time range. In this way, as long as the functional circuit 40 ( Figure 1a ) The tolerance of each relevant timing parameter in the operation timing can cover the aforementioned timing parameter range. No matter which mode the circuit module 10 maintains or whether the mode is switched in the same operation round TC1, the functional circuit 40 can operate correctly.

[0129] In the prior art, an existing circuit module sets a mode-specific circuit for different modes, and the operating timing of its internal functional circuit depends on the enabled mode-specific circuit. For example, an existing circuit module sets a first mode-specific circuit and a second mode-specific circuit for a first mode and a second mode, respectively. When the existing circuit module operates in the first mode, the first mode-specific circuit is enabled, the second mode-specific circuit is disabled, and the operating timing of the functional circuit depends on the first mode-specific circuit; for example, the first mode-specific circuit can make a timing parameter related to the operating timing equal to a first value. When operating in the second mode, the first mode-specific circuit is disabled, the second mode-specific circuit is enabled, and the operating timing of the functional circuit depends on the second mode-specific circuit; for example, the second mode-specific circuit can make the timing parameter equal to a second value.

[0130] However, this prior art has many disadvantages. For example, to completely switch from the first mode to the second mode (or completely switch from the second mode to the first mode), a mode handover period is required. During this mode handover period, the enabling and disabling of the circuits dedicated to the first mode and the circuits dedicated to the second mode are unpredictable and random; although ideally one is enabled and the other is disabled, there may be a period of time when both are enabled, both are disabled, or the enabled one is not enabled and the disabled one is not disabled, etc. Due to the uncertainty of the mode handover period, the timing parameters related to the operating timing will not have a clear timing parameter range. For example, if the circuits dedicated to the first and second modes are both enabled, it is difficult to determine whether the aforementioned timing parameters are the first value, the second value, or other values.

[0131] Furthermore, each mode-specific circuit also needs a transient period to switch from enabled to completely disabled or from disabled to fully enabled. During the mode handover period, even if the two mode-specific circuits are correctly switched from enabled to disabled and from disabled to enabled, the two mode-specific circuits will cause unpredictable effects on the overall operation of the circuit module during the transient period between enabling and disabling. For example, when the existing circuit module switches from the first mode to the second mode, the timing parameter should ideally become the second value, but if the first mode-specific circuit is not completely disabled when the second mode-specific circuit is enabled, the timing parameter will deviate from the second value, but not the first value.

[0132] In order to avoid the uncertainty caused by mode handover and transient state, the prior art will interrupt the normal operation of the circuit module when switching modes, and continue to operate after the mode switch is completed. For example, the prior art circuit module can perform mode handover after a running round ends, and stop the operation in the normal running round during the mode handover period, and continue to start the next running round after the circuits dedicated to different modes have been correctly enabled and disabled. Since the normal operation of the circuit module must be interrupted when switching modes, this prior art will reduce the operating performance of the circuit module.

[0133] In contrast, in the present invention, the timing parameters related to the timing control are associated with the auxiliary circuits 310 and 320, but the enabling and disabling of the auxiliary circuits 310 and 320 are not mutually exclusive. When the control circuit 20 performs the timing control, the auxiliary circuit 310 will continue to be enabled, and the auxiliary circuit 320 will be enabled or disabled in response to the different levels (corresponding to different modes) of the signal dvs_sa_relax. Under such an arrangement, the timing parameters in the timing control of the present invention will have a clear timing parameter range, avoiding the uncertainty and transient state of the enabling and disabling of the circuits dedicated to different modes in the prior art and being unable to reliably infer the timing parameter range. In the present invention, even if the signal dvs_sa_relax switches the level in the same operation round TC1 (the operation mode is switched in the same operation round TC1), the functional circuit 40 and the circuit module 10 can still continue the normal operation (such as data sensing, reading) in the operation round, and will not affect the operation correctness (such as data sensing correctness) in the operation round TC1.

[0134] Figure 4a The auxiliary circuit 420 according to one embodiment of the present invention is shown; the auxiliary circuit 420 can be used with Figure 3a The auxiliary circuit 310 in (also reproduced in Figure 4a ) to achieve Figure 2 The auxiliary circuits 220 and 210 in FIG. Figure 4aAs shown, the auxiliary circuit 420 may include Q*Q' modified memory cells u[1,1] to u[Q,Q'], and an inverter L41; wherein the number Q and Q' may be integer constants greater than or equal to one. The inverter L41 may include an input terminal and an output terminal, coupled to a node n3 and another node n6, respectively. Each modified memory cell u[q,q'] (for subscript q=1 to Q, subscript q'=1 to Q') may be coupled to a node n0 (ground voltage Gnd), a node n1 (following the bit line TBL), a node n2 (following the word line TWL) and a node n6 (the output terminal of the inverter L41).

[0135] Figure 4b It indicates Figure 4a An embodiment of a modified memory cell u[q,q'] in FIG. The modified memory cell u[q,q'] may include transistors gd41[q,q'], gd42[q,q'] and transistors d41[q,q'] to d44[q,q']. The transistors gd41[q,q'], gd42[q,q'], d41[q,q'] and d42[q,q'] may be n-channel metal oxide semiconductor transistors, and the transistors d43[q,q'] and d44[q,q'] may be p-channel metal oxide semiconductor transistors. The transistor gd41[q,q'] may be a pass transistor and may include a controlled terminal and two channel terminals (such as a gate, a drain and a source), which are respectively coupled to a node n2 (following a word line TWL), a node n1 (following a bit line TBL) and a node nd41[q,q']. The transistor gd42[q,q'] may include a controlled terminal and two channel terminals, which are respectively coupled to the three nodes nd45[q,q'], nd46[q,q'] and nd42[q,q']. The transistor d41[q,q'] may be a data transistor, and may include a controlled terminal and two channel terminals (such as a gate, a drain and a source), which are respectively coupled to the nodes n6, nd41[q,q'] and n0 (ground voltage Gnd). The transistor d42[q,q'] may include a controlled terminal and two channel terminals, which are respectively coupled to a node nd43[q,q'], a node nd42[q,q'] and a node n0. The transistor d43[q,q'] may include a controlled terminal and two channel terminals (such as a gate, a drain and a source), which are respectively coupled to the supply voltage Vcc, the node nd43[q,q'] and the supply voltage Vcc. The transistor d44[q,q'] may include a controlled terminal and two channel terminals, respectively coupled to the node nd43[q,q'], another node nd44[q,q'] and the supply voltage Vcc. The nodes nd41[q,q'] to nd44[q,q'] may be insulated from each other. In one embodiment, the number I( Figure 1a ) and quantity Q( Figure 4a) may be equal, and the node nd45[q,q'] may be coupled to the word line WL[q] for indices q=1 to Q. In one embodiment, the node nd46[q,q'] may be floating.

[0136] In the modified memory cell u[q,q'], when the following word line TWL is driven, if the signal dvs_sa_relax is at level v0, the transistors gd41[q,q'] and d41[q,q'] are turned on, providing a conductive path between the node n1 and the node n0. In contrast, when the following word line TWL is driven, if the signal dvs_sa_relax is at level v1, the transistor d41[q,q'] is not turned on, and the modified memory cell u[q,q'] does not provide a conductive path between the node n1 and the node n0. When the following word line TWL is not driven, the transistor gd41[q,q'] is turned off, and the modified memory cell u[q,q'] does not provide a conductive path between the nodes n1 and n0.

[0137] Based on the operation of each modified memory cell u[q,q'], when the following word line TWL is driven, if the signal dvs_sa_relax is at level v0, the auxiliary circuit 420 ( Figure 4a ) can be enabled, and the modified memory cells u[1,1] to u[Q,Q'] can provide Q*Q' parallel conductive paths between nodes n1 to n0 as additional conductive paths. When the following word line TWL is driven, if the signal dvs_sa_relax is at level v1, the auxiliary circuit 420 can be disabled and does not provide the Q*Q' conductive paths between nodes n1 to n0. When the following word line TWL is not driven, the auxiliary circuit 420 can also be disabled.

[0138] In other words, Figure 4a The auxiliary circuit 420 and Figure 3a The function of the auxiliary circuit 320 is the same. When the following word line TWL is driven, the auxiliary circuit 310 remains enabled to provide the main conductive path, and the auxiliary circuit 420 is enabled or disabled according to the signal dvs_sa_relax being at level v0 or v1; if the signal dvs_sa_relax is at level v0, the auxiliary circuit 420 is enabled, and in conjunction with the auxiliary circuit 310, provides a parallel main conductive path and an additional conductive path between nodes n1 and n0; if the signal dvs_sa_relax is at level v1, the auxiliary circuit 420 is disabled, and the auxiliary circuit 310 provides the main conductive path between nodes n1 and n0. Under the operation of the auxiliary circuits 310 and 420, the response characteristics of the node n1 (such as the discharge time of the following bit line) will dynamically change according to the signal dvs_sa_relax being at level v0 or v1 (associated with different modes respectively). Therefore, when the control circuit 20 ( Figure 1a) controls the operation timing of the functional circuit 40 according to the response characteristics of the node n1, the operation timing will also be adaptively changed according to the different modes. In this way, in the same operation round TC1 ( Figure 3c ), no matter which mode the circuit module 10 is maintained in or whether the mode is switched, the functional circuit 40 can operate correctly.

[0139] exist Figure 4b Transform storage unit u[q,q'] and Figure 1c In the storage unit c[i,i'], Figure 4b Transistors d41[q,q'], d42[q,q'] and Figure 1c The data transistors a1[i,i'] and a2[i,i'] may be matched with each other; for example, the dimensions (such as channel length and / or width) of the transistors d41[q,q'], d42[q,q'], a1[i,i'] and a2[i,i'] may be substantially equal, and the doped regions used to form the channels may also be formed in the same semiconductor layer. And / or, Figure 4b Transistors d43[q,q'], d44[q,q'] and Figure 1c Data transistors a3[i,i'] and a4[i,i'] may be matched with each other; for example, the sizes of transistors d43[q,q'], d44[q,q'], a3[i,i'] and a4[i,i'] may be substantially equal, and the doped regions for forming the channel may be formed in the same semiconductor layer. And / or, Figure 4b Transistors gd41[q,q'], gd42[q,q'] and Figure 1c The pass transistors ga1[i,i'] and ga2[i,i'] can be matched to each other; for example, the sizes of transistors gd41[q,q'], gd42[q,q'], ga1[i,i'] and ga2[i,i'] can be substantially equal, and the doped regions used to form the channels can be formed in the same semiconductor layer. That is, the transistors included in the modified memory cell u[q,q'] and the transistors included in the memory cell c[i,i'] can be of the same specifications, with the same layout, structure and characteristics. On the other hand, Figure 1c and Figure 4b It can be seen that the internal connections between transistors of the storage unit c[i,i'] and the internal connections between transistors of the modified storage unit u[q,q'] can be different; for example, in Figure 1c In the embodiment, the drain of transistor a1[i,i'] can be coupled to the drain of transistor a3[i,i'], and the gate of transistor a1[i,i'] can be insulated from the supply voltage Vcc; Figure 4b In the embodiment, the drain of the transistor d41 [q, q′] may be insulated from the drain of the transistor d43 [q, q′], and the gate of the transistor d41 [q, q′] may be coupled to the node n6.

[0140] Due to the transformation of storage unit u[q,q']( Figure 4b ) and each storage unit c[i,i']( Figure 1c ) can have the same structure and characteristics as the transistor a1[i,i'], and the transistor gd41[q,q']( Figure 4b ) and ga1[i,i']( Figure 1c ) may also have the same structure and characteristics. When each modified memory cell u[q,q'] provides a conductive path at the node n1, the effect of the conductive path on the following bit line TBL can reflect the effect of each memory cell c[i,i'] on the bit lines BL[i'] and BL'[i'] ( Figure 1a ) effect. If the characteristics of each memory cell c[i,i'] are affected by process drift, the effect of each memory cell c[i,i'] on the bit lines BL[i'] and BL'[i'] after the word line WL[i] is driven will also be affected; however, the characteristics of each modified memory cell u[q,q'] will also be affected by process drift. In conjunction, when the following word line TWL is driven, the effect of each modified memory cell u[q,q'] on the following bit line TBL and the response characteristics of the node n1 will also reflect the influence of process drift. When the control circuit 20( Figure 1a ) When the operating timing of each sense amplifier sa[j] in the functional circuit 40 is controlled according to the response characteristics of the node n1, the operating timing and related timing parameters (such as the storage cell read time) will also adaptively reflect the influence of the process drift. In this way, even if each storage cell c[i,i'] is affected by the process drift, each sense amplifier sa[j] can still correctly sense the data stored in each storage cell c[i,i'].

[0141] Figure 5 The auxiliary circuit set 500 according to one embodiment of the present invention is shown, which can realize Figure 1a Auxiliary circuit set 100 of circuit module 10. Similar Figure 2 Auxiliary circuit set 200, Figure 5 The auxiliary circuit set 500 may include the auxiliary circuits 210 and 220 described previously; and Figure 5 As shown, the auxiliary circuit set 500 may further include a calibration load 550 and a calibration switch circuit 560. The auxiliary circuit 210 may be used Figure 3a The auxiliary circuit 310 is implemented in the auxiliary circuit 220. Figure 3a or Figure 4a The auxiliary circuit 320 or 420 is implemented.

[0142] like Figure 5As shown, the tuning load 550 can be coupled to a node n7. The tuning switch circuit 560 can be coupled to the tuning load 550 at the node n7, coupled to the tracking bit line TBL at the node n1, and coupled to a tuning control signal sc1 at another node n8. The tuning switch circuit 560 can control whether to conduct the tuning load 550 to the node n1 according to the tuning control signal sc1. For example, in one embodiment, when the tuning control signal sc1 is logic 1, the tuning switch circuit 560 can conduct the tuning load 550 to the node n1; when the tuning control signal sc1 is logic 0, the tuning switch circuit 560 does not conduct the tuning load 550 to the node n1. Whether to conduct the tuning load 550 to the node n1 will make the node n1 have different response characteristics. Therefore, when the control circuit 20 controls the operation timing of the functional circuit 40 according to the response characteristics of the node n1, whether to conduct the tuning load 550 to the node n1 will also make the operation timing different. That is, in the present invention Figure 5 In the embodiment of the present invention, not only can the auxiliary circuits 210 and 220 adjust the response characteristics of the node n1 and the operation timing of the functional circuit 40 in response to the level of the signal dvs_sa_relax, but the adjustment switch circuit 560 can also adjust the response characteristics of the node n1 and the operation timing of the functional circuit 40 in response to the logic value of the adjustment control signal sc1, thereby increasing the flexibility of the timing control. That is, the adjustment load 550 and the adjustment switch circuit 560 can increase the options of the present invention to control the timing, making the timing control of the present invention more flexible and diversified.

[0143] Figure 6a The diagram shows that the load adjustment 650 and the switch adjustment circuit 660 according to an embodiment of the present invention can respectively implement Figure 5 The load 550 and the switch circuit 560 are adjusted. Figure 6a As shown, the calibration load 650 may include a set of additional bit lines ABL and ABL', and I additional memory cells ac[1] to ac[I]. The additional bit line ABL may be coupled to the node n7. Each additional memory cell ac[i], for index i=1 to I, may be coupled to the word line WL[i] and the additional bit lines ABL and ABL'. The calibration switch circuit 660 may include an inverter L61, a main switch ss1, and an additional switch ss2. The inverter L61 may include an input terminal and an output terminal, respectively coupled to the node n8 (calibration control signal sc1) and another node n9. The main switch ss1 may be a transmission gate, and may include two connection terminals and two main switch control terminals, respectively coupled to the nodes n1, n7, n8, and n9. The additional switch ss2 may be a p-channel metal oxide semiconductor transistor, and may include a controlled terminal and two channel terminals (eg, a gate, a drain, and a source), respectively coupled to the node n8, the node n7, and the supply voltage Vcc.

[0144] When the logic value of the adjustment control signal sc1 at the node n8 is logic 1, the main switch ss1 can conduct the node n7 (additional bit line ABL) to the node n1, so as to conduct the adjustment load 650 to the node n1; the additional switch ss2 does not conduct the node n7 to the supply voltage Vcc. When the logic value of the adjustment control signal sc1 is logic 0, the main switch ss1 does not conduct the node n7 to the node n1, so that the adjustment load 650 is no longer conducted to the node n1; the additional switch ss2 conducts the node n7 to the supply voltage Vcc, so as to conduct the adjustment load 650 to the supply voltage Vcc.

[0145] Figure 6b It indicates Figure 6a An embodiment of each additional storage unit ac[i]. Figure 6b As shown, the additional memory cell ac[i] may include transistors gd61[i] and gd62[i] and transistors d61[i] to d64[i]. Transistors gd61[i], gd62[i], d61[i] and d62[i] may be n-channel metal oxide semiconductor transistors, and transistors d63[i] and d64[i] may be p-channel metal oxide semiconductor transistors. Transistor gd61[i] may include a controlled terminal and two channel terminals (such as a gate, a drain and a source), which are respectively coupled to a ground voltage Gnd, an additional bit line ABL and a node nd63[i]. Transistor gd62[i] may include a controlled terminal and two channel terminals, which are respectively coupled to word line WL[i], additional bit line ABL' and another node nd62[i]. Transistor d61[i] may include a controlled terminal and two channel terminals (such as a gate, a drain and a source), respectively coupled to nodes nd62[i], nd63[i] and the ground voltage Gnd. Transistor d62[i] may include a controlled terminal and two channel terminals, respectively coupled to nodes nd61[i], nd62[i] and the ground voltage Gnd. Transistor d63[i] may include a controlled terminal and two channel terminals (such as a gate, a drain and a source), respectively coupled to nodes nd62[i], node nd61[i] and the supply voltage Vcc. Transistor d64[i] may include a controlled terminal and two channel terminals, respectively coupled to nodes nd61[i], node nd62[i] and the supply voltage Vcc. When word line WL[i] is driven, pass transistor gd62[i] will conduct node nd62[i] to additional bit line ABL'. When the tracking word line WL[i] is not driven, the pass transistor gd62[i] does not conduct the node nd62[i] to the additional bit line ABL′.

[0146] exist Figure 6b Following the storage unit ac[i] and Figure 1c In the storage unit c[i,i'], Figure 6b Transistors D61[i], D62[i] and Figure 1c The data transistors a1[i,i'] and a2[i,i'] may be matched with each other; for example, the dimensions (such as channel length and / or width) of transistors d61[i], d62[i], a1[i,i'] and a2[i,i'] may be substantially equal, and the doped regions used to form the channels may also be formed in the same semiconductor layer. And / or, Figure 6b Transistors D63[i], D64[i] and Figure 1c The data transistors a3[i,i'] and a4[i,i'] may be matched with each other; for example, the sizes of the transistors d63[i], d64[i], a3[i,i'] and a4[i,i'] may be substantially equal, and the doped regions for forming the channels may be formed in the same semiconductor layer. And / or, Figure 6b Transistors gd61[i], gd62[i] and Figure 1c The pass transistors ga1[i,i'] and ga2[i,i'] may be matched to each other; for example, the sizes of the transistors gd61[i], gd62[i], ga1[i,i'] and ga2[i,i'] may be substantially equal, and the doping regions used to form the channels may be formed in the same semiconductor layer. Due to the above transistor matching arrangement, when the tuning switch circuit 660 switches the node n7 to the node n1, the equivalent load of the additional bit line ABL at the node n1 may reflect the equivalent load of the bit lines BL[i'] and BL'[i'] to the sense amplifier sa[j].

[0147] Figure 6c Hint Figure 6a The waveform timing of the relevant signals in FIG. 1 is shown in FIG. 1 ; wherein the waveform vTWL represents the voltage of the following word line TWL, and the waveforms vTBL00, vTBL00n, vTBL11 and vTBL11n respectively represent the voltage responses of the following bit line TBL in different scenarios. Figure 6c As shown in the waveform vTWL in FIG. Figure 1a ) starts, the voltage of the following word line TWL can be driven from the level vw30 to the level vw31 at the time point tc0, just like Figure 3c After time tc0, as the following word line TWL is driven, the voltage of the following bit line TBL at the node n1 starts to change (eg, decrease) from the level v31.

[0148] like Figure 6c As shown in the waveform vTBL00 in FIG. 1 , when the following word line TWL is driven at time tc0, if the signal dvs_sa_relax ( Figure 1b ) maintains level v0 and adjusts control signal sc1 ( Figure 6a) so that the adjustment switch circuit 660 does not conduct the adjustment load 650 to the node n1, and the tracking bit line TBL coupled to the node n1 can be enabled at the time point tc0 through the enabled auxiliary circuits 210 and 220 ( Figure 5 ) starts to discharge from level v31 to node n0 and changes to level v30 at time td00, just like Figure 3c In the first scenario, the discharge time of the following bit line is the time value T00 (from the time point tc0 to td00).

[0149] like Figure 6c As shown in the waveform vTBL11 in FIG. 1 , after the following word line TWL is driven at time tc0, if the signal dvs_sa_relax maintains the level v1 and the adjustment control signal sc1 causes the adjustment switch circuit 660 not to conduct the adjustment load 650 to the node n1, the following bit line TBL coupled to the node n1 can be discharged from the level v31 to the node n0 at time tc0 through the enabled auxiliary circuit 210, and change to the level v30 at time td11, just like Figure 3c In the fourth scenario, the following bit line discharge time is the time value T11 (from time point tc0 to td11).

[0150] In a fifth scenario, the signal dvs_sa_relax maintains the level v0 after the time point tc0, and the adjustment control signal sc1 causes the adjustment switch circuit 660 to turn on the adjustment load 650 to the node n1; therefore, when the tracking word line TWL is driven at the time point tc0, the tracking bit line TBL coupled to the node n1 and the adjustment load 650 can be discharged from the level v31 to the node n0 through the enabled auxiliary circuits 210 and 220, and change to the level v30 at the time point tn00, as shown in FIG. Figure 6c In the fifth scenario, the discharge time of the following bit line is the time value T00n (from the time point tc0 to tn00).

[0151] In a sixth scenario, the signal dvs_sa_relax maintains the level v1 after the time point tc0, and the adjustment control signal sc1 causes the adjustment switch circuit 660 to conduct the adjustment load 650 to the node n1; therefore, when the tracking word line TWL is driven at the time point tc0, the tracking bit line TBL coupled to the node n1 and the adjustment load 650 can be discharged from the level v31 to the node n0 through the enabled auxiliary circuit 210, and change to the level v30 at the time point tn11, such as Figure 6c In the sixth scenario, the discharge time of the following bit line is the time value T11n (from the time point tc0 to tn11).

[0152] When the adjustment control signal sc1 causes the adjustment switch circuit 660 not to conduct the adjustment load 650 to the node n1, if the signal dvs_sa_relax is switched from level v0 to level v1 or from level v1 to level v0 in the same operation cycle TC1 after the time point tc0, the voltage response waveform of the tracking bit line TBL will be enveloped between the waveforms vTBL00 and vTBL11, and the discharge time of the tracking bit line will be between the time values ​​T00 and T11, as previously described by Figure 3c Similarly, Figure 6c It can be seen that when the adjustment control signal sc1 causes the adjustment switch circuit 660 to turn on the adjustment load 650 to the node n1, if the signal dvs_sa_relax is switched from the level v0 to the level v1 or from the level v1 to the level v0 in the same operation cycle TC1 after the time point tc0, the voltage response waveform of the tracking bit line TBL will be enveloped between the waveforms vTBL00n and vTBL11n, and the discharge time of the tracking bit line will be between the time values ​​T00n and T11n.

[0153] That is, if Figure 6c As shown, for the response parameters related to the response characteristics of node n1, the response parameter range of the response parameters can be changed by selecting whether to conduct the calibration load 650 to node n1. Figure 5 ) is to control the operation timing of the functional circuit 40 according to the response characteristics of the node n1. Therefore, for the timing parameters related to the operation timing (such as the storage unit read time), whether to conduct the adjustment load 650 to the node n1 will also change the timing parameter range of the timing parameter. It can be seen that through the operation arrangement of the adjustment load 650 and the adjustment switch circuit 660, the present invention can increase the diversity of timing control and provide more options for controlling timing to meet more timing control requirements, such as overcoming process drift.

[0154] Furthermore, in the scenario where the tuning control signal sc1 causes the tuning switch circuit 660 to conduct the tuning load 650 to the node n1, no matter the signal dvs_sa_relax is maintained at the level v0, maintained at the level v1, switched from the level v0 to the level v1, or switched from the level v1 to the level v0 in the same operation cycle TC1, the response parameter (such as the discharge time of the tracking bit line) related to the response characteristic of the node n1 (the tracking bit line TBL) will still have a clear and predictable response parameter range (such as the time value between T00n and T11n). Therefore, when the control circuit 20 ( Figure 5 ) When the operating timing of the functional circuit 40 is controlled according to the response characteristics of the node n1, the timing parameters related to the operating timing (such as the storage unit read time) will also have a clear timing parameter range.

[0155] And, in Figure 6bAdditional storage unit ac[i] and Figure 1c In the storage unit c[i,i'], Figure 6b Transistors D61[i], D62[i] and Figure 1c Transistors a1[i,i'] and a2[i,i'] can have the same structure and characteristics. Figure 6b Transistors D63[i], D64[i] and Figure 1c Transistors a3[i,i'] and a4[i,i'] can have the same structure and characteristics. Figure 6b Transistors gd61[i], gd62[i] and Figure 1c The transistors ga1[i,i'] and ga2[i,i'] may have the same structure and characteristics. Therefore, when the switch circuit 660 ( Figure 6a ) turns on the additional bit line ABL coupled to the node n7 to the node n1, the effect of the additional bit line ABL on the node n1 can reflect the difference between each bit line BL[i'] and BL'[i']( Figure 1a ) on the sense amplifier sa[j]. If the characteristics of each memory cell c[i,i'] are affected by process drift, the effect of the bit lines BL[i'] and BL'[i'] on the sense amplifier sa[j] will also be affected; however, the effect of each additional memory cell ac[i] on the additional bit line ABL will also reflect the effect of process drift. In conjunction, in the scenario where the adjustment switch circuit 660 turns on the additional bit line ABL to the node n1, when the control circuit 20( Figure 5 ) When the operating timing of each sense amplifier sa[j] in the functional circuit 40 is controlled according to the response characteristics of the node n1, the operating timing and related timing parameters (such as the storage cell read time) will also adaptively reflect the influence of the process drift. In this way, even if each storage cell c[i,i'] is affected by the process drift, each sense amplifier sa[j] can still correctly sense the data stored in each storage cell c[i,i'].

[0156] Figure 7a The diagram shows a calibration switch circuit 760 according to an embodiment of the present invention. Figure 7b The diagram shows the waveform timing of the relevant signals when the switch circuit 760 is in operation. Figure 7a The adjustment switch circuit 760 in the Figure 6a The calibration load in 650 (also reproduced in Figure 7a ) respectively realize Figure 5 The adjustment switch circuit 560 and the adjustment load 550 in FIG. Figure 7aAs shown, the adjustment switch circuit 760 may include an inverter L71, a main switch ss1, an additional switch ss2 and an adjustment logic circuit 770. The inverter L71 may include an input terminal and an output terminal, respectively coupled to two nodes n10 and n11. The main switch ss1 may be a transmission gate, and may include two connection terminals and two main switch control terminals, respectively coupled to nodes n1, n7, n10 and n11. The additional switch ss2 may be a p-channel metal oxide semiconductor transistor, and may include a controlled terminal and two channel terminals (such as a gate, a drain and a source), respectively coupled to node n10, node n7 and the supply voltage Vcc. When the logic value of node n10 is logic 1, the main switch ss1 may conduct node n7 to node n1 to conduct the adjustment load 650 to node n1; the additional switch ss2 does not conduct node n7 to the supply voltage Vcc. When the logic value of node n10 is logic 0, the main switch ss1 does not conduct node n7 to node n1, so that the regulated load 650 is no longer conducted to node n1; the additional switch ss2 conducts node n7 to the supply voltage Vcc, so as to conduct the regulated load 650 to the supply voltage Vcc.

[0157] The calibration logic circuit 770 may include a first logic input terminal, a second logic input terminal and a logic input terminal, which are respectively coupled to nodes n1 (following the bit line TBL), n8 (calibration control signal sc1) and n10. Figure 7a As shown, in one embodiment of the present invention, the calibration logic circuit 770 may include a logic gate L72 (e.g., a dual-input NAND gate) and an inverter L73; the logic gate L72 may include two input terminals and an output terminal, respectively coupled to nodes n1, n8 and another node n12, and the inverter L73 may include an input terminal and an output terminal, respectively coupled to nodes n12 and n10. The two input terminals of the logic gate L72 at nodes n1 and n8 and the output terminal of the inverter L73 at node n10 may respectively form a first logic input terminal, a second logic input terminal, and a logic output terminal of the calibration logic circuit 770. The logic gate L72 in the calibration logic circuit 770 may be configured to adjust the voltage of the node n1 based on whether it is greater than a calibration logic trip point level vp_L72 ( Figure 7b ) determines whether the logic value of node n1 is logic 1 or logic 0, and determines the logic value of node n10 according to the logic values ​​of nodes n1 and n8. On the other hand, the control circuit 20 can determine whether the voltage of node n1 is greater than a control logic inversion point level vp_20 ( Figure 7b ) determines whether the logic value of the node n1 is logic 1 or logic 0, and controls the operating timing of each sense amplifier sa[j] in the functional circuit 40 according to the logic value of the node n1.

[0158] When the adjustment control signal sc1 of the node n8 is logic 1, if the adjustment logic circuit 770 determines that the logic value of the node n1 is logic 1, the adjustment logic circuit 770 can output logic 1 at the node n10, so that the adjustment switch circuit 760 conducts the adjustment load 650 to the node n1. When the adjustment control signal sc1 of the node n8 is logic 1, if the adjustment logic circuit 770 determines that the logic value of the node n1 is logic 0, the adjustment logic circuit 770 can output logic 0 at the node n10, so that the adjustment switch circuit 760 does not conduct the adjustment load 650 to the node n1. When the adjustment control signal sc1 of the node n8 is logic 0, the adjustment logic circuit 770 can output logic 0 at the node n10, so that the adjustment switch circuit 760 does not conduct the adjustment load 650 to the node n1, regardless of the logic value of the node n1.

[0159] exist Figure 7b In FIG. 1 , waveform vTBL shows the voltage response of the bit line TBL (node ​​n1). Figure 3c and 6c As mentioned in the previous section, in an operation cycle TC1, when the following word line TWL is driven at time tc0, the following bit line TBL starts to discharge from the level v31, such as Figure 7b In one embodiment of the present invention, the adjustment logic inversion point level vp_L72 used by the adjustment logic circuit 770 to determine whether the voltage at the node n1 is logic 1 or logic 0 and the control logic inversion point level vp_20 used by the control circuit 20 to determine whether the voltage at the node n1 is logic 1 or logic 0 may be different; for example, Figure 7b As shown, the adjustment logic inversion point level vp_L72 can be higher than the control logic inversion point level vp_20. Therefore, when the tracking bit line TBL is discharged to the adjustment logic inversion point level vp_L72 at a time point ti1, the logic gate L72 in the adjustment logic circuit 770 will determine that the logic value of the node n1 has been converted from logic 1 to logic 0, but the control circuit 20 ( Figure 7a ) still determines the logic value of node n1 as logic 1. Based on the operation of logic gate L72, no matter the adjustment control signal sc1 of node n8 is logic 0 or logic 1, the adjustment logic circuit 770 will make the logic value of node n10 be logic 0 after time point ti1; thus, after time point ti1, the adjustment switch circuit 760 will not conduct the adjustment load 650 to the node n1.

[0160] After time point ti1, since the control circuit 20 still determines the logic value of node n1 as logic 1, the tracking bit line TBL (node ​​n1) will continue to discharge, and discharge to the control logic inversion point level vp_20 of the control circuit 20 at another time point ti2 later. Therefore, at time point ti2, the control circuit 20 will determine that the logic value of node n1 has switched from logic 1 to logic 0, and switch the operating timing of the control function circuit 40 according to this logic value. Figure 7b As shown, in one embodiment of the present invention, the adjustment logic reversal point level vp_L72 can be lower than the level v31, and between the level v31 and the control logic reversal point level vp_20. In one embodiment, the control logic reversal point level vp_20 can be equal to Figure 3c and 6c Level v30 in.

[0161] As can be seen from the above description, if the adjustment control signal sc1 maintains logic 1 in the operation round TC1, the adjustment switch circuit 760 will conduct the adjustment load 650 to the node n1 before the time point ti1, but will stop conducting the adjustment load 650 to the node n1 after the time point ti1. That is, even if the adjustment control signal sc1 maintains logic 1, when the discharge of the tracking bit line TBL has approached the control logic reversal point level vp_20 (has entered between the adjustment logic reversal point level vp_L72 and the control logic reversal point level vp_20) but has not reached the control logic reversal point level vp_20, the adjustment switch circuit 760 that originally conducts the adjustment load 650 to the node n1 can stop conducting the adjustment load 650 to the node n1. Under this operation arrangement, when the tracking bit line TBL (node ​​n1) is about to be discharged to the control logic inversion point level vp_20, the charge accumulated by pre-charge on the additional bit line ABL (node ​​n7) will not interfere with the discharge of the tracking bit line TBL (node ​​n1) through the conduction of the adjustment switch circuit 760. On the other hand, if the adjustment control signal sc1 maintains logic 0 in the operation round TC1, the adjustment switch circuit 760 will continue to make the adjustment load 650 non-conductive to the node n1.

[0162] exist Figure 7b In the embodiment, the control logic inversion point level vp_20 can also be regarded as a reference level, and the adjustment logic inversion point level vp_L72 can be regarded as an intermediate level. When the control circuit 20 controls the operation timing of the functional circuit 40 according to the response characteristics of the node n1 (following the bit line TBL), the response characteristics of the node n1 will be related to the period Ti3 (time point tc0 to ti2) when the voltage of the node n1 changes from the level v31 to the reference level vp_20. Figure 7a and 7bIt can be seen that during the period Ti1 (time point tc0 to ti1) when the voltage at the node n1 changes from the initial level v31 to the intermediate level vp_L72, the tuning switch circuit 760 can control whether to conduct the tuning load 650 to the node n1 according to whether the tuning control signal sc1 is logic 1. During the period Ti2 (time point ti1 to ti2) when the voltage at the node n1 changes from the intermediate level vp_L72 to the reference level vp_20, the tuning switch circuit 760 can stop conducting the tuning load 650 to the node n1, regardless of whether the tuning control signal is logic 1.

[0163] Figure 8a The auxiliary circuit 820 according to one embodiment of the present invention is shown; the auxiliary circuit 820 can be used with Figure 3a The auxiliary circuit 310 in (also reproduced in Figure 8a ) to achieve Figure 2 or Figure 5 The auxiliary circuits 220 and 210 in FIG. Figure 8a As shown, the auxiliary circuit 820 may include Q*Q' modified memory cells z[1,1] to z[Q,Q'], two inverters L81 and L83, and a dual-input NAND gate L82. Each modified memory cell z[q,q'] (for subscripts q=1 to Q, subscripts q'=1 to Q') may be coupled to a node n1 (following the bit line TBL), a node n0 (ground voltage Gnd) and another node n83. The inverter L81 may include an input terminal and an output terminal, respectively coupled to the node n3 (signal dvs_sa_relax) and another node n81. The NAND gate L82 may include two input terminals and an output terminal, respectively coupled to the node n81, the node n2 (following the word line TWL) and another node n82. The inverter L83 may include an input terminal and an output terminal, respectively coupled to the nodes n82 and n83.

[0164] Figure 8b It indicates Figure 8aAn embodiment of a modified memory cell z[q,q'] in FIG. The modified memory cell z[q,q'] may include transistors gd81[q,q'], gd82[q,q'] and transistors d81[q,q'] to d84[q,q']. Transistors gd81[q,q'], gd82[q,q'], d81[q,q'] and d82[q,q'] may be n-channel metal oxide semiconductor transistors, and transistors d83[q,q'] and d84[q,q'] may be p-channel metal oxide semiconductor transistors. Transistor gd81[q,q'] may include a controlled terminal and two channel terminals (such as a gate, a drain and a source), which are respectively coupled to a node n83, a node n1 (following a bit line TBL) and another node nd81[q,q']. The transistor gd82[q,q'] may include a controlled terminal and two channel terminals, which are respectively coupled to the three nodes nd85[q,q'], nd86[q,q'] and nd82[q,q']. The transistor d81[q,q'] may include a controlled terminal and two channel terminals (such as a gate, a drain and a source), which are respectively coupled to the supply voltage Vcc, the node nd81[q,q'] and the node n0 (ground voltage Gnd). The transistor d82[q,q'] may include a controlled terminal and two channel terminals, which are respectively coupled to a node nd83[q,q'], the node nd82[q,q'] and the node n0. The transistor d83[q,q'] may include a controlled terminal and two channel terminals (such as a gate, a drain and a source), which are respectively coupled to the supply voltage Vcc, the node nd83[q,q'] and the supply voltage Vcc. The transistor d84[q,q'] may include a controlled terminal and two channel terminals, respectively coupled to the node nd83[q,q'], another node nd84[q,q'] and the supply voltage Vcc. The nodes nd81[q,q'] to nd84[q,q'] may be insulated from each other. In one embodiment, the number I( Figure 1a ) and quantity Q( Figure 8a ) may be equal, and the node nd85[q,q'] may be coupled to the word line WL[q] for indices q=1 to Q. In one embodiment, the node nd86[q,q'] may be floating.

[0165] In the modified storage cell z[q,q'], when following the word line TWL( Figure 8a) is driven, if the signal dvs_sa_relax is at level v0, transistors gd81[q,q'] and d81[q,q'] are both turned on, providing a conductive path between node n1 and node n0. Conversely, when the following word line TWL is driven, if the signal dvs_sa_relax is at level v1, transistor gd81[q,q'] is not turned on, and the modified memory cell z[q,q'] does not provide a conductive path between node n1 and node n0. When the following word line TWL is not driven, transistor gd81[q,q'] is also not turned on, and the modified memory cell z[q,q'] does not provide a conductive path between nodes n1 to n0.

[0166] Based on the operation of each modified memory cell z[q,q'], when the following word line TWL is driven, if the signal dvs_sa_relax is at level v0, the auxiliary circuit 820 ( Figure 8a ) can be enabled, and the modified storage cells z[1,1] to z[Q,Q'] can provide Q*Q' parallel conductive paths between nodes n1 to n0 as additional conductive paths. When the following word line TWL is driven, if the signal dvs_sa_relax is at level v1, the auxiliary circuit 820 can be disabled and does not provide the Q*Q' conductive paths between nodes n1 to n0. When the following word line TWL is not driven, the auxiliary circuit 820 can also be disabled. In other words, Figure 8a The auxiliary circuit 820 and Figure 3a The auxiliary circuit 320 has the same function.

[0167] Fig. 9 The auxiliary circuit 910 according to one embodiment of the present invention is shown; the auxiliary circuit 910 can be used with Figure 8a Auxiliary circuit 820 in (also reproduced in Fig. 9 ) respectively realize Figure 2 or the auxiliary circuits 210 and 220 in 5. The auxiliary circuit 910 may include K*Q' modified memory cells h[1,1] to h[K,Q'], each modified memory cell h[k,q'] (for subscript k=1 to K, subscript q'=1 to Q') may be coupled to a node n1 (following a bit line TBL), a node n2 (following a word line TWL) and a node n0 (ground voltage Gnd). The modified memory cells h[1,q'] to h[K,q'] in the auxiliary circuit 910 and the modified memory cells z[1,q'] to z[Q,q'] in the auxiliary circuit 820 may be coupled to the node n1 via the same connection hBL[q'], for subscript q'=1 to Q'. Fig. 9 The transformed storage unit h[k,q'] in Figure 3b The transformation storage unit h[k,k'] in Figure 3b In one embodiment, Fig. 9 The sum of the quantities K and Q can be equal to K+Q Figure 1a The number I in Figure 3b In the transformation of storage unit h[k,k'] to achieve Fig. 9 When the storage unit h[k,q'] is transformed, Figure 3b The node nd35[k,k'] in the word line WL[k] ( Figure 1a ), for all indices k = 1 to K. Fig. 9 In the auxiliary circuit 820, each node nd85[q,q']( Figure 8b ) can couple the word line WL[K+q] to match q=1 to Q.

[0168] In summary, the present invention can be a circuit module (eg Figure 1a 10) set up an auxiliary circuit set (for example Figure 1a 100 out of 100 Figure 2 200 or Figure 5 500), which may include two auxiliary circuits (e.g. Figure 2 or Figure 5 210 and 220, Figure 3a 310 and 320, Figure 4a 310 and 420, Figure 8a 310 and 820 or Fig. 9 910 and 820 in the circuit module are respectively a main auxiliary circuit and an additional auxiliary circuit, both of which are coupled to a first node (e.g., n1). This circuit module can operate in different modes (e.g., different supply voltages and / or different clock cycles) and receive one or more mode signals (e.g., dvs_sa_relax), and different levels of each mode signal are associated with different modes. When a control circuit (e.g., 20) in the circuit module controls the operating timing of a functional circuit (e.g., 40) according to the response characteristics of the first node, the main auxiliary circuit will remain enabled to provide a main conductive path at the first node, and the additional auxiliary circuit will be enabled or disabled when the mode signal is at the second level or the first level to provide or not provide an additional conductive path at the first node. Based on the operating arrangement of the main auxiliary circuit and the additional auxiliary circuit, the present invention can clearly and reliably know the change range and corresponding tolerance of the timing parameter (e.g., storage cell read time), and even if the mode switch occurs in an operating round, the circuit module of the present invention can continue the normal operation in the operating round. Furthermore, the auxiliary circuit set of the present invention may also include a calibration load and a calibration switch circuit (eg Figure 5 550 and 560, Figure 6a 650 and 660, or Figure 7a 650 and 760), the switch circuit can be calibrated according to a calibration control signal (eg Figure 5 , Figure 6a and Figure 7a The circuit module of the present invention may include one or more storage units (e.g., Figure 1a and 1c c[i,i'] in ), the functional circuit may include one or more sense amplifiers (e.g. Figure 1a , Figure 2 and Figure 5 sa[1] to sa[J]), the main auxiliary circuit and / or the additional auxiliary circuit may include one or more modified storage units (e.g. Figure 3a and Figure 3b h[k,k'] and / or Figure 4a and Figure 4b u[q,q'] in , the calibration load may include one or more additional storage units (e.g. Figure 6a and Figure 6b The characteristics of each modified storage unit and the additional storage unit can reflect the characteristics of the storage unit, so that the main conductive path, the additional conductive path and the adjustment load can reflect (follow) the characteristics of the storage unit, and the timing control of the control circuit on the functional circuit can dynamically reflect the characteristics of the storage unit.

[0169] In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. A person with ordinary knowledge in the technical field to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the following claims.

Claims

1. A circuit module with improved timing control, comprising: A functional circuit; a control circuit coupled between the functional circuit and a first node; a main auxiliary circuit coupled to the first node; and an additional auxiliary circuit, coupling the first node and a mode signal; wherein: The control circuit controls the operation timing of the functional circuit according to the response characteristic of the first node; The main auxiliary circuit provides one or more main conductive paths between the first node and a base node when enabled; The additional auxiliary circuit provides one or more additional conductive paths between the first node and the base node when enabled, and does not provide the one or more additional conductive paths when disabled; as well as When the control circuit controls the operation timing of the functional circuit according to the response characteristic of the first node, the main auxiliary circuit is enabled, and the additional auxiliary circuit is disabled or enabled according to whether the mode signal is a first mode level or a second mode level.

2. The circuit module according to claim 1, further comprising: one or more character lines; one or more bit lines; One or more memory cells, each of the memory cells being coupled to one of the one or more word lines and one of the one or more bit lines; - Follow the character line; a follow bit line; and One or more tracking memory cells, each of which is coupled to the tracking bit line and one of the one or more word lines; wherein: The first node is further coupled to the tracking bit line; and The functional circuit includes one or more sense amplifiers, each of which senses a voltage of one of the one or more bit lines according to the operating timing.

3. The circuit module according to claim 2, wherein: The control circuit controls the operation timing of the functional circuit according to the response characteristic of the first node when the tracking word line is driven.

4. The circuit module according to claim 2, wherein: The main auxiliary circuit includes one or more first modified storage units; Each of the first modified memory cells includes a gate pass transistor and a data transistor; The data transistor includes a data controlled terminal and two data channel terminals; The gate-pass transistor comprises a gate-pass controlled terminal and two gate-pass channel terminals; The two gate channel ends and the two data channel ends are serially connected between the first node and the base node; and One of the gate-controlled terminal and the data-controlled terminal is coupled to the following word line, and the other is coupled to a supply voltage.

5. The circuit module according to claim 2, wherein: The additional auxiliary circuit includes a front-stage transistor and a rear-stage transistor; The front-stage transistor comprises a front-stage controlled terminal and two front-stage channel terminals; The rear stage transistor comprises a rear stage controlled terminal and two rear stage channel terminals; The two front-stage channel ends and the two rear-stage channel ends are connected in series between the first node and the base node; and One of the front-stage controlled terminal and the rear-stage controlled terminal is coupled to the mode signal, and the other is coupled to the following word line. 6 . The circuit module as claimed in claim 5 , wherein the additional auxiliary circuit further comprises an inverter, and the one of the front-stage controlled end and the rear-stage controlled end is coupled to the mode signal via the inverter.

7. The circuit module according to claim 2, wherein: The additional auxiliary circuit includes one or more second modified storage units; Each of the second modified memory cells includes a gate pass transistor and a data transistor; The data transistor includes a data controlled terminal and two data channel terminals; The gate-pass transistor comprises a gate-pass controlled terminal and two gate-pass channel terminals; The two gate channel ends and the two data channel ends are serially connected between the first node and the base node; One of the gate-controlled terminal and the data-controlled terminal is coupled to the mode signal, and the other is coupled to the following word line. 8 . The circuit module as claimed in claim 7 , wherein the additional auxiliary circuit further comprises an inverter, and the one of the gate-controlled terminal and the data-controlled terminal is coupled to the mode signal via the inverter.

9. The circuit module according to claim 1, further comprising: a load adjustment; and A tuning switch circuit is coupled between the tuning load and the first node, and controls whether to conduct the tuning load to the first node according to a tuning control signal.

10. The circuit module according to claim 9, wherein: The calibration load includes: an additional bit line; and One or more additional memory cells, each of which is coupled to the additional bit line; wherein: The adjustment switch circuit is coupled to the adjustment load at the additional bit line.

11. The circuit module as claimed in claim 9, wherein the adjustment switch circuit comprises a main switch; the main switch is coupled between the first node and the adjustment load, and comprises a main switch control terminal; when the logic value of the main switch control terminal is a first logic value, the main switch conducts the adjustment load to the first node; when the logic value of the main switch control terminal is a second logic value, the main switch does not conduct the adjustment load to the first node.

12. The circuit module according to claim 11, wherein: The adjustment switch circuit further includes an additional switch coupled between the main switch control terminal, the adjustment load and a supply voltage; when the logic value of the main switch control terminal is the second logic value, the additional switch conducts the adjustment load to the supply voltage; when the logic value of the main switch control terminal is the first logic value, the additional switch does not conduct the adjustment load to the supply voltage.

13. The circuit module according to claim 11, wherein: The adjustment switch circuit further includes an adjustment logic circuit; the adjustment logic circuit includes a first logic input terminal, a second logic input terminal and a logic output terminal, which are respectively coupled to the first node, the adjustment control signal and the main switch control terminal.

14. The circuit module according to claim 13, wherein: The adjustment logic circuit determines whether the logic value of the first logic input terminal is the first logic value or the second logic value according to whether the voltage of the first logic input terminal is greater than an adjustment logic inversion point level, and determines the logic value of the logic output terminal according to the logic values ​​of the first logic input terminal and the second logic input terminal; The control circuit determines whether the logic value of the first node is the first logic value or the second logic value according to whether the voltage of the first node is greater than a control logic inversion point level; as well as The adjustment logic reversal point level is different from the control logic reversal point level. 15 . The circuit module as claimed in claim 14 , wherein the adjustment logic inversion point level is higher than the control logic inversion point level.

16. The circuit module as claimed in claim 13, wherein the calibration logic circuit further comprises a dual-input NAND gate and an inverter.

17. The circuit module according to claim 9, wherein: The response characteristic of the first node is related to a period during which the voltage of the first node changes from an initial level to a reference level; There is an intermediate level between the initial level and the reference level; When the tuning switch circuit controls whether to conduct the tuning load to the first node according to the tuning control signal, the tuning switch circuit controls whether to conduct the tuning load to the first node according to whether the tuning control signal is a first logic value during a period when the voltage of the first node changes from the initial level to the intermediate level; as well as During the period when the voltage of the first node changes from the intermediate level to the reference level, the tuning switch circuit stops conducting the tuning load to the first node, no matter whether the tuning control signal is the first logic value or not.

18. The circuit module according to claim 9, wherein: The response characteristic of the first node is related to a period during which the voltage of the first node changes from an initial level to a reference level; When the adjustment switch circuit controls whether to conduct the adjustment load to the first node according to the adjustment control signal, the adjustment switch circuit controls whether to conduct the adjustment load to the first node according to whether the adjustment control signal is a first logic value in a first part of the period; as well as During a second portion of the period, the tuning switch circuit stops conducting the tuning load to the first node, regardless of whether the tuning control signal is at the first logic value.

19. The circuit module according to claim 1, wherein: The circuit module is powered by a supply voltage; When the supply voltage is a first voltage value, the mode signal is the first mode level; When the supply voltage is a second voltage value, the mode signal is at the second mode level; and The first voltage value is different from the second voltage value.

20. The circuit module of claim 1, wherein: The circuit module is triggered by a clock; When the period of the clock is a first period value, the mode signal is the first mode level; When the period of the clock is a second period value, the mode signal is at the second mode level; and The first period value is different from the second period value.

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