A method of writing to an array of ferroelectric field effect transistors

Abstract

The application discloses a writing method of a ferroelectric field effect transistor array, and belongs to the technical field of micro-nano electronics. The method is used for a multi-level storage ferroelectric field effect transistor array with a 1T structure, and a self-compensation writing method is provided. A pulse sequence with a self-compensation waveform is used for writing, and different storage states in the multi-level storage are corresponded. A positive pulse is used for writing when the storage state is higher than a middle storage state, and a negative pulse is used for writing when the storage state is lower than the middle storage state. The state of a FeFET storage unit after writing is read and verified. When a writing error is found, an error correction program is started to correct the error to reach a target state. If the error correction program fails, a durability recovery program is started to recover the performance of the FeFET storage device. The application solves the reliability problems of large fluctuation between devices and cycles, limited durability and serious writing crosstalk between devices, has the advantages of simple process and small hardware cost, and is compatible with current advanced CMOS technology and easy to implement.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of micro-nano electronics, and particularly relates to a writing method of a ferroelectric field effect transistor (FeFET) array. BACKGROUND

[0002] With the advent of the post-moore era, new technologies such as artificial intelligence, Internet of Things, autonomous driving, and cloud computing are developing rapidly, and the total amount of global data is increasing year by year, which puts higher requirements on data storage and efficient processing. When processing data, a large amount of data needs to be frequently moved between computing units and storage units at all levels, which restricts the further improvement of computing power and causes serious power consumption bottlenecks. The root cause of this is that traditional storage units cannot simultaneously achieve the requirements of non-volatility, high storage density, and high-speed data access, thereby severely limiting the storage and efficient processing capacity of massive data, and therefore there is an urgent need to develop new non-volatile memory devices with high speed, high integration density, and low power consumption.

[0003] Among many new non-volatile memory device candidates, hafnium oxide-based ferroelectric field effect transistors (FeFETs) have great development prospects due to their ultra-low power consumption, high speed, potential for miniaturization, and potential for multi-level storage. However, FeFETs still face serious reliability problems, including fluctuations between devices and cycles, limited endurance, and serious write crosstalk problems in 1T structure arrays. When FeFETs are expanded to multi-level storage, i.e., storing multiple bits of information in a single cell, these reliability problems become even more serious. Any of the above reliability problems can become a bottleneck limiting the future application of FeFETs, and therefore needs to be addressed simultaneously.

[0004] Past research efforts have mostly focused on optimizing reliability from the perspective of device structure or materials. In recent years, the academic community has begun to focus on reliability improvement routes based on operation methods, such as target programming, endurance recovery, and V w / 2 or V w / 3 writing methods. However, at the current stage, there is still a lack of in-depth research on array operation methods, and the reliability of FeFET arrays needs to be further improved, especially in terms of write crosstalk. In addition, existing work is limited to solving single-angle reliability problems, and lacks comprehensive optimization of reliability. Integrating the proposed optimization methods into a compact and mutually compatible operation method is indispensable for the implementation of FeFET arrays. SUMMARY

[0005] In view of the problems in the prior art, the application provides a writing method for a ferroelectric field effect transistor (FeFET) array, which is used for a multi-level storage FeFET array with a 1T structure, and simultaneously solves the reliability problems of large fluctuation between devices and cycles (D2D and C2C), limited endurance and serious write crosstalk by using a self-compensation writing, error correction program and endurance recovery program, and has the advantages of simple process, small hardware overhead and the like, and is compatible with current advanced CMOS technology and easy to implement.

[0006] The technical scheme of the application is as follows:

[0007] A writing method for a ferroelectric field effect transistor (FeFET) array, the FeFET array is composed of FeFET storage units, word lines, bit lines and source lines to form a multi-level storage array with a 1T structure, FeFET storage units in the same row share the same word line, and FeFET storage units in the same column share the same bit line and source line, characterized in that, in the writing process of the FeFET array, a pulse sequence of self-compensation waveforms of positive and negative voltage pulses is used for writing, the state of the FeFET storage unit after writing is read and verified, when a writing error is found, an error correction program is started to correct, so as to reach the target state, if the error correction program fails, an endurance recovery program is started to recover the performance of the FeFET storage device; the method comprises the following steps:

[0008] 1) initializing the FeFET array, and setting each FeFET storage unit to an intermediate storage state;

[0009] 2) using a pulse sequence of self-compensation waveforms to write each row of the FeFET array, the pulse sequence of self-compensation waveforms is a pulse sequence of positive and negative voltage pulses alternately, and the absolute values of the amplitudes of adjacent positive and negative voltage pulses are substantially equal;

[0010] In the writing of each row, the pulse sequence of self-compensation waveforms, i.e., the positive and negative voltage pulses alternately, is used for writing, and different storage states in the multi-level storage are corresponded, a positive pulse is used for writing a storage state higher than the intermediate storage state, and a negative pulse is used for writing a storage state lower than the intermediate storage state; the sequence in writing is: first, a highest storage state, i.e., a positive pulse, is written, then a lowest storage state, i.e., a negative pulse, is written, then a second highest storage state, i.e., a positive pulse, is written, then a second lowest storage state, i.e., a negative pulse, is written, then a third highest storage state, i.e., a positive pulse, is written, then a third lowest storage state, i.e., a negative pulse, is written, and then storage states with different high and low states are written in turn.

[0011] Further, the step 1) initializes the FeFET array by first erasing the whole array to make every FeFET memory cell in the lowest state, then selecting all word lines of the array and applying a programming pulse corresponding to the middle storage state on the word lines while grounding all bit lines and source lines, so that all FeFET memory cells in the array are in the middle storage state, thus completing the initialization.

[0012] Further, in the step 2), when writing to a row of the FeFET array, the different storage states are written in order, and the writing step of each storage state includes:

[0013] 2-1) writing a positive / negative pulse corresponding to the current state to the FeFET memory cells to be written in the row;

[0014] 2-2) performing a read-after-write verification on the written FeFET memory cells: if the write verification is passed, the current state is successfully written; if the write verification fails, proceed to step 2-3) to start an error correction program to correct the written state to the target state;

[0015] 2-3) starting an error correction program to correct the written state: if the error correction is passed and the target state is reached, the current state is successfully written; if the error correction fails, proceed to step 2-4) to start a durability recovery program;

[0016] 2-4) starting a durability recovery program, after recovering the performance of the FeFET memory device, re-writing the pulse corresponding to the current state to the recovered FeFET memory device, and repeating step 2-2) until the current state is successfully written.

[0017] Further, in the step 2), when writing to a row of the FeFET array, the different storage states are written in order, and the writing step of each storage state includes:

[0018] Further, in the step 2), when writing to a row of the FeFET array, the different storage states are written in order, and the writing step of each storage state includes:

[0019] Further, the read-after-write verification of step 2-2) is used to verify whether the storage state of the FeFET memory cell meets the requirements after writing to the FeFET memory cell, by measuring the I d -V gThe threshold voltage of the FeFET is extracted from the curve, and the test is performed according to whether the threshold voltage is within the threshold interval.

[0020] Further, the error correction procedure of the step 2-3) is used to correct the error storage state; when the write error is detected, according to whether the error threshold state is higher than the upper limit or lower than the lower limit of the threshold interval, a pulse sequence with a certain step increment or decrement is selected for re-writing; when the threshold voltage exceeds the upper limit of the threshold interval, a positive pulse sequence with increment is used for error correction, and each time the amplitude of the previous pulse is increased by a step to re-write, and after each write, the read verification is performed, until the threshold voltage is within the correct interval, and then the error correction procedure is stopped; similarly, when the threshold voltage is less than the lower limit of the threshold interval, a negative pulse sequence with decrement is used for re-writing until the threshold voltage reaches the correct interval; the pulse number of the pulse sequence for error correction is set to a limit, and if the error storage state is not restored after exceeding the limit, it is determined that the error correction procedure fails, and the endurance recovery procedure needs to be started.

[0021] Further, the endurance recovery procedure of the step 2-4) is used to recover the degraded FeFET device performance after cycling; according to the actual device characteristics, a negative voltage pulse with a larger amplitude is applied to the gate of the FeFET, so that the trapped electrons accumulated in the cycle are de-trapped, thereby recovering the threshold voltage drift caused by the cycle process; the selected recovery voltage pulse amplitude has an absolute value of 6-10V, and the pulse width is 10us-1ms.

[0022] The technical effects of the present application are as follows:

[0023] I. In the proposed new FeFET array writing method, by using the error correction method, if write error is detected after each write, error correction is performed to adjust the threshold voltage to reach the correct storage state, thereby effectively avoiding the write error caused by the D2D or C2C fluctuation of the FeFET storage unit, and reducing the error rate of the FeFET memory. Compared with the commonly used target programming method, the proposed error correction method has the advantages of small time cost and simple operation.

[0024] The error correction method proposed in the application uses an increasing or decreasing pulse sequence to correct the error storage state. If the threshold voltage is detected to exceed the upper limit of the threshold interval, a positive pulse sequence with voltage increment (fixed step) is used for error correction, and each time the amplitude is increased by a step on the basis of the previous pulse to re-write. Due to the increase of the amplitude, the polarization intensity in the FeFET ferroelectric layer pointing to the channel direction increases, and the influence of the polarization charge on the channel potential is more significant, and the threshold voltage decreases. After each write pulse, it is read and verified, and once the threshold voltage returns to the correct interval, the error correction is stopped. Correspondingly, if the threshold voltage is detected to be less than the lower limit of the threshold interval, a negative pulse sequence with voltage decrement (fixed step) is used for error correction. Since the negative pulse amplitude increases, the polarization intensity in the FeFET ferroelectric layer pointing to the gate direction increases, and therefore the threshold voltage increases.

[0025] II. In the proposed new FeFET array write method, a durable recovery method is used to recover the degraded device performance after the FeFET is fatigued due to the increase of the cycle number (i.e. the number of write times), so as to further prolong the durability of the FeFET.

[0026] With the increase of the cycle number of the FeFET, the electrons captured by the interface traps in the FeFET gradually accumulate, and the shielding effect of the polarization charge of the ferroelectric layer increases, which leads to the gradual shift of the threshold voltage of the highest storage state of the FeFET to the negative direction. At the same time, it is also observed that the D2D and C2C fluctuations of the FeFET gradually increase. The shift of the threshold voltage and the increase of the fluctuations lead to the gradual increase of the error rate of the FeFET with the cycle number, which may cause the error correction program to fail. When the error correction program is detected to fail, the durable recovery program starts: by applying a negative voltage pulse with a larger amplitude and pulse width to the gate of the FeFET, the accumulated electrons in the cycle are de-trapped, so as to shift the threshold voltage of the highest storage state to the positive direction, and restore the storage performance.

[0027] III. In the proposed new FeFET write method, a novel self-compensation write method is proposed. Compared with the traditional write method, the self-compensation waveform used causes the write crosstalk of other unselected cells in the FeFET array to cancel each other out during each write, thereby suppressing the accumulation of write crosstalk.

[0028] In the traditional write method, the FeFET memory array is first completely erased to the lowest storage state, and then programmed row by row. When programming each row, only an incremental positive voltage pulse is used for programming, which causes a positive write crosstalk to other FeFET storage units in the array each time programming, and the write crosstalk gradually accumulates, causing the threshold voltage of the FeFET storage unit to deviate. In the proposed self-compensating write method, the FeFET array is first initialized to the intermediate state, and then written row by row. When writing each row, a pulse sequence of alternating positive and negative pulses is used for writing, which causes the write crosstalk to unselected cells to also be positive and negative alternation each time writing, and the absolute value of the amplitude is basically equal, so the write crosstalk cancels out each other, thereby suppressing the threshold voltage deviation and reducing the write crosstalk.

[0029] Fourthly, in the novel FeFET array write method proposed by the present application, the error correction program, the endurance recovery program and the self-compensating programming waveform are compatible with each other, and can be realized in a single workflow, while solving the reliability problems of D2D and C2C large fluctuation, limited endurance and serious write crosstalk faced by FeFET. At the same time, the novel FeFET array write scheme proposed is simple to operate, the process is compact, and can be realized by simple circuit design, with small hardware overhead of peripheral circuit. The present application lays a foundation for developing high-reliability FeFET memory array. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 In the figure, (a) is a schematic diagram of a multi-level storage FeFET array with a 1T structure, and (b) is a working flowchart of the write method of the ferroelectric field effect transistor array of the embodiment of the present application;

[0031] Figure 2 is a waveform diagram comparison between the traditional FeFET array write method and the FeFET array automatic compensation write method of the present application;

[0032] Figure 3 is the error correction program and result of the embodiment of the present application, wherein:

[0033] (a) is a pulse sequence for the error correction program, including an incremental positive pulse sequence and a decreasing negative pulse sequence;

[0034] (b) is the D2D and C2C fluctuation of FeFET extracted before and after error correction and the calculated error rate in the initial state before error correction and after error correction;

[0035] (c) is the D2D and C2C fluctuation of FeFET extracted before and after error correction and the calculated error rate after 10 3 cycles of error correction and after error correction;

[0036] Figure 4 This is a schematic diagram of the durability recovery process and results of an embodiment of the present invention, wherein:

[0037] (a) is a schematic diagram of the endurance recovery process. After the error correction process fails, a negative voltage pulse of -9 V and 100 μs is used for endurance recovery.

[0038] (b) shows two durability recovery processes before and after the durability recovery process according to the embodiment of the present invention;

[0039] (c) is the FeFET of the embodiment of the present invention after 10 6 After durability cycles and durability recovery treatment d -V g curve;

[0040] (d) shows the change of threshold voltage with cycle number after configuring the durability recovery program of the FeFET according to the embodiment of the present invention. After configuring the durability recovery program, the durability of the FeFET is improved to more than 10 8 Secondary cycle;

[0041] (e) shows the variation of error rate and D2D and C2C fluctuations with cycle number of the FeFET according to an embodiment of the present invention after configuring the durability recovery program and error correction program;

[0042] Figure 5 The following is a comparison of the write crosstalk between the self-compensation write method and the traditional write method for the 6×6 FeFET array prepared in accordance with an embodiment of the present invention, wherein:

[0043] (a) is a schematic diagram of specific waveforms of the self-compensation writing method according to an embodiment of the present invention;

[0044] (b) is a schematic diagram of specific waveforms of a conventional writing method for comparison in an embodiment of the present invention;

[0045] (c) is a comparison of the threshold voltage offsets of each memory cell in the first row of a 6×6 FeFET array prepared in accordance with an embodiment of the present invention, after the entire array is written using the self-compensating writing method of the present invention and the conventional writing method based on a randomly generated state table. DETAILED DESCRIPTION

[0046] The present invention will be further described below with reference to the accompanying drawings and through examples.

[0047] 1T structure multi-level storage FeFET array Figure 1 As shown in (a), FeFET memory cells in the same row share the same word line, while FeFET memory cells in the same column share the same bit line and source line.Figure 1 (b) shows, including self-compensating write waveform, read-after-write verification, error correction procedure, endurance recovery procedure, etc. In actual work, firstly, the entire FeFET memory array is initialized to the intermediate state, that is, between the 01 state and the 10 state, and then the row-by-row writing is performed. When writing a row, the writing is performed in the order of 11, 00, 10 and 01 states. After each time of writing the current state, the read-after-write verification is performed, the threshold voltage of the FeFET is extracted, if it is in the correct threshold voltage interval, it means that the writing is correct, and the next storage state continues to be written; if it is not in the correct threshold voltage interval, it means that the writing is incorrect, and the error correction procedure is started to correct, if the error correction procedure passes, the writing of the next storage state continues, otherwise, the endurance recovery procedure is continued to be started to recover the incorrect FeFET memory unit. Correspondingly, the error correction procedure can reduce the D2D and C2C fluctuations of the FeFET, the endurance recovery procedure can prolong the endurance of the FeFET, and the self-compensating waveform can suppress the write crosstalk of the array.

[0048] The novel self-compensating write method of the present application is compared with the conventional write method as shown in Figure 2 (b) shows that in the conventional write method, only a positive voltage pulse is used for programming, which will cause the accumulation of write crosstalk, and in the self-compensating write method, since the positive and negative voltage pulses are alternately used for writing, the polarity of the crosstalk between each time of writing is opposite, and the size is similar, so the crosstalk between each time of writing is compensated, which can effectively suppress the write crosstalk.

[0049] As shown in Figure 3 (a), the error correction procedure in the embodiment of the present application includes two types of pulse sequences, if the detected threshold voltage is greater than the upper threshold, the incremental positive pulse sequence with a step of +0.1V is used for error correction; if the detected threshold voltage is less than the upper threshold, the decremental negative pulse sequence with a compensation of -0.1V is used for error correction. Each error correction pulse contains at most 10 correction pulses, if after 10 correction pulses, the threshold voltage of the FeFET memory unit still does not return to the correct threshold interval, it means that the error correction procedure fails. The D2D and C2C fluctuations of the FeFET before and after error correction and the calculated error rate after the initial state and after 10 3 endurance cycles are extracted as shown in Figure 3 (b) and Figure 3 (c). In the initial state, the error rate of the FeFET before error correction is about 0.725%, and after the error correction procedure, the error rate of the FeFET is reduced to about 0.02%; the 10 3After the first endurance cycle, the error rate of the FeFET before error correction was approximately 2.1%, while after the error correction process, the error rate of the FeFET was reduced to approximately 0.5%. This significant reduction in the error rate of the FeFET after error correction demonstrates that the error correction process of the present invention can effectively suppress storage state errors caused by D2D and C2C fluctuations in the FeFET.

[0050] The durability recovery process of the embodiment of the present invention is as follows Figure 4 As shown in (a), after a certain number of durability cycles, due to device performance degradation, read verification errors may occur and the error correction program may fail. At this time, the durability recovery program is started, using a negative voltage pulse of -9V, 100μs for durability recovery, and then the durability cycle is continued. The two durability fatigue processes of the FeFET of the embodiment of the present invention before and after durability recovery are shown in Figure 2. Figure 4 As shown in (b), after the durability recovery process, the error rate of the FeFET is reduced to the same as that of the initial state, and the two durability fatigue processes are almost completely consistent, which shows that the durability recovery process can completely restore the storage performance of the FeFET that has degraded due to the accumulation of cycle times. 6 After durability cycles and durability recovery treatment d -V g Curves such as Figure 4 As shown in (c), after durability recovery, the I corresponding to state 11 d -V g The curve shifts toward the negative direction of the x-axis and returns to the position at the initial state. This is mainly because the large negative voltage pulse applied during the durability recovery process causes the electrons accumulated in the interface traps during the cycle to be decaptured. The change of the threshold voltage of the FeFET of the embodiment of the present invention with the durability recovery process as the number of cycles is shown in Figure 2. Figure 4 (d) As shown in 6 After the durability cycle, a durability recovery pulse is applied as a cycle. After 100 cycles, the threshold voltage of each state of FeFET has no obvious shift, which shows that after configuring the durability recovery program, the durability of FeFET can be improved to more than 10 8 The error rate and D2D and C2C fluctuations of the FeFET of the embodiment of the present invention after configuring the durability recovery program vary with the number of cycles. Figure 4 As shown in (e), the error rate of FeFET is reduced from 6% to 0.8% after the durability recovery procedure, and further reduced to 0.4% after the configuration error correction procedure. 8 The value of D2D and C2C of FeFET remains low at about 0.4% within the cycle. In addition, the fluctuation of D2D and C2C of FeFET remains almost unchanged during the cycle after durability recovery. This further shows that the durability of FeFET can be improved to more than 108 Second cycle.

[0051] The specific waveform diagram of the self-compensation writing method according to the embodiment of the present invention is as follows: Figure 5 As shown in (a), the entire array is first erased to the 00 state, and then a suitable positive voltage pulse is applied to initialize all FeFET memory cells to the intermediate state. Then, writing is performed row by row. When writing a row, the corresponding positive and negative voltage pulses are applied alternately to the selected word line WL in the order of 11, 00, 10 and 00 states, and the voltage of the selected bit line BL is 0. At the same time, a voltage pulse with an amplitude of half the amplitude of the write pulse is applied to the unselected word line WL and bit line BL to suppress the write crosstalk to the unselected cells, which is the conventionally used V w / 2 suppression scheme. Each time a state is written, read I d -V g Curve, extract V th Perform read verification. After completing the write of one row, proceed to the next row until the entire array is written. Finally, read the threshold voltage of the FeFET storage unit in the first row again to check the write crosstalk. The specific waveform of the traditional write method is as follows Figure 5 As shown in (b), the entire array is first erased to the 00 state, and then written row by row. When writing a row, the corresponding positive voltage pulses are used to write in the order of 01, 10, and 11 states, and V is used on the unselected WL and BL. w / 2 suppression scheme is used to suppress write crosstalk. After completing the writing of one row, continue writing the next row until the entire array is written. Similarly, the threshold voltage of the FeFET storage unit in the first row is read to check the write crosstalk. The results after writing using the self-compensation writing method of the embodiment of the present invention and the traditional method are shown as follows: Figure 5 As shown in (c), when using the traditional write method, the FeFET has a serious threshold voltage shift, especially in the 00 state. This is due to the accumulation of write crosstalk in the traditional write method. However, when using the self-compensation write method, there is almost no threshold voltage shift in each storage state of the FeFET. This is because the self-compensation write waveform cancels out the write crosstalk. Therefore, the self-compensation write method of the embodiment of the present invention can effectively suppress write crosstalk in the FeFET array.

[0052] Finally, it should be noted that the purpose of disclosing the embodiments is to facilitate a further understanding of the present invention. However, those skilled in the art will appreciate that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments; the scope of protection claimed by the present invention shall be determined by the scope defined in the claims.

Claims

1. A write method of a FeFET array, the FeFET array consisting of a multi-level storage array of a 1T structure of FeFET storage cells, word lines, bit lines, and source lines, FeFET storage cells of the same row sharing the same word line, FeFET storage cells of the same column sharing the same bit line and source line, characterized by, In the writing process of the FeFET array, a pulse sequence of self-compensating waveforms of positive and negative voltage pulses is used for writing, the written state of the FeFET storage unit is verified, when a writing error is found, an error correction program is started to correct, to achieve the target state, if the error correction program fails, a durability recovery program is started to restore the performance of the FeFET storage device; the method comprises the following steps: 1) initializing the FeFET array, setting each FeFET storage unit to an intermediate storage state; 2) using a pulse sequence of self-compensating waveforms, writing each row of the FeFET array, the pulse sequence of self-compensating waveforms is a pulse sequence of positive and negative voltage pulses alternately, the absolute values of the amplitudes of adjacent positive and negative voltage pulses are substantially equal; In the writing of each row, the pulse sequence of self-compensating waveforms, i.e. positive and negative voltage pulses alternately, is used for writing, corresponding to different storage states in the multi-level storage, the storage state higher than the intermediate storage state is written by a positive pulse, and the storage state lower than the intermediate storage state is written by a negative pulse; the sequence during writing is: first writing the highest storage state, i.e. a positive pulse, then writing the lowest storage state, i.e. a negative pulse, then writing the second highest storage state, i.e. a positive pulse, then writing the second lowest storage state, i.e. a negative pulse, then writing the third highest storage state, i.e. a positive pulse, then writing the third lowest storage state, i.e. a negative pulse, and then writing the storage states with different high and low states.

2. The method of writing to a FeFET array of claim 1, wherein, The step 1) initializes the FeFET array, the method is: first erasing the entire array, so that each FeFET storage unit is in the lowest state, then selecting all word lines of the array, applying a programming pulse corresponding to the intermediate storage state on the word line, and grounding all bit lines and source lines, so that all FeFET storage units in the array are in the intermediate storage state, completing the initialization.

3. The method of writing to a FeFET array of claim 1, wherein, In the step 2), when writing a row of the FeFET array, the storage states with different high and low states are written in turn according to the sequence, and the writing step of each storage state comprises: 2-1) writing a positive / negative pulse corresponding to the current state to the FeFET storage unit to be written in the row; 2-2) verifying the written state of the written FeFET storage unit after writing: if the writing is verified to be correct, the current state is written successfully; if the writing is verified to be incorrect, step 2-3) is entered to start an error correction program to correct the written state to achieve the target state; 2-3) starting the error correction program to correct the written state: if the error correction is successful and the target state is achieved, the current state is written successfully; if the error correction fails, step 2-4) is entered to start a durability recovery program; 2-4) starting the durability recovery program, after restoring the performance of the FeFET storage device, re-writing the pulse corresponding to the current state to the restored FeFET storage device, and repeating step 2-2) until the current state is written successfully.

4. The method of writing to a FeFET array of claim 1, wherein, In the step 2), each row of the FeFET array is written by selecting the corresponding word line of each row.

5. The method of writing to a FeFET array of claim 1, wherein, In the step 2), when writing to a row of the FeFET array, the FeFET memory cells in the row storing the same storage state are simultaneously written by: applying a corresponding write pulse on the word line corresponding to the selected row, grounding the bit line and source line corresponding to the memory cells to be written, and applying a voltage pulse with an amplitude of 1 / 2 of the amplitude of the write pulse on the bit line and source line of the other unselected memory cells in the row and the word line corresponding to the other unselected rows, for suppressing write crosstalk.

6. The method of writing to a FeFET array of claim 3, wherein, The read-after-write verification of step 2-2) is used to verify whether the storage state of the FeFET memory cell meets the requirements after writing to the FeFET memory cell, by measuring the I d -V g The threshold voltage of the FeFET memory cell is extracted from the curve, and the verification is performed according to whether it is within the threshold interval.

7. The method of writing to a FeFET array of claim 3, wherein, The error correction procedure of the step 2-3) is used to correct the error storage state; when the write error is detected, according to whether the error threshold state is above the upper limit or below the lower limit of the threshold interval, a pulse sequence with a certain step size is selected to be increased or decreased to re-write; When the threshold voltage exceeds the upper limit of the threshold interval, the error correction is performed by using an increasing positive pulse sequence, each time the amplitude of the previous pulse is increased by a step size to re-write, and after each write, the read verification is performed until the threshold voltage is in the correct interval, and then the error correction procedure is stopped; Similarly, when the threshold voltage is less than the lower limit of the threshold interval, a decreasing negative pulse sequence is used to re-write until the threshold voltage reaches the correct interval. The pulse number of the pulse sequence for error correction is set to a limit, and if the error storage state is not restored after exceeding the limit, it is determined that the error correction procedure fails, and a durability recovery procedure needs to be started.

8. The method of writing to a FeFET array of claim 3, wherein, The durability recovery procedure of the step 2-4) is used to recover the performance of the degraded FeFET device after cycling; according to the actual device characteristics, a larger amplitude negative voltage pulse is applied to the gate of the FeFET, so that the trapped electrons accumulated in the cycle are de-trapped, thereby recovering the threshold voltage drift caused by the cycle process; the absolute value of the selected recovery voltage pulse amplitude is 6-10V, and the pulse width is 10μs-1ms.

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