A silicon carbide wafer level packaging structure and a manufacturing method thereof

Abstract

The application discloses a silicon carbide wafer-level packaging structure and a manufacturing method thereof, which comprises a silicon carbide chip, an under-bump metal, a first insulating material, a second insulating material, a third insulating material, a first metal bump, and a second metal bump. The second metal bump is matched with an electrode metal structure on the lower surface of the silicon carbide chip. The outer end of the first metal bump is provided with a third metal bump. The outer end of the second metal bump is provided with a fourth metal bump. The outer side of the silicon carbide chip is provided with a fourth insulating material. The application optimizes the volume of the silicon carbide device, has no connecting lead wire, has low stray inductance caused by packaging, has fast transmission speed, is suitable for high-frequency application, has a short production cycle in wafer-level operation, saves packaging cost, has a short distance between the chip and the pin, has good heat dissipation, has no lead wire heating, and is suitable for high-temperature working conditions.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor power device packaging, and more particularly to a silicon carbide wafer-level packaging structure and a manufacturing method thereof. BACKGROUND

[0002] The main component material of the silicon carbide device is silicon carbide. Compared with ordinary silicon material, the breakdown field strength of silicon carbide can reach 3.5 (MV / cm), which is about 10 times that of silicon. Therefore, the thickness of the required drift layer for voltage resistance is reduced, and the characteristics of high voltage resistance and low on-resistance and low on-resistance thermal resistance are combined. The thermal conductivity of silicon carbide can reach 4.0 (W / cm·K), which is about 3 times that of silicon. Silicon carbide is suitable for high-temperature working conditions. The saturated electron drift velocity of silicon carbide can reach 2.0*10 7 (cm / s), which is about 2 times that of silicon, and can realize high-frequency application.

[0003] For the silicon carbide device, the traditional packaging needs to cut the silicon carbide wafer into a single chip, then the chip is welded on the substrate, the lead wire is welded on the front surface of the chip, then the chip is placed in a mold for plastic encapsulation and solidification, the pins are electroplated, and the ribs are formed. This traditional packaging form has many steps, a large amount of manual operation, low efficiency, large stray inductance, slow heat dissipation and other problems. SUMMARY

[0004] (I) Technical problems to be solved

[0005] In view of the problems in the prior art, the present application provides a silicon carbide wafer-level packaging structure and a manufacturing method thereof to solve the technical problems mentioned in the background.

[0006] (II) Technical solutions

[0007] To achieve the above object, the present application provides the following technical scheme: A silicon carbide wafer level packaging structure and a manufacturing method thereof, the first aspect of the present application provides a silicon carbide wafer level packaging structure, comprising a silicon carbide chip, a bump-down metal is arranged on the upper end of the silicon carbide chip, the bump-down metal is matched with the electrode metal structure on the upper surface of the silicon carbide chip, the upper side of the silicon carbide chip and the two sides of the bump-down metal are both provided with a first insulating material, the upper end of the first insulating material is provided with a second insulating material, the lower end of the silicon carbide chip is provided with a third insulating material, the upper end of the bump-down metal is provided with a first metal bump, the lower end of the silicon carbide chip is provided with a second metal bump, the second metal bump is matched with the electrode metal structure on the lower surface of the silicon carbide chip, the outer end of the first metal bump is provided with a third metal bump, the outer end of the second metal bump is provided with a fourth metal bump, the outer side of the silicon carbide chip is provided with a fourth insulating material, the silicon carbide chip, the bump-down metal, the first insulating material, the second insulating material, the third insulating material, the first metal bump and the second metal bump are all located in the fourth insulating material, and the outer ends of the third metal bump and the fourth metal bump protrude from the fourth insulating material.

[0008] The present application is further provided that the composition material of the silicon carbide chip includes silicon carbide MOSFET, silicon carbide diode, silicon carbide JFET, silicon carbide IGBT, silicon carbide BJT and silicon carbide GTO, and the thickness of the silicon carbide chip is 100-400 um.

[0009] The present application is further provided that the material of the bump-down metal is titanium-nickel-vanadium-silver, nickel-gold or nickel-palladium-gold, if the material is titanium-nickel-vanadium-silver, the thickness of the metal titanium is less than 0.5 um, the thickness of the metal nickel-vanadium is less than 1 um, and the thickness of the metal silver is 1-10 um, if the material is nickel-gold or nickel-palladium-gold, the thickness of the metal nickel is 1-10 um, the thickness of the metal palladium is less than 1 um, and the thickness of the metal gold is less than 0.5 um.

[0010] The present application is further provided that the material of the first insulating material is silicon oxide or silicon nitride, and the thickness is 0.1-10 um, and the materials of the second insulating material and the third insulating material are baked and cured polyimide, and the thickness is 10-200 um.

[0011] The present application is further provided that the metal material of the first metal bump and the second metal bump is copper, and the thickness is 30-200 um, and the metal material of the third metal bump and the fourth metal bump includes tin-lead alloy, tin-copper alloy, tin-silver alloy, tin-antimony alloy and tin-bismuth alloy, and the thickness is 100-300 um.

[0012] The second aspect of the present application provides a manufacturing method of a silicon carbide wafer level packaging structure, the method comprises:

[0013] Step one:

[0014] The bump under metal is prepared on the silicon carbide chip by evaporation peeling or chemical plating;

[0015] Step two:

[0016] Then, the first insulating material is deposited on the front surface of the wafer by photolithography etching, and then the second insulating material is sprayed on the front surface of the wafer and baked and cured by photolithography, and the third insulating material is sprayed on the back surface and baked and cured by photolithography.

[0017] Step three:

[0018] The first metal bump and the second metal bump are prepared on the front and back surfaces of the wafer by electroplating peeling process, and then the third metal bump and the fourth metal bump are prepared on the front and back surfaces of the wafer by laser ball planting process or column planting process.

[0019] Step four:

[0020] The wafer is cut into single chips and placed in a packaging mold for packaging, and the fourth insulating material in a hot melt state is injected, and after the fourth insulating material is cooled and solidified, the chip is wrapped and packaged, and the packaging mold is removed, and the packaging is completed.

[0021] The packaging mold is further provided by the block level upper mold and the block level lower mold, and the block level third metal bump socket, the block level fourth metal bump socket and the block level feeding port are provided in the block level upper mold and the block level lower mold, the wafer is cut into single chips and placed in the packaging mold, and the fourth insulating material is injected through the block level feeding port.

[0022] The packaging mold is further provided by the block level upper mold and the block level lower mold, and the block level third metal bump socket, the block level fourth metal bump socket and the block level feeding port are provided in the block level upper mold and the block level lower mold, the wafer is cut into single chips and placed in the packaging mold, and the fourth insulating material is injected through the block level feeding port.

[0023] (Three) beneficial effects

[0024] Compared with the prior art, the present application provides a silicon carbide wafer level packaging structure and a manufacturing method thereof, which has the following beneficial effects:

[0025] 1. Through wafer-level operation, the packaging efficiency is improved, and the device size is reduced; a polyimide insulating layer is made on the front and back of the wafer, which has good insulating support and thermal expansion coefficient matching with the chip, can reduce the risk of cracking and delamination under high temperature working environment, and improve the reliability of the device; metal bumps are used instead of leads, there is no connecting lead, the stray inductance is reduced, the transmission speed is improved, and it is suitable for high-frequency applications; the distance between the chip and the pin is short, the thickness of the metal bump is thin, the heat dissipation is good, and there is no lead heating, which is suitable for high temperature working conditions; the area of the packaged device is close to 1:1 with the chip area, the thickness is about 0.5-2mm, the overall size is small, and it is suitable for the future development trend of small and integrated packaging. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 It is a front structure diagram of a silicon carbide wafer-level packaging structure and a manufacturing method thereof in the application.

[0027] Figure 2 It is a structure diagram when the silicon carbide wafer is not divided in the application.

[0028] Figure 3 It is a structure diagram of the cooperation of the block-level upper half mold and the block-level lower half mold in the application.

[0029] Figure 4 It is a structure diagram of the cooperation of the board-level upper half mold and the board-level lower half mold in the application.

[0030] In the figure: 1, silicon carbide chip; 2, metal under bump; 3, first insulating material; 4, second insulating material; 5, third insulating material; 6, first metal bump; 7, second metal bump; 8, third metal bump; 9, fourth metal bump; 10, fourth insulating material; 11, silicon carbide wafer; 12, block-level upper half mold; 13, block-level lower half mold; 14, block-level third metal bump socket; 15, block-level fourth metal bump socket; 16, block-level feed port; 17, board-level upper half mold; 18, board-level lower half mold; 19, board-level third metal bump socket; 20, board-level fourth metal bump socket; 21, board-level feed port. DETAILED DESCRIPTION

[0031] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0032] It should be noted that, unless otherwise specified, all technical and scientific terms used in the present application have the same meaning as generally understood by those skilled in the art to which the present application belongs.

[0033] In the present application, the orientation such as "upper, lower" is generally directed to the direction shown in the drawings, or is directed to the vertical, perpendicular or gravity direction, unless otherwise stated; similarly, for the convenience of understanding and description, "left, right" is generally directed to the left and right shown in the drawings; "inner, outer" refers to the inner and outer relative to the contour of each component itself, but the above orientation words are not used to limit the present application.

[0034] Referring to Figure 1 A silicon carbide wafer level packaging structure and a manufacturing method thereof, comprising a silicon carbide chip 1, a bump-down metal 2 arranged on the upper end of the silicon carbide chip 1, the bump-down metal 2 cooperating with the electrode metal structure on the upper surface of the silicon carbide chip 1, a first insulating material 3 arranged on both sides of the bump-down metal 2 and above the silicon carbide chip 1, a second insulating material 4 arranged on the upper end of the first insulating material 3, a third insulating material 5 arranged on the lower end of the silicon carbide chip 1, a first metal bump 6 arranged on the upper end of the bump-down metal 2, a second metal bump 7 arranged on the lower end of the silicon carbide chip 1, the second metal bump 7 cooperating with the electrode metal structure on the lower surface of the silicon carbide chip 1, a third metal bump 8 arranged on the outer end of the first metal bump 6, a fourth metal bump 9 arranged on the outer end of the second metal bump 7, a fourth insulating material 10 arranged on the outer side of the silicon carbide chip 1, the silicon carbide chip 1, the bump-down metal 2, the first insulating material 3, the second insulating material 4, the third insulating material 5, the first metal bump 6 and the second metal bump 7 are all located within the fourth insulating material 10, and the outer ends of the third metal bump 8 and the fourth metal bump 9 protrude from the fourth insulating material 10.

[0035] In the present embodiment, the bump-down metal 2 on the front electrode of the silicon carbide chip 1 can improve the adhesion between the chip and the metal bump, the first insulating material 3, the second insulating material 4 and the third insulating material 5 between the bump-down metals 2 form respective insulating layers cooperating to play an electrical isolation role, the first metal bump 6, the second metal bump 7, the third metal bump 8 and the fourth metal bump 9 on the front and back of the silicon carbide chip 1 cooperate to provide an electrical connection and a heat dissipation channel, and the insulating layer formed by the fourth insulating material 10 between the respective metal bumps plays an electrical isolation and support role.

[0036] Referring to Figure 1 and Figure 2As an embodiment of the wafer level packaging structure: the constituent material of the silicon carbide chip 1 includes silicon carbide MOSFET, silicon carbide diode, silicon carbide JFET, silicon carbide IGBT, silicon carbide BJT, silicon carbide GTO, and the thickness of the silicon carbide chip 1 is 100-400um, the material of the bump under metal 2 is titanium nickel vanadium silver, nickel gold or nickel palladium gold, and if it is titanium nickel vanadium silver material, the thickness of the metal titanium is less than 0.5um, the thickness of the metal nickel vanadium is less than 1um, and the thickness of the metal silver is 1-10um, if it is nickel gold or nickel palladium gold material, the thickness of the metal nickel is 1-10um, the thickness of the metal palladium is less than 1um, and the thickness of the metal gold is less than 0.5um, the material of the first insulating material 3 is silicon oxide or silicon nitride, and the thickness is 0.1-10um, and the second insulating material 4 and the third insulating material 5 are the material of baked and cured polyimide, and the thickness is 10-200um, the metal material of the first metal bump 6 and the second metal bump 7 is copper, and the thickness is 30-200um, the metal material of the third metal bump 8 and the fourth metal bump 9 includes tin-lead alloy, tin-copper alloy, tin-silver alloy, tin-antimony alloy and tin-bismuth alloy, and the thickness is 100-300um.

[0037] Please refer to Figures 1-2 The present application provides a manufacturing method of a silicon carbide wafer level packaging structure, the method comprising:

[0038] Step one:

[0039] The bump under metal 2 is prepared on the silicon carbide chip 1 by evaporation stripping or electroplating;

[0040] Step two:

[0041] Then the first insulating material 3 is deposited and etched by photolithography on the front surface of the wafer, then the second insulating material 4 is sprayed and baked and cured by photolithography on the front surface of the wafer, and the third insulating material 5 is sprayed and baked and cured by photolithography on the back surface of the wafer;

[0042] Step three:

[0043] The first metal bump 6 and the second metal bump 7 are prepared on the front and back surfaces of the wafer by electroplating stripping process, and then the third metal bump 8 and the fourth metal bump 9 are prepared on the front and back surfaces of the wafer by laser ball planting process or column planting process.

[0044] Step four:

[0045] The wafer is cut into single chips and placed in a packaging mold for packaging, and the fourth insulating material 10 in a hot melt state is injected, and after the fourth insulating material 10 is cooled and solidified, the chip is wrapped and packaged, the packaging mold is removed, and the packaging is completed.

[0046] Specifically, during the production, the silicon carbide wafer 11 is marked with a reference numeral 11 for easy identification in the drawings and the specification. The silicon carbide wafer 11 contains a plurality of silicon carbide chips 1, and the under-bump metal 2 is prepared by evaporation stripping or chemical plating. If the evaporation stripping method is adopted, the contact area between the front electrode metal and the under-bump metal 2 is first defined on the front side of the silicon carbide wafer 11 by photolithography, and then the under-bump metal 2 is evaporated on the front side of the silicon carbide wafer 11, and then the photoresist and the metal thereon are removed by stripping liquid, and then the front side of the silicon carbide wafer 11 and the bump are removed. The first insulating material 3 is deposited on the surface of the metal under the block 2, and then the metal under the bump 2 opening area is defined by photolithography, and then the photoresist is removed. Then, polyimide is sprayed on the front and back of the silicon carbide wafer 11 respectively, and then the metal under the bump 2 opening area and the electrode metal opening area on the back of the silicon carbide wafer 11 are defined by photolithography. The insulating material made of polyimide is formed by baking and curing to become the second insulating material 4 and the third insulating material 5. The polyimide provides good insulating support and matches the thermal expansion coefficient and the silicon carbide chip 1. Good moisture-proof performance can reduce the risk of device cracking and delamination in high-temperature working environments, and reduce the risk of moisture entering the chip and causing failure in high-humidity working environments, so as to improve device reliability. Then, the first metal bump 6 and the second metal bump 7 are prepared on the front and back sides of the silicon carbide wafer 11 through the electroplating stripping process, and a seed copper layer is sputtered on the front and back sides of the silicon carbide wafer 11. Then, the metal 2 opening area under the wafer front bump and the metal opening area of ​​the wafer back electrode are defined by photolithography on the front and back sides of the wafer. Copper plating layer, then remove the photoresist and upper metal on the front and back of the wafer with a stripping solution, and then etch away the excess seed copper layer. The size of the metal bumps can be flexibly adjusted according to the specific device electrode metal size, and then the third metal bump 8 and the fourth metal bump 9 are prepared by laser ball planting or pillar planting process, the metal is melted by heating, and then the molten metal is accurately planted above the first metal bump 6 on the front of the silicon carbide wafer 11 and below the second metal bump 7 on the back of the silicon carbide wafer 11 through computer positioning, and finally the packaging is completed by the packaging mold.

[0047] In addition, when the UBM 2 is prepared by chemical plating, the silicon carbide wafer 11 is placed in a chemical plating solution to form the UBM 2 on the front electrode metal of the silicon carbide wafer 11 through a replacement reaction.

[0048] See also Figure 3 As a further implementation method of the packaging mold: the packaging mold consists of a block-level upper mold 12 and a block-level lower mold 13, and the block-level upper mold 12 and the block-level lower mold 13 are provided with a block-level third metal bump clip 14, a block-level fourth metal bump clip 15 and a block-level feed port 16. The wafer is cut into single chips and placed in the packaging mold, and the fourth insulating material 10 is injected through the block-level feed port 16.

[0049] Specifically, when packaging, the silicon carbide wafer 11 is cut into individual chips, and then the cut individual chips are placed in a plastic packaging mold, the mold has two parts of a block level upper mold and a block level lower mold, the block level fourth metal bump socket 15 below the mold is fixed with the fourth metal bump 9 below, and then the block level third metal bump socket 14 above the mold is aligned with the third metal bump 8 to be fixed, and then the fourth insulating material 10 in a hot molten state is injected through the block level feeding port 16. After the fourth insulating material 10 is cooled and solidified, the mold is removed, the packaging is completed, and in addition, the fourth insulating material 10 includes epoxy resin, silicon gel, polymer, and a polymer of bisphenol F epoxy chloropropane, and the thickness after solidification is 100-300um.

[0050] Please refer to Figure 4 As a further embodiment of the packaging mold: the packaging mold is composed of a board level upper mold 17 and a board level lower mold 18, and the board level upper mold 17 and the board level lower mold 18 have a board level third metal bump socket 19, a board level fourth metal bump socket 20, and a board level feeding port 21. The wafer is cut into individual chips and arranged in order in the packaging mold, the fourth insulating material 10 is injected through the board level feeding port 21 for packaging, and then the board level arranged device is cut into individual chips.

[0051] Specifically, after the wafer is cut into individual chips, the individual chips are further arranged in order in the board level packaging mold, and the third metal bump 8 is aligned with the board level third metal bump socket 19 of the board level upper mold 17 for cooperation, and the fourth metal bump 9 is aligned with the board level fourth metal bump socket 20 of the board level lower mold 18 for cooperation. After being fixed, the fourth insulating material 10 in a hot molten state is injected through the board level feeding port 21, the fourth insulating material 10 is cooled and solidified, and then the mold is removed. The board level arranged device is cut into individual devices, and the use of the board level packaging mold further improves the work efficiency and reduces the time cost.

[0052] In summary, when the silicon carbide wafer level packaging structure is manufactured;

[0053] The silicon carbide wafer 11 is marked with the number 11 for easy identification in the drawings. The silicon carbide wafer 11 contains a plurality of silicon carbide chips 1. The front and back surfaces of the silicon carbide chips 1 are provided with electrode metal. The silicon carbide chips 1 include silicon carbide MOSFET, silicon carbide diode, silicon carbide JFET, silicon carbide IGBT, silicon carbide BJT, and silicon carbide GTO. The thickness is 100-400 um. The bump-down metal 2 is prepared by evaporation stripping or chemical plating. If the evaporation stripping method is used, the front surface of the silicon carbide wafer 11 is first defined by photolithography to form a contact area between the front surface electrode metal and the bump-down metal 2. Then, the bump-down metal 2 is evaporated on the front surface of the silicon carbide wafer 11. Then, the photoresist and the metal thereon are removed using a stripping solution. The metal material of the bump-down metal 2 can be titanium-nickel-vanadium-silver. The thickness of the metal titanium is less than 0.5 um, the thickness of the metal nickel-vanadium is less than 1 um, and the thickness of the metal silver is 1-10 um. Then, the first insulating material 3 is deposited on the front surface of the silicon carbide wafer 11 and the surface of the bump-down metal 2. Then, the bump-down metal 2 opening area is defined by photolithography and etching. Then, the photoresist is removed. The first insulating material 3 is made of one or more of silicon oxide, silicon nitride, and silicon oxynitride, and the material thickness is 0.1-10um, then the front and back of the silicon carbide wafer 11 are sprayed with polyimide, then the metal 2 opening area under the bump and the electrode metal opening area on the back of the silicon carbide wafer 11 are defined by photolithography, and the polyimide insulation material is cured by baking to form the second insulation material 4 and the third insulation material 5 with a thickness of 10-200um. The polyimide provides good insulation support, a matching thermal expansion coefficient with the silicon carbide chip 1, and good moisture resistance, which can reduce the risk of device cracking and delamination in high-temperature working environment, reduce the risk of moisture entering the chip and causing failure in high-humidity working environment, and improve device reliability. Then, the first metal bump 6 and the second metal bump 7 are prepared on the front and back of the silicon carbide wafer 11 by electroplating stripping process, the copper seed layer is sputtered on the front and back of the silicon carbide wafer 11, then the metal 2 opening area under the bump on the front of the wafer and the electrode metal opening area on the back of the wafer are defined by photolithography on the front and back of the wafer, and then the copper layer is electroplated on the front and back of the wafer. Then, the photoresist and the upper metal on the front and back of the wafer are removed using stripping liquid, and the excess seed copper layer is etched off. The metal material of the first metal bump 6 and the second metal bump 7 is copper, the length and width of the first metal bump 6 is 200-500um, and the thickness is 30-200um. The length and width of the second metal bump 7 is 200-1000um, and the thickness is 30-200um. The size of the metal bump can be flexibly adjusted and arranged according to the size of the electrode metal of the specific device. Then, the third metal bump 8 and the fourth metal bump 9 are prepared by laser ball planting or column planting process. The metal material of the third metal bump 8 and the fourth metal bump 9 includes tin-lead alloy, tin-copper alloy, tin-silver alloy, tin-antimony alloy, and tin-bismuth alloy. The metal is melted by heating, and then the molten metal is accurately planted on the first metal bump 6 on the front of the silicon carbide wafer 11 and under the second metal bump 7 on the back of the silicon carbide wafer 11 by computer positioning. The length and width of the third metal bump 8 is 200-500um, and the thickness is 100-300um. The length and width of the fourth metal bump 9 is 200-1000um, and the thickness is 100-300um.

[0054] In addition, when the metal 2 under the bump is prepared by electroless plating, the silicon carbide wafer 11 is placed in the electroless plating solution to form the metal 2 under the bump on the electrode metal on the front of the silicon carbide wafer 11 by displacement reaction. At this time, the metal material of the metal 2 under the bump can be nickel gold or nickel palladium gold. The thickness of the metal nickel is 1-10um, the thickness of the metal palladium is less than 1um, and the thickness of the metal gold is less than 0.5um.

[0055] And when packaging, the silicon carbide wafer 11 is cut into individual chips, and then the cut individual chips are placed in a plastic packaging mold, the mold has two parts, a block level upper mold 12 and a block level lower mold 13, the block level fourth metal bump socket 15 at the bottom of the mold is fixed with the fourth metal bump 9, then the block level third metal bump socket 14 at the top of the mold is fixed with the third metal bump 8, and then the fourth insulating material 10 in a hot melt state is injected through the block level feeding port 16. After the fourth insulating material 10 is cooled and solidified, the mold is removed, and the packaging is completed. In addition, the fourth insulating material 10 includes epoxy resin, silicon gel, polymer, and bisphenol F epoxy chloropropane polymer, and has a thickness of 100-300um after solidification. After the wafer is cut into individual chips, the individual chips can be further arranged in a board level packaging mold, and the third metal bump 8 is aligned with the board level third metal bump socket 19 of the board level upper mold 17, and the fourth metal bump 9 is aligned with the board level fourth metal bump socket 20 of the board level lower mold 18. After being fixed, the fourth insulating material 10 in a hot melt state is injected through the board level feeding port 21. After the fourth insulating material 10 is cooled and solidified, the mold is removed, and the board level arranged device is cut into individual devices. The use of the board level packaging mold further improves the work efficiency and reduces the time cost.

[0056] When the device with the silicon carbide wafer level packaging structure is used, the bump down metal 2 on the front electrode of the silicon carbide chip 1 can improve the adhesion between the chip and the metal bump. The first insulating material 3, the second insulating material 4 and the third insulating material 5 between the bump down metals 2 form respective insulating layers, which cooperate to play an electrical isolation role. The first metal bump 6, the second metal bump 7, the third metal bump 8 and the fourth metal bump 9 on the front and back surfaces of the silicon carbide chip 1 cooperate to provide electrical connection and heat dissipation channels. The insulating layer formed by the fourth insulating material 10 between the respective metal bumps plays an electrical isolation and support role.

[0057] In the above-mentioned all solutions, although the embodiments of the present application have been shown and described, it can be understood by those skilled in the art that various changes, modifications, replacements and variations can be made to the embodiments without departing from the principles and spirits of the present application, and the scope of the present application is defined by the appended claims and their equivalents.

Claims

1. A silicon carbide wafer-level packaging structure, comprising a silicon carbide chip (1), characterized in that: The upper end of the silicon carbide chip (1) is provided with an underbump metal (2), and the underbump metal (2) cooperates with the electrode metal structure on the upper surface of the silicon carbide chip (1). A first insulating material (3) is provided above the silicon carbide chip (1) and on both sides of the underbump metal (2). A second insulating material (4) is provided on the upper end of the first insulating material (3). A third insulating material (5) is provided on the lower end of the silicon carbide chip (1). A first metal bump (6) is provided on the upper end of the underbump metal (2). A second metal bump (7) is provided on the lower end of the silicon carbide chip (1). The second metal bump (7) is in contact with the silicon carbide chip (1). The electrode metal structure on the lower surface is matched, the outer end of the first metal bump (6) is provided with a third metal bump (8), the outer end of the second metal bump (7) is provided with a fourth metal bump (9), the outer side of the silicon carbide chip (1) is provided with a fourth insulating material (10), the silicon carbide chip (1), the under-bump metal (2), the first insulating material (3), the second insulating material (4), the third insulating material (5), the first metal bump (6) and the second metal bump (7) are all located in the fourth insulating material (10), and the outer ends of the third metal bump (8) and the fourth metal bump (9) protrude from the fourth insulating material (10).

2. The silicon carbide wafer-level packaging structure according to claim 1, wherein: The constituent materials of the silicon carbide chip (1) include silicon carbide MOSFET, silicon carbide diode, silicon carbide JFET, silicon carbide IGBT, silicon carbide BJT, and silicon carbide GTO, and the thickness of the silicon carbide chip (1) is 100-400 μm.

3. The silicon carbide wafer-level packaging structure according to claim 1, wherein: The material of the under-bump metal (2) is titanium nickel vanadium silver, nickel gold or nickel palladium gold, and if it is titanium nickel vanadium silver, the thickness of the metal titanium is less than 0.5um, the thickness of the metal nickel vanadium is less than 1um, and the thickness of the metal silver is 1-10um; if it is nickel gold or nickel palladium gold, the thickness of the metal nickel is 1-10um, the thickness of the metal palladium is less than 1um, and the thickness of the metal gold is less than 0.5um.

4. The silicon carbide wafer-level packaging structure according to claim 1, wherein: The first insulating material (3) is made of silicon oxide or silicon nitride, with a thickness of 0.1-10 μm, while the second insulating material (4) and the third insulating material (5) are made of baked and cured polyimide, with a thickness of 10-200 μm.

5. The silicon carbide wafer-level packaging structure according to claim 1, wherein: The metal material of the first metal bump (6) and the second metal bump (7) is copper, with a thickness of 30-200 μm; the metal material of the third metal bump (8) and the fourth metal bump (9) includes tin-lead alloy, tin-copper alloy, tin-silver alloy, tin-antimony alloy and tin-bismuth alloy, with a thickness of 100-300 μm.

6. The method for manufacturing a silicon carbide wafer-level packaging structure according to claim 1, wherein: The method comprises: Step 1: Preparing an under-bump metal (2) on a silicon carbide chip (1) by evaporation stripping or chemical plating; Step 2: Then, a first insulating material (3) is formed by depositing and photolithography etching on the front side of the wafer, a second insulating material (4) is formed by spraying and photolithography baking and curing on the front side of the wafer, and a third insulating material (5) is formed by spraying and photolithography baking and curing on the back side of the wafer; Step 3: A first metal bump (6) and a second metal bump (7) are respectively prepared on the front and back surfaces of the wafer by an electroplating stripping process, and then a third metal bump (8) and a fourth metal bump (9) are prepared on the front and back surfaces of the wafer by a laser ball implantation process or a column implantation process; Step 4: The wafer is cut into individual chips and placed in a packaging mold for packaging. A fourth insulating material (10) in a hot melt state is injected. After the fourth insulating material (10) is cooled and solidified, the chip is wrapped and packaged. The packaging mold is removed to complete the packaging.

7. The method for manufacturing a silicon carbide wafer-level packaging structure according to claim 6, wherein: The packaging mold is composed of a block-level upper mold (12) and a block-level lower mold (13), and the block-level upper mold (12) and the block-level lower mold (13) are provided with a block-level third metal bump clamp (14), a block-level fourth metal bump clamp (15) and a block-level feed port (16). A wafer is cut into individual chips, which are placed in the packaging mold, and a fourth insulating material (10) is injected through the block-level feed port (16).

8. The method for manufacturing a silicon carbide wafer-level packaging structure according to claim 6, wherein: The packaging mold is composed of a board-level upper mold (17) and a board-level lower mold (18), and the board-level upper mold (17) and the board-level lower mold (18) are provided with a board-level third metal bump socket (19), a board-level fourth metal bump socket (20) and a board-level feed port (21). The wafer is cut into individual chips and arranged in order in the packaging mold. The fourth insulating material (10) is injected through the board-level feed port (21) for packaging, and then the board-level arranged devices are cut into individual devices.

Images