A high-power SSPC hardware circuit based on dual-step channel protection

Abstract

This invention belongs to the technical field of aviation power distribution systems and discloses a design method for a high-power dual-step SSPC hardware circuit based on channel protection, using two short-circuit protection circuits to set two flip-points. In the hardware design, two independent short-circuit protection circuits are designed, and the output signals of the two protection circuits are connected one-to-one to two I / O ports of the processor. The two flip-points are designed, one for identifying low-multiple currents and the other for identifying high-multiple currents. The outputs of the two short-circuit protection circuits are fed into the processor for an AND logic operation, thereby implementing the short-circuit protection function.

Description

Technical Field

[0001] The present invention relates to an aviation power distribution system, belongs to the field of MOSFET protection of power distribution systems, and particularly relates to a design method for a dual-step high-power SSPC hardware circuit based on channel protection. Background Art

[0002] With the rapid development of more-electric and all-electric aircraft, electricity has become a critical secondary energy source onboard. This significantly simplifies aircraft structure, reduces weight and lifecycle costs, and improves safety, reliability, and maintainability. Solid-state power controllers, as a crucial component of the power distribution systems of more-electric and all-electric aircraft, offer advantages such as fast switching speed, contactlessness, low electromagnetic interference, and high reliability. As the capacity and variety of electrical loads onboard aircraft increase, the power rating of DC solid-state power controllers (SSPCs) needs to be increased, leading to research into high-power DC SSPCs.

[0003] High-power DC SSPCs generate large current surges when starting capacitive loads or encountering short-circuit faults, which can endanger the safe and reliable operation of aircraft electrical systems. Therefore, it is necessary to suppress the current surges and study the short-circuit protection technology of high-power DC SSPCs.

[0004] In summary, a high-power SSPC hardware circuit based on dual-step channel protection is urgently needed. Summary of the Invention

[0005] The present invention provides a high-power SSPC hardware circuit design method based on channel protection double-step in a high-power distribution network, thereby realizing reliable protection of MOSFET in the distribution system.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] In the first aspect, a high-power SSPC hardware circuit based on dual-step channel protection is provided, which includes: comparing the current acquisition value with the threshold of the resistor network flip point, and performing short-circuit protection through the high and low levels output by the comparator and the output level of the processor algorithm.

[0008] The dual-step high-power SSPC hardware circuit includes: a current acquisition circuit, a high-multiple flip circuit, a low-multiple flip circuit, a comparator circuit, a comparator output circuit and a processor operation circuit.

[0009] The value of the current acquisition circuit is used as the reference value of the comparator circuit input. The thresholds of the high-multiple flip circuit and the low-multiple flip circuit are compared with the reference value through the comparator circuit, and then output to the processor operation circuit through the comparator output circuit. After operation, the corresponding high and low levels are output.

[0010] One end of the current acquisition circuit is connected to the sampling resistor of the power circuit, and the other end is connected to the non-inverting input of the comparator circuit. The high-multiple flip circuit and the low-multiple flip circuit are respectively connected to the inverting input of the two comparators. After comparison by the comparator circuit, the output is connected to the I / O pin of the processor, enters the processor operation circuit, and is output after the "AND" logic operation of the processor operation circuit. The output of the processor operation circuit is connected to the executive mechanism of the SSPC, thereby performing the short-circuit protection function.

[0011] As a further technical solution of the present invention, the non-inverting input terminals of the two comparator circuits are commonly connected to a sampling resistor of the power circuit, and the collected values ​​serve as reference values ​​of the comparator circuits.

[0012] As a further technical solution of the present invention, the high-multiple flip circuit and the low-multiple flip circuit are formed by resistor voltage division in the same resistor network to form different voltage values ​​as high-multiple and low-multiple flip values.

[0013] As a further technical solution of the present invention, the flip value of the high-multiple flip circuit is compared with the reference value through the comparator circuit 1.

[0014] As a further technical solution of the present invention, the flip value of the low-multiple flip circuit is compared with the reference value through the comparator circuit 2.

[0015] As a further technical solution of the present invention, the flip value of the high-multiple flip circuit comes from point b, that is, the value of the voltage divider of the resistors R1 and R2 in the resistor network (R1, R2, R3).

[0016] As a further technical solution of the present invention, the flip value of the low-multiple flip circuit comes from point a, that is, the value of the voltage divider of the resistor R1 in the resistor network (R1, R2, R3).

[0017] As a further technical solution of the present invention, the reference value of the current acquisition circuit is input into the comparator (U1A and U1B) through the non-inverting input terminal, and the threshold values ​​of the high-multiple flip circuit and the low-multiple flip circuit are input into the comparator (U1A and U1B) through the inverting input terminal of the comparator, and are output after being calculated by multiple logic gates inside the comparator (U1A and U1B).

[0018] As a further technical solution of the present invention, the outputs ITRIP_1 and ITRIP_2 of the comparator circuit 1 (U1A) and the comparator circuit 2 (U1B) are electrically connected to the I / O ports of the processor operation circuit respectively to provide input to the processor.

[0019] ITRIP_1 and ITRIP_2 enter the processor and undergo an AND logic operation. The logic operation rules are as follows: when the current value is less than h times, comparator circuit 1 outputs a high level, and comparator circuit 2 also outputs a high level. When the current value is greater than h times but less than g times, comparator circuit 1 outputs a high level, and comparator circuit 2 outputs a low level. When the current value is greater than g times, comparator circuit 1 outputs a low level, and comparator circuit 2 also outputs a low level. The processor performs an AND logic operation on the levels of comparator 1 and comparator 2 and outputs the result.

[0020] As a further technical solution of the present invention, the level output after performing "AND" logic is sent to a driver chip that drives the SSPC to turn on and off, and then the SSPC trip protection is executed.

[0021] In the second aspect, a dual-step high-power SSPC hardware circuit design method based on channel protection is provided, which includes: sequentially designing a current acquisition circuit, a high-multiple flip circuit, a low-multiple flip circuit, a comparator circuit, a comparator output circuit, and a processor operation circuit;

[0022] The voltage reference value collected by the current acquisition circuit is compared with the preset thresholds of the high-multiple flip circuit and the low-multiple flip circuit through a comparator. The corresponding logic level is output to the processor operation circuit through the comparator output circuit. After the "AND" logic operation in the processor operation circuit, it is output to the driver chip to control the SSPC actuator to perform SSPC trip protection.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] 1. The circuit is simple and reliable, covering a wide range of short-circuit protection multiples. It is suitable for use in high-power SSPC applications. At the same time, it achieves precise protection for different multiples, improving the reliability and safety of equipment and distribution systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, without paying any creative work, other drawings obtained based on these drawings still fall within the scope of the present invention.

[0026] Figure 1 This is a block diagram of the dual-step high-power SSPC short-circuit protection principle of the present invention;

[0027] Figure 2 This is a schematic diagram of the high-power SSPC acquisition circuit of the present invention;

[0028] Figure 3 This is a schematic diagram of the dual-step high-power SSPC short-circuit protection circuit of the present invention;

[0029] Figure 4 This is the protection curve of the double-step high-power SSPC short-circuit protection circuit of the present invention. DETAILED DESCRIPTION

[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0031] A hardware circuit design method for a high-power SSPC with dual-step channel protection requires two independent short-circuit protection circuits and a current sampling circuit to work together to implement the high-power SSPC's short-circuit protection function, ensuring precise protection at different short-circuit protection multiples. The circuit consists of a current acquisition circuit, a high-multiplier flip circuit, a low-multiplier flip circuit, a comparator circuit, a comparator output circuit, and a processor operation circuit. This circuit achieves level flipping by comparing the acquisition circuit's baseline value with the preset thresholds of the high-multiplier flip circuit and the low-multiplier flip circuit. When the processor operation circuit outputs a high level, the SSPC operates normally. When the high level flips to a low level, short-circuit protection is implemented. Precise and real-time protection is provided based on the preset thresholds of the short-circuit protection multiple, ensuring reliable and safe operation of the power distribution equipment.

[0032] Figure 1 This is a block diagram of the dual-step high-power SSPC short-circuit protection principle, illustrating the circuit composition of the short-circuit protection function of the entire distribution network. Figure 2 This is the schematic diagram of the high-power SSPC acquisition circuit, which realizes the source of the comparator reference value input. Figure 3 This is the schematic diagram of a dual-step high-power SSPC short-circuit protection circuit. It is the core design of the short-circuit protection circuit and uses two independent short-circuit protection circuits. Figure 4 This is the protection curve of the double-step high-power SSPC short-circuit protection circuit, which shows the range and protection time of short-circuit protection.

[0033] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] like Figure 1As shown, the reference value of the current acquisition circuit and the high-multiple value of the high-multiple flip circuit are compared in comparator circuit 1, and the reference value of the current acquisition circuit and the low-multiple value of the low-multiple flip circuit are compared in comparator circuit 2. The outputs of comparator circuit 1 and comparator circuit 2 are input into the processor operation circuit for "AND" logic processing. The logic processing in the processor operation circuit is as follows:

[0035] Process the input signal a and perform I2T tripping or not tripping according to the result collected by the current collection circuit;

[0036] Processor signal b does not appear when the control circuit is fault-free, so it is an abnormal signal. Since the current multiple identified by the short-circuit protection circuit 1 is very large, the circuit indicates the presence of g times (immediate trip) current, and the immediate trip strategy is adopted;

[0037] Processor signal c is a fixed time-delay trip. If the short-circuit current disappears (the short-circuit signal disappears) within the delay time, the timer for the delayed tripping must be reset to ensure that the next time the delayed tripping short-circuit signal arrives, the timer starts from 0.

[0038] The processor signals d, deeming that there is a g-fold short-circuit current and adopting an immediate tripping strategy.

[0039] The above trip signal is input to the drive circuit of the high-power SSPC, causing the drive circuit to output a control signal to turn on or off the high-power load.

[0040] like Figure 2 As shown, the current acquisition circuit collects the current signal passing through the sampling resistor in the power circuit in the form of voltage and isolates it from the power circuit. By designing the resistance value outside the operational amplifier to match the high and low levels, and matching the voltage value of the operational amplifier, the amplification factor is designed to complete the normal current acquisition function.

[0041] like Figure 3 As shown, in the hardware design, two independent short-circuit protection circuits are set up (the output signals of the two circuits are connected one-to-one with the two I / O ports of the processor respectively), one circuit is used to identify h times the current, and the other circuit is used to identify g times the current.

[0042] Each short-circuit protection circuit is mainly composed of one comparator, and the overall output of the circuit is the output of the two comparators performing "AND" logic.

[0043] When the current value is less than h times, the comparator circuit 1 outputs a high level, and the comparator circuit 2 also outputs a high level; when the current value is greater than h times and less than g times, the comparator circuit 1 outputs a high level, and the comparator circuit 2 outputs a low level. At this time, the short-circuit protection is low-multiple protection; when the current value is greater than g times, the comparator circuit 1 outputs a low level, and the comparator circuit 2 also outputs a low level. At this time, it is high-multiple protection.

[0044] As Figure 4 shown, the entire tripping curve is divided into three major parts, including an immediate tripping protection curve, a time-delay tripping protection curve, and an I2T tripping protection curve.

[0045] a) Immediate tripping strategy and protection curve

[0046] For the current of "MAX_LEVEL", since there is no requirement for the lower limit of the tripping time and the current level is relatively large, an immediate tripping strategy is adopted. That is, when the current of "MAX_LEVEL" is recognized, a tripping operation is directly performed (it is necessary to ensure that the tripping time t < t3, and the actual immediate action can meet the requirements), and the fault current is cut off as soon as possible;

[0047] The actual protection curve is the first-segment ideal curve. The current level selected for the first-segment tripping curve is I ≥ g (g = (f + c) / 2, corresponding to the current multiple in the middle of the JA line and the KF line (ideal voltage division)), and the corresponding protection time is immediate protection (< t3 (corresponding to the time of the AE line), and actually < t4 can be guaranteed).

[0048] b) Time-delay tripping strategy and protection curve

[0049] For the current of "MIDDLE_LEVEL", a time-delay tripping strategy is adopted, and a fixed time t (t1 < t < t3) (t < t3 is to ensure that t meets the tripping time requirements of all currents of this level) is selected as the tripping time for all currents of this level;

[0050] The actual protection curve is the second-segment ideal curve. The current level selected for the second-segment tripping curve is h ≤ I < g (h = (d + e) / 2, corresponding to the current multiple in the middle of the EC line and the BD line), and the corresponding protection time is a fixed delay t4 (t4 = (t1 + t3) / 2, corresponding to the time of the vertical line II).

[0051] c) I2T tripping strategy and protection curve

[0052] For the current of "MINI_LEVEL", an I2T tripping strategy is adopted to ensure that the tripping time of the current of this level meets the requirements of the tripping curve (the I2T curve is between "DI" and "GH").

[0053] The actual protection curve is the third ideal curve. The current level selected for the third short - circuit tripping curve is I < h, and the corresponding protection time is the I2T delay protection (the time corresponding to line III). The actual I2T curve will be designed at the middle position between the curves "DI" and "GH". When it is lower than a certain specific value, the SSPC does not require protection.

[0054] Thus, the object of the present invention is achieved.

[0055] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above - mentioned exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, in any respect, the embodiments should be regarded as exemplary and non - restrictive. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present invention. Any reference signs in the claims should not be regarded as limiting the claims involved.

Claims

1. A high-power SSPC hardware circuit based on channel protection dual-step, characterized by , including: current acquisition circuit, high-multiple flip circuit, low-multiple flip circuit, comparator circuit, comparator output circuit and processor operation circuit; The value of the current acquisition circuit is used as a reference value input to the comparator circuit. The values ​​of the high-multiple flip circuit and the low-multiple flip circuit are compared with the reference value by the comparator circuit, and then output to the processor operation circuit through the comparator output circuit. After operation, the corresponding high and low levels are output; One end of the current acquisition circuit is connected to the sampling resistor of the power circuit, and the other end is connected to the non-inverting input end of the comparator circuit. The high-multiple flip circuit and the low-multiple flip circuit are respectively connected to the inverting input ends of the two comparators. After comparison by the comparator circuit, the output is output. The comparator output circuit is connected to the I / O pin of the processor and enters the processor operation circuit. After the "AND" logic operation of the processor operation circuit, the output is connected to the execution mechanism of the SSPC, thereby performing the short-circuit protection function, specifically: The outputs ITRIP_1 and ITRIP_2 of the comparator circuit 1 and the comparator circuit 2 are electrically connected to the I / O ports of the processor operation circuit respectively, and input to the processor to perform an "AND" logic operation; When the current value is less than h times, the comparator circuit 1 outputs a high level, and the comparator circuit 2 outputs a high level as well, and no tripping occurs; When the current value is greater than h times and less than g times, comparator circuit 1 outputs a high level and comparator circuit 2 outputs a low level. At this time, the short-circuit protection is a low-multiple protection and a delayed tripping strategy is adopted; When the current value is greater than g times, the comparator circuit 1 outputs a low level, and the comparator circuit 2 outputs a low level as well. This is a high-multiple protection, and an immediate tripping strategy is adopted.

2. A high-power SSPC hardware circuit based on channel protection dual-step according to claim 1, characterized in that: The non-inverting input terminals of the two comparator circuits are commonly connected to the sampling resistor of the power circuit, and the collected values ​​are used as reference values ​​of the comparator circuits.

3. The high-power SSPC hardware circuit based on channel protection dual-step according to claim 1 is characterized in that: The high-multiple flip circuit and the low-multiple flip circuit are formed by dividing the voltage of the resistors in the same resistor network to form different voltage values ​​as the high-multiple and low-multiple flip values.

4. A high-power SSPC hardware circuit based on channel protection dual-step according to claim 3, characterized in that: The flip value of the high-multiple flip circuit is compared with a reference value through a comparator circuit 1 , and the flip value of the low-multiple flip circuit is compared with a reference value through a comparator circuit 2 .

5. A high-power SSPC hardware circuit based on channel protection dual-step according to claim 4, characterized in that: The flip value of the high-multiple flip circuit comes from the value of the voltage divider between R1 and R2; the flip value of the low-multiple flip circuit comes from the value of the voltage divider between R1.

6. A high-power SSPC hardware circuit based on channel protection dual-step according to claim 5, characterized in that: The reference value of the current acquisition circuit is input into the comparator circuit through the non-inverting input terminal, and the values ​​of the high-multiple flip circuit and the low-multiple flip circuit are input into the comparator circuit through the inverting input terminal of the comparator circuit, and are output after being calculated by multiple logic gates inside the comparator circuit.

7. The high-power SSPC hardware circuit based on channel protection dual-step according to claim 1 is characterized in that: After performing the "AND" logic, the output level is sent to the driver chip that drives the SSPC to turn on and off, and then the SSPC trip protection is executed.

Images