A high common-mode rejection ratio operational amplifier

Abstract

This invention discloses a high common-mode rejection ratio (CMRR) operational amplifier, primarily addressing the problems of low robustness and low signal transmission quality in existing technologies. It includes a main circuit, a CMRR enhancement circuit, and a bias circuit T5. The main circuit comprises a main voltage-to-current module T1 and a current-to-voltage module T2. The CMRR enhancement circuit includes a low-gain differential amplifier T3 and an auxiliary voltage-to-current module T4. The two input terminals of module T3 are connected to differential input voltage signals, and the amplified two differential output voltage signals are then converted into current by the auxiliary voltage-to-current module T4 and transmitted to the current-to-voltage module T2. T2 performs current-to-voltage conversion and merging processing on the output currents of the main voltage-to-current module T1 and the auxiliary voltage-to-current module T4, outputting a high CMRR voltage signal. This invention exhibits strong robustness and high signal transmission quality, and can be used in various analog and mixed-signal systems.

Description

Technical Field

[0001] This invention belongs to the field of electronic component technology, and specifically designs a high common-mode rejection ratio operational amplifier that can be used in various analog systems and mixed-signal systems. Background Technology

[0002] In recent years, with the rapid development of electronic products, semiconductor integrated circuits have been widely used in various fields such as military and civilian applications. In areas such as computers, multimedia, and digital signal processing, the performance requirements for electronic products are becoming increasingly demanding. A fundamental analysis reveals that this boils down to increasingly higher requirements for operational amplifiers. This has driven the development of operational amplifiers towards lower power consumption, higher speed, higher precision, higher common-mode rejection ratio (CMRR), and higher power supply rejection ratio (PSRR). However, the requirements for operational amplifiers vary depending on the application. For example, in signal chain systems, which often use fully differential inputs, ideally the input common-mode level remains constant, and the operational amplifier in the system only processes the differential signal. However, because the common-mode level of external input signals often contains certain disturbances, and the frequency and amplitude of these disturbances are related to the external environment, these disturbances introduce additional interference into the output signal, degrading the output signal quality and reducing system accuracy. Therefore, in such applications, operational amplifiers are often required to have a high CMRR.

[0003] Patent document CN201210591649.6 discloses a low-voltage, high common-mode rejection ratio operational amplifier circuit, such as... Figure 1As shown, its main structure is a five-transistor amplifier. The circuit within the dashed box assists the five-transistor amplifier in improving the common-mode rejection ratio. The differential input signals within the dashed box are connected to the gates of the fourth P-type transistor MP4 and the fifth P-type transistor MP5, respectively. The source and drain of MP4 and MP5 are connected together. The drains of MP4 and MP5 are connected to the gates of the sixth P-type transistor MP6 and the third P-type transistor MP3. Simultaneously, the drain of the first N-type transistor MN1 is connected to the drain of MP1, and its gate is connected to the gate and drain of the second N-type transistor MN2. The drain of the third N-type transistor MN3 is connected to the drains of MP4 and MP5, and its gate is connected to the gate and drain of the fourth N-type transistor MN4. The sources of MN1, MN2, MN3, and MN4 are all connected to ground. Assuming that the common-mode levels of the differential input signals VIN and VIP have a small positive increment, the sources of the first P-type transistor MP1 and the second P-type transistor MP2, and the gate of MP3 will also have a positive increment. Similarly, the drains of MP4 and MP5 will have a negative increment, meaning the gate of MP3 will have a negative increment. Therefore, the drain potential of MP3 increases and the gate potential decreases, thus ensuring that the source-drain current of MP3 remains essentially unchanged. At this time, the current flowing through MP1 and MP2 remains unchanged, thereby improving the common-mode rejection ratio of the operational amplifier. However, because the gate of MP3 is biased to the drains of MP4 and MP5, the quiescent current in MP3 is difficult to determine, resulting in low robustness and unsuitability for other complex applications. Furthermore, the circuit within the dashed box introduces additional noise sources, deteriorating the overall noise performance of the circuit. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of the prior art by proposing a high common-mode rejection ratio operational amplifier, which ensures that while improving the common-mode rejection ratio of the amplifier, it also has strong robustness, avoids additional noise sources, and improves the signal transmission quality.

[0005] To achieve the above objectives, the high common-mode rejection ratio (CMRR) operational amplifier of the present invention includes a main circuit, a CMRR enhancement circuit, and a bias circuit T5. The main circuit is a dual-input, single-output amplifier comprising a main voltage-to-current module T1 and a current-to-voltage module T2 connected together. Its characteristic is that:

[0006] The common-mode rejection ratio improvement circuit includes a low-gain differential amplifier T3 and an auxiliary voltage-to-current module T4. The low-gain differential amplifier T3 has two input terminals and two output terminals, and the auxiliary voltage-to-current module T4 has four input terminals and two output terminals.

[0007] The two input terminals of the low-gain differential amplifier T3 are connected to the differential input voltage signal respectively, which is used to amplify the differential input voltage signal. Two amplified differential output voltage signals are output from the two output terminals. One output voltage signal is connected to two inputs of the auxiliary voltage to current module T4, and the other output voltage signal is connected to the other two inputs of the auxiliary voltage to current module T4.

[0008] The auxiliary voltage-to-current module T4 processes the four input voltage signals into current signals, outputs two current signals, and transmits them to the two input terminals of T2.

[0009] Preferably, the low-gain differential amplifier T3 includes: a pre-voltage to current conversion module T31 and a pre-current to voltage conversion module T32;

[0010] The pre-voltage to current conversion module T31 has a set of differential voltage signals VIP and VIN connected to its input terminal. It is used to convert the differential input signal into a differential current signal and output it to the pre-current to voltage conversion module T32.

[0011] The pre-current to voltage module T32 is used to convert the differential current signal output by the pre-voltage to current module T31 into a differential voltage signal and output it to the auxiliary voltage to current module T4.

[0012] Preferably, the first input terminal of the main voltage-to-current module T1 is connected to a differential signal VIP for voltage-to-current conversion, and the second input terminal is connected to another differential signal VIN for voltage-to-current conversion. The two differential current signals after conversion are connected to the two input terminals of the current-to-voltage module T2.

[0013] Preferably, the current-to-voltage module T2 has its first input terminal connected to one output current signal of both the main voltage-to-current module T1 and the auxiliary voltage-to-current module T4 for current-to-voltage conversion, and its second input terminal connected to the other output current signal of both the main voltage-to-current module T1 and the auxiliary voltage-to-current module T4 for current-to-voltage conversion. The two converted voltage signals are then combined and a high common-mode rejection ratio voltage signal is output from the output terminal VOUT.

[0014] Compared with the prior art, the present invention has the following advantages:

[0015] Firstly, this invention incorporates a common-mode rejection ratio (CMRR) enhancement circuit, including a low-gain differential amplifier T3 and an auxiliary voltage-to-current module T4. The common-mode disturbance voltage component in the differential input signal is obtained through the low-gain differential amplifier T3, converted into a common-mode disturbance current component by the auxiliary voltage-to-current module T4, and then injected into the current-to-voltage module T2 to cancel out the inverted common-mode disturbance current component output by the main voltage-to-current module T1. This significantly improves the common-mode rejection capability of the main circuit.

[0016] Secondly, the common-mode rejection ratio enhancement circuit in this invention is connected to a differential input voltage signal, which is processed sequentially by its internal low-gain differential amplifier T3 and auxiliary voltage-to-current module T4, and then input as current into current-to-voltage module T2. Since it does not affect the current bias of the main circuit, it can not only determine the static current of all branches of the main circuit, but also make the common-mode rejection ratio enhancement circuit applicable to almost all types of operational amplifiers, such as: folded cascode amplifiers, five-transistor amplifiers, sleeve amplifiers, rail-to-rail input amplifiers, etc., and has strong robustness.

[0017] Thirdly, in this invention, since the relevant noise sources of the low-gain differential amplifier T3 are connected to the input terminal of the current-to-voltage module T2 through the auxiliary voltage-to-current module T4, the relevant noise sources can ultimately cancel each other out at the output terminal of the current-to-voltage module T2, thereby improving the signal transmission quality of the main circuit. Attached Figure Description

[0018] Figure 1 This is a circuit diagram of an existing low-voltage, high common-mode rejection ratio operational amplifier.

[0019] Figure 2 This is a block diagram of the high common-mode rejection ratio operational amplifier of the present invention;

[0020] Figure 3 This is a circuit diagram of a high common-mode rejection ratio operational amplifier according to Embodiment 1 of the present invention;

[0021] Figure 4 This is a circuit diagram of a high common-mode rejection ratio operational amplifier according to Embodiment 2 of the present invention;

[0022] Figure 5 The simulation comparison charts show the common-mode rejection capabilities of the operational amplifiers in Example 1 of this invention and those in the prior art that do not include a common-mode rejection enhancement module. Detailed Implementation

[0023] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0024] Reference Figure 2 The high common-mode rejection ratio (CMRR) operational amplifier in this example includes a main circuit, a CMRR enhancement circuit, and a bias circuit. The main circuit includes a voltage-to-current module T1 and a current-to-voltage module T2, which is a dual-input, single-output amplifier. The CMRR enhancement circuit includes a low-gain differential amplifier T3 and an auxiliary voltage-to-current module T4. The low-gain differential amplifier T3 further includes a pre-voltage-to-current module T31 and a pre-current-to-voltage module T32. The bias circuit T5 is used to provide bias voltage for the main circuit.

[0025] The first input terminal of the main voltage-to-current module T1 is connected to a differential signal VIP for voltage-to-current conversion, and the second input terminal is connected to another differential signal VIN for voltage-to-current conversion. The two differential current signals after conversion are connected to the two input terminals of the current-to-voltage module T2 respectively.

[0026] The pre-amplifier voltage-to-current module T31 has a set of differential voltage signals VIP and VIN connected to its input terminals. It converts the differential input signal into a differential current signal and outputs it to the pre-amplifier current-to-voltage module T32. The pre-amplifier current-to-voltage module T32 converts the differential current signal output from the pre-amplifier voltage-to-current module T31 into a differential voltage signal. One of its output voltage signals is connected to two input terminals of the auxiliary voltage-to-current module T4, and the other output voltage signal is connected to the other two input terminals of the auxiliary voltage-to-current module T4. The auxiliary voltage-to-current module T4 performs voltage-to-current conversion on the four input voltage signals, outputs two current signals, and transmits them to the two input terminals of T2.

[0027] The first input terminal of the current-to-voltage module T2 is connected to one output current signal of both the main voltage-to-current module T1 and the auxiliary voltage-to-current module T4 for current-to-voltage conversion. The second input terminal is connected to the other output current signal of both the main voltage-to-current module T1 and the auxiliary voltage-to-current module T4 for current-to-voltage conversion. The two converted voltage signals are then combined and a high common-mode rejection ratio voltage signal is output from the output terminal VOUT.

[0028] The modules T1, T2, T3, and T4 mentioned above can be implemented using different circuit structures built with multiple P-type transistors and multiple N-type transistors as needed.

[0029] It should be noted that the terms "first", "second"... "Nth" in this specification, claims and the above drawings are used.

[0030] Example 1:

[0031] Reference Figure 3 The high common-mode rejection ratio (CMRR) operational amplifier in this example has a bias circuit T5 comprising 4 P-type transistors MP and 8 N-type transistors MN; main circuits T1 and T2 comprising 7 P-type transistors MP and 4 N-type transistors MN; and common-mode rejection ratio enhancement circuits T3 and T4 comprising 3 P-type transistors MP and 6 N-type transistors MN. Wherein:

[0032] The main voltage-to-current module T1 includes a fifth P-type transistor MP5, a sixth P-type transistor MP6, and a seventh P-type transistor MP7. The source terminal of MP5 is connected to the power supply VDD, the gate terminal is connected to the bias circuit module, and the drain terminal is connected to the source terminals of MP6 and MP7. The gate terminals of MP6 and MP7 are respectively connected to the differential input signals VIN and VIP, and are also connected to the two input terminals of the low-gain differential amplifier T3, respectively, for processing the differential input signals into voltage-to-current and outputting differential current from their respective drain terminals.

[0033] The low-gain differential amplifier T3 includes a twelfth P-type transistor MP12, a thirteenth P-type transistor MP13, a fourteenth P-type transistor MP14, a thirteenth N-type transistor MN13, and a fourteenth N-type transistor MN14. The source terminal of MP12 is connected to the power supply VDD, the gate terminal is connected to the bias circuit module, and the drain terminal is connected to the source terminals of MP13 and MP14. The gate terminals of MP13 and MP14 are respectively connected to the differential input signals VIN and VIP, and are also connected to the two input terminals of the main voltage-to-current module T1. The gate terminal and drain terminal of MN13 are connected to the drain terminal of MP13. The gate terminal and drain terminal of MN14 are connected to the drain terminal of MP14.

[0034] The auxiliary voltage-to-current module T4 includes a fifteenth N-type transistor MN15, a sixteenth N-type transistor MN16, a seventeenth N-type transistor MN17, and an eighteenth N-type transistor MN18. The gate terminals of MN15 and MN16 are connected to the gate terminal of MN14; the gate terminals of MN17 and MN18 are connected to the gate terminal of MN13; the drain terminal of MN15 is connected to the drain terminal of MN17, forming one output of the T4 module, and is connected to one output of the main voltage-to-current module T1 to cancel the common-mode component on this path; the drain terminal of MN16 is connected to the drain terminal of MN18, forming another output of the T4 module, and is connected to the other output of the main voltage-to-current module T1 to cancel the common-mode component on this path.

[0035] The current-to-voltage module T2 includes an eighth P-type transistor MP8, a ninth P-type transistor MP9, a tenth P-type transistor MP10, an eleventh P-type transistor MP11, a ninth N-type transistor MN9, a tenth N-type transistor MN10, an eleventh N-type transistor MN11, and a twelfth P-type transistor MP12. The gate terminals of MN11, MN12, MN9, MN10, MP10, and MP11 are all connected to the bias circuit module. The drain terminal of MN9 is connected to the drain terminal of MP10 and the gate terminal of MP8. The drain terminal of MN10 is connected to the output terminal VOUT and the drain terminal of MP11. The source terminal of MP10 is connected to the drain terminal of MP8, and the source terminal of MP11 is connected to the drain terminal of MP9. The drain of MN11 is connected to the source of MN9, one output of the main voltage-to-current module T1, and one output of the auxiliary voltage-to-current module T4, respectively. This is used to combine the output current of the main voltage-to-current module T1 and one output current of the auxiliary voltage-to-current module T4, and then convert them into voltage through the gate of MP8. This voltage is then converted into current through MP9. The drain of MN12 is connected to the source of MN10, another output of the main voltage-to-current module T1, and another output of the auxiliary voltage-to-current module T4, respectively. This is used to combine the output current of the main voltage-to-current module T1 and another output current of the auxiliary voltage-to-current module T4, and convert them into a high common-mode rejection ratio voltage signal, which is output from the output terminal VOUT.

[0036] The bias circuit T5 includes a first P-type transistor MP1, a second P-type transistor MP2, a third P-type transistor MP3, a fourth P-type transistor MP4, a first N-type transistor MN1, a second N-type transistor MN2, a third N-type transistor MN3, a fourth N-type transistor MN4, a fifth N-type transistor MN5, a sixth N-type transistor MN6, a seventh N-type transistor MN7, and an eighth N-type transistor MN8. The gate terminals of MN1 and MN2 are both connected to the drain terminal of MN1, and the source terminal of MN1 is connected to the drain terminal of MN2, outputting a first bias voltage signal VBNC. This voltage signal is also connected to the gate terminals of MN9 and MN10 in the current-to-voltage module T2, providing bias voltages for MN9 and MN10. The drain terminal of MN3 is connected to the gate terminals of MN4, MN6, and MN8, outputting a second bias voltage signal VBN. This voltage signal is also connected to the gate terminals of MN11 and MN12 in the current-to-voltage module T2, providing bias voltages for MN11 and MN12. The gate terminal of MN3 is connected to the gate terminals of MN1, MN2, MN5, and MN7, respectively. The source terminal of N5 is connected to the drain terminal of MN6, and the source terminal of MN7 is connected to the drain terminal of MN8. The gate terminal of MP1 is connected to the gate terminal of MP2, the drain terminal of MP2, the gate terminal of MP4, and the drain terminal of MN5, outputting a third bias voltage signal VBPC. This voltage signal is also connected to the gate terminals of MP10 and MP11 in the current-to-voltage module T2, providing bias voltage for MP10 and MP11. The drain terminal of MP1 is connected to the source terminal of MP2. The gate terminal of MP3 is connected to the drain terminal of MP4 and the drain terminal of MN7, outputting a fourth bias voltage signal VBP. This voltage signal is also connected to the gate terminal of MP5 in the main voltage-to-current module T1, providing bias voltage for MP5. The drain terminal of MP3 is connected to the source terminal of MP4.

[0037] The circuit works as follows:

[0038] One current source generates a first bias voltage VBNC through MN1 and MN2, and another current source generates a second bias voltage VBN through MN3 and MN4. The first bias voltage VBNC and the second bias voltage VBN generate a bias current through the gate terminals of MN6 and MN5, respectively, and then generate a third bias voltage VBPC through MP1 and MP2. The first bias voltage VBNC and the second bias voltage VBN simultaneously generate another bias current through the gate terminals of MN8 and MN7, respectively, and then generate a fourth bias voltage VBP through MP3 and MP4.

[0039] The fourth bias voltage VBP provides bias to MP5 and MP12 through the gate terminals of MP5 and MP12; the third bias voltage VBPC provides bias to MP10 and MP11 through the gate terminals of MP10 and MP11; the first bias voltage VBNC provides bias to MN9 and MN10 through MN9 and MN10; the second bias voltage VBN provides bias to MN11 and MN12 through MN11 and MN12; the input fully differential voltage signal is converted into a differential current signal through MP13 and MP14, then converted into a differential voltage signal through MN13 and MN14, and then through MN15 and MN16... MN17 and MN18 are converted into two current signals; the input fully differential voltage signal is also converted into a differential current signal through MP6 and MP7. The current signal in MP6 is combined with the current in MN15 and MN17, and then converted into a voltage signal through MN11, MN9, MP10, and MP8, and then converted into a current signal through MP9. The current signal in MP7 is combined with the current in MN16 and MN18, and then combined with the current signal converted by MP9, and then passed through the small signal impedance of MN12, MN10, MP11, and MP9 to be converted into a high common-mode rejection ratio voltage signal, and output from the output terminal VOUT.

[0040] Example 2:

[0041] Reference Figure 4 The high common-mode rejection ratio operational amplifier in this example includes main circuits T1 and T2, which consist of 4 P-type transistors MP and 7 N-type transistors MN; common-mode rejection ratio enhancement circuits T3 and T4, which consist of 6 P-type transistors MP and 3 N-type transistors MN; and bias circuit T5, which is the same as in Example 1.

[0042] The main voltage-to-current module T1 includes a twenty-fourth N-type transistor MN24, a twenty-fifth N-type transistor MN25, and a twenty-ninth N-type transistor MN19. The source terminal of MN19 is connected to ground, the gate terminal is connected to the bias circuit module, and the drain terminal is connected to the source terminals of MN24 and MN25. The gate terminals of MN25 and MN25 are connected to the differential input signals VIN and VIP, and are also connected to the two input terminals of the low-gain differential amplifier T3, respectively. After the differential input signals are processed into voltage-to-current signals, the current is output from their respective drain terminals and connected to the two input terminals of the current-to-voltage module T2.

[0043] The low-gain differential amplifier T3 includes a pre-amplifier voltage-to-current module T31 and a pre-amplifier current-to-voltage module T32. The pre-amplifier voltage-to-current module T31 includes a 26th N-type transistor MN26, a 27th N-type transistor MN27, and a 28th N-type transistor MN28. The pre-amplifier current-to-voltage module T32 includes a 23rd P-type transistor MP23 and a 24th P-type transistor MP24. The source terminal of MN28 is connected to ground, the gate terminal is connected to the bias circuit module, and the drain terminal is connected to the source terminals of MN26 and MN27. The gate terminals of MN26 and MN27 are respectively connected to the differential input signals VIN and VIP, and are also connected to the two input terminals of the main voltage-to-current module T1. The gate terminal and drain terminal of MP23 are connected to the drain terminal of MN27. The gate terminal and drain terminal of MP24 are connected to the drain terminal of MN26.

[0044] The auxiliary voltage-to-current module T4 includes a 22nd P-type transistor MP22, a 21st P-type transistor MP21, a 19th P-type transistor MP19, and a 20th P-type transistor MP20. The gate terminals of MP22 and MP21 are both connected to the gate terminal of MP23. The gate terminals of MP19 and MP20 are both connected to the gate terminal of MP24. The drain terminal of MP19 is connected to the drain terminal of MP21, forming one output of the T4 module, and is connected to one output terminal of the main voltage-to-current module T1, namely the drain terminal of MN24, to cancel the common-mode component on this path. The drain terminal of MP20 is connected to the drain terminal of MP22, forming another output of the T4 module, and is connected to another output terminal of the main voltage-to-current module T1, namely the drain terminal of MN25, to cancel the common-mode component on this path. By canceling the common-mode components of the two paths, the common-mode rejection ratio is improved.

[0045] The current-to-voltage module T2 includes a seventeenth P-type transistor MP17, an eighteenth P-type transistor MP18, a fifteenth P-type transistor MP15, a sixteenth P-type transistor MP16, a twenty-second N-type transistor MN22, a twenty-third N-type transistor MN23, a twentieth N-type transistor MN20, and a twenty-first P-type transistor MP21. The gate terminals of MN22, MN23, MP15, MP16, MP17, and MP18 are all connected to the bias circuit module. The drain terminal of MP15 is connected to the drain terminal of MN22 and the gate terminal of MN20. The drain terminal of MN23 is connected to the output terminal VOUT and the drain terminal of MP16. The source terminal of MN22 is connected to the drain terminal of MN20, and the source terminal of MN23 is connected to the drain terminal of MN21. The drain terminal of MP17 is connected to the source terminal of MP15 and the main voltage. One output terminal of the current conversion module T1, namely the drain terminal of MN25, and one output terminal of the auxiliary voltage to current conversion module T4, namely the drain terminals of MN20 and MN22, are connected to combine the output current of the drain terminal of MN25 with the output current of the drain terminals of MN20 and MN22, and then convert it into voltage through the gate terminal of MN20. This voltage is then converted into current through MN21. The drain terminal of MP18 is connected to the source terminal of MP16, the drain terminal of another output terminal of the main voltage to current conversion module T1, namely the drain terminal of MN24, and the drain terminals of another output terminal of the auxiliary voltage to current conversion module T4, namely the drain terminals of MN19 and MN21, respectively. This is used to combine the output current of the drain terminal of MN24 with the output current of the drain terminals of MN19 and MN21, and then, together with the current of the drain terminal of MN21, pass through the small signal impedance of MP16, MP18, MN23, and MN21 to convert it into a high common-mode rejection ratio voltage signal, which is output from the output terminal VOUT.

[0046] The bias circuit T5 has the same circuit structure as in Example 1. Its connection relationship with the relevant transistors in the main voltage-to-current module T1 and the current-to-voltage module T2 is as follows: the first bias voltage VBNC is connected to the drain terminals of MN22 and MN23 in the current-to-voltage module T2; the second bias voltage VBN is connected to the gate terminal of MN19 in the main voltage-to-current module T1 and the gate terminal of MN28 in the pre-voltage-to-current module T3, respectively; the third bias voltage VBPC is connected to the gate terminals of MP15 and MP16 in the current-to-voltage module T2; and the fourth bias voltage VBP is connected to the gate terminals of MP17 and MP18 in the current-to-voltage module T2.

[0047] The circuit works as follows:

[0048] One current source generates a first bias voltage VBNC through MN1 and MN2, and another current source generates a second bias voltage VBN through MN3 and MN4. The first bias voltage VBNC and the second bias voltage VBN generate a bias current through the gate terminals of MN6 and MN5, respectively, and then generate a third bias voltage VBPC through MP1 and MP2. The first bias voltage VBNC and the second bias voltage VBN simultaneously generate another bias current through the gate terminals of MN8 and MN7, respectively, and then generate a fourth bias voltage VBP through MP3 and MP4.

[0049] The second bias voltage VBN provides bias to MN19 and MN28 through the gate terminals of MN19 and MN28; the first bias voltage VBNC provides bias to MP17 and MP18 through the gate terminals of MP17 and MP18; the third bias voltage VBPC provides bias to MP15 and MP16 through MP15 and MP16; the fourth bias voltage VBP provides bias to MP17 and MP18 through MP17 and MP18; the input fully differential voltage signal is converted into a differential current signal through MN26 and MN27, then converted into a differential voltage signal through MP24 and MP23, and then through MP19, MP20, and MP28. 21. MP22 converts to two current signals; the input fully differential voltage signal is also converted to a differential current signal through MN24 and MN25; the current signal in MN25 is combined with the current in MP20 and MP22, and converted into a voltage signal through MP17, MP15, MN22 and MN20, and then converted into a current signal through MN21; the current signal in MN24 is combined with the current in MP19 and MP21, and then combined with the current signal converted by MN21, and then converted into a high common-mode rejection ratio voltage signal through the small signal impedance of MP18, MP16, MN23 and MN21, and output from the output terminal VOUT.

[0050] The effects of this invention can be further illustrated by the following simulation experiments.

[0051] I. Simulation Conditions

[0052] The Cadance Virtuoso software was used, with the temperature set to 27℃ and the power supply voltage to 3.3V.

[0053] II. Simulation Content

[0054] Based on the above simulation conditions, common-mode rejection capability simulations were performed on Embodiment 1 of the present invention and a conventional operational amplifier without a common-mode rejection ratio enhancement module, respectively. The results are as follows: Figure 5 As shown.

[0055] from Figure 5As can be seen, the common-mode rejection capability of Embodiment 1 of the present invention weakens with increasing frequency. In the frequency range of 1 Hz to 1000 Hz, the common-mode rejection capability of Embodiment 1 of the present invention is approximately -157 dB; while the common-mode rejection capability of existing operational amplifiers without common-mode rejection ratio enhancement modules weakens with increasing frequency. In the frequency range of 1 Hz to 1000 Hz, the common-mode rejection capability of existing operational amplifiers without common-mode rejection ratio enhancement modules is approximately -124 dB.

[0056] The comparison revealed that the common-mode rejection capability of Embodiment 1 of the present invention is enhanced by 33dB compared to the existing operational amplifiers that do not include a common-mode rejection ratio enhancement module, indicating that the present invention has a stronger common-mode rejection capability.

Claims

1. A high common-mode rejection ratio (CMRR) operational amplifier, comprising a main circuit, a CMRR enhancement circuit, and a bias circuit T5, wherein the main circuit is a dual-input, single-output amplifier including a main voltage-to-current module T1 and a current-to-voltage module T2 connected together, characterized in that: The common-mode rejection ratio (CMRR) improvement circuit includes a low-gain differential amplifier T3 and an auxiliary voltage-to-current converter T4. The low-gain differential amplifier T3 has two input terminals and two output terminals, and the auxiliary voltage-to-current module T4 has four input terminals and two output terminals. The two input terminals of the low-gain differential amplifier T3 are connected to the differential input voltage signal respectively, which is used to amplify the differential input voltage signal. Two amplified differential output voltage signals are output from the two output terminals. One output voltage signal is connected to two inputs of the auxiliary voltage to current module T4, and the other output voltage signal is connected to the other two inputs of the auxiliary voltage to current module T4. The auxiliary voltage-to-current module T4 processes the four input voltage signals into current signals, outputs two current signals, and transmits them to the two input terminals of T2. The low-gain differential amplifier T3 includes: a pre-voltage to current conversion module T31 and a pre-current to voltage conversion module T32; the pre-voltage to current conversion module T31 has a set of differential voltage signals VIP and VIN connected to its input terminal, which is used to convert the differential voltage input signal into a differential current signal and output it to the pre-current to voltage conversion module T32. The pre-current to voltage module T32 is used to convert the differential current signal output by the pre-voltage to current module T31 into a differential voltage signal and output it to the auxiliary voltage to current module T4. The auxiliary voltage-to-current module T4 is constructed from multiple P-type transistors or multiple N-type transistors; The auxiliary voltage-to-current module T4, which is constructed from multiple N-type transistors, includes the fifteenth N-type transistor MN15, the sixteenth N-type transistor MN16, the seventeenth N-type transistor MN17, and the eighteenth N-type transistor MN18. The gate terminals of MN15 and MN16 are both connected to the gate terminal of MN14. The gate terminals of MN17 and MN18 are both connected to the gate terminal of MN13; The drain of MN15 is connected to the drain of MN17 to form one output of the T4 module, and is connected to one output of the main voltage-to-current module T1 to cancel the common-mode component on this path. The drain of MN16 is connected to the drain of MN18 to form another output of the T4 module, and is connected to another output of the main voltage-to-current module T1 to cancel the common-mode component on this path. The auxiliary voltage-to-current module T4, which is constructed from multiple P-type transistors, includes the nineteenth P-type transistor MP19, the twentieth P-type transistor MP20, the twenty-second P-type transistor MP22, and the twenty-first P-type transistor MP21. The gate terminals of MP22 and MP21 are both connected to the gate terminal of MP23; The gate terminals of MP19 and MP20 are both connected to the gate terminal of MP24; The drain of MP19 is connected to the drain of MP21 to form one output of the T4 module, and is connected to one output of the main voltage-to-current module T1 to cancel the common-mode component on this path. The drain of MP20 is connected to the drain of MP22 to form another output of the T4 module, and is connected to another output of the main voltage-to-current module T1 to cancel the common-mode component on this path. The common-mode rejection ratio is improved by canceling out the two common-mode components.

2. The high common-mode rejection ratio operational amplifier according to claim 1, characterized in that: The first input terminal of the main voltage-to-current module T1 is connected to a differential signal VIP for voltage-to-current conversion, and the second input terminal is connected to another differential signal VIN for voltage-to-current conversion. The two differential current signals after conversion are connected to the two input terminals of the current-to-voltage module T2.

3. The high common-mode rejection ratio operational amplifier according to claim 1, characterized in that: The current-to-voltage module T2 has its first input terminal connected to one output current signal of both the main voltage-to-current module T1 and the auxiliary voltage-to-current module T4 for current-to-voltage conversion. Its second input terminal is connected to the other output current signal of both the main voltage-to-current module T1 and the auxiliary voltage-to-current module T4 for current-to-voltage conversion. The two converted voltage signals are then combined and a high common-mode rejection ratio voltage signal is output from the output terminal VOUT.

4. The high common-mode rejection ratio operational amplifier according to claim 1, characterized in that: The pre-voltage to current conversion module T31 is constructed from multiple P-type transistors or multiple N-type transistors; The pre-voltage to current conversion module T31, composed of multiple P-type transistors, includes a twelfth P-type transistor MP12, a thirteenth P-type transistor MP13, and a fourteenth P-type transistor MP14. The source terminal of MP12 is connected to the power supply VDD, the gate terminal is connected to the bias circuit module, and the drain terminal is connected to the source terminal of MP13 and MP14. The gate terminals of MP13 and MP14 are respectively connected to the differential input signals VIN and VIP, and are also connected to the two input terminals of the main voltage-to-current module T1. They are used to process the differential input signals from voltage to current, output current from their respective drain terminals, and connect to the two input terminals of the pre-current to voltage module T32. The pre-voltage to current conversion module T31, composed of multiple N-type transistors, includes the twenty-sixth N-type transistor MN26, the twenty-seventh N-type transistor MN27, and the twenty-eighth N-type transistor MN28. The source terminal of MN28 is connected to ground, the gate terminal is connected to the bias circuit module, and the drain terminal is connected to the source terminals of MN26 and MN27. The gate terminals of MN26 and MN27 are connected to the differential input signals VIN and VIP, respectively, and are also connected to the two input terminals of the main voltage-to-current module T1. They are used to process the differential input signals from voltage to current, output current from their respective drain terminals, and connect to the two input terminals of the pre-current to voltage module T32.

5. The high common-mode rejection ratio operational amplifier according to claim 1, characterized in that: The pre-current to voltage conversion module T32 is constructed from multiple P-type transistors or multiple N-type transistors; The pre-current to voltage conversion module T32, composed of multiple N-type transistors, includes a thirteenth N-type transistor MN13 and a fourteenth N-type transistor MN14; The gate and drain of MN13 are connected. The drain of MN13 is connected to one output current of the pre-voltage to current conversion module T31 and converts it into a voltage signal, which is then output to the auxiliary voltage to current conversion module T4. The gate and drain of MN14 are connected. The drain of MN14 is connected to another output current of the pre-voltage to current conversion module T31 and converts it into another voltage signal, which is then output to the auxiliary voltage to current conversion module T4. The pre-current to voltage conversion module T32, composed of multiple P-type transistors, includes the twenty-third P-type transistor MP23 and the twenty-fourth P-type transistor MP24; The gate and drain of the MP23 are connected. The drain of the MP23 is connected to one output current of the pre-voltage to current conversion module T31 and converts it into a voltage signal, which is then output to the auxiliary voltage to current conversion module T4. The gate and drain of the MP24 are connected. The drain of the MP24 is connected to another output current of the pre-voltage to current conversion module T31 and converts it into another voltage signal, which is then output to the auxiliary voltage to current conversion module T4.

6. The high common-mode rejection ratio operational amplifier according to claim 1, characterized in that: The main voltage-to-current module T1 is constructed from multiple P-type transistors or multiple N-type transistors; The main voltage-to-current module T1, composed of multiple P-type transistors, includes a fifth P-type transistor MP5, a sixth P-type transistor MP6, and a seventh P-type transistor MP7. The source terminal of the MP5 is connected to the power supply VDD, the gate terminal is connected to the bias circuit module, and the drain terminal is connected to the source terminal of the MP6 and MP7. The gate terminals of MP6 and MP7 are connected to the differential input signals VIN and VIP, respectively, and are also connected to the two input terminals of the low-gain differential amplifier T3. This is used to convert the differential input signals from voltage to current, and then output current from their respective drain terminals to the two input terminals of the current-to-voltage module T2. The main voltage-to-current module T1, composed of multiple N-type transistors, includes the twenty-fourth N-type transistor MN24, the twenty-fifth N-type transistor MN25, and the twenty-ninth N-type transistor MN19. The source terminal of MN19 is connected to ground, the gate terminal is connected to the bias circuit module, and the drain terminal is connected to the source terminals of MN24 and MN25. The gate terminals of MN25 and MN25 are connected to the differential input signals VIN and VIP, respectively, and are also connected to the two input terminals of the low-gain differential amplifier T3. This is used to process the differential input signals from voltage to current, and then output current from their respective drain terminals to the two input terminals of the current-to-voltage module T2.

7. The high common-mode rejection ratio operational amplifier according to claim 1, characterized in that: The current-to-voltage module T2 includes multiple P-type transistors and multiple N-type transistors, which can be formed through different connection relationships; Connection relationship 1: The current to voltage module T2 includes the eighth P-type transistor MP8, the ninth P-type transistor MP9, the tenth P-type transistor MP10, the eleventh P-type transistor MP11, the ninth N-type transistor MN9, the tenth N-type transistor MN10, the eleventh N-type transistor MN11, and the twelfth P-type transistor MP12. The gate terminals of MN11, MN12, MN9, MN10, MP10, and MP11 are all connected to the bias circuit module. The drain of MN9 is connected to the drain of MP10 and the gate of MP8, respectively. The drain of MN10 is connected to the drain of output VOUT and MP11 respectively; The source terminal of MP10 is connected to the drain terminal of MP8, and the source terminal of MP11 is connected to the drain terminal of MP9. The drain of MN11 is connected to the source of MN9, one output of the main voltage-to-current module T1, and one output of the auxiliary voltage-to-current module T4, respectively. It is used to combine the output current of the main voltage-to-current module T1 and one output current of the auxiliary voltage-to-current module T4, and then convert them into voltage through the gate of MP8. The voltage is then converted into current through MP9. The drain of MN12 is connected to the source of MN10, another output of the main voltage-to-current module T1, and another output of the auxiliary voltage-to-current module T4, respectively, to combine the output current of the main voltage-to-current module T1 and the other output current of the auxiliary voltage-to-current module T4. The two currents mentioned above pass through MP9, MP11, MN10, and MN12 simultaneously, and are converted into a high common-mode rejection ratio voltage signal, which is output from the output terminal VOUT. Connection Relationship 2: The current-to-voltage module T2 includes the seventeenth P-type transistor MP17, the eighteenth P-type transistor MP18, the fifteenth P-type transistor MP15, the sixteenth P-type transistor MP16, the twenty-second N-type transistor MN22, the twenty-third N-type transistor MN23, the twentieth N-type transistor MN20, and the twenty-first P-type transistor MP21; The gate terminals of MN22, MN23, MP15, MP16, MP17, and MP18 are all connected to the bias circuit module. The drain of MP15 is connected to the drain of MN22 and the gate of MN20, respectively. The drain of MN23 is connected to the output terminal VOUT and the drain of MP16 respectively; The source of MN22 is connected to the drain of MN20, and the source of MN23 is connected to the drain of MN21. The drain of MP17 is connected to the source of MP15, one output of the main voltage-to-current module T1, and one output of the auxiliary voltage-to-current module T4, respectively. It is used to combine the output current of the main voltage-to-current module T1 and one output current of the auxiliary voltage-to-current module T4, and then convert them into voltage through the gate of MN20. The voltage is then converted into current through MN21. The drain of MP18 is connected to the source of MP16, another output of the main voltage-to-current module T1, and another output of the auxiliary voltage-to-current module T4, respectively, to combine the output current of the main voltage-to-current module T1 and the other output current of the auxiliary voltage-to-current module T4. The two currents mentioned above pass through MP16, MP18, MN23, and MN21 simultaneously, and are converted into a high common-mode rejection ratio voltage signal, which is output from the output terminal VOUT.

8. The high common-mode rejection ratio operational amplifier according to claim 1, characterized in that: The bias circuit T5 includes multiple P-type transistors and multiple N-type transistors, namely, first P-type transistor MP1, second P-type transistor MP2, third P-type transistor MP3, fourth P-type transistor MP4, first N-type transistor MN1, second N-type transistor MN2, third N-type transistor MN3, fourth N-type transistor MN4, fifth N-type transistor MN5, sixth N-type transistor MN6, seventh N-type transistor MN7, and eighth N-type transistor MN8; The gate terminals of MN1 and MN2 are both connected to the drain terminal of MN1, and the source terminal of MN1 is connected to the drain terminal of MN2, outputting a first voltage signal VBNC. This voltage signal is also connected to the gate terminals of MN9 and MN10 in the current-to-voltage module T2. The drain of MN3 is connected to the gate of MN4, the gate of MN6, and the gate of MN8, and outputs a second voltage signal VBN. This voltage signal is also connected to the gates of MN11 and MN12 in the current-to-voltage module T2. The gate of MN3 is connected to the gates of MN1, MN2, MN5, and MN7, respectively. The source of MN5 is connected to the drain of MN6, and the source of MN7 is connected to the drain of MN8. The gate of MP1 is connected to the gate of MP2, the drain of MP2, the gate of MP4, and the drain of MN5, and outputs a third voltage signal VBPC. This voltage signal is also connected to the gates of MP10 and MP11 in the current-to-voltage module T2, and the drain of MP1 is connected to the source of MP2. The gate of MP3 is connected to the drain of MP4 and the drain of MN7, and outputs a fourth voltage signal VBP. This voltage signal is also connected to the gate of MP5 in the main voltage-to-current module T1, and the drain of MP3 is connected to the source of MP4.

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