A variable-resistance active gate driver, driving method, and medium

Abstract

The present invention relates to the field of power electronics technology, and provides a variable-resistance active gate driver, a driving method and a medium. The variable-resistance active gate driver includes: a control unit, an isolation gate driving module, a gate driving resistance network, a current change rate monitoring module and a target MOSFET circuit; one end of the isolation gate driving module is connected to the control unit, and the other end is connected to the gate driving resistance network; one end of the current change rate monitoring module is connected to the target MOSFET circuit, and the other end is connected to the control unit; the gate driving resistance network is connected to the target MOSFET circuit; the current change rate monitoring module monitors the drain-source current change rate of the target MOSFET circuit and feeds it back to the control unit, and according to the drain-source current change rate, sends a control signal to adjust the resistance value provided by the gate driving resistance network at the gate of the target MOSFET circuit. The present invention reduces the overshoot and oscillation of the source-drain voltage and current of the MOSFET, and improves the flexibility and dynamic adjustment ability of the active gate driving technology.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and more specifically, to a variable-resistance active gate driver, a driving method, and a medium. Background Art

[0002] In modern electronic devices and power systems, power devices are increasingly widely used and important, and their design trends are towards high power density, high operating voltage, and current. However, this trend has brought a series of challenges, especially the drain-source overshoot voltage and overshoot current problems faced by power devices during operation. These overshoot phenomena mainly occur during the switching operation of the device, and it is very likely that the transient voltage and current peaks exceed the limit specifications of the device, thereby damaging the device itself and threatening the safety of the entire system.

[0003] Traditionally, the methods to solve the overshoot problem of power devices usually focus on circuit design, such as increasing the driving resistance and optimizing the circuit layout to reduce the inductance effect and capacitance effect during device switching. However, the improvement effects of these means are not satisfactory, especially in the face of complex and diverse application scenarios, they seem to have great limitations. The active gate driving technology has been proposed as an innovative solution, which controls the switching waveform by dynamically adjusting the gate driving parameters. However, the current active gate driving technology has deficiencies in applicability and flexibility and is difficult to fully meet the diverse application requirements. Summary of the Invention

[0004] In order to overcome the defects of the existing active gate driving technology, such as low flexibility and dynamic adjustment ability, the present invention provides a variable-resistance active gate driver, a driving method, and a medium.

[0005] To solve the above technical problems, the technical solution of the present invention is as follows:

[0006] In a first aspect, the present invention proposes a variable-resistance active gate driver, including: a control unit, an isolation gate driving module, a gate driving resistance network, a current change rate monitoring module, and a target MOSFET circuit.

[0007] One end of the isolation gate driving module is connected to the control unit, and the other end is connected to the gate driving resistance network.

[0008] One end of the current change rate monitoring module is connected to the target MOSFET circuit, and the other end is connected to the control unit.

[0009] The gate driving resistance network is connected to the target MOSFET circuit.

[0010] The current change rate monitoring module monitors the drain-source current change rate of the target MOSFET circuit and feeds it back to the control unit. The control unit sends a control signal through the isolated gate drive module according to the drain-source current change rate to adjust the resistance value provided by the gate drive resistance network at the gate of the target MOSFET circuit.

[0011] As a preferred technical solution, the target MOSFET circuit includes a MOSFET device DUT and a parasitic inductance LP.

[0012] The gate of the MOSFET device DUT is connected to the output end of the gate drive resistance network, the drain is connected to an external power circuit, the source is connected to one end of the parasitic inductance LP, and the other end of the parasitic inductance LP is connected to the external power circuit.

[0013] As a preferred technical solution, the current change rate monitoring module includes an amplifier U4. The output end of the amplifier U4 is connected to the control unit, the positive input end is connected to the source of the driver of the MOSFET device DUT, and the negative input end is connected to the end of the parasitic inductance LP connected to the external power circuit.

[0014] As a preferred technical solution, the isolated gate drive module includes an isolation driver U1 and an isolation driver U2.

[0015] The input end of the isolation driver U1 is connected to the control unit, and the output end is connected to the connection in the gate drive resistance network.

[0016] The input end of the isolation driver U2 is connected to the control unit, and the output end is connected to the gate drive resistance network.

[0017] As a preferred technical solution, the gate drive resistance network includes transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, resistors R1, R2, R3, R4, R5, R6, R7, R8, a positive power supply VDD, and a negative power supply VSS.

[0018] The output end of the isolation driver U1 is respectively connected to the gates of the transistors Q1, Q3, Q5, and Q7.

[0019] The output end of the isolation driver U2 is respectively connected to the gates of the transistors Q2, Q4, Q6, and Q8.

[0020] One end of the resistor R1 is connected to the source of the transistor Q1, and the other end is connected to the gate of the MOSFET DUT. One end of the resistor R3 is connected to the source of the transistor Q3, and the other end is connected to the gate of the MOSFET DUT. One end of the resistor R5 is connected to the source of the transistor Q5, and the other end is connected to the gate of the MOSFET DUT. One end of the resistor R7 is connected to the source of the transistor Q7, and the other end is connected to the gate of the MOSFET DUT.

[0021] One end of the resistor R2 is connected to the drain of the transistor Q2, and the other end is connected to the gate of the MOSFET DUT. One end of the resistor R4 is connected to the drain of the transistor Q4, and the other end is connected to the gate of the MOSFET DUT. One end of the resistor R6 is connected to the drain of the transistor Q6, and the other end is connected to the gate of the MOSFET DUT. One end of the resistor R8 is connected to the drain of the transistor Q8, and the other end is connected to the gate of the MOSFET DUT.

[0022] The positive output terminal of the positive power supply VDD is connected to the drains of the transistor Q1, the transistor Q3, the transistor Q5, and the transistor Q7. The negative output terminal is connected to the driver source of the MOSFET DUT, the positive input terminal of the amplifier U4, and the positive output terminal of the negative power supply VSS. The negative output terminal of the negative power supply VSS is connected to the drains of the transistor Q2, the transistor Q4, the transistor Q6, and the transistor Q8.

[0023] As a preferred technical solution, the resistors R1, R2, R3, R4, R5, R6, R7, and R8 are precision resistors with different resistance values.

[0024] In a second aspect, the present invention also provides a variable-resistance active gate driving method, which is applied to the variable-resistance active gate driver in any of the above solutions, and includes:

[0025] Monitoring the working state of the target MOSFET circuit through the current change rate monitoring module.

[0026] During the turn-on process of the target MOSFET circuit, the control unit controls the low-resistance combination resistors in the gate driving resistor network to conduct through the isolation gate driving module. The current change rate monitoring module continuously monitors the drain-source current change rate of the target MOSFET. When it detects that the drain-source current change rate reaches the set threshold, the control unit controls the high-resistance combination resistors in the gate driving resistor network to conduct through the isolation gate driving module. When the drain-source current tends to be stable, the control unit controls the low-resistance combination resistors in the gate driving resistor network to conduct again through the isolation gate driving module.

[0027] During the turn-off process of the target MOSFET circuit, the control unit controls the conduction of the resistors in the low-resistance combination in the gate drive resistor network through the isolated gate drive module. The current change rate monitoring module continuously monitors the drain-source current change rate of the target MOSFET. When the drain-source current change rate reaches a predetermined threshold, the control unit controls the conduction of the resistors in the high-resistance combination in the gate drive resistor network through the isolated gate drive module.

[0028] As a preferred technical solution, the control unit controls the conduction of the resistors in the low-resistance combination in the gate drive resistor network through the isolated gate drive module, including:

[0029] The control unit sends a control signal through the isolated gate drive module to make the multiple parallel low-resistance resistor combinations in the gate drive resistor network conduct, and at the same time make the high-resistance resistor combination disconnect, so as to provide a low equivalent resistance value at the gate of the target MOSFET circuit.

[0030] As a preferred technical solution, the control unit controls the conduction of the resistors in the high-resistance combination in the gate drive resistor network through the isolated gate drive module, including:

[0031] The control unit sends a control signal through the isolated gate drive module to make the multiple parallel high-resistance resistor combinations in the gate drive resistor network conduct, and at the same time make the low-resistance resistor combination disconnect, so as to provide a high equivalent resistance value at the gate of the target MOSFET circuit.

[0032] In a third aspect, the present invention also proposes a computer-readable storage medium, on which a program is stored, and the program is executed by a processor to perform the operations performed by the variable-resistance active gate drive method according to any one of the solutions in the second aspect.

[0033] Compared with the prior art, the beneficial effects of the technical solution of the present invention include: through the collaborative work of the control unit, the isolated gate drive module, the gate drive resistor network, and the current change rate monitoring module, the present invention can effectively monitor and adjust the drain-source current change rate of the target MOSFET circuit, dynamically control the gate resistance value, overcome the deficiencies of the existing active gate drive technology in terms of flexibility and dynamic adjustment ability, and improve flexibility. At the same time, through the optimized gate drive resistor network and dynamic feedback control, the present invention significantly reduces the overshoot and oscillation of the source-drain voltage and current of the MOSFET, and improves the reliability and stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic circuit structure diagram of the variable-resistance active gate driver provided by the embodiment of the present application.

[0035] Figure 2 Schematic flow diagram of the variable - resistance active gate driving method provided by the embodiments of the present application.

[0036] Figure 3 Waveform diagram of the switching process of the variable - resistance active gate driving method provided by the embodiments of the present application. Among them, 1 - control unit, 2 - isolation gate driving module, 3 - gate driving resistance network, 4 - current change rate monitoring module, 5 - target MOSFET circuit. Detailed implementation manners

[0037] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The manners described in the following exemplary embodiments do not represent all manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0038] The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. The singular forms "a", "the" and "said" used in the present application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0039] It should be understood that the "first", "second" and similar terms used in the specification of the present application and the claims do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms such as "a" or "one" do not denote a quantity limitation, but mean that there is at least one. Unless otherwise specified, the similar terms such as "front part", "rear part", "lower part" and / or "upper part" are only for convenience of description and are not limited to a position or a spatial orientation. The terms "including" or "comprising" and the like mean that the elements or items appearing before "including" or "comprising" cover the elements or items listed after "including" or "comprising" and their equivalents, and do not exclude other elements or items. The terms "connected" or "coupled" and the like are not limited to physical or mechanical connections, and may include electrical connections, whether direct or indirect.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this disclosure belongs. The terms used in the specification of this disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit this disclosure.

[0041] The embodiments of the present application will be described in detail below with reference to the accompanying drawings. Without conflict, the features in the following embodiments can be combined with each other.

[0042] The technical solution of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0043] Embodiment 1

[0044] Refer to Figure 1 , an active gate driver with variable resistance proposed in the embodiment of the present application includes: a control unit 1, an isolated gate drive module 2, a gate drive resistor network 3, a current change rate monitoring module 4, and a target MOSFET circuit 5. One end of the isolated gate drive module 2 is connected to the control unit 1, and the other end is connected to the gate drive resistor network 3. One end of the current change rate monitoring module 4 is connected to the target MOSFET circuit 5, and the other end is connected to the control unit 1. The gate drive resistor network 3 is connected to the target MOSFET circuit 5. The current change rate monitoring module 4 monitors the drain-source current change rate of the target MOSFET circuit 5 and feeds it back to the control unit 1. The control unit 1 sends a control signal through the isolated gate drive module 2 according to the drain-source current change rate, so as to adjust the resistance value provided by the gate drive resistor network 3 at the gate of the target MOSFET circuit 5.

[0045] In the specific implementation process, the current change rate monitoring module 4 monitors the drain-source current change of the target MOSFET circuit 5 in real time and feeds the change rate back to the control unit 1. The control unit 1 adjusts the conduction of the gate drive resistor network 3 through the isolated gate drive module 2 according to the feedback signal to realize the dynamic adjustment of the gate resistance, so as to control the gate current and further control the change rate of the drain-source current. This process is particularly effective during the Miller plateau stage (when the drain-source voltage drops rapidly) to prevent current overshoot and oscillation.

[0046] It can be understood that through the collaborative work of the control unit 1, the isolated gate drive module 2, the gate drive resistor network 3, and the current change rate monitoring module 4, the drain-source current change rate of the target MOSFET circuit 5 can be effectively monitored and adjusted, and the gate resistance value can be dynamically controlled, overcoming the deficiencies of the existing active gate drive technology in terms of flexibility and dynamic adjustment ability. At the same time, the present invention significantly reduces the overshoot and oscillation of the source-drain voltage and current of the MOSFET through the optimized gate drive resistor network 3 and dynamic feedback control, improving the reliability and stability of the system.

[0047] Embodiment 2

[0048] Refer to Figure 1 , this embodiment makes improvements on the basis of the active gate driver with variable resistance proposed in Embodiment 1.

[0049] In this embodiment, the target MOSFET circuit 5 includes a MOSFET device under test (DUT) and a parasitic inductance LP. The gate of the MOSFET DUT is connected to the output terminal of the gate drive resistance network 3, the drain is connected to an external power circuit, the source is connected to one end of the parasitic inductance LP, and the other end of the parasitic inductance LP is connected to the external power circuit. The parasitic inductance LP represents the sum of the drain-source parasitic inductance of the target MOSFET DUT and the circuit parasitic inductance, which does not exist in the actual application circuit.

[0050] In the specific implementation process, the MOSFET DUT and the parasitic inductance LP form a part of the MOSFET switching path. The existence of the parasitic inductance may cause a drain-source current overshoot during the switching process. The current change rate monitoring module 4 monitors this current change and feeds it back to the control unit 1, and the control unit 1 alleviates the current spike by adjusting the resistance of the gate drive resistance network 3.

[0051] It can be understood that by using the parasitic inductance LP to simulate the actual working environment of the MOSFET, the current change rate can be precisely controlled, the overshoot suppression effect can be optimized, the influence of the reverse electromotive force during turn-off can be reduced, and the reliability can be improved.

[0052] In this embodiment, the current change rate monitoring module 4 includes an amplifier U4. The output terminal of the 1st pin of the amplifier U4 is connected to the input terminal of the 1st pin of the control unit 1, the positive input terminal of the 2nd pin is connected to the source of the driver of the MOSFET DUT, and the negative input terminal of the 1st pin is connected to the end of the parasitic inductance LP connected to the external power circuit.

[0053] In the specific implementation process, the amplifier U4 is used to collect the current change rate between the source of the driver of the MOSFET DUT and the parasitic inductance LP in real time, and amplify and transmit this signal to the control unit 1. Based on the real-time signal of the current change rate, the control unit 1 dynamically adjusts the conduction state of the gate drive resistance network 3 to achieve precise control.

[0054] It can be understood that by monitoring the real-time and high-precision drain-source current change rate signal, it is beneficial to respond more quickly to the gate resistance adjustment requirement, and improve the response speed and control effect of the driver.

[0055] In this embodiment, the isolated gate drive module 2 includes isolated drivers U1 and U2. The input terminal of the 5th pin of the isolated driver U1 is connected to the output terminal of the 3rd pin of the control unit 1, and the output terminals of the 1st - 4th pins are connected to some transistors of the gate drive resistance network 3. The input terminal of the 5th pin of the isolated driver U2 is connected to the output terminal of the 2nd pin of the control unit 1, and the 1st - 4th output terminals are connected to other transistors of the gate drive resistance network 3.

[0056] In the specific implementation process, the control unit 1 is isolated from the gate drive resistor network 3 to prevent the control signal from directly affecting the stability of the resistor network. The isolation effect of U1 and U2 further reduces the impact of high-voltage transients on the control unit 1.

[0057] It can be understood that the isolation drive module improves the electrical isolation and anti-interference ability of the system, protects the control unit 1, and enables the driver to operate stably in high-voltage applications.

[0058] In this embodiment, the gate drive resistor network 3 includes transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, resistors R1, R2, R3, R4, R5, R6, R7, R8, a positive power supply VDD, and a negative power supply VSS.

[0059] The output terminals of pins 1-4 of the isolation driver U1 are respectively connected to the gates of transistors Q1, Q3, Q5, and Q7. The output terminals of pins 1-4 of the isolation driver U2 are respectively connected to the gates of transistors Q2, Q4, Q6, and Q8.

[0060] In the specific implementation process, the output terminals of the isolation driver U1 are respectively connected to the gates of transistors Q1, Q3, Q5, and Q7 to control the turn-on and turn-off of these transistors. The output terminals of the isolation driver U2 are respectively connected to the gates of transistors Q2, Q4, Q6, and Q8 to independently control the turn-on and turn-off states of these transistors.

[0061] Each of the transistors Q1 to Q8 is connected to a resistor to form a parallel structure, thereby providing different equivalent resistances in different combinations of conduction states:

[0062] One end of resistor R1 is connected to the source of transistor Q1, and the other end is connected to the gate of the MOSFET DUT. One end of resistor R3 is connected to the source of transistor Q3, and the other end is connected to the gate of the MOSFET DUT. One end of resistor R5 is connected to the source of transistor Q5, and the other end is connected to the gate of the MOSFET DUT. One end of resistor R7 is connected to the source of transistor Q7, and the other end is connected to the gate of the MOSFET DUT. One end of resistor R2 is connected to the drain of transistor Q2, and the other end is connected to the gate of the MOSFET DUT. One end of resistor R4 is connected to the drain of transistor Q4, and the other end is connected to the gate of the MOSFET DUT. One end of resistor R6 is connected to the drain of transistor Q6, and the other end is connected to the gate of the MOSFET DUT. One end of resistor R8 is connected to the drain of transistor Q8, and the other end is connected to the gate of the MOSFET DUT.

[0063] The positive output terminal of the positive power supply VDD is connected to the drains of transistors Q1, Q3, Q5, and Q7. The negative output terminal is connected to the driver source of the MOSFET DUT, the positive input terminal of the amplifier U4, and the positive output terminal of the negative power supply VSS. The negative output terminal of the negative power supply VSS is connected to the drains of transistors Q2, Q4, Q6, and Q8

[0064] In the specific implementation process, by controlling the output signals of the isolation drivers U1 and U2, the on - off control of transistors Q1 to Q8 can be achieved. By selecting different resistor combinations, the equivalent resistance value at the MOSFET gate changes dynamically during the turn - on and turn - off processes. For example, during the turn - on process, a low - resistance combination (e.g., Q1, Q3, Q5, Q7 and their corresponding resistors R1, R3, R5, R7) can be turned on to provide a smaller gate equivalent resistance value to accelerate the charging speed of the gate current. During the turn - off process, a high - resistance combination (e.g., Q2, Q4, Q6, Q8 and their corresponding resistors R2, R4, R6, R8) can be turned on to increase the gate resistance, slow down the turn - off speed, control the falling rate of the drain - source current, and thus effectively suppress the overshoot phenomenon.

[0065] It can be understood that the gate drive resistor network 3 can accurately control the gate current by dynamically combining different resistors in different operating states of the MOSFET. This structure provides appropriate equivalent resistances during the turn - on and turn - off processes respectively to reduce the overshoot of the drain - source current and voltage, extend the service life of the MOSFET, and improve the stability and reliability of the circuit. In addition, controlling transistors Q1 to Q8 through the isolation driver helps to maintain the isolation of the control signal in a high - voltage environment and avoid the control unit 1 from being interfered by high voltage.

[0066] In this embodiment, resistors R1 to R8 are precision resistors with different resistance values.

[0067] Embodiment 3

[0068] Refer to Figure 2 , this embodiment proposes a variable - resistance active gate drive method, which is applied to the variable - resistance active gate driver described in any of the above embodiments, and includes:

[0069] Monitor the working state of the target MOSFET circuit 5 through the current change rate monitoring module 4.

[0070] During the turn-on process of the target MOSFET circuit 5, the control unit 1 controls the conduction of the low-resistance combination in the gate drive resistor network 3 through the isolated gate drive module 2. The current change rate monitoring module 4 continuously monitors the change rate of the MOSFET drain-source current. When the change rate reaches the set threshold, the control unit 1 switches to the conduction of the high-resistance combination through the isolated gate drive module 2. When the drain-source current tends to be stable, the control unit 1 switches back to the conduction of the low-resistance combination again.

[0071] During the turn-off process of the target MOSFET circuit 5, the control unit 1 makes the low-resistance combination in the gate drive resistor network 3 conduct through the isolated gate drive module 2, and the current change rate monitoring module 4 continuously monitors the change rate of the MOSFET drain-source current. When the change rate of the drain-source current reaches the predetermined threshold, the control unit 1 switches to the conduction of the high-resistance combination again through the isolated gate drive module 2 to achieve dynamic gate current control.

[0072] In this embodiment, the control unit 1 controls the conduction of the low-resistance combination in the gate drive resistor network 3 through the isolated gate drive module 2, including: the control unit 1 sends a control signal through the isolated gate drive module 2 to make the multiple parallel low-resistance resistor combinations in the gate drive resistor network 3 conduct, and at the same time makes the high-resistance resistor combination disconnect, so as to provide a low equivalent resistance value at the gate of the target MOSFET circuit 5.

[0073] In this embodiment, the control unit 1 controls the conduction of the high-resistance combination in the gate drive resistor network 3 through the isolated gate drive module 2, including: the control unit 1 sends a control signal through the isolated gate drive module 2 to make the multiple parallel high-resistance resistor combinations in the gate drive resistor network 3 conduct, and at the same time makes the low-resistance resistor combination disconnect, so as to provide a high equivalent resistance value at the gate of the target MOSFET circuit 5.

[0074] As an exemplary illustration, during the Miller plateau stage in the MOSFET turn-on process, the gate current starts to charge the gate-drain capacitance and the drain-source voltage starts to drop. At this time, due to the reverse recovery of the junction capacitance of the MOSFET anti-parallel diode and the parasitic inductance, the drain-source current will generate spikes and oscillations, and the overshoot current can be approximated as:

[0075]

[0076] And the change rate of the drain-source voltage can be approximated as:

[0077]

[0078] where is the gate current of the MOSFET. Therefore, the above analysis shows that the drain-source overshoot current of the MOSFET can be controlled by controlling the magnitude of the gate current during the Miller plateau phase. Combining the variable-resistance active gate driver proposed in Embodiments 1 and 2, the following method can effectively reduce the drain-source overshoot current during the turn-on process of the MOSFET:

[0079] The current change rate monitoring module 4 monitors the drain-source current change rate of the target MOSFET circuit 5 and determines the turn-on state of the MOSFET.

[0080] The control unit 1 first controls the conduction of the low-resistance combination through the isolated gate drive module 2 to provide a larger gate current, accelerate the injection speed of the MOSFET gate charge, and thus accelerate the turn-on speed of the MOSFET.

[0081] As the turn-on process progresses, when the drain-source current change rate reaches the set threshold, it indicates that the turn-on process enters the Miller plateau phase. At this time, the control unit 1 switches to the conduction of the high-resistance combination, reduces the gate current, and reduces the peak value of the overshoot current.

[0082] When the drain-source current tends to be stable and the turn-on is nearly complete, the control unit 1 switches back to the conduction of the low-resistance combination again to ensure the smooth end of the turn-on process.

[0083] After the Miller plateau phase during the turn-off process of the MOSFET, the drain-source voltage reaches the bus voltage. At the same time, the drain-source current begins to decrease. However, due to the parasitic inductance in the MOSFET device and the circuit, a back electromotive force that prevents the current from decreasing is generated across the drain-source of the MOSFET. This back electromotive force causes the drain-source voltage of the MOSFET to exceed the bus voltage, forming an overshoot voltage. The overshoot voltage can be approximated as:

[0084]

[0085] And the drain-source current change rate can be approximated as:

[0086]

[0087] Where is the transconductance of the MOSFET, is the input resistance of the MOSFET. The above analysis shows that the drain-source overshoot voltage of the MOSFET can be controlled by controlling the magnitude of the gate current after the Miller plateau phase. Combining the variable-resistance active gate driver proposed in Embodiments 1 and 2, the following method can effectively reduce the drain-source overshoot voltage during the turn-off process of the MOSFET:

[0088] The current change rate monitoring module 4 is also used to monitor the drain-source current change rate in real time and determine that the MOSFET is in the turn-off state.

[0089] The control unit 1 first controls the low-resistance combination to conduct through the isolation gate drive module 2 to quickly reduce the gate charge and accelerate the turn-off speed.

[0090] When the rate of change of the drain-source current reaches the set threshold, the control unit 1 switches to the high-resistance combination to conduct, so as to slow down the rate of current decline and suppress the back electromotive force caused by the parasitic inductance, thereby effectively controlling the overshoot of the drain-source voltage.

[0091] As Figure 3 shown, Figure 3 It is the waveform diagram of the switching process of the variable-resistance active gate drive method provided by the embodiment of the present application.

[0092] During the turn-on process ( t 1 to t 6):

[0093] t 1 to t 3: At the initial stage of turn-on, the gate drive resistance network 3 is in a low-resistance state to accelerate the gate charge injection of the MOSFET and quickly reduce the drain-source voltage.

[0094] t 3 to t 5: When the rate of change of the drain-source current reaches the set threshold, the control unit 1 switches to the high-resistance combination to conduct, so as to reduce the gate current, reduce the current overshoot during turn-on, and control the turn-on loss area.

[0095] t 5 to t 6: As the drain-source current tends to be stable, the control unit 1 switches to the low-resistance combination again to ensure the completion of the turn-on process.

[0096] During the turn-off process ( t 7 to t 13 ):

[0097] t 7 to t 10 : At the initial stage of turn-off, the low-resistance combination conducts to accelerate the release of the gate charge.

[0098] t 10 to t 12 : When the rate of change of the drain-source current reaches the threshold, the control unit 1 switches to the high-resistance combination to limit the rate of decline of the drain-source current and reduce the overshoot of the drain-source voltage caused by the parasitic inductance.

[0099] t 12 to t13 : The control unit 1 maintains a high resistance state until the end of the turn-off process to reduce the turn-off loss area.

[0100] It can be understood that by dynamically adjusting the resistance combination in the gate drive resistor network 3, the overshoot phenomena of the drain-source current and drain-source voltage during the turn-on and turn-off processes of the MOSFET can be effectively suppressed. Compared with the traditional fixed-resistance drive method, this method can reduce the impact of overshoot on the device without affecting the switching speed, improve the reliability and lifespan of the MOSFET and the entire circuit system, and is applicable to power electronic applications with high requirements for switching characteristics.

[0101] Embodiment 4

[0102] The embodiment of the present application also provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, it implements the variable-resistance active gate drive method as described above.

[0103] In the description of this specification, the description with reference to terms such as "an embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms are not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or N embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0104] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "N" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0105] Any process or method description shown in the flowchart or described in other ways herein can be understood as representing a module, segment, or part of code including one or more executable instructions for implementing a customized logic function or process, and the scope of the preferred embodiments of the present application includes additional implementations, where the functions can be executed in a substantially simultaneous manner or in the reverse order according to the involved functions, rather than in the order shown or discussed, which should be understood by those skilled in the art of the embodiments of the present application.

[0106] It should be understood that each part of the present application can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logic functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays, field programmable gate arrays, and the like.

[0107] Those of ordinary skill in the art can understand that all or part of the steps carried by the method of the above embodiments can be completed by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0108] Obviously, the above embodiments of the present invention are merely examples for clearly explaining the present invention, rather than limitations on the embodiments of the present invention. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all the embodiments here. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the claims of the present invention.

Claims

1. A variable resistor active gate driver, characterized in that: include: A control unit (1), an isolated gate drive module (2), a gate drive resistor network (3), a current change rate monitoring module (4) and a target MOSFET circuit (5); The isolated gate drive module (2) comprises an isolated driver U1 and an isolated driver U2; the input end of the isolated driver U1 is connected to the control unit (1), and the output end is connected to the input end of the gate drive resistor network (3); the input end of the isolated driver U2 is connected to the control unit (1), and the output end is connected to the input end of the gate drive resistor network (3); The current change rate monitoring module (4) comprises an amplifier U4, the output end of the amplifier U4 is connected to the control unit (1), the positive input end is connected to the source of the MOSFET tube DUT, and the negative input end is connected to one end of the parasitic inductance LP connected to the external power circuit; The target MOSFET circuit (5) comprises a MOSFET tube DUT and a parasitic inductance LP; the gate of the MOSFET tube DUT is connected to the output end of the gate drive resistor network (3), the drain is connected to an external power circuit, the source is connected to one end of the parasitic inductance LP, and the other end of the parasitic inductance LP is connected to the external power circuit; The gate drive resistor network (3) comprises a transistor Q1, a transistor Q2, a transistor Q3, a transistor Q4, a transistor Q5, a transistor Q6, a transistor Q7, a transistor Q8, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, and a positive power supply VDD and a negative power supply VSS; The output end of the isolation driver U1 is connected to the gates of the transistor Q1, the transistor Q3, the transistor Q5 and the transistor Q7 respectively; The output end of the isolation driver U2 is connected to the gates of the transistor Q2, the transistor Q4, the transistor Q6 and the transistor Q8 respectively; One end of the resistor R1 is connected to the source of the transistor Q1, and the other end is connected to the gate of the MOSFET tube DUT; one end of the resistor R3 is connected to the source of the transistor Q3, and the other end is connected to the gate of the MOSFET tube DUT; one end of the resistor R5 is connected to the source of the transistor Q5, and the other end is connected to the gate of the MOSFET tube DUT; one end of the resistor R7 is connected to the source of the transistor Q7, and the other end is connected to the gate of the MOSFET tube DUT; One end of the resistor R2 is connected to the drain of the transistor Q2, and the other end is connected to the gate of the MOSFET tube DUT; one end of the resistor R4 is connected to the drain of the transistor Q4, and the other end is connected to the gate of the MOSFET tube DUT; one end of the resistor R6 is connected to the drain of the transistor Q6, and the other end is connected to the gate of the MOSFET tube DUT; one end of the resistor R8 is connected to the drain of the transistor Q8, and the other end is connected to the gate of the MOSFET tube DUT; The positive output terminal of the positive power supply VDD is connected to the drains of the transistors Q1, Q3, Q5 and Q7, and the negative output terminal is connected to the source of the MOSFET tube DUT, the positive input terminal of the amplifier U4 and the positive output terminal of the negative power supply VSS; the negative output terminal of the negative power supply VSS is connected to the drains of the transistors Q2, Q4, Q6 and Q8; The current change rate monitoring module (4) monitors the drain-source current change rate of the target MOSFET circuit (5) and feeds back to the control unit (1); the control unit (1) sends a control signal through the isolation gate drive module (2) according to the drain-source current change rate to adjust the resistance value provided by the gate drive resistor network (3) at the gate of the target MOSFET circuit (5).

2. The variable resistor active gate driver according to claim 1, characterized in that: The resistor R1 , the resistor R2 , the resistor R3 , the resistor R4 , the resistor R5 , the resistor R6 , the resistor R7 and the resistor R8 are precision resistors with different resistance values.

3. A variable resistance active gate driving method, characterized in that: include: Monitoring the operating state of the target MOSFET circuit (5) through a current change rate monitoring module (4); During the opening process of the target MOSFET circuit (5), the control unit (1) sends a control signal through the isolated gate drive module (2) to turn on a plurality of parallel low-resistance resistor combinations in the gate drive resistor network (3), and at the same time disconnect the high-resistance resistor combination, so that a low equivalent resistance value is provided at the gate of the target MOSFET circuit (5); the current change rate monitoring module (4) continuously monitors the drain-source current change rate of the target MOSFET. When it is detected that the drain-source current change rate reaches a set threshold, the control unit (1) sends a control signal through the isolated gate drive module (2) to turn on a plurality of parallel high-resistance resistor combinations in the gate drive resistor network (3), and at the same time disconnect the low-resistance resistor combination, so that a high equivalent resistance value is provided at the gate of the target MOSFET circuit (5). When the drain-source current tends to be stable, the control unit (1) again controls the low-resistance resistor combination in the gate drive resistor network (3) to turn on through the isolated gate drive module (2); During the shutdown process of the target MOSFET circuit (5), the control unit (1) sends a control signal through the isolated gate drive module (2) to turn on the multiple parallel low-resistance resistor combinations in the gate drive resistor network (3) and disconnect the high-resistance resistor combinations, so that a low equivalent resistance value is provided at the gate of the target MOSFET circuit (5). The current change rate monitoring module (4) continuously monitors the drain-source current change rate of the target MOSFET. When the drain-source current change rate reaches a predetermined threshold, the control unit (1) sends a control signal through the isolated gate drive module (2) to turn on the multiple parallel high-resistance resistor combinations in the gate drive resistor network (3) and disconnect the low-resistance resistor combinations, so that a high equivalent resistance value is provided at the gate of the target MOSFET circuit (5).

4. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a program, and the program is used by a processor to execute the operations performed by the variable resistance active gate driving method as claimed in claim 3.

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