Multi-zone transmitter output waveform control

Abstract

The invention relates to multi-zone transmitter output waveform control. Systems and methods for operating a driver circuit are described. In a first region of a transition from an input signal to an output signal, a circuit may control a slew rate of the output signal to a first rate. The first region may terminate before the output signal reaches a predefined threshold voltage. In a second region of the transition, the circuit may reduce a slew rate of the output signal to a second rate that is lower than the first rate. The output signal crosses a predefined threshold voltage in the second region. In a third region of the transition, the circuit may increase a slew rate of the output signal to a third rate that is greater than the second rate. The transition may be done in a third region. The circuit may output an output signal to drive a transistor in an output driving stage of the driver circuit.

Description

Technical Field

[0001] The present disclosure relates to a data signal driver in a transmitter, and more particularly, to waveform control of an output of the transmitter. Background Art

[0002] A data signal driver (such as a push-pull driver) can output a signal that can control two power transistors (a high-side switch and a low-side switch) to switch a direct current (DC) input voltage in alternating half cycles to generate an output signal. Each power transistor can be responsible for the positive half cycle and the negative half cycle of the waveform of the output signal. In operation, one power transistor can be turned on at a time. The output signal can supply current to the load (e.g., push), or can absorb current from the load (e.g., pull). Summary of the invention

[0003] In one embodiment, a semiconductor device is generally described. The semiconductor may include a pre-driver circuit and a circuit. The pre-driver circuit may include a complementary metal oxide semiconductor (CMOS) inverter configured to invert an input signal to generate an output signal. The circuit may be configured to control the conversion rate of the output signal to a first rate in a first region of the transition from the input signal to the output signal. The first region may terminate before the output signal reaches a predefined threshold voltage. The circuit may be further configured to reduce the conversion rate of the output signal to a second rate lower than the first rate in a second region of the transition from the input signal to the output signal. The output signal may cross the predefined threshold voltage in the second region. The circuit may be further configured to increase the conversion rate of the output signal to a third rate greater than the second rate in a third region of the transition from the input signal to the output signal, wherein the transition is completed in the third region. The circuit may be further configured to output the output signal to drive a transistor in an output driver stage of the driver circuit.

[0004] In one embodiment, a device is generally described. The device may include a controller, an output driver stage, and a circuit. The controller may be configured to provide an input signal. The output driver stage may include a high-side transistor and a low-side transistor. The output driver stage may be configured to drive the high-side transistor and the low-side transistor using paired drive signals. The circuit may be configured to control the slew rate of the paired drive signals. The slew rate may be controlled to have different rates in different regions of the transition from the input signal to the paired drive signal. The crowbar current in the output driver stage may depend on the different rates in different regions of the transition.

[0005] In one embodiment, a method for operating a driver circuit is generally described. The method may include, in a first region of transition from an input signal to an output signal, controlling a slew rate of an output signal to a first rate. The first region may terminate before the output signal reaches a predefined threshold voltage. The method may further include, in a second region of transition from an input signal to an output signal, reducing the slew rate of the output signal to a second rate lower than the first rate. The output signal may cross the predefined threshold voltage in the second region. The method may further include, in a third region of transition from an input signal to an output signal, increasing the slew rate of the output signal to a third rate greater than the second rate. The transition may be completed in the third region. The method may further include using the output signal to drive a transistor in an output driver stage of the driver circuit.

[0006] The foregoing summary is merely illustrative and is not intended to be limiting in any way. In addition to the above illustrative aspects, embodiments, and features, further aspects, embodiments, and features will become apparent by reference to the accompanying drawings and the following detailed description. In the accompanying drawings, the same reference numerals indicate identical or functionally similar elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a diagram showing an apparatus that can implement multi-region transmitter output waveform control in one embodiment.

[0008] Figure 2 is a diagram showing waveforms of driver outputs resulting from implementation of multi-zone transmitter output waveform control in one embodiment.

[0009] Figure 3 is a diagram illustrating waveforms of multiple driver outputs resulting from implementation of multi-region transmitter output waveform control in one embodiment.

[0010] Figure 4 is a diagram illustrating an example waveform control circuit that may be used to implement multi-region transmitter output waveform control in one embodiment.

[0011] Figure 5 is a flow chart of an example process that may implement multi-zone transmitter output waveform control in one embodiment. DETAILED DESCRIPTION

[0012] In the following description, many specific details, such as specific structures, components, materials, dimensions, processing steps and techniques are set forth to provide an understanding of the various embodiments of the present application. However, those of ordinary skill in the art will appreciate that the various embodiments of the present application can be practiced without these specific details. In other examples, in order to avoid obscuring the present application, well-known structures or processing steps are not described in detail.

[0013] Figure 1 is a diagram showing an apparatus that may implement bevel drive compensation in one embodiment. Figure 1 The device shown can be a semiconductor device that implements the driver circuit 100. In one embodiment, the driver circuit 100 can be a multi-branch push-pull data driver. The driver circuit 100 may include multiple branches, such as N branches ranging from Leg-1 to Leg-N. A branch can be a portion that can be configured to perform a specific task. For example, one branch can provide data and commands (e.g., in the form of voltage) to control one load of the device, while another branch can provide data and commands to control another load of the device.

[0014] Using Leg-1 as an example, each leg may include at least a data interface 102, a controller 103, a waveform control circuit 110, and an output driver stage 108. The controller 103 may be, for example, a microcontroller that includes various types of hardware and circuit elements (such as logic gates and other specialized circuits). Figure 1 In the example shown, the controller 103 may include at least a NAND gate 104 and a NOR gate 106. The output driver stage 108 may include a pair of power transistors, which include a high-side (HS) transistor and a low-side (LS) transistor. The output driver stage 108 may further include a driver circuit device configured to drive the HS transistor and the LS transistor. The HS transistor may be a P-type metal-oxide-semiconductor (PMOS) device, such as a P-type metal-oxide-semiconductor field effect transistor (MOSFET). The LS transistor may be an N-type metal-oxide-semiconductor (NMOS) device, such as an N-type MOSFET.

[0015] The data interface 102 may be configured to receive input data 101 for a load 109. Leg-1 may be configured to provide data to the load 109 in the form of an output voltage Vout. The driver circuit 100 may receive an input voltage Vin from, for example, a power supply, and the output driver stage 108 may switch the HS transistor and the LS transistor to convert Vin to Vout. The NAND gate 104 in the controller 103 may receive an enable signal EN to turn on the HS transistor, and the NOR gate 106 in the controller 103 may receive an enable signal EN_n to turn on the LS transistor. The enable signals EN and EN_n may be complementary so that only one of the HS transistor and the LS transistor is turned on at a time.

[0016] The output driver stage 108 can be configured to drive the HS transistor on and off based on the output or drive signal from the NAND gate 104. The output driver stage 108 can be configured to drive the LS transistor on and off based on the output or drive signal from the NOR gate 106. During the push phase, the NAND gate 104 can output a low logic voltage level (e.g., representing a logic 0), and the HS transistor can be activated (e.g., closed) or turned on. Current can flow from Vin to Vout through the activated HS transistor. During the push phase, the LS transistor remains inactive (e.g., disconnected) and non-conductive, so that no current flows through the LS transistor. During the pull phase, the NOR gate 106 can output a high logic voltage level (e.g., representing a logic one), and the LS transistor can be activated (e.g., closed) or turned on. Current can flow from Vout to ground (GND) through the activated LS transistor. During the pull phase, the HS transistor remains inactive (e.g., disconnected) and non-conductive, so that no current flows through the HS transistor.

[0017] On the one hand, the driving signal used by the push-pull driver can be a pull-up signal or a pull-down signal. The pull-up signal can drive the output voltage to a high level (e.g., Vin), and the pull-down signal can drive the output voltage to a low level (e.g., GND). When the pull-up signal pulls the output voltage from low to high, the rate of rise of the output voltage can be referred to as the rising slew rate. When the pull-down signal pulls the output voltage from high to low, the rate of fall of the output voltage can be referred to as the falling slew rate.

[0018] In one aspect, a crowbar current Icb (also referred to as a switching current or transient current) between two transistors (such as MOSFETs) is a current that flows during a switching transition when one of the HS transistor and the LS transistor is turned on and the other is turned off. If the HS transistor and the LS transistor transition at about the same time (e.g., cross their respective gate threshold voltages), there may be a relatively small moment when both the HS transistor and the LS transistor are turned on at the same time, which allows the crowbar current Icb to flow from Vin to GND. The crowbar current may cause voltage spikes, ringing, and other undesirable effects at Vout. These effects may also stress the HS transistor and the LS transistor and other components in the device 100.

[0019] While maintaining data integrity at Vout, the crowbar current is minimized (e.g., an accurately smoothed output waveform). The waveform control circuit 110 can be implemented to provide relatively accurate control of the high impedance state at Vout. Each branch of the device 100 can include a respective waveform control circuit 110, which is configured to provide waveform control to shape the waveform of the gate voltage applied to the HS transistor and the LS transistor. Each waveform control circuit 110 may include an HS control circuit 112 and an LS control circuit 114, which are configured to control the rising slew rate and the falling slew rate of the gate voltage for driving the HS transistor and the LS transistor, respectively. The HS control circuit 112 and the LS control circuit 114 can be exactly the same circuit. In one embodiment, the waveform control circuit 110 can be configured to control the gate voltage change rate in different operating regions of the pre-driver stage of the HS transistor and the LS transistor. Control of different operating regions can shape the waveform of the gate voltage applied to the HS transistor and the LS transistor. Since the waveform control circuit 110 is used to control the gate voltage waveform, the crowbar current Icb can be reduced and / or minimized, and the output voltage Vout waveform can be maintained as an accurate and smooth output waveform. The waveform control circuit 110 can also be implemented as an architecture using multiple branches of a push-pull pair. In one embodiment, multiple parallel branches simultaneously enable their respective waveform control circuits 110 to control their respective effective impedances.

[0020] Figure 2 is a diagram illustrating an example waveform control circuit that may be used to implement multi-region transmitter output waveform control in one embodiment. Figure 2 The description can be found in Figure 1 Components shown in . Figure 2 , example waveforms of the gate voltage VgLS and the gate voltage VgHS applied to the gate terminals of the LS transistor and the HS transistor, respectively, are shown in FIG. Figure 2Also shown in FIG. 5 is an example waveform of Vout corresponding to VgLS and VgHS.

[0021] The waveform control circuit 110 may control a pre-driver stage including a plurality of operating regions 201, 202, 203 (e.g., before the drive signal reaches the output driver stage 108). The operating region 201 may be a transition preparation region, in which the LS transistor and the HS transistor are ready to transition from one state to another, such as from off to on, or from on to off. The operating region 202 may be a transition region, in which the LS transistor and the HS transistor transition from one state to another, such as from off to on, or from on to off. The operating region 203 may be a reset region, in which the LS transistor and the HS transistor are reset to a fully switched condition and maintained at a constant voltage level, reflecting the completion of the transition to the on or off state.

[0022] At the beginning of the operation region 201, such as time t1, a transition cycle of driving the output voltage Vout from high (HIGH) to low (LOW) is initiated. In order to drive Vout from high to low, the PMOS device or HS transistor needs to be turned off, and the NMOS device or LS transistor needs to be turned on. In order to turn off the HS transistor, the gate voltage VgHS driving the HS transistor needs to be pulled up to a high voltage or pulled up to the power rail (for example, the HS transistor is a PMOS device). In order to turn on the LS transistor, the gate voltage VgLS driving the LS transistor needs to be pulled up to a high voltage or pulled up to Vin (for example, the LS transistor is an NMOS device). Under the operation region 201, the waveform control circuit 110 can change the gate voltage VgLS and the gate voltage VgHS at a relatively fast speed (for example, increase VgLS and decrease VgHS). At time t2, before the gate voltage reaches the threshold voltage of any transistor, the rapid voltage change is terminated. In the operation region 201 , Vout may be maintained at a high voltage level during at least a portion of the time interval t2 - t1 (eg, the duration of the operation region 201 is t2 - t1 ) because the HS transistor and the LS transistor may not switch states instantly.

[0023] At the beginning of the operating region 202, such as at time t2, the waveform control circuit 110 can reduce the gate voltage change rate, or the change of VgHS and VgLS, so that when compared to the operating region 201, VgHS increases at a slower rate and VgLS increases at a slower rate. Under the operating region 202, the HS transistor and the LS transistor can both transition from one state to another in response to reaching their respective threshold voltages VthHS and threshold voltages VthLS. The HS transistor can transition from an on state to an off state in the operating region 202, and the LS transistor can transition from an off state to an on state in the operating region 202. As the rate of change of VgLS decreases in the region 202, the slew rate of the on LS transistor can also decrease. In addition, as the rate of change of VgHS decreases in the region 202, the slew rate of the off HS transistor can also decrease. In one aspect, as long as the slew rate of the on LS transistor is less than the slew rate of the on HS transistor, the crowbar current Icb can be slowed down, and vice versa. The waveform control circuit 110 can be configured to control the gate voltage change rate of the HS transistor and the LS transistor separately. The separate control of the gate voltage change rate of the HS transistor and the LS transistor can maintain the slew rate of the LS transistor turned on less than the slew rate of the HS transistor turned on, and vice versa. Therefore, in the potential case where both the HS transistor and the LS transistor are turned on, the waveform control circuit 110 can be configured to: if the HS transistor and the LS transistor are both turned on at the same time, slow down the crowbar current Icb flowing through the LS transistor, and then slow down the crowbar current Icb flowing from Vin to GND.

[0024] At the beginning of the operating region 203, such as time t3, the waveform control circuit 110 can increase the rate of change of the gate voltage VgHS and the gate voltage VgLS until the desired voltage is reached. In the operating region 203, the HS transistor and the LS transistor can be in a fully switched condition reflecting the completion of the state transition. The waveform control circuit 110 can be configured to arbitrarily adjust the rate of change of VgHS and VgLS in the operating regions 201, 202 and / or 203. Therefore, the crowbar current Icb can also be controlled by the waveform control circuit 110. The waveform control circuit 110 can provide improved control of the transition points of the HS transistor and the LS transistor to allow minimization of the crowbar current Icb and control of the high impedance state. In Figure 2In the illustrated embodiment, the waveform control circuit 110 symmetrically drives the HS transistor and the LS transistor in the operating regions 201 and 202, so that the magnitude of the rate of change of VgHS and VgLS in the operating regions 201 and 202 is the same (e.g., the same magnitude but different directions of change). In some embodiments, the waveform control circuit 110 may asymmetrically drive the HS transistor and the LS transistor in the operating regions 201 and / or 202, so that the magnitude of the rate of change of VgHS and VgLS in the operating regions 201 and / or 202 may be different. The asymmetrical drive may provide a trade-off between the crowbar current and the transient impedance depending on the application of the system 100.

[0025] Figure 3 is a diagram illustrating an example waveform control circuit that may be used to implement multi-region transmitter output waveform control in one embodiment. Figure 3 The description can be found in Figure 1 to Figure 2 The components shown in Figure 3 In the example shown, Figure 1 Four branches Leg-1 to Leg-4 among the N branches in are activated to drive the respective output driver stages to generate Vout. The four branches can be switched sequentially. Waveform 301 shows a scenario where the waveform control circuit ("circuit 110") is enabled in all four branches, and waveform 301 shows a scenario where the waveform control circuit ("circuit 110") is disabled in all four branches.

[0026] Comparing waveform 301 with waveform 302, when the waveform control circuits 110 in the four branches are disabled, the crowbar current Icb occurring during the transition of each transistor pair in each branch is significant enough to generate a disturbance 310, such as a voltage spike, to the output voltage Vout. When the waveform control circuits 110 in the four branches are enabled, the crowbar current Icb decreases, and there may be no disturbance to the output voltage Vout, and Vout may have a relatively smooth waveform.

[0027] Figure 4 is a diagram illustrating an example waveform control circuit that may be used to implement multi-region transmitter output waveform control in one embodiment. Figure 4 The description can be found in Figures 1 to 3 Components shown in . Figure 4 The waveform control circuit 400 is shown in FIG. The waveform control circuit 400 may be Figure 1HS control circuit 112 or LS control circuit 114 shown. In one embodiment, waveform control circuit 400 may include inverters 406, 408, current sources 402, 404, 412, 414, transistors M1, M2, M3, M4, and delay module 420. In one embodiment, pre-driver circuit 422 ("pre-driver 422") may also be part of waveform control circuit 400. Transistors M1, M2, M3, M4 may be MOSFETs. Transistors M1 and M3 may be PMOS devices or P-type MOSFETs, and transistors M2 and M4 may be NMOS devices or N-type MOSFETs. Pre-driver 422 may include a complementary metal-oxide semiconductor (CMOS) inverter 424 ("CMOS 424") configured to select input signal data_in to output signal 410. The current sources 402 , 404 , 412 , 414 and the delay block 420 may be digitally controlled using a current digital-to-analog converter (DAC) that may be located in the waveform control circuit 110 (or 112 , 114 , 400 ).

[0028] If the waveform control circuit 400 is implemented to control the HS transistor, the input signal data_in may be Figure 1 If the waveform control circuit 400 is implemented to control the LS transistor, the input signal data_in may be a driving signal provided by the NAND gate 104 shown. Figure 1 The output signal 410 of the waveform control circuit 400 may be a gate voltage signal (eg, Figure 2 To drive the HS transistor or LS transistor from off to on, data_in may be a low voltage (e.g., a voltage representing a logical low) or 0V, and the output signal 410 may be a high voltage (e.g., a voltage representing a logical high). To drive the HS transistor or LS transistor from on to off, data_in may be a low voltage, and the output signal 410 may be a high voltage.

[0029] In order to operate in the area 201 (see Figure 2 ) control signal 410 slew rate or gate voltage change rate, the waveform control circuit 400 can control one of the current sources 402 and 404 depending on the value of the input signal data_in. If the driven device (e.g., HS transistor or LS transistor) is in the off state, then at the beginning of the operation region 201, such as Figure 2At time t1 shown, the PMOS device ("P") of the CMOS inverter 424 may be turned off, and the NMOS device ("N") of the CMOS inverter 424 may be turned on. In order to output the signal 410 as a high voltage signal to turn on the HS transistor or the LS transistor, data_in may be a low voltage signal or 0V to cause the CMOS inverter 424 to turn on the PMOS device and turn off the NMOS device.

[0030] If data_in is a low voltage or 0V, the inverters 406, 408 may output a high voltage, the transistors M1, M4 may be turned off, and the transistors M2, M3 may be turned on. Figure 2 At t1 shown in FIG. 4 , in response to transistor M2 being turned on and transistor M1 being turned off, waveform control circuit 400 can control current source 404 to draw additional current from the PMOS device, thereby increasing the rising slew rate of signal 410. The duration of operating region 201 can be arbitrary and can be achieved when signal 410 reaches the threshold voltage of the transistor driven by signal 410 (e.g., see Figure 2 The voltage at the input terminal is preferably VthHS and VthLS in the operating region 202 .

[0031] Under the operation region 202, if data_in is a low voltage or 0V, the waveform control circuit 400 can adjust the current source 412 and / or the current source 414 to control the rising slew rate of the pre-driver 422. For example, the waveform control circuit 400 can reduce the amount of current drawn toward ground by the current sources 412, 414 to reduce the rising slew rate of the signal 410. The waveform control circuit 400 can control the rising slew rate of the signal 410 in the operation region 202 to be lower than the rising slew rate of the signal 410 in the operation region 201. Under the operation region 202, the voltage level of the signal 410 can cross the threshold voltage of the transistor driven by the signal 410, such as Figure 2 shown.

[0032] In the operation region 203, in response to transistor M3 being turned on and transistor M4 being turned off, additional current may be provided from transistor M3 to the PMOS device in the CMOS inverter 424 to increase the rising transition rate of the signal 410, thereby completing the transition of the signal 410 from a low voltage to a high voltage. In one embodiment, the delay block 420 may apply a delay to prevent the transistor M3 from being turned on until the beginning of the operation region 203, such as Figure 2Preventing transistor M3 from turning on can maintain the relatively slow rising slew rate of signal 410 in operating region 202. When operating region 202 is completed, the delay applied by delay block 420 also expires, and transistor M3 can be turned on to increase the rising slew rate of signal 410.

[0033] If the driven device (e.g., HS transistor or LS transistor) is in the on state, the PMOS device of the CMOS inverter 424 may be on and the NMOS device of the CMOS inverter 424 may be off at the beginning of the operation region 201. In order to output the signal 410 as a low voltage signal to turn off the HS transistor or the LS transistor, data_in may be a high voltage signal so that the CMOS inverter 424 turns off the PMOS device and turns on the NMOS device.

[0034] If data_in is a high voltage, inverters 406, 408 may output a low voltage, transistors M2, M4 may be turned off, and transistors M1, M4 may be turned on. At the beginning of the operating region 201, in response to transistor M1 being turned on and transistor M2 being turned off, the waveform control circuit 400 may control the current source 402 to push additional current to the PMOS device, thereby increasing the falling slew rate of the signal 410. The duration of the operating region 201 may be arbitrary and may be started when the signal 410 reaches the threshold voltage of the transistor driven by the signal 410 (e.g., see Figure 2 The voltage at the input terminal is preferably VthHS and VthLS in the operating region 202 .

[0035] Under the operation region 202, if data_in is a high voltage, the waveform control circuit 400 may adjust the current source 412 and / or the current source 414 to control the falling slew rate of the pre-driver 422. For example, the waveform control circuit 400 may reduce the amount of current drawn toward ground by the current sources 412, 414 to reduce the falling slew rate of the signal 410. The waveform control circuit 400 may control the falling slew rate of the signal 410 in the operation region 202 to be lower than the falling slew rate of the signal 410 in the operation region 201. Under the operation region 202, the voltage level of the signal 410 may cross the threshold voltage of the transistor driven by the signal 410, such as Figure 2 shown.

[0036] In response to transistor M4 being turned on and transistor M3 being turned off under operation region 203, additional current may be provided from transistor M4 to the NMOS device in CMOS inverter 424 to increase the falling slew rate of signal 410, thereby completing the transition of signal 410 from a high voltage to a low voltage. In one embodiment, delay block 420 may apply a delay to prevent transistor M4 from being turned on until the beginning of operation region 203, such as Figure 2 Preventing transistor M4 from turning on can maintain the relatively slow rising slew rate of signal 410 in operating region 202. When operating region 202 is completed, the delay applied by delay block 420 also expires, and transistor M4 can be turned on to increase the rising slew rate of signal 410.

[0037] In one embodiment, delay block 420 may be set to a delay amount that allows the output critical transition (e.g., transition in operating region 202) region to expire before the start of operating region 203 so that hard switching of CMOS inverter 424 in pre-driver 422 does not affect the critical transition portion of the waveform of signal 410. In one embodiment, the delay applied by delay block 420 may be less than Figure 1 The data interval of the input data 101 is shown to prevent the introduction of jitter.

[0038] In one embodiment, each branch in the device 100 may include two copies of the waveform control circuit 400 to implement the HS control circuit 112 and the LS control circuit 114. The HS control circuit 112 and the LS control circuit 114 may drive VgHS and VgLS symmetrically or asymmetrically in the operating regions 201 and 202. If the HS control circuit 112 and the LS control circuit 114 drive VgHS and VgLS symmetrically, the current sources 402, 404, 412, and 414 in different copies of the waveform control circuit 400 may be controlled with exactly the same amount of current in the operating regions 201 and / or 202. If the HS control circuit 112 and the LS control circuit 114 drive VgHS and VgLS asymmetrically, the current sources 402, 404, 412, and 414 in different copies of the waveform control circuit 400 may be controlled with different amounts of current in the operating regions 201 and / or 202.

[0039] Furthermore, multiple copies of the waveform control circuit 400 may be instantiated in parallel so that multiple branches of the device 100 may be activated to drive respective output driver stages to generate Vout, such as Figure 3As shown. The gate voltage slew rate control of the waveform control circuit 400 can reduce the crowbar current Icb and prevent interference, such as voltage spikes, on the output voltage Vout generated by multiple activated branches. In addition, the pre-driver circuit 422 in different copies of the waveform control circuit 400 can be sized to control any number of activated branches in the device 100.

[0040] Figure 5 is a flow chart of an example process that can implement bevel drive compensation in one embodiment. The apparatus 100 discussed above can be used to implement Figure 5 500. Process 500 may include one or more operations, actions, or functions as shown in one or more of blocks 502, 504, 506, and / or 508. Although shown as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, eliminated, performed in a different order, or performed in parallel, depending on the desired implementation.

[0041] Process 500 may be performed by a driver circuit such as a push-pull driver. Process 500 may begin at block 502, where in a first region of transition from an input signal to an output signal, the driver circuit may control a slew rate of the output signal to a first rate. The first region may terminate before the output signal reaches a predefined threshold voltage. Process 500 may proceed from block 502 to block 504. At block 504, in a second region of transition from an input signal to an output signal, the driver circuit may reduce a slew rate of the output signal to a second rate that is lower than the first rate. The output signal may cross a predefined threshold voltage in the second region. Process 500 may proceed from block 504 to block 506. At block 506, in a third region of transition from an input signal to an output signal, the driver circuit may increase a slew rate of the output signal to a third rate that is greater than the second rate, wherein the transition may be completed in the third region. Process 500 may proceed from block 506 to block 508. At block 508, the driver circuit may use the output signal to drive a transistor in an output driver stage of the driver circuit.

[0042] In one embodiment, in the first region, the driver circuit may control the first current source and the second current source to set the slew rate to the first rate. In the second region, the driver circuit may control the third current source and the fourth current source in the pre-driver circuit of the driver circuit to set the slew rate to the second rate. In one embodiment, in the first region, the driver circuit may apply a delay to start the third region after the second region is completed.

[0043] In one embodiment, in response to the input signal being a low voltage signal, the driver circuit may enable a first transistor to connect a current source to an N-type metal oxide semiconductor (NMOS) device of a complementary metal oxide semiconductor (CMOS) inverter of a pre-driver in the driver circuit. The driver circuit may further control the current source to set the conversion rate to a first rate. The driver circuit may further enable a second transistor of a P-type metal oxide semiconductor (PMOS) device connected to the CMOS inverter to increase the conversion rate from the second rate to the third rate at the beginning of the third region.

[0044] In one embodiment, in response to the input signal being a high voltage signal, the driver circuit may enable a first transistor to connect a current source to a PMOS device of a CMOS inverter of a pre-driver in the driver circuit. The driver circuit may further control the current source to set the slew rate to a first rate. The driver circuit may further enable a second transistor of an NMOS device connected to the CMOS inverter to increase the slew rate from the second rate to a third rate at the beginning of the third region.

[0045] Flowcharts and block diagrams in the accompanying drawings show the architecture, function and operation of the possible implementation of the system, method and computer program product according to various embodiments of the present invention. In this regard, each frame in the flow chart or block diagram can represent a module, a fragment or a part of an instruction, and the instruction includes one or more executable instructions for realizing (multiple) specified logical functions. In some alternative implementations, the function marked in the frame may not occur in the order marked in the figure. For example, two frames shown in succession can actually be implemented substantially at the same time, or these frames can sometimes be implemented in reverse order, depending on the function involved. It will also be noted that each frame of the block diagram and / or flow chart illustration and the combination of the frames in the block diagram and / or flow chart illustration can be implemented by a system based on special-purpose hardware, and the system based on special-purpose hardware performs specified functions or actions or implements the combination of special-purpose hardware and computer instructions.

[0046] The terms used herein are intended only to describe specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms "comprises" and / or "comprising" when used in this specification specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0047] The corresponding structures, materials, actions, and equivalents (if any) of all method or step plus function elements in the claims below are intended to include any structure, material, or action as specifically claimed, in combination with other claimed elements to perform the function. For the purposes of illustration and description, disclosed embodiments of the present invention have been presented, but these embodiments are not intended to be exhaustive or to limit the invention to the disclosed forms. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the present invention. These embodiments are selected and described in order to best explain the principles and practical applications of the present invention, and to enable others of ordinary skill in the art to understand the present invention for various embodiments with various modifications suitable for the intended specific use.

Claims

1. A semiconductor device, comprising: a pre-driver circuit including a complementary metal oxide semiconductor (CMOS) inverter configured to invert an input signal to generate an output signal; The circuit is configured as: controlling a slew rate of the output signal to a first rate in a first region of transition from the input signal to the output signal, wherein the first region terminates before the output signal reaches a predefined threshold voltage; reducing a slew rate of the output signal to a second rate lower than the first rate in a second region of the transition from the input signal to the output signal, wherein the output signal crosses the predefined threshold voltage in the second region; and increasing a slew rate of the output signal to a third rate greater than the second rate in a third region of the transition from the input signal to the output signal, wherein the transition is complete in the third region; as well as The output signal is output to drive a transistor in an output driving stage of a driver circuit.

2. The semiconductor device according to claim 1, wherein the circuit is configured as: In the first region, controlling a first current source and a second current source to set the slew rate to the first rate; and In the second region, a third current source and a fourth current source in the pre-driver circuit are controlled to set the slew rate to the second rate. 3 . The semiconductor device according to claim 2 , wherein the circuit is configured to control the first current source, the second current source, the third current source, and the fourth current source using a digital-to-analog converter (DAC). 4 . The semiconductor device according to claim 1 , wherein the circuit is configured to, in the first region, apply a delay to start the third region after the second region is completed.

5. The semiconductor device according to claim 1 , wherein the circuit is configured to, in response to the input signal being a low voltage signal: enabling a first transistor to connect a current source to an N-type metal oxide semiconductor (NMOS) device of the CMOS inverter; controlling the current source to set the slew rate to the first rate; and A second transistor of a P-type metal oxide semiconductor (PMOS) device connected to the CMOS inverter is enabled to increase the slew rate from the second rate to the third rate at the beginning of the third region.

6. The semiconductor device according to claim 1, wherein the circuit is configured to, in response to the input signal being a high voltage signal: enabling a first transistor to connect a current source to a PMOS device of the CMOS inverter; controlling the current source to set the slew rate to the first rate; and A second transistor of an NMOS device connected to the CMOS inverter is enabled to increase the slew rate from the second rate to the third rate at the beginning of the third region.

7. A device comprising: a controller configured to provide an input signal; an output driver stage including a high-side transistor and a low-side transistor, the output driver stage being configured to drive the high-side transistor and the low-side transistor using a paired drive signal; as well as A circuit is configured to control the slew rate of the paired drive signals, wherein the slew rate is controlled to have different rates in different regions of the transition from the input signal to the paired drive signals, and the crowbar current in the output driver stage depends on the different rates in the different regions of the transition. 8 . The apparatus of claim 7 , wherein the circuit is configured to symmetrically control the slew rates of the pair of drive signals. 9 . The apparatus of claim 7 , wherein the circuit is configured to asymmetrically control the slew rates of the pair of drive signals.

10. The apparatus of claim 7, wherein the circuit is configured to control at least one current source to set the slew rates of the pair of drive signals to the different rates. 11 . The apparatus of claim 10 , wherein the circuit is configured to control the at least one current source using a digital-to-analog converter (DAC).

12. The apparatus of claim 7, wherein the circuit comprises: A first part configured to control a slew rate of a first driving signal of the pair of driving signals for driving the high-side transistor; as well as The second part is configured to control a slew rate of a second driving signal in the pair of driving signals for driving the low-side transistor.

13. The apparatus according to claim 7, wherein in order to control the slew rate of the paired drive signals, the circuit is configured to: increasing the slew rate of the drive signal in a first region of the transition from the input signal to the paired drive signal, wherein the first region is terminated before the drive signal reaches a threshold voltage of the high-side transistor and a threshold voltage of the low-side transistor; reducing the slew rate of the pair of drive signals in a second region of the transition from the input signal to the pair of drive signals, wherein the drive signal crosses a threshold voltage of the high-side transistor and the threshold voltage of the low-side transistor in the second region; and The slew rate of the drive signal is increased in a third region of the transition from the input signal to the pair of drive signals, wherein the transition from the input signal to the pair of drive signals is completed in the third region.

14. The apparatus of claim 13, wherein the circuit is configured to, in the first region of the transition from the input signal to the paired drive signals, apply a delay to start the third region after the second region is completed.

15. The apparatus of claim 7, wherein the controller, the output driver stage, and the circuit are parts of a push-pull driver.

16. A method for operating a driver circuit, the method comprising: controlling a slew rate of the output signal to a first rate in a first region of transition from an input signal to an output signal, wherein the first region terminates before the output signal reaches a predefined threshold voltage; reducing the slew rate of the output signal to a second rate lower than the first rate in a second region of the transition from the input signal to the output signal, wherein the output signal crosses the predefined threshold voltage in the second region; increasing the slew rate of the output signal to a third rate greater than the second rate in a third region of the transition from the input signal to the output signal, wherein the transition is complete in the third region; as well as The output signal is used to drive a transistor in an output driver stage of a driver circuit.

17. The method according to claim 16, further comprising: In the first region, controlling a first current source and a second current source to set the slew rate to the first rate; as well as In the second region, a third current source and a fourth current source in a pre-driver circuit of the driver circuit are controlled to set the slew rate to the second rate.

18. The method according to claim 16, further comprising: In the first zone, a delay is applied to start the third zone after the second zone is completed.

19. The method of claim 16, further comprising, in response to the input signal being a low voltage signal: enabling a first transistor to connect a current source to an N-type metal oxide semiconductor (NMOS) device of a complementary metal oxide semiconductor (CMOS) inverter of a pre-driver in the driver circuit; controlling the current source to set the conversion rate to the first rate; as well as A second transistor of a P-type metal oxide semiconductor (PMOS) device connected to the CMOS inverter is enabled to increase the slew rate from the second rate to a third rate at the beginning of the third region.

20. The method of claim 16, further comprising, in response to the input signal being a high voltage signal: enabling a first transistor to connect a current source to a PMOS device of a CMOS inverter of a pre-driver in the driver circuit; controlling the current source to set the slew rate to the first rate; and A second transistor of an NMOS device connected to the CMOS inverter is enabled to increase the slew rate from the second rate to a third rate at the beginning of the third region.

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