Reference voltage buffer circuit of high-precision analog-to-digital converter and calibration method thereof

Abstract

This invention provides a reference voltage buffer circuit and calibration method for a high-precision analog-to-digital converter (ADC). The circuit includes a first operational amplifier whose inverting input is connected to a reference voltage, and whose output is fed back to the non-inverting input via a first driving transistor and a voltage divider circuit. A second operational amplifier's non-inverting input is connected to a first voltage divider node, its inverting input is connected to a second voltage divider node, and its output is connected to the gates of several third driving transistors and a second driving transistor. The drains of the third driving transistors are all connected to the first voltage divider node via switches. The width-to-length ratios of the second driving transistors and the several third driving transistors are linearly related. The switches are all input with logic control signals to control their states for linear calibration of the reference voltage. This invention uses binary encoding to control the switch states for linear calibration of the output reference voltage and significantly reduces the total resistance by designing a linear relationship between the resistors, thus reducing chip area and cost.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and specifically to a reference voltage buffer circuit for a high-precision analog-to-digital converter and its calibration method. Background Technology

[0002] In high-precision signal chain conversion, it is usually necessary to first determine the reference voltage of the data converter to establish the correspondence between digital code values ​​and physical quantities in the real environment. Especially in the field of high-precision measurement, an accurate and stable reference voltage is a prerequisite for obtaining accurate analog signals during high-precision analog-to-digital conversion. In an analog-to-digital converter (ADC), to obtain a large ADC input range and meet the requirements of fast signal setup and conversion, the reference voltage usually needs to be followed by a buffer to amplify the reference voltage and provide strong driving capability. The voltage output from the buffer becomes the new reference voltage for the ADC, and this output voltage also needs to achieve the accuracy, stability, and other performance indicators of the reference voltage. However, since the performance of the ADC's reference voltage often affects the gain error, noise, and dynamic error during analog-to-digital conversion, and given that signals are very sensitive to changes in gain or noise errors in many signal chain applications, the reference output voltage in the signal chain is usually required to be the most accurate voltage available to the data converter. To meet the above requirements for the reference voltage, it is usually necessary to calibrate the DC error of the buffer output voltage to achieve accurate amplification of the reference voltage. At the same time, it is necessary to eliminate or reduce the influence of non-ideal factors such as mismatch and temperature drift to achieve the performance of the reference voltage. In addition, the cost of the buffer circuit, including mass production testing costs and chip area costs, must also be considered.

[0003] See Figure 1 , Figure 1 This is a traditional buffer circuit for high-precision analog-to-digital converters, comprising an operational amplifier (OPA), a common-source PMOS transistor MP1, and a negative feedback network consisting of a resistor divider. The negative input of the OPA is connected to a reference voltage signal Vbg, which is a low-temperature-drift, high-precision voltage generated by a bandgap reference circuit. The output of the OPA is connected to the gate of the common-source PMOS transistor MP1. The drain of the common-source PMOS transistor is grounded through series resistors R1 and R2, and the voltage divider formed by resistors R1 and R2 is fed back to the positive input of the OPA, forming a negative feedback loop. Based on the virtual short and virtual open characteristics of the operational amplifier and the characteristics of the negative feedback network, the output voltage VREF of this buffer circuit can be obtained as follows:

[0004]

[0005] Among them, resistor R1 is a variable value resistor, and the output voltage VREF can be adjusted by adjusting the value of resistor R1.

[0006] See Figure 2 In high-precision analog-to-digital converter (ADC) applications, a high level of accuracy in the reference voltage is typically required to ensure that the code value of the input signal after analog-to-digital conversion accurately represents the input value. Figure 2 This is a calibration circuit that adjusts the output reference voltage by digitally adjusting the resistance value of resistor R1 based on the above-mentioned buffer circuit. Resistor R1 is composed of resistor R0 and k resistors Rs connected in series, where each resistor Rs is connected in parallel with a complementary metal-oxide-semiconductor (CMOS) switch, controlled by signals T(1) to T(k). Ignoring the impedance of the CMOS switch, the resistance R1 of this calibration circuit can be obtained as follows:

[0007] R1 = R0 + k*R S (2)

[0008] Substituting equation (2) into equation (1), we get:

[0009]

[0010] Linear adjustment of VREF is achieved by adjusting the values ​​of the thermometer codes T(1) to T(k). From equation (3), the accuracy r of the linear adjustment is:

[0011]

[0012] For high-precision reference voltages, the accuracy requirement is less than 0.05%, therefore the adjustment accuracy must be at least 0.025%. For example, assuming the ADC's reference voltage VREF is 3V and the reference voltage Vbg is 1.2V, substituting into equation (4) yields:

[0013]

[0014] Next, substituting equations (1) and (5) into equation (3) yields R0≈2400Rs. To reduce the influence of resistor temperature drift and achieve good matching, R0, R2, and Rs are usually made to have the same root resistance. If Rs is taken as the smallest root resistance, the entire adjustment network needs to be composed of at least 4000 Rs. Since the area of ​​the resistor adjustment network is proportional to the area of ​​Rs, it consumes a large chip area.

[0015] Furthermore, considering that the CMOS switch connected in parallel with Rs in the calibration circuit is not an ideal switch and has an equivalent on-resistance, the actual output voltage of the corrected buffer circuit is:

[0016]

[0017] Where N is the bit width of the thermometer code, k is the code value of the thermometer code, and R SW R is the on-resistance of the switch. SW Its magnitude is a quantity that changes with temperature and voltage.

[0018] It is evident that, due to the substrate bias effect, the equivalent on-resistance of the CMOS switch changes with the source voltage. This results in a non-linear relationship between the actual adjustment value and the resistance Rs, meaning the output voltage VREF of the buffer circuit is non-linearly adjusted. Therefore, according to equation (6), to achieve linear adjustment of the output voltage VREF to simplify the calibration process and time, the equivalent on-resistance R of the CMOS switch needs to be designed. SW The value is much smaller than that of Rs. This requires the CMOS switch to have an extremely large aspect ratio or the resistor Rs to have an extremely large length, thus requiring more chip area and further increasing costs. At the same time, to ensure a small mismatch between Rs, the size of Rs also needs to be increased, further increasing the chip area consumed. In addition, due to the switch's on-resistance R... SW The temperature drift coefficient of the resistor R1 is different from that of the resistor R2, and their ratios cannot cancel each other out, which leads to a worse temperature stability of the output voltage VREF.

[0019] Based on the above, a large deviation will occur if a low-cost two-point calibration method is used. The two-point calibration method is to configure two calibration codes and obtain two measurements of the output buffer voltage in mass production testing. The calibration code value required for the target value can be calculated through linear characteristics. Compared with the binary search method and the traversal method, it can save mass production testing time and reduce costs.

[0020] In summary, the disadvantages of existing technologies are:

[0021] 1. The ratio of non-adjusting resistors R0 and R2 to adjusting resistor Rs is large, which consumes a large chip area and has a high cost.

[0022] 2. The numerically controlled CMOS switch connected in parallel with the trimming resistor Rs in the calibration circuit has an equivalent impedance that changes with the signal, resulting in trimming nonlinearity. This makes it unsuitable for low-cost calibration schemes with two-point calibration.

[0023] 3. Significant mismatch exists among large-scale resistors, necessitating increased resistor size and further increasing costs.

[0024] 4. The control logic for thermometer code adjustment is complex and requires a logic circuit to convert binary code to thermometer code.

[0025] Therefore, there is a need for a reference voltage buffer circuit and its calibration method that can ensure the linearity of the adjustment, reduce the resistive area, be suitable for low-cost two-point calibration requirements, and have a simple logic control circuit. Summary of the Invention

[0026] This invention provides a reference voltage buffer circuit and calibration method for a high-precision analog-to-digital converter. It is mainly used to solve the problems of large area of ​​the resistor adjustment network, nonlinear adjustment, and inability to apply low-cost two-point calibration methods in existing reference voltage buffer circuits. The invention achieves the effects of ensuring adjustment linearity, reducing resistor area, being suitable for low-cost two-point calibration requirements, and having a simple logic control circuit.

[0027] The present invention achieves the above objectives through the following technical solutions:

[0028] A reference voltage buffer circuit for a high-precision analog-to-digital converter includes:

[0029] The first operational amplifier comprises a first driving transistor and a voltage divider circuit. The inverting input of the first operational amplifier is connected to a reference voltage, and its output is connected to the gate of the first driving transistor. The output of the first driving transistor is used to output a reference voltage, which is then divided by the voltage divider circuit and fed back to the non-inverting input of the first operational amplifier by the first voltage divider node.

[0030] It also includes a second-stage negative feedback circuit and a current adjustment circuit. The second-stage negative feedback circuit includes a second operational amplifier and a second driving transistor. The non-inverting input of the second operational amplifier is connected to the first voltage divider node, and its inverting input is connected to the second voltage divider node of the voltage divider circuit. The current adjustment circuit includes several third driving transistors and several switches. The gates of several third driving transistors and the second driving transistors are all connected to the output of the second operational amplifier, and their sources are all grounded. The drain of the second driving transistor is fed back to the non-inverting input of the second operational amplifier, and the drain of each third driving transistor is connected to the first voltage divider node through a switch.

[0031] The width-to-length ratio between the second driving transistor and the plurality of the third driving transistors is linearly related.

[0032] In this embodiment, several of the switches are input with logic control signals, which are used to control the switch states according to the logic control signals to achieve linear calibration of the reference voltage.

[0033] A further option is that the first driving transistor is a PMOS transistor, and the second driving transistor and several of the third driving transistors are all NMOS transistors.

[0034] A further embodiment is that the voltage divider circuit includes a first resistor, a second resistor, and a third resistor connected in series. One end of the first resistor is connected to the output terminal of the first driving transistor, and the connection point between the other end of the first resistor and the second resistor is the first voltage divider node. The connection point between one end of the third resistor and the second resistor is the second voltage divider node, and the other end of the third resistor is grounded.

[0035] A further embodiment is that the second feedback circuit further includes a fourth resistor and a fifth resistor, the non-inverting input of the second operational amplifier is connected to the first voltage divider node through the fourth resistor, and its inverting input is connected to the second voltage divider node through the fifth resistor.

[0036] A further approach is to increase the size of several of the third driving transistors proportionally according to a coefficient, and then connect them sequentially to the first voltage divider node through the switches connected in series with them to form a parallel network.

[0037] The proportional coefficient is determined based on the target adjustment range.

[0038] A further approach is to assume that the aspect ratio of the second driving transistor is m times the aspect ratio of the smallest third driving transistor in the parallel network, then the current adjustment accuracy r is:

[0039]

[0040] Among them, V bg V is the reference voltage. ref The reference voltage is defined as R1 to R4, which are the resistance values ​​of the first to fourth resistors, respectively.

[0041] A further approach is that the logic control signal uses binary encoding, and the reference voltage is:

[0042]

[0043] Where k is the code value of the binary encoding.

[0044] A further approach is to determine the resistance values ​​of the first, second, third, fourth, and fifth resistors based on the same root resistor using different proportional coefficients.

[0045] A further approach is to use the second resistor as the root resistor, determine the resistance values ​​of the first and third resistors according to the adjustment range, determine the resistance value of the fourth resistor according to the optimal number of resistors in the circuit, and determine the resistance value of the fifth resistor according to the impedance matching rate of the second feedback circuit.

[0046] A calibration method for a reference voltage buffer circuit of a high-precision analog-to-digital converter, applied to the reference voltage buffer circuit of the high-precision analog-to-digital converter, includes:

[0047] S1: Determine the adjustment accuracy based on the accuracy of the target reference voltage, and obtain the circuit relationship regarding the adjustment accuracy.

[0048] S2: Input the width-to-length ratio of the second and third driving transistors, the reference voltage, the reference voltage, and the adjustment accuracy value into the circuit formula to obtain the resistance relationship between the first and fourth resistors.

[0049] S3: Select the root resistor, and determine the resistance values ​​of the first to fourth resistors and the number of third driving transistors in the current adjustment circuit based on the target adjustment range, the root resistor, and the resistance relationship.

[0050] S4: A two-point calibration method is used to configure the binary code, and the corresponding switching action is controlled according to the binary code, thereby linearly calibrating the reference voltage output by the first driving transistor.

[0051] Therefore, the present invention has the following beneficial effects:

[0052] 1. This invention controls the switch state through binary encoding, thereby controlling the proportional change of the current flowing from the driving transistor MP0 through the resistor R1, so that the voltage change across the first resistor changes linearly with the switch S1 to Sj signals, thereby achieving linear calibration of the output reference voltage; and by designing the linear relationship of the resistors in the second negative feedback circuit and the voltage divider circuit, this invention greatly reduces the total resistance compared with traditional circuits while achieving the same adjustment accuracy requirements, thus achieving the effect of significantly reducing chip area and reducing cost while ensuring the linearity of adjustment.

[0053] 2. In this invention, each resistor can be determined by taking the same root resistor, so that the resistance value deviation caused by temperature and process angle deviation can be canceled out, so that the reference voltage and the reference voltage can achieve the same level of accuracy and stability.

[0054] 3. The present invention determines the resistance value of the fifth resistor based on the resistance value of the fourth resistor and the impedance matching rate of the second feedback circuit, avoiding the need to increase the resistor size due to large mismatches between large proportion resistors, further reducing the total resistance, thereby further reducing the chip area and lowering the cost.

[0055] 4. The resistance value of the present invention can be flexibly selected according to the adjustment range, and the number of current mirrors in the current adjustment network can also be flexibly selected according to the adjustment range, which improves the flexibility and applicability of the circuit.

[0056] 5. The present invention greatly simplifies the control circuit by using binary encoding for logic control. The control logic is simple and the area of ​​the control circuit is much smaller than that of a thermometer encoding circuit with the same bit width, which further reduces the chip area and lowers the cost.

[0057] 6. The linearity of the reference voltage adjustment in this invention is determined by the linearity of the current mirror formed by the second driving transistor MN0 and the driving transistors MN1 to MNj. High linearity can be achieved using conventional layout matching methods to meet the low-cost two-point calibration requirements in chip mass production. Compared with the traditional binary search method and traversal method, it can save mass production testing time and reduce costs.

[0058] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0059] Figure 1 This is a circuit diagram of a reference voltage buffer circuit in the prior art.

[0060] Figure 2 This is a calibration diagram of the existing technology reference voltage.

[0061] Figure 3 This is a circuit diagram of the reference voltage buffer circuit of the present invention.

[0062] Figure 4 This is a flowchart of the calibration method for the reference voltage buffer circuit of the present invention. Detailed Implementation

[0063] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0064] An embodiment of a reference voltage buffer circuit and calibration method for a high-precision analog-to-digital converter.

[0065] See Figure 3 The present invention relates to a reference voltage buffer circuit for a high-precision analog-to-digital converter, comprising a first operational amplifier 101, a first driving transistor MP0, and a voltage divider circuit. The inverting input terminal of the first operational amplifier 101 is connected to a reference voltage Vbg, and its output terminal is connected to the gate of the first driving transistor MP0. The output terminal of the first driving transistor MP0 is used to output a reference voltage Vref, which is divided by the voltage divider circuit and fed back to the non-inverting input terminal of the first operational amplifier 101 by the first voltage divider node.

[0066] It also includes a second-stage negative feedback circuit S02 and a current adjustment circuit. The second-stage negative feedback circuit S02 includes a second operational amplifier 102 and a second driving transistor MN0. The non-inverting input terminal of the second operational amplifier 102 is connected to the first voltage divider node, and its inverting input terminal is connected to the second voltage divider node of the voltage divider circuit. The current adjustment circuit includes a plurality of third driving transistors MN1 to MNj and a plurality of switches S1 to Sj. The gates of the plurality of third driving transistors MN1 to MNj and the second driving transistor MN0 are all connected to the output terminal of the second operational amplifier 102, and their sources are all grounded. The drain of the second driving transistor MN0 is fed back to the non-inverting input terminal of the second operational amplifier 102, and the drain of each of the third driving transistors is connected to the first voltage divider node through a switch.

[0067] Among them, the width-to-length ratio between the second driving transistor MN0 and several third driving transistors MN1 to MNj is linearly related.

[0068] Among them, several switches S1 to Sj are all input with logic control signals, which are used to control the switch state according to the logic control signals to achieve linear calibration of the reference voltage.

[0069] Specifically, this embodiment employs a two-stage negative feedback circuit. The first-stage negative feedback circuit S01 consists of a first operational amplifier 101, a first driving transistor MP0, and a voltage divider circuit. The first driving transistor MP0 outputs a reference voltage Vref through its drain and provides strong driving capability. The second-stage negative feedback circuit S02 consists of a second operational amplifier 102, a second driving transistor MN0, a fourth resistor R4, and a fifth resistor R5. Introducing negative feedback improves the nonlinear distortion of the amplifier circuit, enhances linearity, and effectively reduces fluctuations in the output voltage signal, making the circuit more stable and reliable. Simultaneously, it suppresses internal noise and interference, further improving the signal-to-noise ratio and clarity.

[0070] In this embodiment, the first driving transistor MP0 is a PMOS transistor, and the second driving transistor MN0 and several third driving transistors MN1 to MNj are all NMOS transistors.

[0071] In this embodiment, the voltage divider circuit includes a first resistor R1, a second resistor R2, and a third resistor R3 connected in series. One end of the first resistor R1 is connected to the output terminal of the first driving transistor MP0, and the connection point between the other end of the first resistor R1 and the second resistor R2 is the first voltage divider node. The connection point between one end of the third resistor R3 and the second resistor R2 is the second voltage divider node, and the other end of the third resistor R3 is grounded.

[0072] In this embodiment, the second feedback circuit further includes a fourth resistor R4 and a fifth resistor R5. The non-inverting input terminal of the second operational amplifier 102 is connected to the first voltage divider node through the fourth resistor R4, and its inverting input terminal is connected to the second voltage divider node through the fifth resistor R5.

[0073] In this embodiment, the dimensions of several third driving transistors MN1 to MNj are increased proportionally according to a proportional coefficient, and they are sequentially connected to the first voltage divider node through the switches connected in series with them to form a parallel network.

[0074] The proportional coefficient is determined based on the target adjustment range.

[0075] Specifically, in this embodiment, the current adjustment circuit is set as a current adjustment network S03 consisting of j driving transistors MN1 to MNj and j switches S1 to Sj. The driving transistors MN1 to MNj form a current mirror relationship with the second driving transistor MN0. The scaling factor is 2, and the driving transistors MN1 to MNj are proportionally amplified by a factor of 2. The number of bits in the binary code, from low to high, corresponds to the switches S1 to Sj.

[0076] Taking j=3 as an example, the control logic is explained as shown in the table below, where I trim This is the minimum adjustment current.

[0077] Table 1 Control Logic Table for Linear Tuning Implemented by Binary Encoding (Table 1)

[0078] S3 S2 S1 Total adjustment current flowing through R1 0 0 0 <![CDATA[0*I trim ]]> 0 0 1 <![CDATA[1*I trim ]]> 0 1 0 <![CDATA[2*I trim ]]> 0 1 1 <![CDATA[3*I trim ]]> 1 0 0 <![CDATA[4*I trim ]]> 1 0 1 <![CDATA[5*I trim ]]> 1 1 0 <![CDATA[6*I trim ]]> 1 1 1 <![CDATA[7*I trim ]]>

[0079] As shown in Table 1, by controlling the switching states of switches S1 to S3 through binary encoding, the current flowing through the first resistor R1 from the first driving transistor MP0 can be controlled to change proportionally, thereby making the voltage change across the first resistor R1 change linearly with the switching states of switches S1 to S3, achieving linear calibration of the output reference voltage Vref.

[0080] Specifically, in this embodiment, the aspect ratio of the second driving transistor MN0 is set to be m times the aspect ratio of the third driving transistor, which has the smallest size in the parallel network. trim It is equal to 1 / m times the drain current flowing through the second driving transistor MN0. According to the virtual short and virtual open characteristics of the op-amp and Kirchhoff's laws of the circuit, the drain current I of the second driving transistor MN0 can be obtained. MN0 for:

[0081]

[0082] Among them, V bg The reference voltage is R2, and R4 are the resistance values ​​of the second resistor R2 to the fourth resistor R4, respectively.

[0083] From Equation 1-1, the minimum adjustment current I of the current adjustment network S03 can be obtained. trim for:

[0084]

[0085] In this embodiment, if the aspect ratio of the second driving transistor MN0 is m times the aspect ratio of the third driving transistor, which has the smallest size in the parallel network, then the current adjustment accuracy r is:

[0086]

[0087] Among them, V bg V is the reference voltage. ref As the reference voltage, R1 to R4 are the resistance values ​​of the first resistor R1 to the fourth resistor R4, respectively.

[0088] Specifically, in this embodiment, since the adjustment range of the general reference voltage Vref is very small, the reference voltage Vref can be obtained as follows:

[0089]

[0090] Specifically, in this embodiment, V is taken as V bg =1.2V, V ref Taking 3V as an example, substituting into equation 1-4, we get:

[0091]

[0092] Substituting equation 1-5 into equation 1-3, we obtain the current adjustment accuracy r as:

[0093]

[0094] The reference voltage accuracy requirement for a high-precision digital-to-analog converter is less than 0.05%, therefore the adjustment accuracy must be at least 0.025%. Substituting r = 0.025% into equation 1-6 yields:

[0095]

[0096]

[0097] Substituting m = 32 into equation 1-7, we get R4 = 75 * R2. Using R2 as the root resistor, we select R1, R3, and R4. For impedance matching of the second operational amplifier 102, we choose R5 = R4.

[0098] Specifically, as can be seen from Equations 1-7 in this embodiment, the total resistance required to achieve the same adjustment accuracy is greatly reduced compared to traditional circuits. This achieves a significant reduction in chip area and lower cost while ensuring the linearity of the adjustment. In addition, the values ​​of R1 and r3 can be flexibly selected according to the adjustment range, and the number of current mirrors in the current adjustment network S03 can also be flexibly selected according to the adjustment range, improving the flexibility and applicability of the circuit. The logic control through binary encoding greatly simplifies the control circuit. The control logic is simple and the area of ​​the control circuit is much smaller than that of a thermometer encoding circuit with the same bit width, further reducing the chip area and lowering the cost.

[0099] Specifically, as shown in Table 1 of this embodiment, the circuit connection size of the driving transistors controlled by S1 to Sj can be scaled up proportionally according to the binary code. The reference voltage Vref output is controlled by the binary code with a code value of k:

[0100]

[0101] The above equation can be simplified to:

[0102]

[0103] In this embodiment, the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, and the fifth resistor R5 are determined according to different proportional coefficients based on the same root resistor.

[0104] In this embodiment, the second resistor R2 is used as the root resistor, the resistance values ​​of the first resistor R1 and the third resistor R3 are determined according to the adjustment range, the resistance value of the fourth resistor R4 is determined according to the optimal number of resistors in the circuit, and the resistance value of the fifth resistor R5 is determined according to the impedance matching rate in the second feedback circuit.

[0105] As shown in Equations 1-8, the reference voltage Vref is linearly proportional to the base voltage Vbg and is related to the ratio of each resistor, but not significantly to the absolute value of the resistors. Therefore, by using the same root resistor for each resistor, the resistance value deviations caused by temperature and process angle variations can be mutually canceled, achieving the same level of accuracy and stability between the reference voltage Vref and the base voltage Vbg. Furthermore, the linearity of the reference voltage Vref adjustment is determined by the linearity of the current mirror formed by the second driving transistor MN0 and driving transistors MN1 to MNj. High linearity can be achieved using conventional layout matching methods to meet the low-cost two-point calibration requirements in chip mass production.

[0106] An embodiment of a calibration method for a reference voltage buffer circuit of a high-precision analog-to-digital converter.

[0107] See Figure 4The present invention relates to a calibration method for a reference voltage buffer circuit of a high-precision analog-to-digital converter, which is applied to the reference voltage buffer circuit of the high-precision analog-to-digital converter and includes:

[0108] S1: Determine the adjustment accuracy based on the accuracy of the target reference voltage, and obtain the circuit relationship regarding the adjustment accuracy.

[0109] S2: Input the width-to-length ratio of the second driving transistor MN0 and the third driving transistor, the reference voltage Vbg, the reference voltage Vref, and the adjustment accuracy value into the circuit formula to obtain the resistance relationship between the first resistor R1 to the fourth resistor R4.

[0110] S3: Select the root resistor, and determine the resistance values ​​of the first resistor R1 to the fourth resistor R4 and the number of the third driving transistors in the current adjustment circuit according to the target adjustment range, the root resistor and the resistance relationship.

[0111] S4: The binary code is configured using a two-point calibration method, and the corresponding switching action is controlled according to the binary code, thereby linearly calibrating the reference voltage Vref output by the first driving transistor MP0.

[0112] Specifically, step S3 in this embodiment also includes:

[0113] S31: Determine the value of the fifth resistor R5 based on the value of the fourth resistor R4 and the impedance matching rate of the second feedback circuit.

[0114] Specifically, the two-point calibration method in step S4 of this embodiment further includes:

[0115] S41: Configure the binary code twice, and control the corresponding switching action according to the two binary codes respectively to obtain two measured values ​​of the reference voltage Vref;

[0116] S42: Calculate the target code value of binary code required to reach the target reference voltage based on the linearity of the two measurements above;

[0117] S43: Reconfigure the binary encoding according to the target code value.

[0118] The above embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention shall fall within the scope of protection claimed by the present invention.

Claims

1. A reference voltage buffer circuit for a high-precision analog-to-digital converter, comprising a first operational amplifier, a first driving transistor, and a voltage divider circuit, wherein the inverting input terminal of the first operational amplifier is connected to a reference voltage, its output terminal is connected to the gate of the first driving transistor, the output terminal of the first driving transistor is used to output a reference voltage, and after being divided by the voltage divider circuit, it is fed back to the non-inverting input terminal of the first operational amplifier by a first voltage divider node, characterized in that, Also includes: The second-stage negative feedback circuit and the current adjustment circuit are as follows: The second-stage negative feedback circuit includes a second operational amplifier and a second driving transistor. The non-inverting input of the second operational amplifier is connected to the first voltage divider node, and its inverting input is connected to the second voltage divider node of the voltage divider circuit. The current adjustment circuit includes several third driving transistors and several switches. The gates of several third driving transistors and the second driving transistors are all connected to the output of the second operational amplifier, and their sources are all grounded. The drain of the second driving transistor is fed back to the non-inverting input of the second operational amplifier, and the drain of each third driving transistor is connected to the first voltage divider node through a switch. The width-to-length ratio between the second driving transistor and the plurality of the third driving transistors is linearly related. In this embodiment, several of the switches are input with logic control signals, which are used to control the switch states according to the logic control signals to achieve linear calibration of the reference voltage.

2. The reference voltage buffer circuit for the high-precision analog-to-digital converter according to claim 1, characterized in that: The first driving transistor is a PMOS transistor, and the second driving transistor and several of the third driving transistors are all NMOS transistors.

3. The reference voltage buffer circuit for the high-precision analog-to-digital converter according to claim 1, characterized in that: The voltage divider circuit includes a first resistor, a second resistor, and a third resistor connected in series. One end of the first resistor is connected to the output terminal of the first driving transistor, and the connection point between the other end of the first resistor and the second resistor is the first voltage divider node. The connection point between one end of the third resistor and the second resistor is the second voltage divider node, and the other end of the third resistor is grounded.

4. The reference voltage buffer circuit for the high-precision analog-to-digital converter according to claim 3, characterized in that: The second-stage negative feedback circuit also includes a fourth resistor and a fifth resistor. The non-inverting input of the second operational amplifier is connected to the first voltage divider node through the fourth resistor, and its inverting input is connected to the second voltage divider node through the fifth resistor.

5. The reference voltage buffer circuit for the high-precision analog-to-digital converter according to claim 4, characterized in that: The dimensions of several third driving transistors are increased proportionally according to a proportional coefficient, and they are sequentially connected to the first voltage divider node through the switches connected in series with them to form a parallel network; The proportional coefficient is determined based on the target adjustment range.

6. The reference voltage buffer circuit for the high-precision analog-to-digital converter according to claim 5, characterized in that: Assume the aspect ratio of the second driving transistor is the same as the aspect ratio of the third driving transistor, which has the smallest size in the parallel network. If the current adjustment accuracy is increased by a factor of 1, then the current adjustment accuracy will be higher. for: in, The reference voltage is... The reference voltage, These are the resistance values ​​of the first to the fourth resistors, respectively.

7. The reference voltage buffer circuit for the high-precision analog-to-digital converter according to claim 6, characterized in that: The logic control signal is encoded in binary, and the reference voltage is: in, The code value is the binary encoding.

8. The reference voltage buffer circuit for a high-precision analog-to-digital converter according to any one of claims 4-7, characterized in that: The resistance values ​​of the first, second, third, fourth, and fifth resistors are determined based on the same root resistor using different proportional coefficients.

9. The reference voltage buffer circuit for a high-precision analog-to-digital converter according to claim 8, characterized in that: Using the second resistor as the root resistor, the resistance values ​​of the first and third resistors are determined according to the adjustment range, the resistance value of the fourth resistor is determined according to the optimal number of resistors in the circuit, and the resistance value of the fifth resistor is determined according to the impedance matching rate of the second-stage negative feedback circuit.

10. A calibration method for a reference voltage buffer circuit of a high-precision analog-to-digital converter, characterized in that, A reference voltage buffer circuit for a high-precision analog-to-digital converter according to any one of claims 1-9, comprising: S1: Determine the adjustment accuracy based on the accuracy of the target reference voltage, and obtain the circuit relationship regarding the adjustment accuracy; S2: Input the width-to-length ratio of the second driving transistor and the third driving transistor, the reference voltage, the reference voltage and the adjustment accuracy value into the circuit formula to obtain the resistance relationship between the first resistor and the fourth resistor; S3: Select the root resistor, and determine the resistance values ​​of the first to fourth resistors and the number of third driving transistors in the current adjustment circuit according to the target adjustment range, the root resistor and the resistance relationship. S4: A two-point calibration method is used to configure the binary code, and the corresponding switching action is controlled according to the binary code, thereby linearly calibrating the reference voltage output by the first driving transistor.

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