Industrial Ethernet data transmission method and system

Abstract

This application discloses a method and system for transmitting industrial Ethernet data, belonging to the field of industrial communication. The method includes: a first element acquiring a first data frame, wherein the first data frame is an Ethernet data frame to be processed; the first element determining information of a data description area in a memory based on the length information of the first data frame; the information of the data description area including the number of data buffer segments occupied by the first data frame in a data buffer area within the memory; the first element storing the first data frame into a first number of data buffer segments in the data buffer area; the first number being equal to the number of data buffer segments occupied by the first data frame; and a second element performing a data read operation from the data buffer area within the memory.

Description

Technical Field

[0001] This application belongs to the field of industrial communication, and specifically relates to a method and system for transmitting industrial Ethernet data. Background Technology

[0002] In the industrial sector, Ethernet has been widely adopted due to its versatility, high efficiency, security, and long transmission distance. To ensure the reliability of Ethernet data, redundant communication methods are commonly used, which also increases the demand for the number of network interfaces. Therefore, Field Programmable Gate Arrays (FPGAs) are typically used to expand network interfaces, and data transmission between the FPGA and the processor enables the transmission of data across multiple Ethernet interfaces.

[0003] When implementing data frame transmission between FPGA and processor, related technologies typically dynamically allocate a corresponding length of storage space based on the length of the data frame. However, since the length of the data frame is variable, storage space is easily wasted, resulting in low utilization of storage space. Summary of the Invention

[0004] This application provides a method and system for transmitting industrial Ethernet data, which can solve the problem of low storage space utilization in related technologies.

[0005] In a first aspect, embodiments of this application provide a method for transmitting industrial Ethernet data, including:

[0006] The first element acquires a first data frame, which is an Ethernet data frame to be processed.

[0007] The first element determines the information of the data description area in the memory based on the length information of the first data frame; the information of the data description area includes the number of data buffer segments occupied by the first data frame in the data buffer area in the memory;

[0008] The first element stores the first data frame into a first number of data buffer segments in the data buffer area; the first number is equal to the number of data buffer segments occupied by the first data frame;

[0009] The second element performs a data read operation from the data buffer within the memory;

[0010] The data description area contains multiple data description segments, and the data cache area contains multiple data cache segments. The number of the multiple data description segments is the same as the number of the multiple data cache segments. Each of the multiple data description segments corresponds to a data cache segment and contains storage description information associated with the data cache segment.

[0011] Secondly, embodiments of this application also provide an industrial Ethernet data transmission system, comprising: a first element and a second element;

[0012] The first element is used to acquire a first data frame, which is an Ethernet data frame to be processed; based on the length information of the first data frame, determine the information of the data description area in the memory; the information of the data description area includes the number of data buffer segments occupied by the first data frame in the data buffer area in the memory; store the first data frame in a first number of data buffer segments in the data buffer area; the first number is equal to the number of data buffer segments occupied by the first data frame;

[0013] The second element is used to perform a data read operation from the data buffer within the memory;

[0014] The data description area contains multiple data description segments, and the data cache area contains multiple data cache segments. The number of the multiple data description segments is the same as the number of the multiple data cache segments. Each of the multiple data description segments corresponds to a data cache segment and contains storage description information associated with the data cache segment. The first element is one of the CPU and the FPGA, and the second element is the other of the CPU and the FPGA.

[0015] The at least one technical solution provided in the embodiments of this application can achieve the following technical effects:

[0016] In this embodiment, a first element acquires a first data frame, which is an Ethernet data frame to be processed; the first element determines information about a data description area in a memory based on the length information of the first data frame; the information about the data description area includes the number of data buffer segments occupied by the first data frame in the data buffer area of ​​the memory; the first element stores the first data frame into a first number of data buffer segments in the data buffer area; the first number is equal to the number of data buffer segments occupied by the first data frame; a second element performs a data read operation from the data buffer area in the memory; wherein, the data description area includes multiple data description segments, the data buffer area includes multiple data buffer segments, and the number of the multiple data description segments is the same as the number of the multiple data buffer segments; each of the multiple data description segments corresponds to a data buffer segment and includes storage description information associated with the data buffer segment. Thus, the data buffer area in the memory contains multiple data buffer segments. For the first data frame to be processed obtained by the first element, the first number of data buffer segments occupied by the first data frame is determined based on the length information of the first data frame. Based on the first number of data buffer segments occupied by the first data frame, the first data frame is stored in the first number of data buffer segments in the data buffer area of ​​the memory. This method makes full use of the storage space of the memory and solves the problem of low utilization of storage space in related technologies. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating an industrial Ethernet data transmission method provided in an embodiment of this application;

[0019] Figure 2 This is a schematic diagram illustrating the storage information of a memory provided in an embodiment of this application;

[0020] Figure 3 This is a general conceptual diagram of an industrial Ethernet data transmission method provided in an embodiment of this application;

[0021] Figure 4 This is a flowchart of another industrial Ethernet data transmission method provided in the embodiments of this application;

[0022] Figure 5This is a flowchart of another industrial Ethernet data transmission method provided in the embodiments of this application;

[0023] Figure 6 This is a flowchart illustrating a specific method for transmitting industrial Ethernet data according to an embodiment of this application.

[0024] Figure 7 This is a structural block diagram of an industrial Ethernet data transmission system provided in an embodiment of this application. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0027] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0028] The industrial Ethernet data transmission method provided in this application embodiment is applied to data transmission, and in particular, it can be applied to data transmission between the processor and the physical layer chip interface in an Ethernet scenario.

[0029] The industrial Ethernet data transmission method provided in this application embodiment can be executed by a target device including a first element and a second element, wherein the first element is one of a CPU and an FPGA, and the second element is the other of the CPU and the FPGA. The target device can be an electronic device. Specifically, it can be executed by software or hardware installed on the electronic device. The electronic device can be, for example, a terminal device such as a desktop computer, mobile phone, laptop computer, or tablet computer, or a server.

[0030] The embodiments of this application can use various processors, including but not limited to domestically developed processors, such as the Loongson 2K1000 series processors, which are usually used as the core processors for business processing.

[0031] The method for transmitting industrial Ethernet data provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0032] Please see Figure 1 , Figure 1 This is a flowchart illustrating an industrial Ethernet data transmission method provided in an embodiment of this application. Figure 1 As shown, the method includes the following steps:

[0033] Step 110: The first element acquires the first data frame, which is an Ethernet data frame to be processed.

[0034] In this embodiment of the application, the first data frame may be an Ethernet data frame to be sent from the first element to the second element.

[0035] Step 120: The first element determines the information of the data description area in the memory based on the length information of the first data frame; the information of the data description area includes the number of data buffer segments occupied by the first data frame in the data buffer area of ​​the memory.

[0036] In this embodiment, after obtaining the length information of the first data frame, the first element can determine the number of data buffer segments occupied by the first data frame based on the length information of the first data frame and the segment length of the data buffer segment. Specifically, the segment length of the data buffer segment can be preset. When the length of the first data frame is less than or equal to the segment length of the data buffer segment, the number of data buffer segments occupied by the first data frame is 1, and the first data frame is not segmented. When the length of the first data frame is greater than the segment length of the data buffer segment, the first data frame is segmented according to the segment length of the data buffer segment, and the number of data buffer segments occupied by the first data frame is greater than 1.

[0037] For example, the data buffer segment length can be preset to 256 bytes. For an Ethernet data frame (excluding jumbo frames), the minimum length of the Ethernet data frame is 64 bytes, and the maximum length is 1518 bytes. If the length of the first data frame is 64 bytes, then the length of the first data frame is less than the length of the data buffer segment, and the number of data buffer segments occupied by the first data frame is 1. That is, the first data frame can be stored using one data buffer segment. If the first data frame is 1518 bytes, then the length of the first data frame is greater than the length of 5 data buffer segments and less than the length of 6 data buffer segments, and it can be determined that the number of data buffer segments occupied by the first data frame is 6. That is, the first data frame can be stored using 6 data buffer segments.

[0038] After determining the number of data buffer segments occupied by the first data frame in the data buffer area within the memory, the number of data buffer segments occupied by the first data frame can be stored as information in the data description area within the memory.

[0039] Step 130: The first element stores the first data frame into a first number of data buffer segments in the data buffer area; the first number is equal to the number of data buffer segments occupied by the first data frame.

[0040] In this embodiment, after determining the first number of first data frames, i.e., after determining the number of data buffer segments occupied by the first data frames, it can be determined whether there are a first number of free data buffer segments in the data buffer area. If there are a first number of free data buffer segments in the data buffer area, the first element can store the first data frame into the first number of free data buffer segments in the data buffer area. If there are no first number of free data buffer segments in the data buffer area, a signal indicating insufficient buffering in the data buffer area can be returned, and the process can wait until there are a first number of free data buffer segments in the data buffer area before storing the first data frame into the first number of free data buffer segments in the data buffer area.

[0041] Step 140: The second element performs a data read operation from the data cache area in the memory; wherein, the data description area contains a plurality of data description segments, the data cache area contains a plurality of data cache segments, the number of the plurality of data description segments is the same as the number of the plurality of data cache segments; each of the plurality of data description segments corresponds to a data cache segment and contains storage description information associated with the data cache segment.

[0042] Each of the plurality of data cache segments corresponds to a data description segment. That is, there is a one-to-one correspondence between the plurality of data description segments and the plurality of data cache segments. Furthermore, each of the plurality of data description segments corresponds to a storage description information, which describes the storage conditions within the data cache segment corresponding to that data description segment.

[0043] In this embodiment, the second element can determine the storage status of the data cache area of ​​the memory based on the storage description information stored in the data description area of ​​the memory, and then determine whether there is a data frame to be read in the data cache area of ​​the memory. If the second element determines that there is a data frame to be read in the data cache area of ​​the memory, it can perform a data read operation from the data cache area. Specifically, the second element can read the storage description information stored in the data description area sequentially, that is, starting from the first data description segment, traversing the entire data description area, and performing a read operation on the data cache segment when the currently read data description segment indicates that the corresponding data cache segment is to be read.

[0044] In one embodiment of this application, each of the plurality of data description segments includes: a first part, a second part, a third part, and a fourth part; the first part indicates whether the data description segment and the corresponding data buffer segment are valid; the second part indicates the number of data buffer segments occupied by the first data frame; the third part indicates the number of data buffer segments occupied by the first data frame; and the fourth part indicates the valid data length of the data buffer segment corresponding to the data description segment.

[0045] For reference Figure 2 , Figure 2 This is a schematic diagram illustrating the storage information of a memory provided in an embodiment of this application. For example... Figure 2 As shown, label ① (i.e., the ID field) represents the sequence number of the n data description segments, label ⑧ (i.e., the Data field) represents the sequence number of the n data cache segments, and there is a one-to-one correspondence between the n data description segments and the n data cache segments. Label ④ (i.e., the Flag field) indicates the first part within a data description segment, label ⑤ (i.e., the Size field) indicates the second part within a data description segment, label ⑥ (i.e., the No. field) indicates the third part within a data description segment, and label ⑦ (i.e., the Len field) indicates the fourth part within a data description segment.

[0046] Specifically, the four parts of the data description segment can be allocated according to the preset segment length. For example, such as... Figure 2As shown, the data description segment can be 2 bytes long, divided into 16 bits (0~15 bits). Bit 15 stores the first part of the data description segment (1 bit), indicating whether the data description segment and its corresponding data buffer segment are valid. When the first part of the data description segment is 1, it indicates that the corresponding data buffer segment is valid, meaning it stores data. When the first part of the data description segment is 0, it indicates that the corresponding data buffer segment is invalid, meaning it does not store data. Bits 14~12 store the second part of the data description segment (3 bits), indicating the number of data buffer segments occupied by the first data frame. Bits 11~9 store the third part of the data description segment (3 bits), indicating the number of data buffer segments occupied by the first data frame. Bits 8~0 store the fourth part of the data description segment (9 bits), indicating the valid data length of the data buffer segment corresponding to the data description segment.

[0047] For example, if the length of the first data frame is 544 bytes and the preset data buffer segment length is 256 bytes, the first number of data buffer segments occupied by the first data frame can be calculated by dividing the length of the first data frame (544 bytes) by the length of the data buffer segment (256 bytes). This first number is determined to be 3, and the effective lengths of the three occupied data buffer segments are determined to be 256 bytes, 256 bytes, and 32 bytes, respectively. At this point, the specific information of the four parts of the three data description segments corresponding to the three data buffer segments can be determined and stored in the corresponding positions of the three data description segments in the data description area.

[0048] The three data buffer segments occupied by the first data frame can be numbered 1, 2 and 3 respectively. The first part of each of the three data description segments is 1 (indicating that the three data buffer segments corresponding to the three data description segments are stored), the second part is 3 (the number of data buffer segments occupied by the first data frame), the third part is 1, 2 and 3 respectively (the number of data buffer segments occupied by the first data frame), and the fourth part is 256, 256 and 32 respectively (the effective data length of the data buffer segment corresponding to the data description segment).

[0049] It is important to note that Figure 2 The allocation method used in this example is only for illustration; the length and order of each part can be flexibly set.

[0050] In one embodiment of this application, each of the plurality of data cache segments has the same length, and the first number of data cache segments in the data cache area are a first number of consecutive data cache segments in the data cache area, wherein the first number is an integer greater than 1.

[0051] In the embodiments of this application, such as Figure 2 As shown, the n data cache segments within the data cache area are aligned, meaning that each data cache segment has the same length. For example, the length of a data cache segment can be preset to 256 bytes, and the length of each of the multiple data cache segments is 256 bytes. In this case, the n data cache segments within the data cache area are aligned with each other by 256 bytes.

[0052] Simultaneously, during the process of storing the first data frame into the data buffer, the first data frame can be stored in a first number of consecutive data buffer segments within the data buffer. For example, if the first data frame occupies 3 data buffer segments, it can be stored in data buffer segments numbered 1, 2, and 3 within the data buffer.

[0053] In this embodiment, by storing the first data frame in a first number of consecutive data buffer segments in the data buffer area, it is convenient for the second element to read the first data frame. The second element can read the first data frame sequentially from the starting data buffer segment within the data buffer area occupied by the first data frame. In this way, for a complete frame of network data, both the continuity of data in memory and the segmentation of data ensure address alignment by transmitting each segment sequentially, avoiding memory alignment operations during data transmission.

[0054] In one embodiment of this application, the first element is one of a CPU and an FPGA, and the second element is the other of the CPU and the FPGA; when the first element is a CPU and the second element is an FPGA, the Ethernet data frame to be processed is an Ethernet data frame to be sent by the CPU; the data description area includes a transmit data description area, and the data buffer area includes a transmit data buffer area; when the first element is an FPGA and the second element is a CPU, the Ethernet data frame to be processed is an Ethernet data frame to be received by the CPU; the data description area includes a receive data description area, and the data buffer area includes a receive data buffer area.

[0055] In this embodiment, when the first element is a CPU and the second element is an FPGA, the first data frame is an Ethernet data frame to be sent by the CPU to the FPGA, and the first data frame is a network data frame received by the CPU from the network protocol stack. The data description area includes a transmission data description area, and the data buffer area includes a transmission data buffer area. Specifically, the CPU acquires the first data frame, which is an Ethernet data frame to be sent by the CPU; the CPU determines the information of the transmission data description area in the memory based on the length information of the first data frame; the information of the transmission data description area includes the number of transmission data buffer segments occupied by the first data frame in the transmission data buffer area in the memory; the CPU stores the first data frame into a first number of transmission data buffer segments in the transmission data buffer area; the first number is equal to the number of transmission data buffer segments occupied by the first data frame; the FPGA performs a data read operation from the transmission data buffer area in the memory.

[0056] When the first component is an FPGA and the second component is a CPU, the first data frame is an Ethernet data frame to be sent from the FPGA to the CPU. The data description area includes a receive data description area, and the data buffer includes a receive data buffer. Specifically, the FPGA acquires the first data frame, which is an Ethernet data frame to be received by the CPU; the FPGA determines the information of the receive data description area in the memory based on the length information of the first data frame; the information of the receive data description area includes the number of receive data buffer segments occupied by the first data frame in the receive data buffer in the memory; the FPGA stores the first data frame in a first number of receive data buffer segments in the receive data buffer and sends a network interrupt signal to the CPU; the first number is equal to the number of receive data buffer segments occupied by the first data frame; the CPU performs a data read operation from the receive data buffer in the memory in response to the network interrupt signal sent by the CPU.

[0057] The forms of the transmitted data description area and the received data description area can be referred to as follows: Figure 2 The format of the data description area, the format of the data transmission buffer, and the format of the data transmission buffer can be referred to... Figure 2The first data frame can be a data frame transmitted between the CPU and the Peripheral Component Interconnect Express (PCIe) network card extended by the FPGA. Based on the direction of data frame transmission, it is divided into a transmit data area and a receive data area. Based on function, the transmit data area is further divided into a transmit data description area and a transmit data buffer area, and the receive data area is divided into a receive data description area and a receive data buffer area.

[0058] For reference Figure 3 , Figure 3 This is a general conceptual diagram of an industrial Ethernet data transmission method provided in an embodiment of this application. (See diagram for example.) Figure 3 As shown, this method involves a processor (e.g., a Loongson 2K1000 processor, as the host processor), a PCIe network card, and a PCIe interface ( Figure 3 (Not shown) and FPGA. The processor includes a processor core and a Direct Memory Access (DMA) controller. The PCIe network card is a multi-network card extended from the FPGA chip. The PCIe interface is used to handle the physical connection between the processor and the FPGA, ensuring the reliability of data transmission.

[0059] like Figure 3 As shown, the memory contains a dedicated memory area allocated to the PCIe network cards expanded by the FPGA. This dedicated memory area is used to implement network data transmission between the processor and the PCIe network cards expanded by the FPGA. Each PCIe network card corresponds to a dedicated memory area (e.g., Figure 3 Ethernet 0, ..., Ethernet N), the dedicated memory area includes a transmit data description area (such as Ethernet 0, ..., Ethernet N). Figure 3 The Tx description area in the text), the send data buffer (such as...) Figure 3 The Tx buffer in the middle), the receive data description area (such as...) Figure 3 The Rx description area in the image) and the receive data buffer (such as...) Figure 3 The Rx buffer in the processor can poll and complete data transmission for N PCIe network cards. Specifically, the transmit data buffer stores network data to be sent by the processor, the transmit data description area stores storage description information (including frame length and segmentation information) of the network data to be sent, the receive data buffer stores network data received by the processor, and the receive data description area stores storage description information (including frame length and fragmentation information) of the network data received by the processor.

[0060] like Figure 3As shown, for each PCIe network card, the corresponding physical layer (PHY) chip (such as...) Figure 3 The FPGA and the physical layer chip transmit management data clock data and management data input / output (MDIO) data. At the same time, the FPGA and the physical layer chip also transmit data through a media independent interface (MII) and a gigabit media independent interface (GMII).

[0061] Furthermore, an initialization process can be performed before data transfer between the CPU and the PCIe network cards extended to the FPGA. Specifically, firstly, a dedicated memory area is allocated to each PCIe network card based on the number of PCIe network cards extended to the FPGA. This dedicated memory area is then partitioned (divided into four regions: transmit data description area, transmit data buffer area, receive data description area, and receive data buffer area). Next, the processor's PCIe DMA window is configured to point the PCIe interface to the dedicated memory area, establishing a data transfer channel between the FPGA and the dedicated memory area, facilitating subsequent data storage and retrieval.

[0062] In one embodiment of this application, the memory is a memory connected to the CPU.

[0063] In the embodiments of this application, such as Figure 3 As shown, the memory can be CPU-side memory. Therefore, compared to related technologies that store Ethernet data in FPGA-side memory, this method stores Ethernet data in processor-side memory, reducing the demand on FPGA-side memory while simultaneously increasing the read / write speed of Ethernet data, further improving the Ethernet data transmission rate.

[0064] In this embodiment, a first element acquires a first data frame, which is an Ethernet data frame to be processed; the first element determines information about a data description area in a memory based on the length information of the first data frame; the information about the data description area includes the number of data buffer segments occupied by the first data frame in the data buffer area of ​​the memory; the first element stores the first data frame into a first number of data buffer segments in the data buffer area; the first number is equal to the number of data buffer segments occupied by the first data frame; a second element performs a data read operation from the data buffer area in the memory; wherein, the data description area includes multiple data description segments, the data buffer area includes multiple data buffer segments, and the number of the multiple data description segments is the same as the number of the multiple data buffer segments; each of the multiple data description segments corresponds to a data buffer segment and includes storage description information associated with the data buffer segment. Thus, the data buffer area in the memory contains multiple data buffer segments. For the first data frame to be processed obtained by the first element, the first number of data buffer segments occupied by the first data frame is determined based on the length information of the first data frame. Based on the first number of data buffer segments occupied by the first data frame, the first data frame is stored in the first number of data buffer segments in the data buffer area of ​​the memory. This method makes full use of the storage space of the memory and solves the problem of low utilization of storage space in related technologies.

[0065] Please see Figure 4 , Figure 4 This is a flowchart of another industrial Ethernet data transmission method provided in an embodiment of this application. For example... Figure 4 As shown, the method includes the following steps:

[0066] Step 410: The first element acquires the first data frame, which is an Ethernet data frame to be processed.

[0067] Step 420: The first element determines the information of the data description area in the memory based on the length information of the first data frame; the information of the data description area includes the number of data buffer segments occupied by the first data frame in the data buffer area in the memory, and the data description area also includes a first sequence number for the first element, the first sequence number indicating the sequence number of the starting data buffer segment for the first element to perform this storage operation.

[0068] In this embodiment of the application, to facilitate the first element in performing storage operations, the data description area may further include a first sequence number for the first element. This first sequence number indicates the sequence number of the starting data cache segment for the first element to perform this storage operation. For example... Figure 2 As shown, Figure 2The field shown in serial number ② is the first serial number of the first element. The length of the first serial number field can be aligned with the length of the data description segment; that is, the length of the first serial number field can be the same as the length of the data description segment field, for example, both can be 2 bytes.

[0069] Step 430: The first element obtains the first serial number from the data description area.

[0070] In this embodiment of the application, before storing the first data frame into a first number of data buffer segments in the data buffer area, a first sequence number of the first element can be obtained from the data description area to determine the starting data buffer segment for storing the first data frame. For example, if the first sequence number is 3, then the sequence number of the starting data buffer segment for storing the first data frame can be determined to be 3.

[0071] Step 440: The first element, starting from the starting data buffer segment indicated by the first sequence number, stores the first data frame into a first number of data buffer segments in the data buffer area.

[0072] In this embodiment, when storing the first data frame, the first element can start storing from the initial data buffer segment, and can sequentially store each segment of the first data frame into a first number of data buffer segments in the data buffer area. For example, if the first data frame is divided into 3 segments, the first number is 3, and the first sequence number is 3, then the 3 segments of the data frame can be sequentially stored into 3 data buffer segments with sequence numbers 3, 4, and 5.

[0073] In one embodiment of this application, after the first element stores the first data frame into a first number of data buffer segments in the data buffer area, starting from the starting data buffer segment indicated by the first sequence number, the industrial Ethernet data transmission method includes, in addition to steps 310 to 350, steps 310 to 350: the first element determines a first update value based on the first sequence number, the first number, and the total number of data buffer segments contained in the data buffer area; the first element updates the first sequence number in the data description area based on the first update value, wherein the updated first sequence number indicates the sequence number of the starting data buffer segment for the first element to perform the next storage operation.

[0074] In this embodiment, since a first number of data buffer segments, starting from the initial data buffer segment corresponding to the first sequence number, have already stored the first data frame, the first sequence number can be updated so that it indicates the sequence number of the initial data buffer segment for the first element to perform the next storage operation. Specifically, the total number of data buffer segments contained in the data buffer area (including stored and unstored data buffer segments) can be obtained, the first sequence number and the first number can be summed, and the remainder of the summation result divided by the total number of segments can be obtained to obtain the first update value. After determining the first update value, it can be directly determined as the updated first sequence number.

[0075] For example, the data buffer contains 8 data buffer segments, with a first sequence number of 2 and a first count of 5. In this case, the first data frame, divided into 5 segments, can be stored in data buffer segments numbered 2, 3, 4, 5, and 6 respectively. Summing the first sequence number and the first count yields 7. Taking the remainder of the sum 7 divided by the total number of segments 8 also yields 7. Therefore, the first sequence number is updated to 7, which corresponds to the current storage endpoint (data buffer segment number 6). This method achieves sequential storage of the data buffer, preventing situations where the currently stored first data frame is not contiguous with the next stored data frame, thus avoiding memory waste caused by discontinuous buffer space.

[0076] Step 450: The second element performs a data read operation from the data buffer in the memory.

[0077] In this embodiment of the application, the data description area also includes a first sequence number for instructing the first element to perform this storage operation on the starting data cache segment. By introducing the first sequence number, when the first element performs this storage operation, the starting position of storing the first data frame can be directly determined by obtaining the first sequence number, without having to use other more complicated methods to determine the starting position of storing the first data frame, which simplifies the storage process of the first data frame.

[0078] Please see Figure 5 , Figure 5 This is a flowchart of another industrial Ethernet data transmission method provided in an embodiment of this application. For example... Figure 5 As shown, the method includes the following steps:

[0079] Step 510: The first element acquires the first data frame, which is an Ethernet data frame to be processed.

[0080] Step 520: The first element determines the information of the data description area in the memory based on the length information of the first data frame; the information of the data description area includes the number of data buffer segments occupied by the first data frame in the data buffer area in the memory, and the data description area also includes a first serial number for the first element and a second serial number for the second element.

[0081] The first serial number and the second serial number are independent of each other; the second serial number indicates the serial number of the starting data buffer segment for the second element to perform this read operation.

[0082] In this embodiment of the application, corresponding to the first sequence number, in order to facilitate the second element to perform a read operation from the data buffer, the data description area also includes a second sequence number for instructing the second element to perform this read operation on the starting data buffer segment. For example... Figure 2 As shown, Figure 2 The field shown as ③ in the middle is the second serial number of the second element. The length of the second serial number field can be aligned with the length of the data description segment; that is, the length of the second serial number field can be the same as the length of the data description segment field, for example, both can be 2 bytes.

[0083] Step 530: The first element obtains the first serial number from the data description area.

[0084] Step 540: The first element, starting from the starting data buffer segment indicated by the first sequence number, stores the first data frame into a first number of data buffer segments in the data buffer area.

[0085] Step 550: The second element obtains the second serial number from the data description area.

[0086] In this embodiment, the two operations of the first element storing a data frame in the data buffer and the second element reading a data frame from the data buffer are independent of each other. That is, the following scenario may exist: the first element stores data frame A in the data buffer, and the second element reads data frame B from the data buffer.

[0087] Therefore, when the second element performs a read operation, the second serial number of the second element can be obtained from the data description area to determine the starting position of the read data. For example, if the second serial number is 1, it can be determined that the read operation will start from the data buffer segment with serial number 1. Furthermore, before performing the read operation, the storage description information corresponding to the second serial number can be obtained from the data description area to determine whether the data buffer segment indicated by the second serial number is valid. If the data buffer segment indicated by the second serial number is valid (i.e., the first part of the data description segment is 1), the read operation is performed.

[0088] Step 560: The second element reads data stored in at least one data cache segment from the data cache area within the memory, starting from the starting data cache segment indicated by the second serial number.

[0089] In this embodiment of the application, when performing a read operation, the number of data cache segments to be read can be determined based on the content of the data description segment corresponding to the second serial number, and data of at least one data cache segment can be read from the data cache area starting from the starting data cache segment indicated by the second serial number in the data cache area.

[0090] For example, if the second sequence number is 2, and the first part of the data description segment for sequence number 2 is 1, the second part is 3, the third part is 1, and the fourth part is 256, then this read operation can be determined to read three data buffer segments from the data buffer area. First, 256 bytes of data are read from the data buffer segment with sequence number 2. Then, the content of the data description segment with sequence number 3 (first part 1, second part 3, third part 2, fourth part 256) can be obtained, and another 256 bytes of data are read from the data buffer segment with sequence number 3. Then, the content of the data description segment with sequence number 4 (first part 1, second part 3, third part 3, fourth part 32 bytes) can be obtained, and another 32 bytes of data are read from the data buffer segment with sequence number 4. At this point, the three data buffer segments numbered 1, 2, and 3 have been read, completing the current read operation.

[0091] In one embodiment of this application, after the second element reads data stored in at least one data cache segment from the data cache area in the memory, starting from the starting data cache segment indicated by the second serial number, the industrial Ethernet data transmission method includes, in addition to steps 510 to 560, steps 510 to 560, steps 510 to 560, steps 510 to 560, steps 510 to 560, and steps 560 to 560. Step 560 further includes steps 510 to 560, and steps 560 to ...

[0092] In this embodiment, after the current read operation is performed, at least one data cache segment read by the current read operation can be cleared from the data cache area, making the at least one data cache segment available for storage operations by the first element. Simultaneously with clearing the at least one data cache segment, a second sequence number can be updated, indicating the sequence number of the starting data cache segment for the second element to perform the next read operation.

[0093] Specifically, the total number of data cache segments contained in the data cache area (including both stored and unstored data cache segments) can be obtained. The second sequence number and the number of data cache segments read by the second element are summed. The remainder of the summation result divided by the total number of segments is then used to obtain the second update value. After determining the second update value, it can be directly used as the updated second sequence number.

[0094] For example, the data buffer contains 8 data buffer segments, the second sequence number is 1, and the second element reads 2 data buffer segments. In this case, the two data buffer segments corresponding to sequence numbers 1 and 2 can be read from the data buffer. By summing the second sequence number and the number of data buffer segments read by the second element, we get 3. Taking the remainder of the sum 3 divided by the total number of segments 8, we get 3 again. Then, we update the second sequence number to 3, which is exactly the end point of the current read operation (the data buffer segment with sequence number 2). In this way, sequential reading of the data buffer can be achieved, and there will be no discontinuity between the currently read data frame and the next read data frame. This further ensures that the data frames stored in the data buffer are all adjacent, avoiding memory waste caused by non-adjacent data frames stored in the data buffer.

[0095] In this embodiment of the application, the data description area also includes a second sequence number of the starting data buffer segment that indicates the second element to perform this read operation. By introducing the second sequence number, when the second element performs this read operation, the starting position of this read operation can be directly determined by obtaining the second sequence number, without having to use other more complicated methods to determine the starting position of this read operation, which simplifies the process of the second element performing the read operation.

[0096] Please see Figure 6 , Figure 6 This is a flowchart illustrating a method for transmitting industrial Ethernet data according to an embodiment of this application. Figure 6 As shown, the method includes the following steps:

[0097] Step 610: The first element acquires the first data frame, which is an Ethernet data frame to be processed.

[0098] Step 615: The first element determines the information of the data description area in the memory based on the length information of the first data frame; the information of the data description area includes the number of data buffer segments occupied by the first data frame in the data buffer area in the memory, and the data description area also includes a first serial number for the first element and a second serial number for the second element, the first serial number and the second serial number being independent of each other.

[0099] In this embodiment of the application, the data description area includes multiple data description segments, the data cache area includes multiple data cache segments, and the number of the multiple data description segments is the same as the number of the multiple data cache segments; each of the multiple data description segments corresponds to a data cache segment and includes storage description information associated with the data cache segment.

[0100] In this embodiment of the application, each of the plurality of data description segments includes: a first part, a second part, a third part, and a fourth part; the first part indicates whether the data description segment and the corresponding data buffer segment are valid; the second part indicates the number of data buffer segments occupied by the first data frame; the third part indicates the number of data buffer segments occupied by the first data frame; and the fourth part indicates the valid data length of the data buffer segment corresponding to the data description segment.

[0101] Wherein, each of the plurality of data cache segments has the same length, and the first number of data cache segments in the data cache area are a first number of consecutive data cache segments in the data cache area, wherein the first number is an integer greater than 1. The memory is memory connected to the CPU, that is, the memory is CPU-side memory.

[0102] In this embodiment of the application, the first sequence number indicates the sequence number of the starting data buffer segment for the first element to perform this storage operation, and the second sequence number indicates the sequence number of the starting data buffer segment for the second element to perform this read operation.

[0103] Step 620: The first element obtains the first serial number from the data description area.

[0104] Step 625: The first element, starting from the starting data buffer segment indicated by the first sequence number, stores the first data frame into a first number of data buffer segments in the data buffer area.

[0105] Step 630: The first element determines a first update value based on the first serial number, the first number, and the total number of data cache segments contained in the data cache area.

[0106] Step 635: The first element updates the first sequence number in the data description area based on the first update value. The updated first sequence number indicates the sequence number of the starting data cache segment for the first element to perform the next storage operation.

[0107] Step 640: The second element obtains the second serial number from the data description area.

[0108] In the embodiments of this application, the first element is one of a CPU and an FPGA, and the second element is the other of the CPU and the FPGA.

[0109] When the first component is a CPU and the second component is an FPGA, the Ethernet data frame to be processed is the Ethernet data frame to be sent by the CPU; the data description area includes a transmit data description area, and the data buffer area includes a transmit data buffer area. The process of the CPU sending data to the FPGA is as follows: The Loongson 2K1000 driver receives the network data frame from the network protocol stack. Based on the length d of the network data frame divided by the length of the data buffer segment (256 bytes), it determines that the network data frame occupies a transmit data buffer segment to store the data to be sent, and records the effective length b of the last transmit data buffer segment. It checks the first part (flag bit) of the consecutive a-segments of the data description segment corresponding to the processor's operation sequence number c1 to determine whether there are enough free transmit data buffer segments to store the network data frame to be sent. If so, it proceeds to the next step; otherwise, it returns to the network protocol stack that the transmit buffer is insufficient.

[0110] The network data frame is copied to the consecutive 'a' segments of the transmit data buffer corresponding to the processor's operation sequence number c1. The first part of the corresponding transmit data description segment is set to 1 to enable transmission, the second part is set to 'a', the third part is set to the segment sequence numbers 0 to 'a-1', and the fourth part is set to the valid data lengths 256, 256, ..., 'b'. After storage, the sum of the processor's operation sequence number c1 and 'a' is modulo the total number of segments n to obtain the updated processor operation sequence number c1, which points to the sequence number of the next transmit data buffer segment to be stored. Then, the FPGA is notified to read the transmitted network data.

[0111] The FPGA reads a series of consecutive transmit data description segments starting with the FPGA's operation sequence number c2 via the PCIe interface. Based on the first part (flag bit) of the transmit data description segment corresponding to c2, it determines whether there is data to be transmitted; if so, it proceeds to the next step. The FPGA determines and reads the corresponding transmit data buffer segment 'a' based on the second part of the transmit data description segment. After the read operation is complete, the first part (flag bit 15) of the transmit data description segment 'a' is cleared to disable transmit. The sum of the FPGA's operation sequence number c2 and 'a' is then modulo the total number of segments n to obtain the updated processor operation sequence number c2, which points to the sequence number of the next transmit data buffer segment to be read.

[0112] When the first element is an FPGA and the second element is a CPU, the Ethernet data frame to be processed is the Ethernet data frame to be received by the CPU; the data description area includes a receive data description area, and the data buffer area includes a receive data buffer area. The process of the FPGA sending data to the CPU is as follows: First, the FPGA stores the data to be received by the CPU into the receive data buffer area and sends an interrupt signal to the CPU. This is consistent with the CPU's storage process and will not be described in detail. After the CPU receives the network interrupt, it checks the first part (flag bit) of the receive data description segment corresponding to the CPU's receive operation sequence number c3 to determine whether there is network data to be received. If so, it proceeds to the next step; otherwise, it checks the next PCIe network card. The second part (bits 14-12) of the receive data description segment determines that the network data occupies the a-segment receive data buffer segment. Based on the sequence number of the third part (bits 11-9) and the effective data length of the fourth part (bits 8-0) of the a-segment receive data description segment, the data is copied from the receive data buffer area to the network protocol stack. Then, the first part (bit 15, the receive flag) of each of the 'a' receive data description segments is cleared. The sum of the CPU's operation sequence number c3 and 'a' is modulo the total number of segments n, which points to the next receive data description segment to be read. The CPU can then check the flag bits of the receive data description segment corresponding to the new operation sequence number to determine if there is received data. If so, the CPU continues reading data; otherwise, the current reading ends.

[0113] Step 645: The second element reads data stored in at least one data cache segment from the data cache area within the memory, starting from the starting data cache segment indicated by the second serial number.

[0114] Step 650: The second element determines a second update value based on the second serial number, the number of data cache segments read by the second element, and the total number of data cache segments contained in the data cache area.

[0115] Step 655: The second element updates the second sequence number in the data description area based on the second update value. The updated second sequence number indicates the sequence number of the starting data buffer segment for the second element to perform the next read operation.

[0116] In this embodiment, a first element acquires a first data frame, which is an Ethernet data frame to be processed; the first element determines information about a data description area in a memory based on the length information of the first data frame; the information about the data description area includes the number of data buffer segments occupied by the first data frame in the data buffer area of ​​the memory; the first element stores the first data frame into a first number of data buffer segments in the data buffer area; the first number is equal to the number of data buffer segments occupied by the first data frame; a second element performs a data read operation from the data buffer area in the memory; wherein, the data description area includes multiple data description segments, the data buffer area includes multiple data buffer segments, and the number of the multiple data description segments is the same as the number of the multiple data buffer segments; each of the multiple data description segments corresponds to a data buffer segment and includes storage description information associated with the data buffer segment. Thus, the data buffer area in the memory contains multiple data buffer segments. For the first data frame to be processed obtained by the first element, the first number of data buffer segments occupied by the first data frame is determined based on the length information of the first data frame. Based on the first number of data buffer segments occupied by the first data frame, the first data frame is stored in the first number of data buffer segments in the data buffer area of ​​the memory. This method makes full use of the storage space of the memory and solves the problem of low utilization of storage space in related technologies.

[0117] It is important to understand that Figures 1 to 6 The explanations of the same or corresponding steps can be cross-referenced. For example, Figure 1 The explanations of steps 110 and 120 are applicable to Figure 4 Steps 410 and 420 in the process.

[0118] Meanwhile, it should be understood that the industrial Ethernet data transmission method provided in this application embodiment has the following beneficial effects: First, by placing the data description area and data buffer area of ​​the PCIe network card in the processor-side memory, the PCIe network card extended by the FPGA only serves as a control and data transmission channel, and the FPGA does not need to provide storage functions, thereby reducing the demand for FPGA memory. Simultaneously, the data buffer area can also be used to cache network data packets. During the process of sending network packets to the protocol stack, when the protocol stack is not idle, the data buffer area can be used to cache network data packets, resulting in low memory requirements for the protocol stack and reducing its memory overhead. Second, by segmenting the data buffer area, with each segment being fixed to the same number of bytes, an Ethernet data packet can be stored using multiple consecutive data buffer segments. This reduces memory waste caused by storing small packets. Furthermore, aligned memory addresses avoid alignment operations during PCIe transmission, accelerating the data transmission rate. Third, the solution provided in this application is simple in design. Without changing the structure, multiple network ports can be expanded according to actual needs. It supports the customization of the data description area to control the data transmission between the processor and the multiple network cards expanded by the FPGA. Placing the data description area in the processor's memory facilitates the processor's operation and maintenance of the description information. The size of the data buffer area can be adjusted according to the designed network card to achieve efficient utilization of the processor's memory.

[0119] Please see Figure 7 , Figure 7 This is a structural block diagram of an industrial Ethernet data transmission system provided in an embodiment of this application. Figure 7 As shown, the industrial Ethernet data transmission system 700 includes: a first element 710 and a second element 720.

[0120] The first element 710 is used to acquire a first data frame, wherein the first data frame is an Ethernet data frame to be processed; determine information of a data description area in the memory based on the length information of the first data frame; the information of the data description area includes the number of data buffer segments occupied by the first data frame in the data buffer area in the memory; and store the first data frame into a first number of data buffer segments in the data buffer area; the first number is equal to the number of data buffer segments occupied by the first data frame.

[0121] The second element 720 is used to perform a data read operation from the data cache area within the memory; wherein the data description area contains a plurality of data description segments, the data cache area contains a plurality of data cache segments, and the number of the plurality of data description segments is the same as the number of the plurality of data cache segments; each of the plurality of data description segments corresponds to a data cache segment and contains storage description information associated with the data cache segment; the first element is one of a CPU and an FPGA, and the second element is the other of the CPU and the FPGA.

[0122] This application provides an industrial Ethernet data transmission system, including: a first element and a second element; wherein, the first element is used to acquire a first data frame, the first data frame being an Ethernet data frame to be processed; based on the length information of the first data frame, determine information of a data description area in a memory; the information of the data description area includes the number of data buffer segments occupied by the first data frame in a data buffer area in the memory; store the first data frame into a first number of data buffer segments in the data buffer area; the first number is equal to the number of data buffer segments occupied by the first data frame; the second element is used to perform a data read operation from the data buffer area in the memory; wherein, the data description area includes multiple data description segments, the data buffer area includes multiple data buffer segments, the number of the multiple data description segments is the same as the number of the multiple data buffer segments; each of the multiple data description segments corresponds to a data buffer segment and includes storage description information associated with the data buffer segment; the first element is one of a CPU and an FPGA, and the second element is the other of the CPU and the FPGA. Thus, the data buffer area in the memory contains multiple data buffer segments. For the first data frame to be processed obtained by the first element, the first number of data buffer segments occupied by the first data frame is determined based on the length information of the first data frame. Based on the first number of data buffer segments occupied by the first data frame, the first data frame is stored in the first number of data buffer segments in the data buffer area of ​​the memory. This method makes full use of the storage space of the memory and solves the problem of low utilization of storage space in related technologies.

[0123] The industrial Ethernet data transmission system provided in this application embodiment can realize the various processes implemented in the above method embodiments, and will not be repeated here to avoid repetition.

[0124] This application also provides a readable storage medium storing a program or instructions that, when executed by a processor, implement the steps of various embodiments of the industrial Ethernet data transmission method and achieve the same technical effect. To avoid repetition, these steps will not be repeated here.

[0125] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0126] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0127] This application provides a computer program product, which is stored in a storage medium and executed by at least one processor to implement the various processes of the above method embodiments and achieve the same technical effects. To avoid repetition, it will not be described again here.

[0128] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0129] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0130] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A method for transmitting industrial Ethernet data, characterized in that, include: The first element acquires a first data frame, which is an Ethernet data frame to be processed. The first element determines the information of the data description area in the memory based on the length information of the first data frame; the information of the data description area includes the number of data buffer segments occupied by the first data frame in the data buffer area in the memory; The first element stores the first data frame into a first number of data buffer segments in the data buffer area; The first number is equal to the number of data buffer segments occupied by the first data frame; The second element performs a data read operation from the data buffer within the memory; The data description area contains multiple data description segments, and the data cache area contains multiple data cache segments. The number of the multiple data description segments is the same as the number of the multiple data cache segments. Each of the multiple data description segments corresponds to a data cache segment and contains storage description information associated with the data cache segment.

2. The method according to claim 1, characterized in that, Each of the plurality of data description segments includes: a first part, a second part, a third part, and a fourth part; the first part indicates whether the data description segment and the corresponding data buffer segment are valid; the second part indicates the number of data buffer segments occupied by the first data frame; the third part indicates the number of data buffer segments occupied by the first data frame; and the fourth part indicates the valid data length of the data buffer segment corresponding to the data description segment.

3. The method according to claim 1 or 2, characterized in that, Each of the plurality of data cache segments has the same length, and the first number of data cache segments in the data cache area are a first number of consecutive data cache segments in the data cache area, wherein the first number is an integer greater than 1.

4. The method according to claim 1 or 2, characterized in that, The data description area further includes: a first serial number for the first element; the first serial number indicates the serial number of the starting data cache segment for the first element to perform this storage operation; The first element stores the first data frame into a first number of data buffer segments in the data buffer area, including: The first element obtains the first serial number from the data description area; The first element stores the first data frame into a first number of data buffer segments in the data buffer area, starting from the starting data buffer segment indicated by the first sequence number.

5. The method according to claim 4, characterized in that, After the first element stores the first data frame into a first number of data buffer segments in the data buffer area, the method further includes: The first element determines a first update value based on the first sequence number, the first number, and the total number of data cache segments contained in the data cache area; The first element updates the first sequence number in the data description area based on the first update value. The updated first sequence number indicates the sequence number of the starting data cache segment for the first element to perform the next storage operation.

6. The method according to claim 4, characterized in that, The data description area further includes: a second serial number for the second element, wherein the first serial number and the second serial number are independent of each other; the second serial number indicates the serial number of the starting data buffer segment for the second element to perform this read operation; The second element performs a data read operation from the data buffer within the memory, including: The second element obtains the second serial number from the data description area; The second element reads data stored in at least one data cache segment from the data cache area within the memory, starting from the starting data cache segment indicated by the second serial number.

7. The method according to claim 6, characterized in that, After the second element performs a data read operation from the data buffer in the memory, the method further includes: The second element determines the second update value based on the second serial number, the number of data cache segments read by the second element, and the total number of data cache segments contained in the data cache area; The second element updates the second sequence number in the data description area based on the second update value. The updated second sequence number indicates the sequence number of the starting data buffer segment for the second element to perform the next read operation.

8. The method according to claim 1, characterized in that, The first element is one of a CPU and a field-programmable gate array (FPGA), and the second element is the other of the CPU and the FPGA; When the first component is a CPU and the second component is an FPGA, the Ethernet data frame to be processed is the Ethernet data frame to be sent by the CPU; the data description area includes a transmission data description area, and the data buffer area includes a transmission data buffer area; When the first component is an FPGA and the second component is a CPU, the Ethernet data frame to be processed is the Ethernet data frame to be received by the CPU; the data description area includes a received data description area, and the data buffer area includes a received data buffer area.

9. The method according to claim 8, characterized in that, The memory is a memory connected to the CPU.

10. An industrial Ethernet data transmission system, characterized in that, Includes a first element and a second element; The first element is used to acquire a first data frame, which is an Ethernet data frame to be processed; based on the length information of the first data frame, determine the information of the data description area in the memory; the information of the data description area includes the number of data buffer segments occupied by the first data frame in the data buffer area in the memory; and store the first data frame into a first number of data buffer segments in the data buffer area. The first number is equal to the number of data buffer segments occupied by the first data frame; The second element is used to perform a data read operation from the data buffer within the memory; The data description area contains multiple data description segments, and the data cache area contains multiple data cache segments. The number of the multiple data description segments is the same as the number of the multiple data cache segments. Each of the multiple data description segments corresponds to a data cache segment and contains storage description information associated with the data cache segment. The first element is one of a CPU and a field-programmable gate array (FPGA), and the second element is the other of the CPU and the FPGA.

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