Trench gate dual-control electrode 4H-SiC composite transistor structure and fabrication method

Abstract

This invention discloses a trench-gate dual-controller 4H-SiC composite transistor structure and its fabrication method. The structure consists of an active region formed by parallel multi-cell structures and a trench-junction termination extension composite terminal region. The n+ source region and p+ region are separated and introduced into dual controllers to control the turn-on and turn-off of the parallel VUMOS and BJT respectively, thereby reducing the on-resistance and loss of the DCT, while reducing the channel density to increase the short-circuit withstand time, improve the short-circuit resistance, and eliminate the influence of the body diode on the device characteristics. A p-floating region with a side arc shape is formed at the bottom of the trench in the active region, and its edge wraps around the trench corner to reduce the electric field intensity in the gate oxide layer at that location, solving the problem of easy breakdown of the gate oxide layer. The trench-junction termination extension composite terminal is used to reduce the terminal size and obtain high breakdown voltage efficiency, which can meet the requirements of power MOSFET characteristics and reliability in practical applications and has low cost.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device technology, specifically relating to a trench gate dual-control electrode 4H-SiC composite transistor structure and its fabrication method. Background Technology

[0002] Currently, 4H-SiC power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors, or MOS for short) are being used as power switches in new energy, photovoltaic inverters, and power systems. In comparison, due to the simpler fabrication process of planar gate power MOSFETs, most existing power MOSFETs adopt a planar gate MOSFET (VDMOS) structure, with a carrier extension layer above the n-drift region to reduce its on-resistance. However, its on-resistance is still higher than that of trench gate MOSFETs (VUMOS). In addition to setting a carrier extension layer between the n-drift region and the p-body region to reduce on-resistance, existing VUMOS structures typically add a moderately doped p-region directly below the trench gate to suppress the high electric field intensity at the trench corners.

[0003] Despite continuous improvements to the device structure using the aforementioned techniques, VUMOS remains a unipolar device. It cannot generate conductivity modulation during conduction, resulting in a higher on-resistance compared to bipolar devices (such as bipolar junction transistors, BJTs). In practical applications, existing VUMOS devices still suffer from several drawbacks. For example, the high electric field at the trench corners makes the gate oxide layer prone to breakdown; short short-circuit withstand time leads to poor short-circuit immunity; the anti-parallel body diode affects device characteristics; and the large chip termination size, complex manufacturing process, and high cost make them unsuitable for power switching applications. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a trench-gate dual-controller 4H-SiC composite transistor structure and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] In a first aspect, embodiments of the present invention provide a trench gate dual-control electrode 4H-SiC composite transistor structure, which is composed of an active region formed by multiple central cell structures connected in parallel and an outer trench-junction terminal extension composite terminal region.

[0006] The cell structure includes: an n-buffer layer, an n-drift region, an n-carrier extension layer, a p-body region, and an n+ source region sequentially disposed on a 4H-SiC n+ substrate; an active region trench is disposed in the center of the cell structure, extending downward from the n+ source region into the n-drift region; a p-floating region with an outer arc shape is disposed below the active region trench, its arc edge wrapping around the corner of the active region trench; the sides and bottom of the active region trench are covered with a gate oxide layer, and the interior is filled with heavily doped polysilicon as the trench gate G; the n+ source region and p-body region on each side form a mesa structure, and a p+ region is disposed in the top layer region near the outer edge of the p-body region below the mesa structure on each side, with a spacing between it and the n+ source region on the same side; a source electrode S is disposed on the surface of the n+ source region; a base electrode B is disposed on the surface of the p+ region; the surface of the active region trench is covered with a phosphorus silicon glass layer to isolate the trench gate G from the source electrode S; the 4H-SiC The back side of the n+ substrate has a drain D; the trench gate G and the base B are both control electrodes; the cell structure is symmetrical about the central trench gate G, which is equivalent to the parallel connection of VUMOS and BJT.

[0007] The trench-junction terminal extension composite terminal region is connected to the corresponding layer of the outermost cell structure of the active region, including an n-buffer layer, an n-drift region, an n-carrier extension layer, a p-body region, and a drain D on the back side of the 4H-SiC n+ substrate, which are sequentially arranged on the 4H-SiC n+ substrate. The p-body region, the n-carrier extension layer, and a portion of the n-drift region, together with the remaining portion of the n-drift region, form a mesa structure as a terminal trench. A p-junction terminal extension region is provided in a local area of ​​the n-drift region at the corner below the terminal trench. The side of the p-junction terminal extension region near the terminal trench is arc-shaped and wraps around the corner of the terminal trench.

[0008] In one embodiment of the present invention, for the trench-junction terminal extension composite terminal region and the outermost cell structure of the connected active region, there is a naturally formed longitudinal resistance region in the p-body region, n-carrier extension layer and n-drift region of the trench sidewall of the terminal region.

[0009] In one embodiment of the present invention, in the trench gate dual-controllable-electrode 4H-SiC composite transistor structure, the n-drift region of the VUMOS is equivalent to the n-collector region of the BJT, the p-body region of the VUMOS is equivalent to the p-base region of the BJT, the n+ source region of the VUMOS is equivalent to the n+ emitter region of the BJT, and the 4H-SiC n+ substrate of the VUMOS is equivalent to the collector ohmic contact region of the BJT; the source S of the VUMOS is also the emitter E of the BJT, and the drain D of the VUMOS is also the collector C of the BJT; the turn-on and turn-off of the VUMOS and the BJT are controlled by the gate G and the base B, respectively.

[0010] In one embodiment of the present invention, when the trench gate dual-controllable electrode 4H-SiC composite transistor is turned on, by applying a gate voltage to the trench gate G, which serves as a control electrode, and applying a base current to the base B, which serves as the other control electrode, the VUMOS and BJT are simultaneously turned on, so that the n-drift region generates a conductivity modulation effect, and the entire device operates in bipolar mode.

[0011] In one embodiment of the present invention, in the cellular structure,

[0012] The width W of the active region trench TG The depth D of the active region trench is 2–3 μm. TG Its diameter is 1.4–2 μm;

[0013] The concentration N in the p-floating zone p 5×10 17 cm -3 ~6×10 17 cm -3 The depth D of the p floating zone p The thickness is 0.6–0.7 μm;

[0014] The width W of the n+ source region n+ The thickness D of the n+ source region is 5–7 μm. n+ The distance between the n+ source region and the p+ region is 0.3–0.5 μm; B It is 3-5 μm.

[0015] In one embodiment of the present invention, in the trench-junction terminal extension composite terminal region,

[0016] The depth of the trench in the terminal region is 1.7–2.5 μm; the concentration of N in the p-junction terminal extension region is... JTE 3.2×10 17 ~3.6×10 17 cm -3 The junction depth D of the p-junction terminal extension region JTE The width W of the p-junction termination extension region is 0.4–0.6 μm. JTE It is 20–35 μm.

[0017] Secondly, embodiments of the present invention provide a method for fabricating a trench-gate dual-control electrode 4H-SiC composite transistor structure, the method comprising:

[0018] On a 4H-SiC n+ substrate, an n buffer layer, an n-drift region, an n-carrier extension layer, a p-body region, and an n+ source region are sequentially grown using epitaxial technology.

[0019] Dry etching process is used to etch both sides of the n+ source region to form a mesa structure between the n+ source region and the p-body region;

[0020] Using a dry etching process, the n+ source region is etched downwards into the n- drift region to form an active region trench, and the p-body region at the edge is etched downwards into the n- drift region to form a terminal region trench.

[0021] Multiple aluminum ion covering implantations are performed on the active area trench to form a p-floating area at the bottom of the active area trench, and the outer side of the p-floating area is made to wrap around the corner of the active area trench in an arc shape.

[0022] Multiple aluminum ion covering implants are performed on the bottom of the terminal trench to form a p-junction terminal extension region at the bottom of the terminal trench, and the outer side of the p-junction terminal extension region is made to encircle the corner of the terminal trench in an arc shape.

[0023] Aluminum ions are implanted into the outer surface edge region of the p-body region, which has a gap with the n+ source region, to form the p+ region, and then subjected to high-temperature annealing.

[0024] A gate oxide layer is prepared on the side and bottom of the active region trench by thermal oxidation, and then polysilicon is deposited and heavily doped to fill the active region trench to form the trench gate G.

[0025] An oxide film and a borosilicate glass layer are deposited on the surface of the active region trench, and source and base metal contact holes are formed by photolithography. Then, nickel is deposited, and after high-temperature annealing, an ohmic contact for the source S is formed on the surface of the n+ source region, and an ohmic contact for the base B is formed on the surface of the p+ region. Then, the nickel layer on the surface of the borosilicate glass is removed by a lift-off process. Gate bonding holes are etched, and titanium, titanium nitride and aluminum copper films are deposited in sequence. Then, the source, base and gate metal electrodes are formed by reverse etching, and rapid annealing is performed to complete the surface metal electrode preparation.

[0026] Silicon nitride film is deposited and photolithography is performed to passivate the terminal area on the chip surface; then polyimide film is coated, and photolithography is used to form the bonding area pattern of the source, gate and base regions on the surface, and imidization treatment is performed to form the front terminal passivation and protective layer to complete the device surface passivation treatment.

[0027] The lower surface of the 4H-SiC n+ substrate is thinned, and titanium, nickel, and silver are sputtered sequentially to prepare the drain electrode D. Then, laser annealing is performed to reduce the ohmic contact resistance, thus completing the preparation of the back metal electrode.

[0028] In one embodiment of the present invention, the active region trench is subjected to multiple aluminum ion implantations to form a p-floating region at the bottom of the active region trench, and the outer side of the p-floating region is rounded around the corner of the active region trench, including:

[0029] On the upper surface of the current crystal, a 30-50 nm silicon dioxide capping film is deposited, and photoresist is coated as a masking film. Multiple aluminum ion implantations are performed on the bottom of the active region trench at room temperature. By adjusting the implantation dose and energy, a p-floating region is formed at the bottom of the active region trench, and the outer side of the p-floating region is rounded to surround the corner of the active region trench. The concentration N of the p-floating region is... p 5×10 17 cm -3 ~6×10 17 cm -3 The depth D of the p floating zone p It is 0.6–0.7 μm.

[0030] In one embodiment of the present invention, multiple aluminum ion implantations are performed on the bottom of the terminal trench to form a p-junction terminal extension region at the bottom of the terminal trench, and the outer side of the p-junction terminal extension region is rounded to surround the corner of the terminal trench, including:

[0031] The current silicon dioxide capping film on the upper surface of the crystal is removed, and a 30-50 nm silicon dioxide capping film is re-deposited. Photoresist is applied as a masking film. Multiple aluminum ion implantations are performed on the bottom of the terminal trench at room temperature, while adjusting the implantation dose and energy to form a p-junction terminal extension region at the bottom of the terminal trench. The outer side of the p-junction terminal extension region is rounded to surround the corner of the terminal trench. The concentration N of the p-junction terminal extension region is... JTE 3.2×10 17 ~3.6×10 17 cm -3 The junction depth D of the p-junction terminal extension region JTE The width W of the p-junction termination extension region is 0.4–0.6 μm. JTE It is 20–35 μm.

[0032] In one embodiment of the present invention, aluminum ion implantation is performed on the outer surface edge region of the p-body region, which has a spacing with the n+ source region, to form the p+ region, including:

[0033] Remove the silicon dioxide capping film on the surface of the current crystal, re-deposit the silicon dioxide capping film and the polysilicon masking film, etch the polysilicon at the edge of the outer surface of the p-body region with a gap from the n+ source region to form the p+ region implantation window, and then perform aluminum ion implantation at 500°C to form the p+ region.

[0034] The doping concentration of the p+ region after annealing is 3×10⁻⁶. 19 ~5×10 19 cm -3 .

[0035] The beneficial effects of this invention are:

[0036] Compared to existing trench-gate 4H-SiC MOSFET (VUMOS) cell structures, this invention proposes a trench-gate dual-controller 4H-SiC composite transistor structure. First, the n+ source region and p+ ohmic contact region are separated, and a BJT connected in parallel with the VUMOS is introduced to form dual controllers, controlling the turn-on and turn-off of the VUMOS and BJT respectively. This reduces the on-resistance and loss of the DCT, while also reducing the channel density to increase short-circuit withstand time and improve short-circuit immunity, and eliminates the influence of the body diode on device characteristics. Second, a p-floating region with a side arc shape is formed at the bottom of the active region trench, so that its arc edge wraps around the corner of the active region trench, reducing the electric field strength in the gate oxide layer at the corner of the active region trench, thereby solving the problem of easy gate oxide layer breakdown. Furthermore, a trench-junction termination extension composite termination (T-JTE) is used to reduce the termination size and obtain a higher termination breakdown voltage, thus meeting the requirements of practical applications for power MOSFET characteristics and reliability.

[0037] Furthermore, the fabrication process of the trench gate dual-controllable electrode 4H-SiC composite transistor structure in this embodiment of the invention is compatible with the existing VUMOS process. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the existing 4H-SiC VUMOS cell structure;

[0039] Figure 2 This is the equivalent circuit diagram of an existing 4H-SiC VUMOS cell;

[0040] Figure 3 This is a schematic diagram of the trench gate dual-control electrode 4H-SiC composite transistor (T-DCT) structure provided in an embodiment of the present invention;

[0041] Figure 4 This is an equivalent circuit diagram of a 4H-SiC T-DCT cell according to an embodiment of the present invention;

[0042] Figure 5 This is a schematic diagram of the carrier transport trajectory during the initial turn-on of an existing 4H-SiC VUMOS cell;

[0043] Figure 6 This refers to the control timing of the control signals applied to the two control electrodes of the 4H-SiC T-DCT in this embodiment of the invention.

[0044] Figure 7 This is a schematic diagram of the carrier transport trajectory during the initial turn-on stage of a 4H-SiC T-DCT cell according to an embodiment of the present invention.

[0045] Figure 8 This is a comparison curve of the breakdown characteristics of 4H-SiC T-DCT cells in this invention and existing 4H-SiC VUMOS cells;

[0046] Figure 9 This is a comparison curve of the longitudinal electric field intensity distribution during breakdown between the 4H-SiC T-DCT cell of this invention and the existing 4H-SiC VUMOS cell;

[0047] Figure 10 This is a comparison curve of the on-state characteristics of the 4H-SiC T-DCT cell of the present invention and the existing 4H-SiC VUMOS cell;

[0048] Figure 11 This is a comparison curve of the transfer characteristics of 4H-SiC T-DCT cells in this embodiment of the invention and existing 4H-SiC VUMOS cells;

[0049] Figure 12 These are the conduction characteristic curves of the 4H-SiC T-DCT under different base currents according to an embodiment of the present invention.

[0050] Figure 13 This is a comparison curve of the turn-on characteristics of the 4H-SiC T-DCT cell of the present invention and the existing 4H-SiC VUMOS cell under resistive load.

[0051] Figure 14 This is a comparison curve of the turn-off characteristics of the 4H-SiC T-DCT cell of the present invention and the existing 4H-SiC VUMOS cell under resistive load.

[0052] Figure 15 This is a comparison curve of the short-circuit characteristics of the 4H-SiC T-DCT cell in this embodiment of the invention and the existing 4H-SiC VUMOS.

[0053] Figure 16 The 4H-SiC T-DCT cells of this invention are at different gate trench depths D TG Comparison curves of conduction characteristics;

[0054] Figure 17a The 4H-SiC T-DCT cells of this invention are at different p-floating region concentrations of N p Comparison curves of breakdown characteristics;

[0055] Figure 17b The 4H-SiC T-DCT cells of this invention are at different p-floating region concentrations of N p Comparison of longitudinal electric field intensity distribution curves during lower breakdown;

[0056] Figure 18a The 4H-SiC T-DCT cells of this invention are at different p-floating region junction depths D. p Comparison curves of breakdown characteristics;

[0057] Figure 18b The 4H-SiC T-DCT cells of this invention are at different p-floating region junction depths D. p Comparison of electric field intensity distribution curves during lower breakdown;

[0058] Figure 19 The 4H-SiC T-DCT cells of this invention have different n+ source region widths W n+ Comparison curves of conduction characteristics under different conditions;

[0059] Figure 20 The 4H-SiC T-DCT cells of this invention have different n+ source region and p+ region spacing S. B Comparison curves of conduction characteristics under different conditions;

[0060] Figure 21a This is a comparison curve of the terminal breakdown characteristics and the active region breakdown characteristics of the 4H-SiC T-DCT of this invention embodiment;

[0061] Figure 21b This is the transverse electric field intensity distribution curve of the 4H-SiC T-DCT in the embodiment of the present invention during terminal breakdown;

[0062] Figure 22a The concentration N of 4H-SiC T-DCT in different p-JTE regions in embodiments of the present invention. JTE The breakdown characteristic curve below;

[0063] Figure 22b The concentration N of 4H-SiC T-DCT in different p-JTE regions in embodiments of the present invention. JTE Transverse electric field intensity distribution curve during downward breakdown;

[0064] Figure 23a The 4H-SiC T-DCT of this invention is used at different p-JTE region junction depths D. JTE The breakdown characteristic curve below.

[0065] Figure 23b The 4H-SiC T-DCT of this invention is used at different p-JTE region junction depths D. JTE Electric field intensity distribution curve during lower breakdown;

[0066] Figure 24a The 4H-SiC T-DCT of this invention has different p-JTE region widths W JTE The breakdown characteristic curve below;

[0067] Figure 24b The 4H-SiC T-DCT of this invention has different p-JTE region widths W JTE Electric field intensity distribution curve during lower breakdown;

[0068] Figure 25 This is a schematic flowchart of a method for fabricating a trench gate dual-control electrode 4H-SiC composite transistor structure provided in an embodiment of the present invention;

[0069] Figures 26a to 26h This is a cross-sectional view of the key area fabrication of the T-JTE composite terminal 4H-SiC T-DCT of this invention. Detailed Implementation

[0070] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0071] Reference Figure 1 The existing 4H-SiC trench gate power MOSFET (hereinafter referred to as VUMOS) has a multi-cell parallel structure. Its cell structure is as follows: on a 4H-SiC n+ substrate (see... Figure 1 On the 4H-SiC n+sub layer, n buffer layers are sequentially arranged upwards (see... Figure 1 (n buffer in the n-drift region) Figure 1 (n-drift), n-carrier extension layer (see n-drift), n-carrier extension layer (see n-drift) Figure 1 nCSL), p body region (see nCSL), p body region (see nCSL) Figure 1 p-body) and n+ source region (see p-body) and n+ source region (see p-body) Figure 1 (n+ on both sides of the upper middle). A groove is provided in the center of the cell, and a p floating region is provided below the groove (see Figure 1 The trench below G is filled with gate oxide on its sides and bottom, and heavily doped polysilicon inside. The trench gate G is disposed on the polysilicon. An n+ source region is disposed on the p-body region near the trench on both sides. A p+ ohmic contact region is disposed outside the n+ source region, contacting the n+ source region (see [link to documentation]). Figure 1 The p+ regions on both sides of the upper middle section, along with the source electrode S on the upper surface of part of the n+ source region and the p+ ohmic contact region, and the drain electrode D on the back side of the n+ substrate, are arranged. Each cell is symmetrical about the central trench gate.

[0072] Reference Figure 2This is the equivalent circuit of the existing 4H-SiC VUMOS. It can be seen that, since the existing VUMOS structure consists of a p+ ohmic contact region, a p-body region, an n-carrier extension layer (CSL), an n-drift region, an n-buffer layer, and an n+ substrate forming a PIN body diode (parasitic diode), it is equivalent to the VUMOS and the PIN diode being connected in anti-parallel, with the drain D shared with the cathode K, and the source S shared with the anode A.

[0073] In practical applications, existing VUMOS still has many drawbacks. For example, the high electric field at the trench corner makes the gate oxide layer easy to break down; the short short-circuit withstand time results in poor short-circuit resistance; the anti-parallel body diode affects the device characteristics; and the chip terminal size is large, the process is complex, and the cost is high, which cannot meet the application requirements of power switches.

[0074] To address the aforementioned issues, this invention proposes a trench gate dual-control electrode 4H-SiC composite transistor structure and its fabrication method.

[0075] In a first aspect, embodiments of the present invention provide a trench gate dual-control electrode 4H-SiC composite transistor (T-DCT) structure, such as... Figure 3 As shown, it specifically includes:

[0076] It consists of an active region formed by multiple parallel central cell structures and an outer trench-junction terminal extension composite terminal region.

[0077] The cell structure includes: an n-buffer layer, an n-drift region, an n-carrier extension layer, a p-body region, and an n+ source region sequentially disposed on a 4H-SiC n+ substrate; an active region trench is disposed in the center of the cell structure, extending downward from the n+ source region into the n-drift region; a p-floating region with an outer arc shape is disposed below the active region trench, its arc edge wrapping around the corner of the active region trench; the sides and bottom of the active region trench are covered with a gate oxide layer, and the interior is filled with heavily doped polysilicon as the trench gate G; the n+ source region and p-body region on each side form a mesa structure, and a p+ region is disposed in the top layer region near the outer edge of the p-body region below the mesa structure on each side, with a spacing between it and the n+ source region on the same side; a source electrode S is disposed on the surface of the n+ source region; a base electrode B is disposed on the surface of the p+ region; the surface of the active region trench is covered with a phosphorus silicon glass layer to isolate the trench gate G from the source electrode S; the 4H-SiC The back side of the n+ substrate has a drain D; the trench gate G and the base B are both control electrodes; the cell structure is symmetrical about the central trench gate G, which is equivalent to the parallel connection of VUMOS and BJT.

[0078] The trench-junction terminal extension composite terminal region is connected to the corresponding layer of the outermost cell structure of the active region, including an n-buffer layer, an n-drift region, an n-carrier extension layer, a p-body region, and a drain D on the back side of the 4H-SiC n+ substrate, which are sequentially arranged on the 4H-SiC n+ substrate. The p-body region, the n-carrier extension layer, and a portion of the n-drift region, together with the remaining portion of the n-drift region, form a mesa structure as a terminal trench. A p-junction terminal extension region is provided in a local area of ​​the n-drift region at the corner below the terminal trench. The side of the p-junction terminal extension region near the terminal trench is arc-shaped and wraps around the corner of the terminal trench.

[0079] The T-DCT provided in this embodiment of the invention includes an active region and a trench-junction terminal extension complex (T-JTE) region. The active region is located in the center and includes multiple parallel cell structures; the trench-junction terminal extension complex (T-JTE) region is located on the periphery and is connected to the outermost cell structure of the active region. For simplicity, Figure 3 Only the T-JTE and its outermost connected cellular structure are shown.

[0080] Figure 3 In the diagram, the region to the left of the dashed line is the active region. Taking a single cell structure as an example, the region to the right of the dashed line is the termination region, i.e., the T-JTE. Here, 4H-SiC n+sub represents the 4H-SiC n+ substrate; n buffer represents the n buffer layer; n-drift represents the n-drift region; CSL represents the n carrier extension layer; p-body represents the p-body region; n+ represents the n+ source region; p+ represents the p+ region, i.e., the p+ ohmic contact region; p below G represents the p floating region; and the p-junction termination extension region in the T-JTE is simply referred to as the p-JTE region. It can be seen that the T-JTE and the connected cell structure are connected correspondingly to the 4H-SiC n+ substrate, the n buffer layer, part of the n-drift region, and the drain D.

[0081] In this embodiment of the invention, for the trench-junction terminal extension composite terminal region and the outermost cell structure of the connected active region, a naturally formed longitudinal resistance region exists within the p-body region, n-carrier extension layer, and n-drift region of the trench sidewall of the terminal region. Please refer to [the relevant documentation] for details regarding this longitudinal resistance region. Figure 3 The three regions above and to the right of the dashed line are shown. This longitudinal resistance zone effectively prevents the trench sidewalls from failing due to current concentration after avalanche breakdown.

[0082] Reference Figure 4This is the equivalent circuit of the T-DCT of the present invention. It can be seen that the T-DCT is equivalent to a VUMOS and a BJT connected in parallel. Specifically, the n-drift region of the VUMOS corresponds to the n-collector region of the BJT, the p-body region of the VUMOS corresponds to the p-base region of the BJT, the n+ source region of the VUMOS corresponds to the n+ emitter region of the BJT, and the 4H-SiC n+ substrate of the VUMOS corresponds to the collector ohmic contact region of the BJT. The source S of the VUMOS is also the emitter E of the BJT, and the drain D of the VUMOS is also the collector C of the BJT. The gate G and the base B control the turn-on and turn-off of the VUMOS and BJT, respectively.

[0083] In a preferred embodiment, the cell structure,

[0084] The width W of the active region trench TG The depth D of the active region trench is 2–3 μm. TG Its diameter is 1.4–2 μm;

[0085] The concentration N in the p-floating zone p 5×10 17 cm -3 ~6×10 17 cm -3 The depth W of the p floating area p The thickness is 0.5–0.7 μm;

[0086] The width W of the n+ source region n+ The thickness D of the n+ source region is 5–7 μm. n+ The distance between the n+ source region and the p+ region is 0.3–0.5 μm; B It is 3-5 μm.

[0087] In a preferred embodiment, in the trench-junction terminal extension composite terminal region,

[0088] The depth of the trench in the terminal region is 1.7–2.5 μm; the concentration of N in the p-junction terminal extension region is... JTE 3.2×10 17 ~3.6×10 17 cm -3 The junction depth D of the p-junction terminal extension region JTE The width W of the p-junction termination extension region is 0.4–0.6 μm. JTE It is 20–35 μm.

[0089] contrast Figure 1 and Figure 3Compared to existing 4H-SiC VUMOS, the trench-gate dual-controller 4H-SiC composite transistor structure provided in this embodiment differs in that a mesa structure is formed on the surfaces of the p-body region and the n+ source region. The n+ source region is located on the upper part of the mesa structure, and the p+ ohmic contact region is placed within the surface of the lower part of the mesa structure, thereby separating the n+ source region from the p+ ohmic contact region and setting them as the source (S) and base (B) respectively. Thus, the entire T-DCT is equivalent to a parallel connection of a VUMOS and a BJT. When the trench-gate dual-controller 4H-SiC composite transistor is turned on, by applying a gate voltage to the trench gate (G) as one control electrode and a base current to the base (B) as the other control electrode, both the VUMOS and the BJT are triggered to turn on, causing a conductivity modulation effect in the n-drift region, and the entire device operates in bipolar mode. This not only improves the on-resistance of the device, but also reduces the channel density for the same chip area due to the increased width of the n+ source region and its spacing from the p+ ohmic contact region, thereby increasing the short-circuit withstand time and improving the device's short-circuit immunity. Furthermore, the separation of the p+ ohmic contact region from the n+ source region eliminates the PIN body diode present in existing 4H-SiC VUMOS devices, thus avoiding the influence of the body diode on device characteristics.

[0090] In summary, compared to the existing trench gate 4H-SiC MOSFET (VUMOS) cell structure, this invention first separates the n+ source region and p+ ohmic contact region, introducing a BJT in parallel with the VUMOS to form dual control electrodes, which control the turn-on and turn-off of the VUMOS and BJT respectively, thereby reducing the on-resistance and loss of the DCT. Simultaneously, it reduces the channel density to increase short-circuit withstand time and improve short-circuit immunity, while eliminating the influence of the body diode on device characteristics. Second, a p-floating region with a side arc shape is formed at the bottom of the active region trench, so that its arc edge wraps around the corner of the active region trench, thereby reducing the electric field strength in the gate oxide layer at the corner of the active region trench, thus solving the problem of easy gate oxide layer breakdown. Furthermore, a trench-junction termination extension composite termination (T-JTE) is adopted to reduce the termination size and obtain high breakdown voltage efficiency, thus meeting the requirements of practical applications for the characteristics and reliability of power MOSFETs.

[0091] To facilitate understanding of the effectiveness of the trench-gate dual-controllable-electrode 4H-SiC composite transistor structure proposed in this invention, it is compared and analyzed with the existing 4H-SiC VUMOS, as follows:

[0092] 1) The working principle of the trench gate dual-control electrode 4H-SiC T-DCT of the present invention is significantly different from that of the existing VUMOS;

[0093] Reference Figure 5This is a schematic diagram of the carrier transport trajectory during the initial turn-on of an existing VUMOS. It can be seen that when the gate-source voltage is greater than the threshold voltage (V... G >V TH Drain-source voltage greater than zero (V) DS When the voltage is >0, during the initial turn-on of the VUMOS, an N-channel is formed on the surface of the p-body region along the sidewall of the gate G in the trench. Electrons from the n+ source region enter the n-carrier extension layer (n CSL) vertically through the N-channel and reach the n-drift region, finally flowing out from the drain to form the drain current. It can be seen that the drain current is only the electron current flowing through the channel, and its operating mode is also a unipolar operating mode. During conduction, no conductivity modulation effect occurs in the n-drift region, thus exhibiting a high on-resistance.

[0094] Reference Figure 6 , which are the control signals applied to the two control electrodes of the 4H-SiC T-DCT of this invention. It can be seen that when the device is turned on, a positive voltage signal is applied to the gate G, and a positive peak current signal is applied to the base B; after conduction, the gate voltage remains unchanged, and the base current drops to the steady-state base current; when the device is turned off, a negative voltage signal is applied to the gate G, and a negative current signal is applied to the base B.

[0095] Reference Figure 7 This is a schematic diagram of the carrier transport trajectory of the T-DCT of the present invention during the initial turn-on stage. It can be seen that the current distribution of the T-DCT of the present invention is significantly different from that of existing VUMOS during the initial turn-on stage. When the gate-source voltage is greater than the threshold voltage (V... GS >V TH The base-emitter voltage is greater than the turn-on voltage (V) of the J2 junction (i.e., the emitter junction). BE >V TO (corresponding base current I) B >0), drain-source voltage is greater than zero (V DS When the voltage is greater than 0, two vertical N-channels similar to those in a VUMOS are formed along the surface of the p-body region on the sidewall of the trench gate G. Besides the ability of these N-channels to conduct electron current, the positive bias voltage V applied to the base B also contributes to this effect. BE When the J2 junction (emitter junction) is forward biased, electrons are injected from the n+ source region (emitter region) into the p-body region (p-base region). Some of these electrons recombine with some holes in the p-body region, forming a hole current. Holes that do not recombine enter the n+ source region (emitter region) and flow out from the source (emitter). Unrecombined electrons are swept into the n-drift region by the electric field of the reverse-biased J1 junction (collector junction), drift, and then flow out from the collector, forming the drain (collector) current. Therefore, the current in a T-DCT consists of two parts: one is the electron current communicating with the channel, and the other is the current flowing through the BJT, including both electron and hole currents. Thus, the T-DCT operates in bipolar mode, and a conductivity modulation effect occurs during conduction, resulting in a decrease in on-resistance.

[0096] 2) Taking the 2kV withstand voltage rating as an example, a comparative explanation of relevant characteristics is provided;

[0097] Reference Figure 8 The figures show a comparison of the breakdown characteristics of the T-DCT of this invention and the existing VUMOS. Since both have the same breakdown mechanism, the applied voltage is borne by the J1 junction formed by the p-body region and the n-drift region. Under the same longitudinal structural parameters and a leakage current of 10nA, the breakdown voltage of VUMOS is 2181V, and the breakdown voltage of DCT is 2228V. It can be seen that the breakdown voltage of the T-DCT of this invention is slightly higher than that of VDMOS, and both breakdown voltages meet the 2kV withstand voltage requirement.

[0098] Reference Figure 9 The curves show a comparison of the electric field intensity distribution during breakdown between the T-DCT cell of this invention and the existing VUMOS cell. It can be seen that the electric field within the gate oxide layer during breakdown of the existing VUMOS cell is 6.39 × 10⁻⁶. 6 V / cm, while the electric field within the gate oxide layer during T-DCT cell breakdown in this invention is 2.68 × 10⁻⁶. 6 The electric field strength (V / cm) is 58% lower than that at the gate oxide layer of VDMOS. This indicates that the T-DCT of the present invention can effectively reduce the electric field strength within the gate oxide layer at the bottom of the trench, preventing gate oxide layer breakdown.

[0099] Reference Figure 10 The figure shows a comparison curve of the on-state characteristics of the T-DCT cell of the present invention and the existing VUMOS cell. It can be seen that at a rated current of 60A, the on-resistances of the T-DCT of the present invention and VUMOS are 7.1mΩ and 14.3mΩ, respectively. The on-resistance of the T-DCT of the present invention is reduced by 50% compared to that of VUMOS, and its saturation current is lower than that of VUMOS, which is beneficial for improving short-circuit withstand capability.

[0100] Reference Figure 11 The curves show a comparison of the transfer characteristics of the T-DCT of this invention and existing VUMOS. It can be seen that VUMOS exhibits better transfer characteristics in V... DS =20V, I D The threshold voltage at 50mA is 6.17V; however, in the T-DCT of this invention, when voltage is applied to both the gate (G) and base (B) simultaneously, the threshold voltage is 2.27V. This indicates that adding a base is beneficial for reducing the device's threshold voltage.

[0101] Reference Figure 12 The present invention T-DCT is based on different base steady-state currents I B The conduction characteristic curve is shown below. It can be seen that with I... B Increase, conduction resistance R on It decreases slightly, but at the same time the saturation current increases significantly. When I B When choosing 3A, a lower R can be obtained simultaneously.on and saturation current I Dsat .

[0102] Reference Figure 13 This is a comparison curve of the turn-on characteristics of the T-DCT of this invention and the existing VUMOS under resistive load. It can be seen that under the bus voltage V... DD =1000V, gate resistor R G =2Ω, load resistance R L =16.6Ω, gate-source voltage V GS When turned on under +18V conditions, the rise time t of the existing VUMOS is... r The voltage drop time (i.e., the voltage drop time) is 39.7 ns; the T-DCT of this invention at V DD =1000V, R G =2Ω, R L =16.6Ω,V GS =+18V, base trigger peak current I BP =7A and base steady-state current I B When activated under 2A conditions, the rise time t r It is 28.8 ns, which is better than the current VUMOS. r The reduction of 27.5% indicates that the turn-on characteristics of T-DCT are superior to those of VUMOS.

[0103] Reference Figure 14 The curves show a comparison of the turn-off characteristics of the present invention's T-DCT and existing VUMOS under resistive load. It can be seen that under V... DD =1000V, I DS =60A, R G =2Ω, R L =16.6Ω, V GS When a 60A current is turned off under a voltage of -2V, what is the fall time t of the existing VUMOS? f The voltage rise time (i.e., the voltage rise time) is 23.5 ns; the T-DCT of this invention has a voltage rise time of 23.5 ns. DD =1000V, R G =2Ω, R L =16.6Ω,V GS =-2V, I BO = -5A condition to turn off I DS At a current of 60A, the fall time t f It is 18.5 ns, which is better than the current VUMOS. f The reduction was 21.3%. This indicates that the turn-off characteristics of the T-DCT of this invention are superior to those of VUMOS.

[0104] Reference Figure 15The figure shows a comparison of the short-circuit characteristics of the present invention's T-DCT and the existing VUMOS at a bus voltage of 1000V. It can be seen that the short-circuit withstand time of VUMOS is 3.6μs, while the short-circuit withstand time of the present invention's T-DCT is 4.3μs, an improvement of 19.4%. This is because the present invention's T-DCT has a lower saturation current and a negative base current extraction capability.

[0105] 4) Explanation of the influence trend of the key structural parameters of the DCT of this invention on the properties;

[0106] Reference Figure 16 The present invention relates to T-DCT cells at different gate trench depths (i.e., active region trench depths). TG The curves comparing the conduction characteristics at different depths show that the conduction characteristics increase with the gate trench depth D. TG As D increases, the breakdown voltage decreases. TG The breakdown voltage is highest when the thickness is 1.4μm.

[0107] Reference Figure 17a The present invention relates to T-DCT cells with different N concentrations in the p-floating region. p The breakdown characteristic comparison curve is shown in the figure. Figure 17b The present invention relates to T-DCT cells with different N concentrations in the p-floating region. p A comparison curve of electric field intensity at the breakdown point. It can be seen that, with N... p Increasing N will decrease both the breakdown voltage and the electric field strength within the gate oxide layer. p Take 6×10 17 cm -3 At this time, a higher breakdown voltage can be obtained, and the electric field strength in the gate oxide layer is close to the electric field strength in the depletion layer of the p floating region at the bottom of the trench, indicating that the p floating region at the bottom of the trench can effectively shield the high electric field in the gate oxide layer.

[0108] Reference Figure 18a The present invention relates to T-DCT cells at different p-float regions and depths D. p The breakdown characteristic comparison curve is shown in the figure. Figure 18b The present invention relates to T-DCT cells at different p-float regions and depths D. p A comparison curve of electric field intensity during breakdown. It can be seen that the electric field intensity increases with the depth D of the floating region. p As D increases, the breakdown voltage decreases slightly, while the electric field strength within the gate oxide layer decreases significantly. p When the diameter is 0.6 to 0.7 μm, a higher breakdown voltage can be obtained, and the depletion layer of the p floating region will shield the high electric field in the gate oxide layer.

[0109] Reference Figure 19 The present invention relates to T-DCT with different n+ source region widths W. n+The following is a graph showing the conduction characteristics. It can be seen that, with the n+ source region width W... n+ Increase, conduction resistance R on Slightly increased, while the saturation current I Dsat It will decrease significantly. When W n+ When using 6μm, a lower R can be obtained simultaneously. on and saturation current I Dsat .

[0110] Reference Figure 20 The present invention relates to T-DCT cells with different n+ source regions and p+ regions spacing S. B The comparison curves of the conduction characteristics are shown below; it can be seen that with the distance S between the n+ source region and the p+ region... B As S increases, the on-resistance increases slightly, while the saturation current decreases significantly. B When the thickness is greater than 5μm, the saturation current I Dsat The rate of decline has decreased.

[0111] Reference Figure 21a The curves show a comparison between the terminal breakdown characteristics and the active region breakdown characteristics of the T-DCT of this invention. It can be seen that the active region breakdown voltage of the T-DCT is 2228V, and the terminal breakdown voltage is 2148V, meeting the 2kV withstand voltage requirement. The withstand voltage efficiency reaches 96.4%, while the terminal size is very small.

[0112] Reference Figure 21b This is the transverse electric field intensity distribution curve of the T-DCT of this invention during terminal breakdown. It can be seen that the electric field intensity at the bottom of the active region trench is 2.8 × 10⁻⁶. 6 The electric field strength at the bottom of the terminal trench is 2.1 × 10 V / cm. 6 The electric field strength at the end of the JTE region is 2.4 × 10 V / cm. 6 The value of V / cm indicates that using a T-JTE terminal can effectively reduce the electric field strength of the terminal.

[0113] Reference Figure 22a The present invention relates to T-DCT with different N concentrations in the p-JTE region. JTE The breakdown characteristic curve below; refer to Figure 22b The present invention relates to T-DCT with different N concentrations in the p-JTE region. JTE The transverse electric field intensity distribution curve during lower breakdown. It can be seen that the electric field intensity distribution increases with the concentration of N in the p-JTE region. JTE As N increases, the breakdown voltage increases, the electric field at the bottom of the trench continuously decreases, while the electric field at the end of the p-JTE region continuously increases. JTE Take 3.2 × 10 17 cm -3 The breakdown voltage is 2019V, meeting the 2kV withstand voltage requirement. When N... JTEMore than 3.5×10 17 cm -3 The electric field at the end of the JTE increases and exceeds the electric field of the active region, causing it to break down first.

[0114] Reference Figure 23a The present invention relates to T-DCT at different p-JTE region junction depths. JTE The breakdown characteristic curve below; refer to Figure 23b The junction depth D of T-DCT in different p-JTE regions is the same as that of the present invention. JTE The transverse electric field intensity distribution curve during lower breakdown. It can be seen that the electric field intensity distribution increases with the junction depth D in the p-JTE region. JTE As the junction depth increases, the breakdown voltage initially increases and then decreases, the electric field at the bottom of the trench decreases, and the electric field at the end of the p-JTE region increases. When the junction depth of the p-JTE region is 0.4–0.6 μm, the breakdown voltage meets the 2kV withstand voltage requirement.

[0115] Reference Figure 24a The width W of the T-DCT in different p-JTE regions of this invention is... JTE The breakdown characteristic curve below; reference Figure 24b The width W of the T-DCT in different p-JTE regions of this invention is... JTE The electric field intensity distribution curve during lower breakdown. It can be seen that, with the width W of the p-JTE region... JTE As the voltage increases, the breakdown voltage increases slowly, the electric field at the bottom of the trench gradually decreases, while the electric field at the end of the p-JTE region remains unchanged. When the length of the JTE region is 15–30 μm, the 2kV withstand voltage requirement is met.

[0116] Secondly, embodiments of the present invention provide a method for fabricating a trench-gate dual-control electrode 4H-SiC composite transistor structure, such as... Figure 25 As shown, the following steps may be included:

[0117] S1, on a 4H-SiC n+ substrate, an n buffer layer, an n- drift region, an n carrier extension layer, a p-body region and an n+ source region are grown sequentially using an epitaxial process;

[0118] Among them, the first choice is crystal orientation as <0001> The n+ type 4H-SiC substrate was obtained by etching and in-situ cleaning the surface.

[0119] Then, on a 4H-SiC n+ substrate, an n-buffer layer, an n-drift region, an n-carrier extension layer, a p-body region, and an n+ source region are sequentially grown using epitaxial technology. The thickness of each layer can be set as needed.

[0120] Both the P-body region and the n+ source region are formed through epitaxial processes and are uniformly doped. By controlling the thickness and concentration of the epitaxial layer in the p-body region, the channel length and threshold voltage can be precisely controlled.

[0121] In a preferred embodiment, the width W of the n+ source region n+ The thickness D of the n+ source region is 5–7 μm. n+ The thickness is 0.3–0.5 μm;

[0122] The crystal structure obtained in this step can be found in [link / reference]. Figure 26a As shown.

[0123] S2, dry etching process is used to etch both sides of the n+ source region to form a mesa structure between the n+ source region and the p body region;

[0124] Specifically, a silicon dioxide masking film is deposited on the upper surface of the crystal obtained in S1, and dry etching is performed on both sides of the n+ source region on the upper surface of the crystal to form a mesa structure of the n+ source region and the p-body region. The over-etching of the n+ source region is controlled to be within 10% of its depth.

[0125] The crystal structure obtained in this step can be found in [link / reference]. Figure 26b As shown (for simplicity, the silicon dioxide film on the upper surface of the crystal is not shown).

[0126] S3, using a dry etching process, the n+ source region is etched downwards into the n- drift region to form an active region trench, and the p-body region at the edge is etched downwards into the n- drift region to form a terminal region trench;

[0127] Specifically, S3 may include:

[0128] S31, remove the silicon dioxide film on the current crystal surface, re-deposit a silicon dioxide masking film, and perform secondary dry etching on the crystal surface, including etching the n+ source region downwards into the n- drift region to form an active region trench, and simultaneously etching the p-body region at the edge downwards into the n- drift region to form a terminal region trench.

[0129] In one preferred embodiment, the width W of the active area trench TG The depth D of the active region trench is 2–3 μm. TG The depth of the trench in the terminal region is 1.4–2 μm;

[0130] S32, remove the silicon dioxide covering film on the current crystal surface and perform NO / N2O nitriding treatment to remove the damage caused by surface etching and reduce surface states.

[0131] As can be seen, the present invention performs only one NO / N2O nitriding treatment after all etching is completed, which can not only remove the damage caused by surface etching to reduce interface states, but also simplify the process and reduce costs.

[0132] The crystal structure obtained in this step can be found in [link / reference]. Figure 26c As shown.

[0133] S4, perform multiple aluminum ion coverage implantations on the active area trench to form a p-floating area at the bottom of the active area trench, and make the outer side of the p-floating area rounded around the corner of the active area trench.

[0134] Specifically, a 30-50 nm silicon dioxide cover film is deposited on the upper surface of the current crystal, and photoresist is applied as a masking film. At room temperature, aluminum ion implantation is performed on the bottom of the active region trench multiple times. By adjusting the implantation dose and energy, a p-floating region is formed at the bottom of the active region trench, and the outer side of the p-floating region is made to wrap around the corner of the active region trench in an arc shape.

[0135] In a preferred embodiment, the concentration N in the p-floating region p 5×10 17 cm -3 ~6×10 17 cm -3 The depth D of the p floating zone p It is 0.6–0.7 μm.

[0136] The crystal structure obtained in this step can be found in [link / reference]. Figure 26d As shown (for simplicity, the silicon dioxide film on the upper surface of the crystal is not shown).

[0137] S5, perform multiple aluminum ion covering implantations on the bottom of the terminal area trench to form a p-junction terminal extension area at the bottom of the terminal area trench, and make the outer side of the p-junction terminal extension area rounded around the corner of the terminal area trench.

[0138] Specifically, the silicon dioxide capping film on the current crystal surface is removed, and a 30-50 nm silicon dioxide capping film is re-deposited. Photoresist is applied as a masking film, and aluminum ion implantation is performed multiple times at room temperature to cover the bottom of the terminal trench. At the same time, the implantation dose and energy are adjusted to form a p-junction terminal extension region at the bottom of the terminal trench, and the outer side of the p-junction terminal extension region is made to surround the corner of the terminal trench in an arc shape.

[0139] In a preferred embodiment, the concentration N of the p-junction terminal extension region is... JTE 3.2×10 17 ~3.6×10 17 cm -3 The depth D of the p-junction terminal extension regionJTE The width W of the p-junction termination extension region is 0.4–0.6 μm. JTE The diameter is 20–35 μm. The p-junction termination extension region is referred to as the p-JTE region.

[0140] The crystal structure obtained in this step can be found in [link / reference]. Figure 26e As shown (for simplicity, the silicon dioxide film on the upper surface of the crystal is not shown).

[0141] S6, aluminum ions are implanted into the outer surface edge region of the p-body region that has a gap with the n+ source region to form the p+ region, and then subjected to high-temperature annealing;

[0142] Specifically, the silicon dioxide capping film on the current crystal surface is removed, and a 30-50 nm silicon dioxide capping film and a polysilicon masking film are re-deposited. Polysilicon is etched at the edge of the outer surface of the p-body region with a gap from the n+ source region to form a p+ region implantation window. Then, aluminum ion implantation is performed at 500 °C to form the p+ region.

[0143] The high-temperature annealing is performed at 1700°C. In a preferred embodiment, the distance S between the n+ source region and the p+ region is... B The doping concentration is 3–5 μm; the doping concentration of the p+ region after high-temperature annealing is 3 × 10⁻⁶. 19 ~5×10 19 cm -3 This is a high-concentration injection.

[0144] The crystal structure obtained in this step can be found in [link / reference]. Figure 26f As shown (for simplicity, the silicon dioxide film on the upper surface of the crystal is not shown).

[0145] S7, a gate oxide layer is prepared on the side and bottom of the active region trench by thermal oxidation, and then polysilicon is deposited and heavily doped to fill the active region trench to form the trench gate G.

[0146] Specifically, S7 may include:

[0147] S71, remove the silicon dioxide covering film on the surface of the current crystal and deposit a carbon film. Under the protection of the carbon film, perform high-temperature annealing at 1700℃ to activate impurities, eliminate damage caused by ion implantation, and prevent impurities from overflowing.

[0148] S72, after removing the carbon film and damage from the current crystal surface, high-temperature thermal oxidation is performed at 1250℃ to form a gate oxide layer on the sides and bottom of the active region trench. Then, polysilicon is deposited and heavily doped to fill the active region trench, forming the polysilicon trench gate G; wherein the doping concentration is 5×10⁻⁶. 19 cm -3 above;

[0149] The crystal structure obtained in this step can be found in [link / reference]. Figure 26g As shown.

[0150] S8, deposit an oxide film and a borosilicate glass layer on the surface of the active region trench, and form source and base metal contact holes by photolithography; then deposit nickel metal, and after high-temperature annealing, form an ohmic contact for the source S on the surface of the n+ source region and an ohmic contact for the base B on the surface of the p+ region; then remove the nickel metal layer on the surface of the borosilicate glass using a lift-off process; and etch out the gate bonding hole, deposit titanium metal, titanium nitride and aluminum copper film in sequence, and then reverse etch to form the source, base and gate metal electrodes, and perform rapid annealing to complete the surface metal electrode preparation;

[0151] This high-temperature annealing step was performed at 1700℃. The resulting crystal structure can be found in [link to crystal structure]. Figure 26h As shown.

[0152] S9, deposit silicon nitride film and photolithography to passivate the terminal area on the chip surface; then coat polyimide film, photolithography to form the surface source, gate and base bonding area pattern, and perform imidization treatment to form the front terminal passivation and protective layer to complete the device surface passivation treatment.

[0153] S10, the lower surface of the 4H-SiC n+ substrate is thinned, and titanium, nickel and silver are sputtered sequentially to prepare the drain electrode D. Then, laser annealing is performed to reduce the ohmic contact resistance and complete the preparation of the back metal electrode.

[0154] Through the above steps, the trench gate dual-controller 4H-SiC composite transistor is successfully fabricated.

[0155] The chip then needs to be diced, packaged, and tested.

[0156] The design features of the above-mentioned process flow of the present invention are as follows:

[0157] In S1, both the P-body region and the n+ source region are formed by epitaxial processes and are uniformly doped. By controlling the thickness and concentration of the epitaxial layer in the p-body region, the channel length and threshold voltage can be precisely controlled.

[0158] First, the p-body region mesa etching is performed (involving step S2), then the active region trench etching and the terminal region trench etching are performed simultaneously (involving step S31), and only one NO / N2O nitriding treatment is performed after all etching is completed (involving step S32). This not only removes the damage caused by surface etching to reduce interface states, but also simplifies the process flow and reduces costs.

[0159] All ion implantations (involving steps S4, S5 and S6) use a 30-50 nm silica overlay film, which not only avoids crystal damage caused by ion implantation, but also shifts the peak implantation concentration to the crystal surface.

[0160] After all ion implantation, only one high-temperature annealing treatment is performed under carbon film protection (involving step S71). This not only activates impurities, eliminates damage caused by ion implantation, and prevents impurity overflow, but also simplifies the process and reduces costs.

[0161] Multiple aluminum ion implantations are performed on the bottom of the trench, with adjustments to the implantation dose and energy, to form a p-floating region at the bottom of the active region trench or a p-junction terminal extension region at the bottom of the terminal region trench. The outer side of the p-floating region or p-junction terminal extension region is then rounded to enclose the corners of the active region trench or terminal region trench. This significantly reduces the electric field within the oxide layer at the trench corners, preventing gate oxide breakdown at the active region trench corners or breakdown at the terminal trench corners.

[0162] Over-etching of the n+ source region needs to be controlled within 10% of its depth to prevent the p-body region from becoming too thin and causing through-through (related to step S2).

[0163] The device fabricated by the trench gate dual-control electrode 4H-SiC composite transistor structure provided in this embodiment of the invention can not only improve the contradiction between on-resistance and breakdown voltage, but also reduce the electric field strength in the gate oxide layer and increase the short-circuit withstand time, thereby improving the characteristics and reliability of the device. At the same time, the size of the terminal region is reduced and it is compatible with the active region process, which reduces the cost.

[0164] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A trench-gate dual-control electrode 4H-SiC composite transistor structure, characterized in that, It consists of an active region formed by multiple parallel central cell structures and an outer trench-junction terminal extension composite terminal region. The cell structure includes: an n-buffer layer, an n-drift region, an n-carrier extension layer, a p-body region, and an n+ source region sequentially disposed on a 4H-SiC n+ substrate; an active region trench is disposed in the center of the cell structure, extending downward from the n+ source region into the n-drift region; a p-floating region with an outer arc shape is disposed below the active region trench, its arc edge wrapping around the corner of the active region trench; the sides and bottom of the active region trench are covered with a gate oxide layer, and the interior is filled with heavily doped polysilicon as the trench gate G; the n+ source region and p-body region on each side form a mesa structure, and a p+ region is disposed in the top layer region near the outer edge of the p-body region below the mesa structure on each side, with a spacing between it and the n+ source region on the same side; a source electrode S is disposed on the surface of the n+ source region; a base electrode B is disposed on the surface of the p+ region; the surface of the active region trench is covered with a phosphorus silicon glass layer to isolate the trench gate G from the source electrode S; the 4H-SiC The back side of the n+ substrate has a drain D; the trench gate G and the base B are both control electrodes; the cell structure is symmetrical about the central trench gate G, which is equivalent to the parallel connection of VUMOS and BJT. The trench-junction terminal extension composite terminal region is connected to the corresponding layer of the outermost cell structure of the active region, including an n-buffer layer, an n-drift region, an n-carrier extension layer, a p-body region, and a drain D on the back side of the 4H-SiC n+ substrate, which are sequentially arranged on the 4H-SiC n+ substrate. The p-body region, the n-carrier extension layer, and a portion of the n-drift region, together with the remaining portion of the n-drift region, form a mesa structure as a terminal trench. A p-junction terminal extension region is provided in a local area of ​​the n-drift region at the corner below the terminal trench. The side of the p-junction terminal extension region near the terminal trench is arc-shaped and wraps around the corner of the terminal trench.

2. The trench gate dual-control electrode 4H-SiC composite transistor structure according to claim 1, characterized in that, For the trench-junction terminal extension composite terminal region and the outermost cell structure of the connected active region, there are naturally formed longitudinal resistance regions in the p-body region, n-carrier extension layer and n-drift region of the trench sidewall of the terminal region.

3. The trench gate dual-control electrode 4H-SiC composite transistor structure according to claim 1, characterized in that, In the trench gate dual-controllable-electrode 4H-SiC composite transistor structure, the n-drift region of the VUMOS is equivalent to the n-collector region of the BJT, the p-body region of the VUMOS is equivalent to the p-base region of the BJT, the n+ source region of the VUMOS is equivalent to the n+ emitter region of the BJT, and the 4H-SiC n+ substrate of the VUMOS is equivalent to the collector ohmic contact region of the BJT. The source S of the VUMOS is also the emitter E of the BJT, and the drain D of the VUMOS is also the collector C of the BJT. The turn-on and turn-off of the VUMOS and the BJT are controlled by the gate G and the base B, respectively.

4. The trench gate dual-control electrode 4H-SiC composite transistor structure according to claim 1, characterized in that, When the trench gate dual-controllable electrode 4H-SiC composite transistor is turned on, by applying a gate voltage to the trench gate G, which serves as one control electrode, and applying a base current to the base B, which serves as the other control electrode, the VUMOS and BJT are simultaneously turned on, so that the n-drift region generates a conductivity modulation effect, and the entire device operates in bipolar mode.

5. The trench gate dual-control electrode 4H-SiC composite transistor structure according to claim 1, characterized in that, In the cellular structure The width W of the active region trench TG The depth D of the active region trench is 2–3 μm. TG Its diameter is 1.4–2 μm; The concentration N in the p-floating zone p 5×10 17 cm -3 ~6×10 17 cm -3 The depth D of the p floating zone p The thickness is 0.6–0.7 μm; The width W of the n+ source region n+ The thickness D of the n+ source region is 5–7 μm. n+ The distance between the n+ source region and the p+ region is 0.3–0.5 μm; B It is 3–5 μm.

6. The trench gate dual-control electrode 4H-SiC composite transistor structure according to claim 1, characterized in that, In the trench-junction terminal extension composite terminal area The depth of the trench in the terminal region is 1.7–2.5 μm; the concentration of N in the p-junction terminal extension region is... JTE 3.2×10 17 ~3.6×10 17 cm -3 The junction depth D of the p-junction terminal extension region JTE The width W of the p-junction termination extension region is 0.4–0.6 μm. JTE It is 20–35 μm.

7. A method for fabricating a trench gate dual-control electrode 4H-SiC composite transistor structure, characterized in that, include: On a 4H-SiC n+ substrate, an n buffer layer, an n-drift region, an n-carrier extension layer, a p-body region, and an n+ source region are sequentially grown using epitaxial technology. Dry etching process is used to etch both sides of the n+ source region to form a mesa structure between the n+ source region and the p-body region; Using a dry etching process, the n+ source region is etched downwards into the n- drift region to form an active region trench, and the p-body region at the edge is etched downwards into the n- drift region to form a terminal region trench. Multiple aluminum ion covering implantations are performed on the active area trench to form a p-floating area at the bottom of the active area trench, and the outer side of the p-floating area is made to wrap around the corner of the active area trench in an arc shape. Multiple aluminum ion covering implants are performed on the bottom of the terminal trench to form a p-junction terminal extension region at the bottom of the terminal trench, and the outer side of the p-junction terminal extension region is made to encircle the corner of the terminal trench in an arc shape. Aluminum ions are implanted into the outer surface edge region of the p-body region, which has a gap with the n+ source region, to form the p+ region, and then subjected to high-temperature annealing. A gate oxide layer is prepared on the side and bottom of the active region trench by thermal oxidation, and then polysilicon is deposited and heavily doped to fill the active region trench to form the trench gate G. An oxide film and a borosilicate glass layer are deposited on the surface of the active region trench, and source and base metal contact holes are formed by photolithography. After further depositing metallic nickel and annealing at high temperature, an ohmic contact for the source S is formed on the surface of the n+ source region, and an ohmic contact for the base B is formed on the surface of the p+ region; then, the metallic nickel layer on the surface of the borosilicate glass is removed using a stripping process. The gate bonding holes are etched out, and titanium metal, titanium nitride and aluminum copper film are deposited in sequence. Then, the source, base and gate metal electrodes are formed by reverse etching, and rapid annealing is performed to complete the surface metal electrode preparation. Silicon nitride film is deposited and photolithography is performed to passivate the terminal area on the chip surface; then polyimide film is coated, and photolithography is used to form the bonding area pattern of the source, gate and base regions on the surface, and imidization treatment is performed to form the front terminal passivation and protective layer to complete the device surface passivation treatment. The lower surface of the 4H-SiC n+ substrate is thinned, and titanium, nickel, and silver are sputtered sequentially to prepare the drain electrode D. Then, laser annealing is performed to reduce the ohmic contact resistance, thus completing the preparation of the back metal electrode.

8. The method for fabricating the trench gate dual-control electrode 4H-SiC composite transistor structure according to claim 7, characterized in that, Multiple aluminum ion implantations are performed on the active region trench to form a p-floating region at the bottom of the active region trench, and the outer side of the p-floating region is rounded to surround the corner of the active region trench, including: On the upper surface of the current crystal, a 30-50 nm silicon dioxide capping film is deposited, and photoresist is coated as a masking film. Multiple aluminum ion implantations are performed on the bottom of the active region trench at room temperature. By adjusting the implantation dose and energy, a p-floating region is formed at the bottom of the active region trench, and the outer side of the p-floating region is rounded to surround the corner of the active region trench. The concentration N of the p-floating region is... p 5×10 17 cm -3 ~6×10 17 cm -3 The depth D of the p floating zone p It is 0.6–0.7 μm.

9. The method for fabricating the trench gate dual-control electrode 4H-SiC composite transistor structure according to claim 8, characterized in that, Multiple aluminum ion implantations are performed on the bottom of the terminal trench to form a p-junction terminal extension region at the bottom of the terminal trench, and the outer side of the p-junction terminal extension region is rounded to surround the corner of the terminal trench, including: The current silicon dioxide capping film on the upper surface of the crystal is removed, and a new 30-50 nm silicon dioxide capping film is deposited. Photoresist is applied as a masking film. Multiple aluminum ion implantations are performed on the bottom of the terminal trench at room temperature, while adjusting the implantation dose and energy to form a p-junction terminal extension region at the bottom of the terminal trench. The outer side of the p-junction terminal extension region is rounded to surround the corner of the terminal trench. The concentration N of the p-junction terminal extension region is... JTE 3.2×10 17 ~3.6×10 17 cm -3 The junction depth D of the p-junction terminal extension region JTE The width W of the p-junction termination extension region is 0.4–0.6 μm. JTE It is 20–35 μm.

10. The method for fabricating the trench gate dual-control electrode 4H-SiC composite transistor structure according to claim 9, characterized in that, Aluminum ions are implanted into the outer surface edge region of the p-body region, which has a gap with the n+ source region, to form the p+ region, including: Remove the silicon dioxide capping film on the surface of the current crystal, re-deposit the silicon dioxide capping film and the polysilicon masking film, etch the polysilicon at the edge of the outer surface of the p-body region with a gap from the n+ source region to form the p+ region implantation window, and then perform aluminum ion implantation at 500°C to form the p+ region. The doping concentration of the p+ region after annealing is 3×10⁻⁶. 19 ~5×10 19 cm -3 .

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