Array substrate, display panel and display device

Abstract

The embodiment of the invention provides an array substrate, a display panel and a display device, relates to the technical field of display, and is used for reducing the risk of negative bias of a thin film transistor, reducing the size of the thin film transistor and improving the aperture opening ratio of the array substrate. The array substrate includes a substrate, a plurality of first semiconductor patterns, and a gate conductive layer. The plurality of first semiconductor patterns are arranged on one side of the substrate and comprise channel parts, first electrode parts and second electrode parts, the first electrode parts and the second electrode parts are located on the two opposite sides of the channel parts and integrally arranged with the channel parts, and the first electrode parts and the second electrode parts are more conductive compared with the channel parts. The gate conductive layer is arranged on the side, away from the substrate, of the first semiconductor pattern, and the orthographic projection of the gate conductive layer on the substrate covers the orthographic projection of the channel part on the substrate. A groove is formed in the surface, away from the substrate, of at least one of the first electrode part and the second electrode part, and the orthographic projection of the groove on the substrate does not coincide with the orthographic projection of the gate conductive layer on the substrate. The array substrate is used for manufacturing the display panel.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] With the continuous development of display technology, display devices (such as mobile phones, televisions, computers, etc.) have been widely used. People's requirements for display devices are getting higher and higher. High resolution and high refresh rate are an important development direction of display devices. Among them, liquid crystal display panels have outstanding advantages in preparation cost and difficulty, and thanks to the simpler pixel circuit structure of liquid crystal display panels, the pixel circuit contains fewer thin film transistors (such as one thin film transistor) and capacitors. Liquid crystal display panels have good development prospects at ultra-high pixel density (such as greater than or equal to 1000PPI).

[0003] A pixel circuit may include at least one thin film transistor. As the pixel density of a display panel increases, the size of the thin film transistor also tends to be miniaturized, that is, the size of the semiconductor layer of the thin film transistor (the size of the channel structure) decreases with the increase of the pixel density, which leads to an increasing possibility of negative bias in the thin film transistor. How to reduce the risk of negative bias in the thin film transistor has become a key factor restricting the further reduction of the size of the thin film transistor. Summary of the invention

[0004] The purpose of the embodiments of the present disclosure is to provide an array substrate, a display panel and a display device, which are used to reduce the risk of negative bias of thin film transistors, reduce the size of thin film transistors and increase the aperture ratio of the array substrate.

[0005] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0006] On the one hand, an array substrate is provided. The array substrate includes a substrate, a plurality of first semiconductor patterns and a gate conductive layer. The plurality of first semiconductor patterns are arranged on one side of the substrate, the first semiconductor pattern includes a channel portion and a first electrode portion and a second electrode portion located on both sides of the channel portion and integrally arranged with the channel portion, the first electrode portion and the second electrode portion being more conductive than the channel portion. The gate conductive layer is arranged on a side of the first semiconductor pattern away from the substrate, the orthographic projection of the gate conductive layer on the substrate covering the orthographic projection of the channel portion on the substrate. At least one of the first electrode portion and the second electrode portion is provided with a groove on a surface away from the substrate, the orthographic projection of the groove on the substrate not overlapping with the orthographic projection of the gate conductive layer on the substrate.

[0007] In the array substrate provided by the embodiment of the present disclosure, the gate conductive layer is arranged on the side of the first semiconductor pattern away from the substrate, and the first semiconductor pattern can be used to form a top-gate transistor. The first electrode portion and the second electrode portion are more conductive than the channel portion. For example, the channel portion, the first electrode portion and the second electrode portion include the same semiconductor material. Unlike the channel portion, the first electrode portion and the second electrode portion are subjected to a process (such as doping) to make them more conductive to form a conductor. At least one of the first electrode portion and the second electrode portion has at least one groove on the surface away from the substrate, and the orthographic projection of the gate conductive layer on the substrate does not overlap with the orthographic projection of the groove on the substrate, that is, the gate conductive layer does not block the groove. The groove can increase the surface area of ​​the first electrode portion and the second electrode portion (at least one of which is provided with the groove) away from the substrate. In the process of doping the first semiconductor pattern with the gate conductive layer as a mask, the groove is beneficial to increase the diffusion path of the doped ions, and enhance the diffusion effect of the doped ions in the first electrode portion and the second electrode portion, thereby reducing the degree of diffusion of the doped ions toward the side close to the channel portion, which is beneficial to increase the interval between the first electrode portion and the second electrode portion, that is, to increase the length of the channel portion. In this way, not only can the risk of negative bias in the channel portion be reduced, but it is also beneficial to reduce the size of the first semiconductor pattern, thereby increasing the size of the transistor formed by the first semiconductor pattern, and improving the aperture ratio and pixel density of the array substrate.

[0008] In some embodiments, a portion where orthographic projections of the gate conductive layer and the first semiconductor pattern on the substrate overlap with each other has a dimension along the length direction of the channel portion that is greater than or equal to 3 μm.

[0009] In some embodiments, the groove is provided on the surface of the first electrode portion away from the substrate, the orthographic projection of the first electrode portion on the substrate partially overlaps with the orthographic projection of the gate conductive layer on the substrate, and the size of the overlapped portion of the first electrode portion and the gate conductive layer along the first direction is less than or equal to 2μm; the first direction is perpendicular to the boundary extension direction of the gate conductive layer. And / or, the groove is provided on the surface of the second electrode portion away from the substrate, the orthographic projection of the second electrode portion on the substrate partially overlaps with the orthographic projection of the gate conductive layer on the substrate, and the size of the overlapped portion of the second electrode portion and the gate conductive layer along the first direction is less than or equal to 2μm.

[0010] In some embodiments, at least one groove is provided on a surface of the first electrode portion away from the substrate, and the groove penetrates the first electrode portion along a second direction, and the second direction is perpendicular to the extension direction of the first electrode portion. At least one groove is provided on a surface of the second electrode portion away from the substrate, and the groove penetrates the second electrode portion along a third direction, and the third direction is perpendicular to the extension direction of the second electrode portion.

[0011] In some embodiments, a plurality of grooves are disposed on surfaces of the first electrode portion and the second electrode portion away from the substrate, and the plurality of grooves are distributed at intervals.

[0012] In some embodiments, a protrusion is formed between adjacent grooves. The array substrate further includes a gate insulating layer, the gate insulating layer is disposed between the first semiconductor pattern and the gate conductive layer, and includes a first pad, the first pad is disposed on a side of the protrusion away from the substrate. The gate conductive layer further includes a second pad, the second pad is disposed on a side of the first pad away from the substrate. The orthographic projections of the first pad and the second pad on the substrate are both located within the range of the orthographic projection of the protrusion on the substrate.

[0013] In some embodiments, a material of the first semiconductor pattern includes an oxide semiconductor material.

[0014] In some embodiments, the gate conductive layer includes a gate line, and an angle between a length direction of the channel portion and an extension direction of the gate line is less than 90°.

[0015] In some embodiments, a depth of the first groove is D1, a thickness of the first semiconductor pattern is D2, and 1 / 3D2≤D1≤1 / 3D2.

[0016] In some embodiments, the array substrate further includes a first conductive layer, a first insulating layer and a first via. The first conductive layer is disposed on a side of the first semiconductor pattern close to the substrate, and includes a light shielding pattern and a first signal line that are spaced apart, and the orthographic projection of the light shielding pattern on the substrate covers the orthographic projection of the channel portion on the substrate. The first insulating layer is disposed between the first conductive layer and the first semiconductor pattern. The first via at least penetrates the first insulating layer and exposes a portion of the first signal line. The gate conductive layer further includes a connecting electrode, which is at least partially located in the first via and is electrically connected to the first electrode portion and the first signal line, respectively.

[0017] On the other hand, a display panel is provided. The display panel comprises an array substrate, an opposing substrate and a liquid crystal layer as described in any of the above embodiments. The opposing substrate is arranged opposite to the array substrate. The liquid crystal layer is arranged between the array substrate and the opposing substrate.

[0018] In another aspect, a display device is provided, wherein the display device comprises the array substrate as described in any of the above embodiments, or the display device comprises the display panel as described above.

[0019] The above-mentioned display panel and display device have the same structure and beneficial technical effects as the array substrate provided in some of the above-mentioned embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0021] Figure 1 is a structural diagram of a display device according to some embodiments;

[0022] Figure 2 is a structural diagram of a display device according to some embodiments;

[0023] Figure 3 A structural diagram of a thin film transistor provided for related technology;

[0024] Figure 4 is a planar structural diagram of a thin film transistor according to some embodiments;

[0025] Figure 5 is a structural diagram of an array substrate according to some embodiments;

[0026] Figure 6 is another planar structural diagram of a thin film transistor according to some embodiments;

[0027] Figure 7 is another structural diagram of an array substrate according to some embodiments;

[0028] Figure 8 to Figure 13 FIG. 1 is a diagram of the process steps for preparing an array substrate according to some embodiments. DETAILED DESCRIPTION

[0029] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0030] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0031] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0032] When describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0033] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0034] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0035] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0036] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0037] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0038] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism may be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, the difference between the two equalities is less than or equal to 5% of either one.

[0039] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0040] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0041] The embodiment of the present disclosure provides a display device, referring to Figure 1 The display device 1000 is a product having an image display function. Exemplarily, the display device 1000 may be any device that displays either motion (eg, video) or fixed (eg, still image) and either text or image.

[0042] In some embodiments, the display device may be an augmented reality (AR) device, a virtual reality (VR) device, or a mixed reality (MR) device. Alternatively, in some other embodiments, the display device may also be a television, a laptop, a tablet computer, a personal digital assistant (PDA), a mobile phone (cell phone), a watch, a clock, a calculator, a GPS receiver / navigator, a camera, a display of a camera view (e.g., a display of a rear-view camera in a vehicle), a wearable device, a vehicle display, a flight display, or any other product or component with a display function. In one example, the display device provided in an embodiment of the present disclosure may be an AR device, a VR device, or an MR device, etc., which generally has a higher pixel density, such as a pixel density of an AR device, a VR device, or an MR device may be greater than 1000PPI, 1500PPI, or 2000PPI, etc.

[0043] In some embodiments, from the perspective of the light-emitting type of the display device 1000, the display device 1000 may be an organic light-emitting diode display device (OLED) or a liquid crystal display device (LCD). From the perspective of the form of the display device 1000, the display device 1000 may be a flat display device or a curved display device. From the perspective of the shape of the display device 1000, the display device 1000 may be rectangular or circular. Some embodiments of the present disclosure are schematically described below using a rectangular and flat liquid crystal display device as an example, but the embodiments of the present disclosure are not limited thereto, and any other display device may also be considered as long as the same technical concept is applied.

[0044] In some embodiments, see Figure 2, the display device 1000 includes a display panel 1100 and a driving circuit board (not shown in the figure). The driving circuit board may include, for example, a timing controller (Timing Controller, referred to as: TCON), a power management chip (DC / DC) and an adjustable resistor divider circuit (generating Vcom) and other driving circuits. Of course, the driving circuit board may also include other circuit structures, which are not listed here one by one. The driving circuit board is electrically connected to the display panel 1100, and is used to transmit a control signal to the display panel 1100 to drive the display panel 1100 to realize image display. In addition, the display device 1000 may also include but is not limited to a touch structure, an under-screen camera, and an under-screen fingerprint recognition sensor, so that the display device 1000 can realize a variety of different functions such as touch, photo taking, video recording or fingerprint recognition, which are not listed here one by one.

[0045] Continue reading Figure 2 In the case where the display device 1000 is a liquid crystal display device, the display device 1000 may further include a backlight module 1200 disposed on the backlight side of the display panel 1100. Exemplarily, the backlight module 1200 may be a direct-type backlight module or an edge-type backlight module, etc., and the backlight module 1200 is used to provide a light source for the display panel 1100. The display panel 1100 includes a plurality of sub-pixels, each of which can adjust the amount of light passing through the display panel 1100, thereby making each sub-pixel display the same or different grayscales to achieve the purpose of image display.

[0046] In the case where the display panel 1100 is a liquid crystal display panel, Figure 2 , the display panel 1100 may include an array substrate 100 and an opposing substrate 200 that are arranged opposite to each other, and a liquid crystal layer 300 disposed between the array substrate 100 and the opposing substrate 200. Among them, the opposing substrate 200 may also be called a color filter substrate or a packaging substrate. In an example, the opposing substrate 200 may filter the light incident on the opposing substrate 200 so that each sub-pixel emits a light of a color (such as red, green or blue), and different sub-pixels may emit light of the same or different colors, thereby enabling the display panel 1100 to achieve color display. Of course, the structure of the display panel 1100 is not limited to this, and the display panel 1100 may also include other structures, as long as the same technical ideas are adopted. For example, the display panel 1100 may also include a first alignment film (not shown in the figure) disposed on a side of the array substrate 100 close to the liquid crystal layer 300, and a second alignment film (not shown in the figure) disposed on a side of the opposing substrate 200 close to the liquid crystal layer 300, etc.

[0047] In the case where the display panel 1100 is an organic light emitting diode display panel, the display panel may include an array substrate, a light emitting device disposed on the array substrate, and an encapsulation layer, etc. Exemplarily, the light emitting device may include, for example, an anode layer, a light emitting functional layer, and a cathode layer that are stacked, and the display panel may also include other structures, which will not be described one by one here.

[0048] Hereinafter, the present disclosure will be described exemplarily by taking a liquid crystal display panel as an example.

[0049] In some embodiments, the array substrate 100 may include a plurality of pixel circuits, and the pixel circuit may include at least one thin film transistor (TFT) and at least one capacitor. For example, the pixel circuit may be a "1T1C" circuit or a "3T1C" circuit, etc., wherein "T" refers to a thin film transistor, and the number before "T" refers to the number of thin film transistors; "C" refers to a capacitor, and the number before "C" refers to the number of capacitors.

[0050] Thanks to the simpler pixel circuit structure of the liquid crystal display panel, the liquid crystal display panel has good application prospects in the field of ultra-high PPI (for example, greater than 1000PPI) display. In one embodiment, the pixel circuit can be a "1T1C" circuit. In this case, the pixel circuit can include a thin film transistor and a capacitor. The capacitor can be a capacitor formed between the pixel electrode and the common electrode. The "1T1C" circuit can greatly reduce the number of thin film transistors included in the pixel circuit, reduce the space occupied by the pixel circuit, and help to improve the aperture ratio of the array substrate, thereby improving the pixel density of the array substrate.

[0051] See also Figure 3 The thin film transistor may include a semiconductor pattern 101 and a gate 102 disposed on a side of the semiconductor pattern 101 away from the substrate 10. The manufacturing process of the thin film transistor may include sequentially forming the semiconductor pattern 101 and the gate 102, and then performing a conductorization (such as doping) process on the semiconductor pattern 101 using the gate 102 as a mask. Figure 3In the embodiment, different filling patterns are used in different areas of the semiconductor pattern 101, and different filling patterns only represent the conductive part and the non-conductive part thereof. During the conductive process, the doped ions will diffuse laterally, causing some of the doped ions to diffuse to the lower side of the gate 102; that is, some areas of the semiconductor pattern 101 opposite to the gate 102 will also be doped as conductors. For example, the width of the area of ​​the semiconductor pattern 101 opposite to the gate 102 and doped as a conductor is ΔD. As the display device develops towards high PPI, the size D3 of the gate 102 is getting smaller and smaller, and the width D4 of the channel part of the semiconductor pattern 101 that is actually kept as a semiconductor is getting smaller and smaller, which may cause the characteristics of the thin film transistor to be negatively biased. In order to avoid the occurrence of this problem, the related art usually sets a larger gate 102 and a semiconductor pattern 101, which is not conducive to improving the pixel density and aperture ratio of the array substrate.

[0052] To overcome at least one of the above technical problems, see Figure 4 and Figure 5 The present disclosure provides an array substrate 100 including a substrate 10, a plurality of first semiconductor patterns 20 and a gate conductive layer 30. The plurality of first semiconductor patterns 20 are disposed on one side of the substrate 10, and the first semiconductor pattern 20 includes a channel portion 23 and a first electrode portion 21 and a second electrode portion 22 located on both sides of the channel portion 23 and integrally disposed with the channel portion 23, and the first electrode portion 21 and the second electrode portion 22 are more conductive than the channel portion 23.

[0053] In some embodiments, the material of the first semiconductor pattern 20 includes an oxide semiconductor material. That is, the thin film transistor (hereinafter referred to as the first transistor) formed by the first semiconductor pattern 20 is an oxide thin film transistor (Oxide Thin-film transistor, referred to as OTFT). The oxide thin film transistor has the characteristic of low leakage current, which is conducive to reducing the leakage current of the thin film transistor, thereby simplifying the circuit structure of the pixel circuit, thereby improving the aperture ratio of the array substrate 100 and improving the light transmittance of the array substrate 100.

[0054] The oxide semiconductor material may include metal oxides, including but not limited to: indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxide (In-free OS), rare earth doped oxide (Ln-OS, such as rare earth element doped IGZO / IZO), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb and Cd-Sn-O. The material of the first semiconductor pattern 20 may be amorphous, partially crystalline, single crystal or polycrystalline, and may also be a single layer or multilayer structure.

[0055] The first semiconductor pattern 20 may also use a high-mobility oxide semiconductor material (High Mobility Metal Oxide Semiconductor; HMOS for short), which is beneficial to improving the electron mobility of the first semiconductor pattern 20 and increasing the on-state current of the thin film transistor. The high-mobility metal oxide semiconductor material also has good light stability, which is beneficial to improving the light stability of the thin film transistor. The high-mobility metal oxide semiconductor material includes but is not limited to IZO and IGZO doped with rare earth elements.

[0056] Exemplarily, the first electrode portion 21, the second electrode portion 22 and the channel portion 23 all include the same semiconductor material, but the first electrode portion 21 and the second electrode portion 22 are subjected to a process (such as a doping process) to make them more conductive than the channel portion 23. The first electrode portion 21 and the second electrode portion 22 are doped to form conductors, and the channel portion 23 remains a semiconductor. Therefore, the first electrode portion 21 and the second electrode portion 22 are more conductive than the channel portion 23.

[0057] The gate conductive layer 30 is disposed on a side of the first semiconductor pattern 20 away from the substrate 10. The gate conductive layer 30 includes a gate line 31. The gate line 31 is configured as a gate of the first semiconductor pattern 20. Based on this, the first semiconductor pattern 20 and the gate conductive layer 30 can form a top-gate transistor together. The orthographic projection of the gate conductive layer 30 on the substrate 10 covers the orthographic projection of the channel portion 23 on the substrate 10, so that the channel portion 23 is not doped into a conductor during the conductorization process of the first semiconductor pattern 20. A groove 24 is provided on a surface away from the substrate 10 of at least one of the first electrode portion 21 and the second electrode portion 22. The orthographic projection of the groove 24 on the substrate 10 does not overlap with the orthographic projection of the gate conductive layer 30 on the substrate 10. In this way, the gate conductive layer 30 does not block the groove 24. The groove 24 can increase the surface area of ​​the first electrode portion 21 and the second electrode portion 22 (the one with the groove 24) away from the substrate 10. In the process of doping the first semiconductor pattern 20 with the gate conductive layer 30 as a mask, the groove 24 is beneficial to increase the diffusion path of the doped ions, and enhance the diffusion effect of the doped ions in the first electrode portion 21 and the second electrode portion 22, thereby reducing the degree of lateral diffusion of the doped ions to the side close to the channel portion 23, that is, reducing the size of the above-mentioned ΔD, which is beneficial to increase the interval between the first electrode portion 21 and the second electrode portion 22, that is, increasing the length of the channel portion 23. In this way, not only can the risk of negative bias of the first transistor be reduced, but it is also beneficial to reduce the size of the first semiconductor pattern 20, thereby increasing the size of the first transistor formed by the first semiconductor pattern 20, and improving the aperture ratio and pixel density of the array substrate 100.

[0058] Exemplarily, the groove 24 may be provided on the first electrode portion 21, and the groove 24 may not be provided on the second electrode portion 22. Alternatively, the groove 24 may not be provided on the first electrode portion 21, and the groove 24 may be provided on the second electrode portion 22. Alternatively, the grooves may be provided on both the first electrode portion 21 and the second electrode portion 22.

[0059] In some embodiments, Figure 5 As shown, the depth of the first groove 24 is D1, the thickness of the first semiconductor pattern 20 is D2, and 1 / 3D2<D1<1 / 3D2. In this way, not only can the depth of the groove 24 be greatly increased, the diffusion effect of the doped ions on the first electrode portion 21 and the second electrode portion 22 (at least one of which the groove 24 is provided) be improved, and the degree of lateral diffusion of the doped ions to the side close to the channel portion 23 is reduced, but also the risk of increased resistance due to too small thickness of the first electrode portion 21 and the second electrode portion 22 at the groove 24 can be avoided, and the risk of fracture of the first electrode portion 21 and the second electrode portion 22 at the groove 24 can be avoided.

[0060] In some embodiments, continue to refer to Figure 4The gate conductive layer 30 may include a gate line 31, and the gate line 31 is configured to form a gate of the first semiconductor pattern 20. The angle α between the length direction M4 of the channel portion 23 and the extension direction of the gate line 31 is less than 90 degrees, which is conducive to increasing the length of the channel portion 23, thereby reducing the size of the gate line 31 along the fourth direction M4, reducing the line width of the gate line 31, and improving the aperture ratio and pixel density of the array substrate 100.

[0061] In some embodiments, the first semiconductor pattern 20 may be in the shape of a long strip (eg Figure 4 Alternatively, the first semiconductor pattern 20 may also be in a zigzag shape, a curve shape, or any other shape. The embodiment of the present disclosure does not specifically limit the shape and extension direction of the first semiconductor pattern 20.

[0062] In the embodiment of the present disclosure, the length direction M4 of the channel portion 23 (hereinafter also referred to as the fourth direction M4) refers to the arrangement direction of the portion of the first electrode portion 21 closest to the channel portion 23, the channel portion 23, and the portion of the second electrode portion 22 closest to the channel portion 23, or in other words, the arrangement direction of at least the portion where the first electrode portion 21 is connected to the channel portion 23, the channel portion 23, and at least the portion where the second electrode portion 22 is connected to the channel portion 23 is the length direction M4 of the channel portion 23. For example, as Figure 4 As shown, when the first semiconductor pattern 20 is in a strip shape, the length direction M4 of the channel portion 23 may be parallel to the extension direction of the first semiconductor pattern 20 .

[0063] The size D5 of the portion where the gate conductive layer 30 and the first semiconductor pattern 20 overlap on the substrate 10 along the length direction M1 of the channel portion 23 is greater than or equal to 3 μm, so that the size of the gate conductive layer 30 along the fourth direction M4 can be reduced, thereby reducing the line width (the size perpendicular to the extension direction of the gate line 31) of the gate conductive layer 30 (gate line 31), which is beneficial to improving the aperture ratio and pixel density of the array substrate. Exemplarily, the size D5 of the portion where the gate conductive layer 30 and the first semiconductor pattern 20 overlap on the substrate 10 along the first direction M1 can be 3 μm, 3.5 μm, 4 μm or 5 μm, etc., and the embodiments of the present disclosure will not list them one by one.

[0064] In some embodiments, a groove 24 is provided on the surface of the first electrode portion 21 away from the substrate 10, and the orthographic projection of the first electrode portion 21 on the substrate 10 overlaps with the orthographic projection of the gate conductive layer 30 on the substrate 10, and the dimension D6 of the overlapped portion of the first electrode portion 21 and the gate conductive layer 30 along the first direction M1 is less than or equal to 2 μm. The first direction M1 is perpendicular to the boundary extension direction of the gate conductive layer 30. In this way, when the line width of the gate line 31 is the same, it is beneficial to increase the length of the channel portion 23, thereby reducing the risk of negative bias of the transistor formed by the first semiconductor pattern 20. Exemplarily, the dimension D6 of the overlapped portion of the first electrode portion 21 and the gate conductive layer 30 along the first direction M1 can be 2 μm, 1.5 μm, 1 μm or 0.5 μm, and the embodiments of the present disclosure will not be listed one by one.

[0065] A groove 24 is provided on the surface of the second electrode portion 22 away from the substrate 10, and the orthographic projection of the second electrode portion 22 on the substrate 10 partially overlaps with the orthographic projection of the gate conductive layer 30 on the substrate 10, and the dimension D7 of the overlapping portion of the second electrode portion 22 and the gate conductive layer 30 along the first direction M1 is less than or equal to 2μm. In this way, when the line width of the gate line 31 is the same, it is beneficial to increase the length of the channel portion 23, thereby reducing the risk of negative bias of the transistor formed by the first semiconductor pattern 20. Exemplarily, the dimension D7 of the overlapping portion of the second electrode portion 22 and the gate conductive layer 30 along the first direction M1 can be 2μm, 1.5μm, 1μm or 0.5μm, and the embodiments of the present disclosure will not be listed one by one.

[0066] In some embodiments, Figure 4 As shown, at least one groove 24 is provided on the surface of the first electrode portion 21 away from the substrate 10, and the groove 24 penetrates the first electrode portion 21 along the second direction M2, and the second direction M2 is perpendicular to the extension direction of the first electrode portion 21. At least one groove 24 is provided on the surface of the second electrode portion 22 away from the substrate 10, and the groove 24 penetrates the second electrode portion 22 along the third direction M3, and the third direction M3 is perpendicular to the extension direction of the second electrode portion 22. In the case where the first semiconductor pattern 20 extends in a straight line, the second direction M2 and the third direction M3 are parallel to each other. In this way, it is beneficial to simplify the structure of the groove 24, increase the area occupied by the groove 24, and improve the diffusion degree of doped ions on the first electrode portion 21 and the second electrode portion 22.

[0067] In some embodiments, see Figure 6, the surfaces of the first electrode portion 21 and the second electrode portion 22 away from the substrate 10 are provided with a plurality of grooves 24, and the plurality of grooves 24 are distributed at intervals. That is to say, the surfaces of the first electrode portion 21 and the second electrode portion 22 away from the substrate 10 are provided with a plurality of discretely distributed grooves 24. The opening shape of the groove 24 (the shape of the boundary of the groove 24) can be circular, elliptical, rectangular (square or rectangular) or any other suitable shape. In addition, the plurality of grooves 24 can be arranged in a plurality of rows and columns on the first electrode portion 21 and the second electrode portion 22, or can be arranged in any other suitable manner, and the embodiments of the present disclosure do not specifically limit this.

[0068] In some embodiments, Figure 7 As shown, a protrusion 25 is formed between adjacent grooves 24. The array substrate 100 further includes a gate insulating layer GI, which is disposed between the first semiconductor pattern 20 and the gate conductive layer 30. The gate insulating layer GI includes a first pad GI1, which is disposed on a side of the protrusion 24 away from the substrate 10. The gate conductive layer 30 further includes a second pad 32, which is disposed on a side of the first pad GI1 away from the substrate 10. The orthographic projections of the first pad GI1 and the second pad 32 on the substrate 10 are both located within the range of the orthographic projections of the protrusion 25 on the substrate 10. The above-mentioned first pad GI1 and the second pad 32 are arranged at the position of the protrusion 25, so that the concentration of doped ions at the protrusion 25 can be reduced, and the doped ions received at the groove 24 can diffuse to the protrusion 25, thereby reducing the concentration and distance of the doped ions diffused to the side close to the channel portion 23, which is conducive to increasing the length of the channel portion 23 and reducing the risk of negative bias of the transistor formed by the first semiconductor pattern 20.

[0069] In some embodiments, Figure 5 and Figure 7 As shown, the array substrate 100 further includes a first conductive layer 40, a first insulating layer ILD and a first via hole V1. The first conductive layer 40 is disposed on a side of the first semiconductor pattern 20 close to the substrate 10, and the first insulating layer ILD is disposed between the first conductive layer 40 and the first semiconductor pattern 20. The first conductive layer 40 includes light shielding patterns 41 and first signal lines 42 that are distributed at intervals. The orthographic projection of the light shielding pattern 41 on the substrate 10 covers the orthographic projection of the channel portion 23 on the substrate 10. The light shielding pattern 41 can shield the light directed to the channel portion 23, thereby reducing the risk of characteristic drift of the channel portion 23 under light irradiation.

[0070] The first via hole V1 at least penetrates the first insulating layer ILD. Exemplarily, the first via hole V1 also penetrates the gate insulating layer GI. The first via hole V1 exposes a portion of the first signal line 42. The first signal line 42 can be configured to transmit a data signal. The first signal line DL is arranged on a side of the first semiconductor pattern 20 close to the substrate 10, which is conducive to improving the aperture ratio and pixel density of the array substrate. The gate conductive layer 30 also includes a connecting electrode 33, which is at least partially located in the first via hole V1, and the connecting electrode 33 is electrically connected to the first electrode portion 21 and the first signal line 42, respectively.

[0071] In some embodiments, Figure 5 and Figure 7 As shown, the orthographic projection of the first electrode portion 21 on the substrate 10 partially overlaps with the orthographic projection of the first signal line 42 on the substrate 10. In this way, the formation of a first via hole V1 with a larger depth between the first electrode portion 21 and the first signal line 42 during the preparation process of the array substrate 100 (see below) can be reduced, and the climbing difficulty of the connecting electrode 33 on the side wall of the first via hole V1 is reduced, which is beneficial to improving the continuity of the connecting electrode 33 in the first via hole V1 and ensuring the connection reliability between the first portion 11 and the first signal line DL.

[0072] In some embodiments, the embodiments of the present disclosure further provide a method for preparing an array substrate, and the preparation method includes S100 to S400.

[0073] S100, see Figure 8 , a first conductive layer 40 , a first insulating layer ILD, a first semiconductor pattern 20 and a gate insulating layer GI are sequentially formed on the substrate 10 .

[0074] Among them, Figure 8 As shown, the first conductive layer 40 may include a light shielding pattern 41 and a first signal line 42. The first semiconductor pattern 20 formed in the above step S100 is not subjected to a conductorization process, that is, the conductivity of the first semiconductor pattern 20 is the same everywhere, and the gate insulating layer GI is a continuous whole layer structure.

[0075] S200, see Figures 9 to 11 , forming a first via hole V1 and a groove 24 .

[0076] In some embodiments, the above step S200 may include steps S210 to S240.

[0077] S210, see Fig. 9 , a mask layer 50 is formed on the gate insulating layer GI.

[0078] The mask layer 50 may expose a region 501 for forming the first via hole V1 and a region 502 for forming the groove 24 in the gate insulating layer GI.

[0079] S220, see Fig.10 , a dry etching process is adopted according to the mask layer 50 to pattern the gate insulating layer GI and the first insulating layer ILD to form a first via hole V1.

[0080] The first via hole V1 exposes the first signal line 42 and a portion of the first semiconductor pattern 20 .

[0081] S230, see Fig.11 According to the above-mentioned mask layer 50 , a wet etching process is adopted to pattern the portion of the first semiconductor pattern 20 exposed by the first via hole V1 and the mask layer 50 to form a groove 24 .

[0082] S240, removing the mask layer.

[0083] In the case where the array substrate includes the first spacer, only the mask layer 50 is removed during the above step S240, and a portion of the gate insulating layer between the mask layer 50 and the first semiconductor pattern 20 is retained to form the first spacer. In the case where the array substrate does not include the first spacer, in the process of removing the mask layer in the above step S240, the gate insulating layer GI between the mask layer and the first semiconductor pattern 20 is also removed at the same time to expose the entire first semiconductor pattern 20 in the first via hole V1.

[0084] S300, see Fig.12 , forming a gate conductive layer 30.

[0085] The gate conductive layer 30 may include a gate line 31 and a connecting electrode 33 . The structures of the gate line 31 and the connecting electrode 33 are referred to above and will not be described in detail herein.

[0086] S400, see Fig.13 , using the gate conductive layer 30 as a mask to remove the portion of the gate insulating layer GI not covered by the gate conductive layer 30 , and performing a patterning process on the first semiconductor pattern 20 .

[0087] Part of the first semiconductor pattern 20 is conductively formed to form a first electrode portion 21 and a second electrode portion 22 , and part of the first semiconductor pattern 20 is not conductively formed to remain as a semiconductor. The part between the first electrode portion 21 and the second electrode portion 22 that remains as a semiconductor forms a channel portion 23 .

[0088] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An array substrate, characterized in that: include: A substrate and a plurality of first semiconductor patterns disposed on one side of the substrate, wherein the first semiconductor pattern includes a channel portion and a first electrode portion and a second electrode portion located on both sides of the channel portion and integrally disposed with the channel portion, wherein the first electrode portion and the second electrode portion are more conductive than the channel portion; A gate conductive layer is disposed on a side of the first semiconductor pattern away from the substrate, wherein an orthographic projection of the gate conductive layer on the substrate covers an orthographic projection of the channel portion on the substrate; At least one of the first electrode portion and the second electrode portion is provided with a groove on a surface away from the substrate, and an orthographic projection of the groove on the substrate does not overlap with an orthographic projection of the gate conductive layer on the substrate.

2. The array substrate according to claim 1, characterized in that: A dimension of a portion where the orthographic projections of the gate conductive layer and the first semiconductor pattern on the substrate overlap with each other along the length direction of the channel portion is greater than or equal to 3 μm.

3. The array substrate according to claim 2, characterized in that: The groove is provided on a surface of the first electrode portion away from the substrate, an orthographic projection of the first electrode portion on the substrate overlaps with an orthographic projection of the gate conductive layer on the substrate, and a size of a portion where the first electrode portion and the gate conductive layer overlap each other along a first direction is less than or equal to 2 μm; and the first direction is perpendicular to an extension direction of a boundary of the gate conductive layer; and / or, The groove is provided on the surface of the second electrode portion away from the substrate, the orthographic projection of the second electrode portion on the substrate overlaps with the orthographic projection of the gate conductive layer on the substrate, and the size of the overlapping portion of the second electrode portion and the gate conductive layer along the first direction is less than or equal to 2μm.

4. The array substrate according to claim 1, characterized in that: At least one groove is provided on a surface of the first electrode portion away from the substrate, and the groove penetrates the first electrode portion along a second direction, and the second direction is perpendicular to an extension direction of the first electrode portion; At least one groove is disposed on a surface of the second electrode portion away from the substrate. The groove penetrates the second electrode portion along a third direction, and the third direction is perpendicular to an extending direction of the second electrode portion.

5. The array substrate according to claim 1, characterized in that: A plurality of grooves are disposed on surfaces of the first electrode portion and the second electrode portion away from the substrate, and the plurality of grooves are distributed at intervals.

6. The array substrate according to any one of claims 1 to 5, characterized in that: A protrusion is formed between adjacent grooves; The array substrate further comprises a gate insulating layer, the gate insulating layer is arranged between the first semiconductor pattern and the gate conductive layer, and comprises a first pad, the first pad is arranged on a side of the protrusion away from the substrate; The gate conductive layer further comprises a second pad, and the second pad is arranged on a side of the first pad away from the substrate; The orthographic projections of the first cushion block and the second cushion block on the substrate are both located within the range of the orthographic projection of the protrusion on the substrate.

7. The array substrate according to any one of claims 1 to 5, characterized in that: A material of the first semiconductor pattern includes an oxide semiconductor material.

8. The array substrate according to any one of claims 1 to 5, characterized in that: The gate conductive layer includes a gate line, and an angle between a length direction of the channel portion and an extension direction of the gate line is less than 90°.

9. The array substrate according to claim 1, characterized in that: The depth of the first groove is D1, the thickness of the first semiconductor pattern is D2, and 1 / 3D2≤D1≤1 / 3D2.

10. The array substrate according to claim 1, characterized in that: The array substrate further includes: A first conductive layer, disposed on a side of the first semiconductor pattern close to the substrate, comprising light shielding patterns and first signal lines that are distributed at intervals, wherein the orthographic projection of the light shielding pattern on the substrate covers the orthographic projection of the channel portion on the substrate; A first insulating layer, disposed between the first conductive layer and the first semiconductor pattern; a first via hole, at least penetrating the first insulating layer and exposing the first signal line; Wherein, the gate conductive layer further includes a connecting electrode, and the connecting electrode is at least partially located in the first via hole and is electrically connected to the first electrode portion and the first signal line respectively.

11. A display panel, characterized in that: include: The array substrate according to any one of claims 1 to 10; An opposing substrate, arranged opposite to the array substrate; The liquid crystal layer is arranged between the array substrate and the counter substrate.

12. A display device, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 10; or comprises the display panel according to claim 11.

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