An SCR device, process method and chip

Abstract

This invention provides an SCR device, a process method, and a chip. Compared to traditional LVT-CR devices, the SCR device of this invention has a lower trigger voltage and a higher sustaining voltage, avoiding deep hysteresis and expanding the application scenarios of the SCR device, enabling it to be used in high-operating-voltage ports. The SCR device of this invention can also form multiple ESD current discharge paths, resulting in higher ESD current discharge capability per unit area of ​​the chip. This gives the SCR device low on-resistance characteristics, effectively saving chip area and reducing chip production costs. Furthermore, multiple ESD current discharge paths make the ESD current distribution within the SCR device more uniform, effectively improving the robustness of the discharge path under high current conditions.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and particularly relates to an SCR device, process method and chip. Background Technology

[0002] Electrostatic discharge (ESD) refers to a momentary current pulse caused by the accumulation of static electricity. ESD can easily damage integrated circuits, therefore, ESD protection circuits need to be designed to protect them. ESD protection circuits primarily rely on ESD protection devices to discharge static charge. The trigger voltage of these devices should be lower than the failure voltage, while their trigger and sustaining voltages should be higher than the operating voltage at their ports. This ensures that the circuit is shut down during normal operation, preventing disruption to circuit function. In the event of an ESD event, the ESD protection device should clamp the port voltage below the failure voltage and promptly discharge the ESD current.

[0003] With the development of integrated circuit technology, various functional integrated circuit products are constantly being launched. The operating voltage of integrated circuits is getting higher and higher, and the margin between the normal operating voltage and the failure voltage is getting smaller and smaller, making the safety window of ESD protection device design increasingly narrow. At present, ESD protection devices are required to have higher self-sustaining voltage to adapt to the ESD protection function of high operating voltage ports, and also to have lower on-resistance and trigger voltage, so that ESD protection devices can be triggered in time and generate a smaller voltage drop when discharging ESD current, enabling ESD protection devices to provide protection within a narrower range of operating voltage and failure voltage.

[0004] Low trigger voltage type SCR (LVTSCR) is an SCR device that embeds a gate-grounded NMOS (ggNMOS) into a traditional SCR device. LVTSCR devices utilize the turn-on of the ggNMOS to trigger the SCR structure, with a trigger voltage lower than that of traditional SCR devices. At the same time, LVTSCR devices retain the low sustaining voltage characteristic of traditional SCR devices, making them widely used in ESD protection applications at low-voltage ports. After triggering, LVTSCR devices require only a small voltage to maintain the SCR structure on. However, to avoid false triggering and latch-up effects, LVTSCR devices cannot be used at ports with higher operating voltages, making it difficult to meet the current ESD protection requirements of integrated circuits.

[0005] Therefore, there is an urgent need for an SCR device with low on-resistance and high holding voltage. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a low on-resistance, high holding voltage SCR device, process method and chip, which aims to solve the problem that LVTSCR devices are difficult to apply to ports with high operating voltage in related technologies.

[0007] To solve the above-mentioned technical problems, the present invention is implemented as follows: an SCR device, comprising:

[0008] A p-type substrate, an n-type deep well region formed in the p-type substrate, a first p-type well region formed in the n-type deep well region, a second p-type well region formed in the p-type substrate, a first n-type well region formed by implanting both the n-type deep well region and the p-type substrate at the boundary between the n-type deep well region and the p-type substrate, a first p-heavy doped region formed on the first n-type well region, a first n-heavy doped region formed by implanting both the first n-type well region and the first p-type well region at the boundary between the first n-type well region and the first p-type well region, a second p-heavy doped region formed on the first p-type well region, a third p-heavy doped region formed on the first p-type well region, a second n-heavy doped region formed on the first p-type well region, a third n-heavy doped region formed by implanting both the first p-type well region and the first n-type well region at the boundary between the first p-type well region and the first n-type well region, and a fourth n-heavy doped region formed on the first n-type well region.

[0009] The first n-type well region is arranged around the outer periphery of the first p-type well region, and the second p-type well region is arranged around the outer periphery of the first n-type well region;

[0010] The first p-doped region, the first n-doped region, the second p-doped region, the third p-doped region, the second n-doped region, the third n-doped region, and the fourth n-doped region are spaced apart along a first direction, which is perpendicular to the thickness direction of the p-type substrate. The SCR device further includes a gate dielectric layer, a cathode, and an anode. The gate dielectric layer is formed between the second n-doped region, the third n-doped region, and the first p-type well region. The first p-doped region and the fourth n-doped region are metal interconnected to the anode. The third p-doped region and the second n-doped region are metal interconnected to the cathode. The first n-doped region is metal interconnected to the third n-doped region. The second p-doped region is metal interconnected to the gate dielectric layer.

[0011] Furthermore, the second p-type well region is isolated from the first p-doped region, the first p-doped region from the first n-doped region, the first n-doped region from the second p-doped region, the second p-doped region from the third p-doped region, the third p-doped region from the second n-doped region, the third n-doped region from the fourth n-doped region, and the fourth n-doped region from the second p-type well region by shallow trench dielectric.

[0012] Furthermore, the n-type deep well region, the first p-type well region, the first n-type well region, the second p-type well region, the first p-heavy doped region, the first n-heavy doped region, the second p-heavy doped region, the third p-heavy doped region, the second n-heavy doped region, the third n-heavy doped region, and the fourth n-heavy doped region are all formed by ion implantation or diffusion.

[0013] Furthermore, the ion doping concentrations of the first p-doped region, the first n-doped region, the second p-doped region, the third p-doped region, the second n-doped region, the third n-doped region, and the fourth n-doped region are all greater than 1 × 10⁻⁶. 18 cm -3 ;

[0014] The ion doping concentration of the first p-type well region, the first n-type well region, and the second p-type well region is 1×10⁻⁶. 16 cm -3 ~ 1×10 18 cm -3 ;

[0015] The ion doping concentration of the n-type deep well region is 1×10⁻⁶. 16 cm -3 ~ 1×10 19 cm -3 .

[0016] This invention also provides a process method for an SCR device, comprising the following steps:

[0017] Prepare a p-type substrate;

[0018] The p-type substrate is etched to form a plurality of shallow trenches, and a shallow trench medium is injected into each of the shallow trenches. The plurality of shallow trenches into which the shallow trench medium is injected are spaced apart along a first direction, the first direction being perpendicular to the thickness direction of the p-type substrate.

[0019] An n-type deep well region is formed in the p-type substrate;

[0020] A first p-type well region is formed in the n-type deep well region, and a second p-type well region is formed in the p-type substrate. At the junction of the n-type deep well region and the p-type substrate, the first n-type well region is simultaneously implanted into the n-type deep well region and the p-type substrate to form the first n-type well region. The first n-type well region is arranged around the outer periphery of the first p-type well region, and the second p-type well region is arranged around the outer periphery of the first n-type well region.

[0021] A first p-doped region is formed on the first n-type well region. At the boundary between the first n-type well region and the first p-type well region, a first n-fold doped region is simultaneously implanted into both the first n-type well region and the first p-type well region to form a first n-fold doped region. A second p-fold doped region is formed on the first p-type well region. A third p-fold doped region is formed on the first p-type well region. A second n-fold doped region is formed on the first p-type well region. At the boundary between the first p-type well region and the first n-type well region, a third n-fold doped region is simultaneously implanted into both the first p-type well region and the first n-type well region to form a third n-fold doped region. A fourth n-fold doped region is formed on the first n-type well region. The first p-fold doped region and the first n-fold doped region... The second p-doped region, the third p-doped region, the second n-doped region, the third n-doped region, and the fourth n-doped region are spaced apart along the first direction, and the second p-type well region is isolated from the first p-doped region, the first p-doped region is isolated from the first n-doped region, the first n-doped region is isolated from the second p-doped region, the second p-doped region is isolated from the third p-doped region, the third p-doped region is isolated from the second n-doped region, the third n-doped region is isolated from the fourth n-doped region, and the fourth n-doped region is isolated from the second p-type well region by the corresponding shallow trench medium.

[0022] The gate dielectric layer is formed between the second n-fold doped region, the third n-fold doped region and the first p-type well region;

[0023] The first p-doped region and the fourth n-doped region are respectively interconnected with the anode, the third p-doped region and the second n-doped region are respectively interconnected with the cathode, the first n-doped region and the third n-doped region are interconnected with each other, and the second p-doped region is interconnected with the gate dielectric layer.

[0024] The present invention also provides a chip comprising the SCR device described above.

[0025] Compared with existing technologies, the SCR device, process method, and chip of this invention have the following advantages:

[0026] Compared to traditional LVT-CR devices, the SCR device in this invention forms multiple ESD current discharge paths, resulting in a lower trigger voltage and a higher sustaining voltage. This avoids deep hysteresis, expands the application scenarios of the SCR device, and enables it to be used in high operating voltage ports.

[0027] On the other hand, SCR devices can form multiple ESD current discharge paths, resulting in higher ESD current discharge capability per unit area of ​​the chip. This gives SCR devices low on-resistance characteristics, effectively saving chip area and reducing chip production costs. In addition, multiple ESD current discharge paths make the distribution of ESD current within the SCR device more uniform and improve the robustness of the discharge path of the SCR device under high current. Attached Figure Description

[0028] Figure 1 This is a cross-sectional schematic diagram of a conventional LVTSCR device in an embodiment of the present invention;

[0029] Figure 2 This is a cross-sectional schematic diagram of the SCR device in an embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of the discharge of ESD current along the RC path, the discharge path of the NMOS transistor structure, and the discharge path of the NPN transistor structure when ESD occurs at the anode of the SCR device and the cathode is grounded, in an embodiment of the present invention.

[0031] Figure 4 This is a schematic diagram of the discharge path of the PNP transistor structure when an ESD occurs at the anode of the SCR device and the cathode is grounded, in an embodiment of the present invention.

[0032] Figure 5 This is a schematic diagram of the ESD current being discharged along the SCR discharge path when an ESD occurs at the anode of the SCR device and the cathode is grounded, according to an embodiment of the present invention.

[0033] Figure 6 This is a schematic diagram of how, in an embodiment of the present invention, when an ESD occurs at the anode of an SCR device and the cathode is grounded, the ESD current is discharged along the auxiliary discharge path of the NMOS transistor structure after the SCR discharge path is opened.

[0034] Figure 7 This is a schematic diagram of the discharge path of the PN junction diode structure when an ESD occurs at the cathode of the SCR device and the anode is grounded, according to an embodiment of the present invention.

[0035] Figure 8This is a schematic diagram of the discharge path of the NMOS transistor structure when an ESD occurs at the cathode of the SCR device and the anode is grounded, according to an embodiment of the present invention.

[0036] Figure 9 This is a schematic diagram of the discharge path of the PNP transistor structure when an ESD occurs at the cathode of the SCR device and the anode is grounded, in an embodiment of the present invention.

[0037] Figure 10 This is a flowchart of the process method for the SCR device in this embodiment of the invention.

[0038] In the accompanying drawings, the reference numerals indicate:

[0039] 100, p-type substrate; 110, second p-type well region; 111, first p-type well region; 120, first heavily p-doped region; 121, second heavily p-doped region; 122, third heavily p-doped region; 200, n-type deep well region; 210, first n-type well region; 220, first heavily n-doped region; 221, second heavily n-doped region; 222, third heavily n-doped region; 223, fourth heavily n-doped region; 300, gate dielectric layer; 400, first interconnect lead; 401, second interconnect lead; 402, third interconnect lead; 403, fourth interconnect lead;

[0040] 500, P-type conductive silicon substrate; 510, first P-type conductive well region; 520, first P-type heavily doped region; 521, second P-type heavily doped region; 610, first N-type conductive well region; 620, first N-type heavily doped region; 621, second N-type heavily doped region; 622, third N-type heavily doped region; 700, gate dielectric layer; 810, first interconnect; 820, second interconnect. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0042] Please see Figure 1 Traditional LVT-CR devices include:

[0043] A P-type conductive silicon substrate 500, a first N-type conductive well region 510 formed on top of the P-type conductive silicon substrate 500, a first P-type conductive well region 510 formed on top of the P-type conductive silicon substrate 500, a first N-type heavily doped region 620 formed on top of the first N-type conductive well region 510, a first P-type heavily doped region 521 formed on top of the first N-type conductive well region 620, a second N-type heavily doped region 621 formed by simultaneously implanting into the first N-type conductive well region 620 and the first P-type conductive well region 510 at the junction of the first N-type conductive well region 620 and the first P-type conductive well region 510, a third N-type heavily doped region 622 formed on top of the first P-type conductive well region 510, a second P-type heavily doped region 520 formed on top of the first P-type conductive well region 510, a gate dielectric layer 700, a first interconnect 810, a second interconnect 820, a cathode, and an anode;

[0044] The first N-type conductivity type well region 610 and the first P-type conductivity type well region 510 are arranged sequentially along a first direction, which is perpendicular to the thickness direction of the P-type conductivity type substrate 500.

[0045] The first N-type heavy doped region 620, the first P-type heavy doped region 510, the second N-type heavy doped region 621, the third N-type heavy doped region 622, and the second P-type heavy doped region 521 are spaced apart along a first direction. The first N-type heavy doped region 620 and the first P-type heavy doped region 520 are isolated by a shallow trench medium. The first P-type heavy doped region 520 and the second N-type heavy doped region 621 are isolated by a shallow trench medium. The third N-type heavy doped region 622 and the second P-type heavy doped region 521 are isolated by a shallow trench medium.

[0046] The gate dielectric layer 700 is formed on top of the second N-type heavily doped region 621, the first P-type well region 510, and the third N-type heavily doped region 622.

[0047] The first N-type conductivity heavily doped region 620, the first P-type conductivity well region 510, and the anode are connected by the first interconnect line 810.

[0048] The second P-type heavily doped region 521, the third N-type heavily doped region 622, the gate dielectric layer 700, and the cathode are connected by a second interconnect 820.

[0049] Traditional LVTSCR devices include a first current discharge path and a second current discharge path;

[0050] The current passes through the anode, the first P-type heavily doped region 520, the first N-type well region 610, the first P-type well region 510, the third N-type heavily doped region 622, and the cathode to form a first current discharge path, which is the SCR discharge path.

[0051] The current passes through the anode, the first N-type heavily doped region 620, the first N-type well region 610, the second N-type heavily doped region 621, the first P-type well region 510, the third N-type heavily doped region 622, and the cathode to form a second current discharge path, which is an ggNMOS path.

[0052] When an ESD event occurs at the anode of a conventional LVTSCR device and the cathode is grounded, the second current discharge path activates, triggering the first current discharge path to discharge. This first current discharge path is simple, and its overlap with the second path reduces the voltage required to maintain its operation. However, the overlap also causes currents to converge at the two paths, leading to current accumulation and localized overheating, potentially causing device failure and reducing the ESD current discharge capability of the conventional LVTSCR device. Since conventional LVTSCR devices require only a small voltage to maintain conduction after triggering, they are often used in low-voltage ESD protection circuits to avoid false triggering and latch-up effects, making them unsuitable for high-voltage protection circuits.

[0053] Please see Figures 2 to 9 This embodiment provides an SCR device, including:

[0054] A p-type substrate 100, an n-type deep well region 200 formed in the p-type substrate 100, a first p-type well region 111 formed in the n-type deep well region 200, a second p-type well region 110 formed in the p-type substrate 100, a first n-type well region 210 formed by simultaneous implantation into the n-type deep well region 200 and the p-type substrate 100 at the boundary between the n-type deep well region 200 and the p-type substrate 100, a first p-heavily doped region 120 formed on the first n-type well region 210, and a first p-heavily doped region 120 formed on the first n-type well region 210 at the boundary between the first n-type well region 210 and the first p-type well region 111. The first n-fold doped region 220 formed by implanting into the first p-type well region 111, the second p-fold doped region 121 formed on the first p-type well region 111, the third p-fold doped region 122 formed on the first p-type well region 111, the second n-fold doped region 221 formed on the first p-type well region 111, the third n-fold doped region 222 formed by simultaneously implanting into the first p-type well region 111 and the first n-type well region 210 at the junction of the first p-type well region 111 and the first n-type well region 210, and the fourth n-fold doped region 223 formed on the first n-type well region 210;

[0055] The first n-type well region 210 is arranged around the outer periphery of the first p-type well region 111, and the second p-type well region 110 is arranged around the outer periphery of the first n-type well region 210;

[0056] The first p-doped region 120, the first n-doped region 220, the second p-doped region 121, the third p-doped region 122, the second n-doped region 221, the third n-doped region 222, and the fourth n-doped region 223 are spaced apart along a first direction, which is perpendicular to the thickness direction of the p-type substrate 100. The SCR device also includes a gate dielectric layer 300, a cathode, and an anode. The gate dielectric layer 300 is formed between the second n-doped region 221, the third n-doped region 222, and the first p-type well region 111. The first p-doped region 120 and the fourth n-doped region 223 are metal interconnected to the anode. The third p-doped region 122 and the second n-doped region 221 are metal interconnected to the cathode. The first n-doped region 220 is metal interconnected to the third n-doped region 222. The second p-doped region 121 is metal interconnected to the gate dielectric layer 300.

[0057] Understandably, from the top view of the SCR device layout, both the first n-type well region 210 and the second p-type well region 110 are closed rings.

[0058] Specifically, such as Figure 2 As shown, the SCR device provided in this embodiment forms various structures, including a PNP transistor structure, an NPN transistor structure, an SCR structure formed by coupling a PNP transistor structure and an NPN transistor structure, an NMOS transistor structure, and a structure with multiple PN junction diodes.

[0059] Among them, such as Figure 2 As shown, the first p-doped region 120, the first n-type well region 210, the first p-type well region 111, and the third p-doped region 122 form a PNP transistor structure connected between the cathode and the anode; the second n-doped region 221, the first p-type well region 111, the first n-type well region 210, the n-type deep well region 200, and the fourth n-doped region 223 form an NPN transistor structure connected between the cathode and the anode;

[0060] The second n-fold doped region 221, the third n-fold doped region 222, the first p-type well region 111, and the gate dielectric layer 300 form an NMOS transistor structure connected between the cathode and the anode; the third p-fold doped region 122, the first p-type well region 111, the third n-fold doped region 222, the second n-type well region, and the fourth n-fold doped region 223 form multiple PN junction diode structures.

[0061] The SCR device in this embodiment also includes a first interconnect lead 400, a second interconnect lead 401, a third interconnect lead 402, and a fourth interconnect lead 403.

[0062] The first p-doped region 120 and the fourth n-doped region 223 are interconnected with the anode metal via the first interconnect lead 400; the third p-doped region 122 and the second n-doped region 221 are interconnected with the cathode metal via the second interconnect lead 401; the first n-doped region 220 and the third n-doped region 222 are interconnected with the metal via the third interconnect lead 402; and the second p-doped region 121 is interconnected with the gate dielectric layer 300 via the fourth interconnect lead 403.

[0063] In this embodiment, when the SCR device experiences ESD at the anode and the cathode is grounded, since the first p-doped region 120 and the fourth n-doped region 223 are electrically connected to the anode, current flows from the anode through the first p-doped region 120 and the fourth n-doped region 223, and the potential of the first p-doped region 120 and the fourth n-doped region 223 rises rapidly. Since the third n-doped region 222 and the fourth n-doped region 223 are both formed on the first n-type well region 210 and are electrically connected, the potential of the third n-doped region 222 also rises rapidly along with the fourth n-doped region 223.

[0064] like Figure 3As shown, there is a first parasitic well resistance generated by the first n-type well region 210 between the fourth n-doped region 223 and the third n-doped region 222, and a parasitic capacitance between the gate dielectric layer 300 and the third n-doped region 222. There is a second parasitic well resistance generated by the first p-type well region 111 between the second p-doped region 121 and the third p-doped region 122. The first parasitic well resistance, the first parasitic capacitance, and the second parasitic well resistance form an RC path. The RC path responds to the ESD current. The displacement current of the parasitic capacitance accumulates a voltage drop on the first parasitic well resistance, which causes the voltage of the gate dielectric layer 300 to increase accordingly. This is conducive to the formation of the NMOS channel region and the turn-on of the NMOS transistor, and accelerates the lateral bipolar breakdown of the NMOS transistor structure, that is, accelerates the breakdown between the second n-doped region 221 and the third n-doped region 222.

[0065] like Figure 3 As shown, after the lateral bipolar breakdown of the NMOS transistor structure, the anode, the fourth n-fold doped region 223, the first n-type well region 210, the third n-fold doped region 222, the first p-type well region 111, the second n-fold doped region 221, and the cathode sequentially form the discharge path of the NPN transistor structure. The ESD current flows along the discharge path of the NPN transistor structure, and the SCR device is turned on.

[0066] Compared to traditional LVT-CR devices, the SCR device in this embodiment introduces an RC path through gate coupling technology, which accelerates the voltage rise of the gate dielectric layer 300, i.e., accelerates the voltage rise of the gate of the NMOS transistor structure, further accelerating the bipolar breakdown of the NMOS transistor structure, realizing the conduction of the SCR device, and making the trigger voltage of the SCR device provided in this embodiment lower.

[0067] Subsequently, the ESD current accumulates a voltage drop due to the first parasitic resistance formed in the first n-type well region 210, pulling down the potential of the first n-fold doped region 220 and the third n-fold doped region 222, causing the PN junction diode structure formed by the first p-fold doped region 120 and the first n-type well region 210 to be forward biased. At this time, as Figure 4 As shown, a small amount of current flows from the third n-doped region 222 to the first n-doped region 220 through the third interconnect lead 402, providing current for the base first p-type well region 111 of the PNP transistor structure, thereby promoting the discharge path of the PNP transistor structure. In the discharge path of the PNP transistor structure, the ESD current passes through the anode, the first p-doped region 120, the first n-type well region 210, the first n-doped region 220, the first p-type well region 111, and the third p-doped region 122 to reach the cathode.

[0068] The multiple discharge paths formed by the NPN transistor structure and the PNP transistor structure make the ESD current distribution more uniform in the first p-type well region 111, which is also more conducive to further opening the discharge path of the SCR.

[0069] As the discharge paths of the NPN transistor and PNP transistor are successively turned on, the SCR device gradually becomes more advanced, the discharge charge increases, the discharge capability is enhanced, and the ESD current flowing through the SCR device increases. Figure 5 As shown, as the current increases, the current discharged from the first p-type well region 111 to the third p-doped region in the discharge path of the PNP transistor structure is drawn by the forward bias diode formed by the first p-type well region 111 and the second n-doped region 221. This ultimately triggers the main SCR discharge path formed by the anode through the first p-doped region 120, the first n-type well region 210, the first p-type well region 111, and the second n-doped region 221, as well as the parasitic secondary SCR discharge path formed by the anode through the first p-doped region 120, the first n-type well region 210, the n-type deep well region 200, the first p-type well region 111, and the second n-doped region 221. The main SCR discharge path and the secondary SCR discharge path together constitute the SCR discharge path.

[0070] Since the main SCR discharge path is built on top of the discharge path of the PNP transistor structure, the current flowing through the main SCR path is drawn by the discharge path of the PNP transistor structure, reducing the current gain of the main SCR path. The NPN structure of the secondary SCR path is formed by an n-type deep well region 200, a first p-type well region 111, and a second n-doped region 221 along the thickness direction of the substrate, and then the n-type deep well region 200 is softly connected to the first n-type well region 210. Therefore, the current amplification capability of the secondary SCR discharge path is weaker than that of the main SCR discharge path. As a result, the SCR device of the present invention has a higher holding voltage than the conventional LVT-CR device, avoiding deep hysteresis.

[0071] Furthermore, such as Figure 6 As shown, when the SCR discharge path is turned on, the current injected into the first p-type well region 111 by the first n-type well region 210 and discharged through the SCR discharge path and the discharge path of the PNP transistor structure accumulates voltage on the second parasitic well resistor between the second p-doped region 121 and the third p-doped region 122, which raises the gate voltage of the NMOS structure and maintains the opening of the NMOS structure current discharge channel. At the same time, the current on the SCR path can also flow from the first n-doped region 220 to the third n-doped region 222 through the third interconnect, and the current is discharged through the NMOS channel.

[0072] During the ESD current discharge process, the discharge paths of the SCR, PNP transistor, NMOS transistor, and NPN transistor work together to give the SCR device low on-resistance characteristics. This also makes the ESD current distribution within the SCR device more uniform, mitigates the effects of local overheating caused by high current, and improves the robustness of the PNP discharge path under high current.

[0073] In this embodiment, as Figure 7 As shown, when an ESD occurs at the cathode of the SCR device and the anode is grounded, the potential of the third p-doped region 122 and the second n-doped region 221 connected to the cathode rises rapidly. The PN junction diodes formed by the first p-type well region 111 and the first n-type well region 210, the first p-type well region 111 and the first n-doped region 220, and the first p-type well region 111 and the n-type deep well region 200 are all forward biased. The ESD current is first discharged to the anode through the third p-doped region 122, the first p-type well region 111, the third n-doped region 222, the first n-type well region 210, and the fourth n-doped region 223. The diode structure formed by the third p-doped region 122, the first p-type well region 111, and the first n-doped region 220 is also forward biased. The ESD current also flows to the third n-doped region 222 through the third interconnect.

[0074] like Figure 8 As shown, when the cathode voltage increases, the gate voltage of the NMOS transistor structure that is softly connected to the cathode also increases. The ESD current can be discharged from the NMOS channel through the second n-fold doped region 221 to the third n-fold doped region 222, and then discharged to the anode. That is, the ESD current is discharged along the discharge path of the NMOS transistor structure.

[0075] like Figure 9 As shown, as the voltage between the cathode and anode increases further, the discharge path of the PNP transistor structure will be opened, and the ESD current flows through the cathode, the third p-doped region 122, the first p-type well region 111, the first n-type well region 210, and the first p-doped region 120 to the anode.

[0076] In summary, compared with traditional LVT-CR devices, the SCR device provided in this embodiment has a lower trigger voltage and a higher sustaining voltage, which can avoid deep hysteresis and expand the application scenarios of SCR devices, enabling SCR devices to be used in high operating voltage ports.

[0077] On the other hand, SCR devices can form multiple ESD current discharge paths, resulting in higher ESD current discharge capability per unit area of ​​the chip. This gives SCR devices low on-resistance characteristics, effectively saving chip area and reducing chip production costs. In addition, multiple ESD current discharge paths make the distribution of ESD current within the SCR device more uniform and improve the robustness of the discharge path of the SCR device under high current.

[0078] Furthermore, the second p-type well region 110 is isolated from the first p-heavily doped region 120, the first p-heavily doped region 120 from the first n-heavily doped region 220, the first n-heavily doped region 220 from the second p-heavily doped region 121, the second p-heavily doped region 121 from the third p-heavily doped region 122, the third p-heavily doped region 122 from the second n-heavily doped region 221, the third n-heavily doped region 222 from the fourth n-heavily doped region 223, and the fourth n-heavily doped region 223 from the second p-type well region 110 by shallow trench isolation (STI). The shallow trench isolation provides an insulating structure between each well region and each heavily doped region, thus serving as an isolation mechanism.

[0079] Furthermore, the n-type deep well region, the first p-type well region, the first n-type well region, the second p-type well region, the first p-heavy doped region, the first n-heavy doped region, the second p-heavy doped region, the third p-heavy doped region, the second n-heavy doped region, the third n-heavy doped region, and the fourth n-heavy doped region are all formed by ion implantation or diffusion.

[0080] Preferably, the ion doping concentrations of the first p-doped region 120, the first n-doped region 220, the second p-doped region 121, the third p-doped region 122, the second n-doped region 221, the third n-doped region 222, and the fourth n-doped region 223 are all greater than 1 × 10⁻⁶. 18 cm -3 ;

[0081] The ion doping concentration of the first p-type well region, the first n-type well region, and the second p-type well region is 1×10⁻⁶. 16 cm -3 ~ 1×10 18 cm -3 ;

[0082] The ion doping concentration of the n-type deep well region 200 is 1×10⁻⁶. 16 cm -3 ~ 1×10 19 cm -3 .

[0083] It is understandable that the ion doping concentration of each heavily doped region, each well region, and the deep well region is affected by the device fabrication process. The ion doping concentration provided in this embodiment is only a preferred embodiment.

[0084] Please see Figure 10 This embodiment also provides a process method for the above-mentioned SCR device, including the following steps:

[0085] Step 101: Prepare a p-type substrate;

[0086] Step 102: Etch a p-type substrate to form multiple shallow trenches, and inject shallow trench medium into each shallow trench. The multiple shallow trenches into which the shallow trench medium is injected are spaced apart along a first direction, which is perpendicular to the thickness direction of the p-type substrate.

[0087] Step 103: Form an n-type deep well region in a p-type substrate;

[0088] Step 104: Form a first p-type well region in an n-type deep well region and a second p-type well region in a p-type substrate. Simultaneously implant into the n-type deep well region and the p-type substrate at the junction of the n-type deep well region and the p-type substrate to form a first n-type well region. The first n-type well region is arranged around the outer periphery of the first p-type well region, and the second p-type well region is arranged around the outer periphery of the first n-type well region.

[0089] Step 105: Form a first p-heavy doped region on the first n-type well region; simultaneously implant into the first n-type well region and the first p-type well region at the boundary between the first n-type well region and the first p-type well region to form a first n-heavy doped region; form a second p-heavy doped region on the first p-type well region; form a third p-heavy doped region on the first p-type well region; form a second n-heavy doped region on the first p-type well region; simultaneously implant into the first p-type well region and the first n-type well region at the boundary between the first p-type well region and the first n-type well region to form a third n-heavy doped region; and form a fourth n-heavy doped region on the first n-type well region. The first p-heavy doped region... The region, the first n-fold doped region, the second p-fold doped region, the third p-fold doped region, the second n-fold doped region, the third n-fold doped region, and the fourth n-fold doped region are spaced apart along the first direction, and the second p-fold well region and the first p-fold doped region, the first p-fold doped region and the first n-fold doped region, the first n-fold doped region and the second p-fold doped region, the second p-fold doped region and the third p-fold doped region, the third p-fold doped region and the second n-fold doped region, the third n-fold doped region and the fourth n-fold doped region, and the fourth n-fold doped region and the second p-fold well region are all isolated by corresponding shallow trench media;

[0090] Step 106: Form a gate dielectric layer between the second n-fold doped region, the third n-fold doped region and the first p-type well region;

[0091] Step 107: Connect the first p-doped region and the fourth n-doped region to the anode, respectively; connect the third p-doped region and the second n-doped region to the cathode, respectively; connect the first n-doped region to the third n-doped region; and connect the second p-doped region to the gate dielectric layer.

[0092] In some embodiments, the n-type deep well region, the first p-type well region, the first n-type well region, the second p-type well region, the first p-heavily doped region, the first n-heavily doped region, the second p-heavily doped region, the third p-heavily doped region, the second n-heavily doped region, the third n-heavily doped region, and the fourth n-heavily doped region are all formed by ion implantation or diffusion.

[0093] The first p-doped region, the fourth n-doped region, and the anode are interconnected; the first n-doped region and the third n-doped region are interconnected; and the second p-doped region and the gate dielectric layer are interconnected through wire bonding or metal deposition to form interconnects.

[0094] In some embodiments, injecting shallow trench medium into each shallow trench includes:

[0095] An oxide layer is grown on the inner surface of each shallow trench, a shallow trench dielectric is deposited in the shallow trench where the oxide layer is grown, and the surface of the SCR device exposed to the shallow trench dielectric is polished.

[0096] The shallow trench dielectric can be silicon dioxide, silicon nitride, or other low dielectric constant materials. The shallow trench dielectric can be deposited by various processes such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). The surface of the SCR device exposed by the shallow trench dielectric can be polished by chemical mechanical polishing (CMP) to planarize the surface of the SCR device after the shallow trench dielectric is filled.

[0097] It should be noted that the process method provided in this embodiment is only a preferred embodiment. In other embodiments, the process method of SCR device is not limited to the order of steps in the above embodiment. In other embodiments, those skilled in the art can change the order of steps of SCR process method according to actual process, such as changing the injection order of each well region, injecting multiple well regions at the same time, etc.

[0098] This embodiment also provides a chip, including the SCR device described above.

[0099] Chips with the aforementioned SCR devices are suitable for a wider range of electronic devices and systems, especially in high-voltage environments where stability is required. Furthermore, due to the low on-resistance of SCR devices, chip area is effectively saved, resulting in lower production costs.

[0100] It should be noted that the various embodiments in this application are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the method embodiments, since they are implemented based on the structure of the product class embodiments, some descriptions of the product structure are omitted; relevant details can be found in the descriptions of the product class embodiments.

[0101] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An SCR device, characterized in that, include: A p-type substrate, an n-type deep well region formed in the p-type substrate, a first p-type well region formed in the n-type deep well region, a second p-type well region formed in the p-type substrate, a first n-type well region formed by implanting both the n-type deep well region and the p-type substrate at the boundary between the n-type deep well region and the p-type substrate, a first p-heavy doped region formed on the first n-type well region, a first n-heavy doped region formed by implanting both the first n-type well region and the first p-type well region at the boundary between the first n-type well region and the first p-type well region, a second p-heavy doped region formed on the first p-type well region, a third p-heavy doped region formed on the first p-type well region, a second n-heavy doped region formed on the first p-type well region, a third n-heavy doped region formed by implanting both the first p-type well region and the first n-type well region at the boundary between the first p-type well region and the first n-type well region, and a fourth n-heavy doped region formed on the first n-type well region. The first n-type well region is arranged around the outer periphery of the first p-type well region, and the second p-type well region is arranged around the outer periphery of the first n-type well region; The first p-doped region, the first n-doped region, the second p-doped region, the third p-doped region, the second n-doped region, the third n-doped region, and the fourth n-doped region are spaced apart along a first direction, which is perpendicular to the thickness direction of the p-type substrate. The SCR device further includes a gate dielectric layer, a cathode, and an anode. The gate dielectric layer is formed between the second n-doped region, the third n-doped region, and the first p-type well region. The first p-doped region and the fourth n-doped region are metal interconnected to the anode. The third p-doped region and the second n-doped region are metal interconnected to the cathode. The first n-doped region is metal interconnected to the third n-doped region. The second p-doped region is metal interconnected to the gate dielectric layer.

2. The SCR device according to claim 1, characterized in that, The second p-type well region is isolated from the first p-doped region, the first p-doped region is isolated from the first n-doped region, the first n-doped region is isolated from the second p-doped region, the second p-doped region is isolated from the third p-doped region, the third p-doped region is isolated from the second n-doped region, the third n-doped region is isolated from the fourth n-doped region, and the fourth n-doped region is isolated from the second p-type well region by shallow trench dielectric.

3. The SCR device according to claim 1, characterized in that, The n-type deep well region, the first p-type well region, the first n-type well region, the second p-type well region, the first p-heavy doped region, the first n-heavy doped region, the second p-heavy doped region, the third p-heavy doped region, the second n-heavy doped region, the third n-heavy doped region, and the fourth n-heavy doped region are all formed by ion implantation or diffusion.

4. The SCR device according to claim 1, characterized in that, The ion doping concentrations of the first p-doped region, the first n-doped region, the second p-doped region, the third p-doped region, the second n-doped region, the third n-doped region, and the fourth n-doped region are all greater than 1 × 10⁻⁶. 18 cm -3 ; The ion doping concentration of the first p-type well region, the first n-type well region, and the second p-type well region is 1×10⁻⁶. 16 cm -3 ~ 1×10 18 cm -3 ; The ion doping concentration of the n-type deep well region is 1×10⁻⁶. 16 cm -3 ~ 1×10 19 cm -3 .

5. A process method for an SCR device as described in any one of claims 1 to 4, characterized in that, Including the following steps: Prepare a p-type substrate; The p-type substrate is etched to form a plurality of shallow trenches, and a shallow trench medium is injected into each of the shallow trenches. The plurality of shallow trenches into which the shallow trench medium is injected are spaced apart along a first direction, the first direction being perpendicular to the thickness direction of the p-type substrate. An n-type deep well region is formed in the p-type substrate; A first p-type well region is formed in the n-type deep well region, and a second p-type well region is formed in the p-type substrate. At the junction of the n-type deep well region and the p-type substrate, the first n-type well region is simultaneously implanted into the n-type deep well region and the p-type substrate to form the first n-type well region. The first n-type well region is arranged around the outer periphery of the first p-type well region, and the second p-type well region is arranged around the outer periphery of the first n-type well region. A first p-doped region is formed on the first n-type well region. At the boundary between the first n-type well region and the first p-type well region, a first n-fold doped region is simultaneously implanted into both the first n-type well region and the first p-type well region to form a first n-fold doped region. A second p-fold doped region is formed on the first p-type well region. A third p-fold doped region is formed on the first p-type well region. A second n-fold doped region is formed on the first p-type well region. At the boundary between the first p-type well region and the first n-type well region, a third n-fold doped region is simultaneously implanted into both the first p-type well region and the first n-type well region to form a third n-fold doped region. A fourth n-fold doped region is formed on the first n-type well region. The first p-fold doped region and the first n-fold doped region... The second p-doped region, the third p-doped region, the second n-doped region, the third n-doped region, and the fourth n-doped region are spaced apart along the first direction, and the second p-type well region is isolated from the first p-doped region, the first p-doped region is isolated from the first n-doped region, the first n-doped region is isolated from the second p-doped region, the second p-doped region is isolated from the third p-doped region, the third p-doped region is isolated from the second n-doped region, the third n-doped region is isolated from the fourth n-doped region, and the fourth n-doped region is isolated from the second p-type well region by the corresponding shallow trench medium. The gate dielectric layer is formed between the second n-fold doped region, the third n-fold doped region and the first p-type well region; The first p-doped region and the fourth n-doped region are respectively interconnected with the anode, the third p-doped region and the second n-doped region are respectively interconnected with the cathode, the first n-doped region and the third n-doped region are interconnected with each other, and the second p-doped region is interconnected with the gate dielectric layer.

6. A chip, characterized in that, Includes the SCR device as described in any one of claims 1 to 4.

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