Array substrate and display panel

Abstract

The invention provides an array substrate and a display panel, and the array substrate comprises a thin film transistor layer which is provided with a plurality of driving transistors arranged in an array mode, and in pixels adjacent in the row direction or the column direction, sub-pixels of the same color are arranged in a zigzag mode; the anode layer is provided with a plurality of anode patterns which are arranged in an array and are in one-to-one correspondence with the sub-pixels with different colors, the anode patterns of the sub-pixels which are at least partially far away from the grid electrode of the driving transistor comprise extension parts, and the extension parts extend to the grid electrode of the driving transistor for driving the sub-pixels corresponding to the anode patterns and are partially overlapped with the grid electrode of the driving transistor; the parasitic capacitance generated by the anodes of the sub-pixels of the same color and the parasitic capacitance generated by the grid electrode of the driving transistor are equal. By changing the shape of the anode pattern, the area of the overlapping area between the anode pattern of the sub-pixel with the same color and the grid electrode of the driving transistor is the same, so that stray capacitance with the same capacitance value is formed, the problem of displayed thin stripes is avoided, and the display effect is improved.

Description

Technical Field

[0001] The present invention relates to the display field of display panels, and in particular to an array substrate and a display panel. Background Art

[0002] AMOLED (Active Matrix Organic Light Emitting Diode) display panels are recognized by the industry as the third generation display technology after liquid crystal displays due to their advantages such as low power consumption, high brightness, high contrast, wide viewing angle, fast response speed, and easy to make flexible panels.

[0003] Since AMOLED sub-pixels are usually arranged in a Delta pattern, sub-pixels of the same color in two adjacent columns of pixels in the same row are not on the same horizontal line. Figure 1 A schematic diagram showing a pixel arrangement structure of a display panel in the prior art is shown; Figure 2 Show Figure 1 Schematic diagram of the overlapping state of the anode pattern and the gate of the driving transistor; Figure 3 Show Figure 1 A physical picture of the overlapping state of the anode pattern and the gate of the driving transistor. Figures 1 to 3 For a single sub-pixel column, taking the first sub-pixel 11 as an example, in the same row of pixels, the first sub-pixels 11 of two adjacent columns are not on the same horizontal line. As a result, the overlapping area 40 of the first anode pattern 21' and the gate 30 of the driving transistor corresponding to the first sub-pixels 11 of the two adjacent columns is different, which causes the image displayed by the display panel to have fine stripes, ultimately affecting the user experience. This problem also widely exists in other sub-pixel arrangements of AMOLED display panels.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] In view of this, the present invention provides an array substrate and a display panel to at least solve the above technical problems.

[0006] One aspect of the present invention provides an array substrate, characterized in that it includes:

[0007] substrate;

[0008] The thin film transistor layer is located on one side of the substrate and is provided with a plurality of driving transistors arranged in an array for driving sub-pixels to emit light. In adjacent pixels along the row direction or the column direction, the sub-pixels of the same color are arranged in a zigzag pattern.

[0009] The anode layer is located on the side of the thin film transistor layer away from the substrate, and is provided with a plurality of anode patterns of different types arranged in an array and corresponding to the sub-pixels of different colors one by one. Among the pixels adjacent along the row direction or the column direction, the anode pattern of the sub-pixel at least partially away from the gate of the driving transistor includes an extension portion, and the extension portion extends to the gate of the driving transistor that drives the sub-pixel corresponding to the anode pattern and partially overlaps with the gate, so that the parasitic capacitance generated by the anode of the sub-pixel of the same color and the gate of the driving transistor are equal.

[0010] In some embodiments, the anode pattern away from the gate of the driving transistor also includes a main body, and the anode pattern close to the gate of the driving transistor also includes a main body, and the projection of the sub-pixel on the substrate is included in the projection of the main body on the substrate.

[0011] In some embodiments, in the same category of the anode patterns, the overlapping area between the extended portion of the anode pattern away from the gate of the driving transistor and the gate of the driving transistor is equal to the overlapping area between the main portion of the anode pattern close to the gate of the driving transistor and the gate of the driving transistor.

[0012] In some embodiments, among the anode patterns of the same category, the capacitance value of the parasitic capacitor formed by the anode patterns and the gate of the driving transistor with the same overlapping area is the same.

[0013] In some embodiments, among the anode patterns of the same category, the anode patterns away from the gate of the driving transistor have the same shape, and the anode patterns close to the gate of the driving transistor also have the same shape.

[0014] In some embodiments, the direction in which the gates of the plurality of driving transistors driving the sub-pixels are sequentially arranged is parallel or perpendicular to the direction in which the pixels are arranged.

[0015] In some embodiments, projections of all the anode patterns on the substrate are separated.

[0016] In some embodiments, in the same category of the anode patterns, the number of the anode patterns including the extension portion and the number of the other anode patterns are the same, and the two are respectively arranged in a uniform array in the anode layer.

[0017] In some embodiments, the array substrate further includes:

[0018] The light emitting layer is located on a side of the anode layer away from the thin film transistor layer. A plurality of sub-pixel arrays are arranged in the light emitting layer. The sub-pixels correspond to the anode patterns one by one.

[0019] Another aspect of the present invention further provides a display panel, characterized by comprising any one of the above array substrates.

[0020] The beneficial effects of the present invention compared with the prior art include at least:

[0021] The array substrate and display panel of the present invention change the shape of the anode pattern so that the area of ​​the overlapping region between the anode pattern of the same-color sub-pixel and the gate of the driving transistor is the same, so that the anode of the same-color sub-pixel and the gate of the driving transistor form a parasitic capacitor with the same capacitance value, thereby avoiding the fine stripe problem of the display panel and improving the display effect of the display panel.

[0022] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification are used to explain the principles of the present invention. Obviously, the accompanying drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0024] Figure 1 A schematic diagram showing a pixel arrangement structure of a display panel in the prior art is shown;

[0025] Figure 2 Show Figure 1 Schematic diagram of the overlapping state of the anode pattern and the gate of the driving transistor;

[0026] Figure 3 Show Figure 1 A physical diagram of the overlapping state of the anode pattern and the gate of the driving transistor;

[0027] Figure 4 A schematic diagram showing an overlapping state of an anode pattern and a gate of a driving transistor in a pixel arrangement structure of the present invention;

[0028] Figure 5 Show Figure 4 A physical picture of the overlapping state of the anode pattern and the gate of the driving transistor;

[0029] Figure 6 A schematic diagram showing an overlapping state of an anode pattern and a gate of a driving transistor in another pixel arrangement structure of the present invention;

[0030] Figure 7 Show Figure 6 A physical picture of the overlapping state of the anode pattern and the gate of the driving transistor;

[0031] Figure 8 A schematic diagram showing the overlapping state of an anode pattern and a gate of a driving transistor in another pixel arrangement structure of the present invention.

[0032] Reference numerals:

[0033] 21' The first anode pattern of the prior art

[0034] 22' Second anode pattern of the prior art

[0035] 23' The third anode pattern of the prior art

[0036] 10 sub-pixels

[0037] 11 First sub-pixel

[0038] 12 Second sub-pixel

[0039] 13 Third sub-pixel

[0040] 20 Anode pattern

[0041] 21. First anode pattern

[0042] 211 Main body

[0043] 212 Extension

[0044] 22. Second anode pattern

[0045] 23. Third anode pattern

[0046] 30 Gate of driver transistor

[0047] 40 Overlapping Area DETAILED DESCRIPTION

[0048] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their repeated description will be omitted.

[0049] The words "first", "second" and the like used in the specific description do not indicate any order, quantity or importance, but are only used to distinguish different components. In addition, in the description of the present invention, the orientation or position relationship indicated by the terms "upper" and "lower" are based on the orientation or position relationship shown in the drawings, which are only for the convenience of description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0050] It should be noted that, in the absence of conflict, the embodiments of the present invention and features in different embodiments may be combined with each other.

[0051] In the prior art, such as Figures 1 to 3 As shown in FIG. 1 , when the AMOLED display panel adopts a pixel arrangement such as Delta arrangement where the sub-pixels of the same color in two adjacent columns of the same row of pixels are not on the same horizontal line, the image displayed by the display panel will produce jagged fine stripes, affecting the display effect. Figure 2 , please refer to the actual picture Figure 3 Taking the first sub-pixel 11 as an example, the first sub-pixels 11 of two adjacent columns in the same row of pixels have two first anode patterns 21' corresponding to the two of them with the same shape, but an overlapping region 40 is formed between one of the first anode patterns 21' and the gate 30 of the driving transistor, thereby forming a larger parasitic capacitance between the anode of the first sub-pixel 11 and the gate 30 of the driving transistor. However, there is no overlap between the first anode patterns 21' corresponding to the adjacent first sub-pixels 11 in the same row of pixels and the gate 30 of the driving transistor, and there is no overlapping region 40, thereby forming a smaller parasitic capacitance between the anode of the first sub-pixel 11 and the gate 30 of the driving transistor. The capacitance value of the parasitic capacitance formed between the anode of the first sub-pixel 11 of two adjacent columns in the same row of pixels and the gate 30 of the driving transistor is incompatible, resulting in display differences, thereby causing the problem of fine stripes in display.

[0052] The inventor of this case has provided a solution to the problems existing in the prior art through careful and in-depth research. Figure 4 , 6 As shown in 8, Figure 4 A schematic diagram showing an overlapping state of an anode pattern and a gate of a driving transistor in a pixel arrangement structure of the present invention; Figure 6 A schematic diagram showing an overlapping state of an anode pattern and a gate of a driving transistor in another pixel arrangement structure of the present invention; Figure 8A schematic diagram showing the overlapping state of the anode pattern and the gate of the driving transistor in another pixel arrangement structure of the present invention is shown. The present invention discloses an array substrate and a display panel, wherein the array substrate comprises: a substrate; a thin film transistor layer, located on one side of the substrate, provided with a plurality of driving transistors arranged in an array, used to drive the sub-pixels 10 to emit light, and in adjacent pixels along the row direction or the column direction, the sub-pixels 10 of the same color are arranged in a zigzag shape; an anode layer, located on the side of the thin film transistor layer away from the substrate, provided with a plurality of anode patterns 20 of different categories arranged in an array corresponding to the sub-pixels 10 of different colors, and in adjacent pixels along the row direction or the column direction, the anode pattern 20 of the sub-pixel 10 at least partially away from the gate 30 of the driving transistor comprises an extension portion 212, and the extension portion 212 extends to the gate 30 of the driving transistor that drives the sub-pixel 10 corresponding to the anode pattern 20 and partially overlaps with it, so that the parasitic capacitance generated by the anode of the sub-pixel 10 of the same color and the gate 30 of the driving transistor are equal. The array substrate and display panel of the present invention change the shape of the anode pattern 20 so that the area of ​​the overlapping region 40 between the anode pattern 20 of the same-color sub-pixel 10 and the gate 30 of the driving transistor is the same, so that the anode of the same-color sub-pixel 10 and the gate 30 of the driving transistor form a parasitic capacitor with the same capacitance value, thereby avoiding the fine stripe problem of the display panel and improving the display effect of the display panel.

[0053] The specific implementation modes of the present invention are further described in detail below with reference to the accompanying drawings.

[0054] The first embodiment of the present invention refers to Figures 4 to 5 , Figure 5 Show Figure 4 A physical diagram of the overlapping state of the anode pattern and the gate of the driving transistor, providing an array substrate, including: a substrate, a thin film transistor layer, an anode layer and a light-emitting layer. The thin film transistor layer is located on one side of the substrate, the anode layer is located on the side of the thin film transistor layer away from the substrate, and the light-emitting layer is located on the side of the anode layer away from the thin film transistor layer.

[0055] In this embodiment, the substrate is located at the bottom of the entire array substrate structure and plays an important role in supporting, connecting and protecting various electronic components.

[0056] In the present embodiment, a plurality of sub-pixels 10 are arranged in an array in the light-emitting layer, and the arrangement adopts a Delta arrangement, and in the adjacent pixels along the row direction, the sub-pixels 10 of the same color are arranged in a zigzag shape. The sub-pixels 10 are divided into three categories: a first sub-pixel 11, a second sub-pixel 12, and a third sub-pixel 13. Among them, the first sub-pixel 11, the second sub-pixel 12, and the third sub-pixel 13 can be one of a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. Here, the first sub-pixel 11 can be a red sub-pixel, the second sub-pixel 12 can be a green sub-pixel, and the third sub-pixel 13 can be a blue sub-pixel, but it is not limited thereto. The projections of all sub-pixels 10 on the substrate are separated. In other embodiments, the sub-pixels 10 of the same color can also be arranged in a zigzag shape along the column direction or other directions due to different pixel arrangement methods.

[0057] In this embodiment, the thin film transistor layer is provided with a plurality of driving transistors arranged in an array, which are used to drive the sub-pixels 10 to emit light under the action of the pixel driving circuit. For pixels arranged adjacently along the row direction, the arrangement direction of the gate 30 of the driving transistor is parallel to the pixels. Figure 4 , the two pixels include 6 sub-pixels in total, which are divided into 2 first sub-pixels 11, 2 second sub-pixels 12 and 2 third sub-pixels 13. There are 6 gates 30 of the driving transistors corresponding to the 6 sub-pixels. In addition, the straight line where the center of the gate 30 of the driving transistor is located is parallel to the straight line where the center of the two pixels is located, but does not overlap. In other embodiments of the present invention, the straight line where the center of the gate 30 of the driving transistor is located and the straight line where the center of the two pixels is located can also be perpendicular to each other, or intersect at other angles.

[0058] In this embodiment, the anode layer is provided with a plurality of anode patterns 20 of different categories arranged in an array and corresponding to sub-pixels 10 of different colors. The anode pattern 20 is a group of conductive areas with a specific pattern on the anode layer, which form a pixel array. Each small area of ​​the anode pattern 20 corresponds to a sub-pixel 10 on the display panel. In the display panel, there are usually anode patterns of three colors, red, green and blue, which control the light emission of each sub-pixel 10 respectively. The shape and layout of the anode pattern 20 determine the light-emitting area and brightness of each pixel. Specifically, the anode pattern 20 is also divided into three categories: a first anode pattern 21, a second anode pattern 22 and a third anode pattern 23. Among them, the first anode pattern 21, the second anode pattern 22 and the third anode pattern 23 correspond to the first sub-pixel 11, the second sub-pixel 12 and the third sub-pixel 13 respectively. In addition, the projection of the sub-pixel 10 on the substrate is included in the projection of the anode pattern 20 on the substrate. That is, the shape of the anode pattern 20 matches the sub-pixel 10, and the size is slightly larger than the sub-pixel 10. Furthermore, the projections of all the anode patterns 20 on the substrate are separated, that is, each anode pattern 20 is not connected with other anode patterns 20 on the anode layer.

[0059] refer to Figure 4 and 5 , for pixels arranged adjacently along the row direction, the sub-pixels 10 of the same color are arranged in a zigzag shape. Taking the first sub-pixel 11 as an example, the distances between the two first sub-pixels 11 of adjacent pixels and the gate 30 of the driving transistor are different. Corresponding to the first sub-pixel 11, the distances between the two first anode patterns 21 of adjacent pixels and the gate 30 of the driving transistor are also different. Among them, in the same row of pixels, the first anode patterns 21 away from the gate 30 of the driving transistor have the same shape, and the first anode patterns 21 close to the gate 30 of the driving transistor also have the same shape. By extension, in the anode patterns arranged in the entire anode layer array, the first anode patterns 21 away from the gate 30 of the driving transistor have the same shape, and the first anode patterns 21 close to the gate 30 of the driving transistor also have the same shape. Correspondingly, the second anode pattern 22 and the third anode pattern 23 also have the same characteristics.

[0060] Continue to refer Figure 4 and 5 For pixels arranged adjacent to each other in the row direction, taking the first anode pattern 21 as an example, the first anode pattern 21 close to the gate 30 of the driving transistor and the first anode pattern 21 far from the gate 30 of the driving transistor have different shapes. However, the overlapping areas of the two with the gate 30 of the driving transistor are the same, and the capacitance values ​​of the parasitic capacitors formed are also the same.

[0061] Specifically, the first anode pattern 21 close to the gate 30 of the driving transistor only includes a main body 211, and an overlapping area 40 is formed between the main body 211 and the gate 30 of the driving transistor, thereby forming a parasitic capacitor between the anode of the first sub-pixel 11 and the gate 30 of the driving transistor. The first anode pattern 21 far from the gate 30 of the driving transistor includes not only the main body 211, but also an extension 212. There is no overlap between the main body 211 and the gate 30 of the driving transistor. In other embodiments of the present invention, the two may also overlap. Another overlapping area 40 is formed between the extension 212 and the gate 30 of the driving transistor, thereby forming a parasitic capacitor between the anode of the first sub-pixel 11 and the gate 30 of the driving transistor. Among them, the area of ​​the overlapping area 40 between the main body 211 of the first anode pattern 21 close to the gate 30 of the driving transistor and the gate 30 of the driving transistor is equal to the area of ​​the overlapping area 40 between the extension 212 of the first anode pattern 21 far from the gate 30 of the driving transistor and the gate 30 of the driving transistor. Furthermore, the capacitance value of the parasitic capacitance formed between the anode of the first sub-pixel 11 close to the gate 30 of the driving transistor and the gate 30 of the driving transistor is equal to the capacitance value of the parasitic capacitance formed between the anode of the first sub-pixel 11 far from the gate 30 of the driving transistor and the gate 30 of the driving transistor. Accordingly, the second anode pattern 22 and the third anode pattern 23 also have the same characteristics.

[0062] In this embodiment, taking the first anode pattern 21 as an example, the number of the anode pattern 20 including the extension portion 212 is the same as that of the other anode patterns 20, and the two are arranged in a uniform array in the anode layer. In other embodiments of the present invention, the two may also be different, but they all satisfy that the area of ​​the overlapping region 40 formed between all the first anode patterns 21 and the gate 30 of the driving transistor is the same, and thus the capacitance value of the parasitic capacitor formed between the anode of all the first sub-pixels 11 and the gate 30 of the driving transistor is the same. Correspondingly, the second anode pattern 22 and the third anode pattern 23 also have the same characteristics.

[0063] In addition, in this embodiment, taking the first sub-pixel 11 as an example, it corresponds to two first anode patterns 21 of different shapes, both of which include a main body 211, and all projections of the first sub-pixels 11 on the substrate are included in the projection of the main body 211 on the substrate. Correspondingly, the second sub-pixel 12 and the third sub-pixel 13 also have the same characteristics.

[0064] The array substrate of the present embodiment changes the shape of the anode pattern 20 so that the area of ​​the overlapping region 40 between the anode pattern 20 of the same-color sub-pixel 10 and the gate 30 of the driving transistor is the same, thereby making the parasitic capacitors formed by the anode of the same-color sub-pixel 10 and the gate 30 of the driving transistor have the same capacitance value, thereby avoiding the fine stripe problem of the display panel and improving the display effect of the display panel.

[0065] In the second embodiment of the present invention, reference Figures 6 to 7 , Figure 7 Show Figure 6 A physical diagram of the overlapping state of the anode pattern and the gate of the driving transistor. In this embodiment, the film layer arrangement of the array substrate is the same as that of the first embodiment, and will not be repeated here.

[0066] In particular, in this embodiment, the pixels of the light-emitting layer of this embodiment adopt a pixel arrangement structure different from that of the first embodiment, and in the pixels adjacent along the column direction, the sub-pixels 10 of the same color are arranged in a zigzag shape. In two pixels adjacent along the column direction, the straight line where the center of the gate 30 of the driving transistor is located is parallel to the row direction. That is, the straight line where the center of the gate 30 of the driving transistor is located and the straight line where the center of the two pixels is located are perpendicular to each other.

[0067] In this embodiment, the second anode pattern 22 and the third anode pattern 23 only include the main body 211, and the overlapping region 40 of the second anode pattern 22 and the gate 30 of the driving transistor has the same area, and thus the parasitic capacitance is also the same. There is no overlap between the third anode pattern 23 and the gate 30 of the driving transistor.

[0068] The overlapping area 40 of the first anode pattern 21 of this embodiment and the gate 30 of the driving transistor is also the same in area, but the overlapping method is different from that of the first embodiment. The first anode pattern 21 of this embodiment is divided into two categories, and both categories of first anode patterns 21 have a main body 211 and an extension 212. However, the overlapping area between the main body 211 of the first category of the first anode pattern 21 and the gate 30 of the driving transistor is equal to the overlapping area between the extension 212 of the second category of the first anode pattern 21 and the gate 30 of the driving transistor; the overlapping area between the extension 212 of the first category of the first anode pattern 21 and the gate 30 of the driving transistor is equal to the overlapping area between the main body 211 of the second category of the first anode pattern 21 and the gate 30 of the driving transistor. Furthermore, the overlapping areas between the two categories of first anode patterns 21 and the gate 30 of the driving transistor are equal as a whole, and the parasitic capacitance formed is also equal. Moreover, the shapes of the two categories of first anode patterns 21 can be different, as long as the area of ​​the overlapping area 40 is the same.

[0069] This embodiment can achieve the same technical effects as the first embodiment, and will not be described in detail here.

[0070] In the third embodiment of the present invention, reference Figure 8 In this embodiment, the film layer setting of the array substrate is the same as that of the first embodiment, and will not be described again here.

[0071] In particular, in this embodiment, the pixels of the light-emitting layer of this embodiment adopt a pixel arrangement structure different from that of the first embodiment, wherein the shapes of the first sub-pixel 11, the second sub-pixel 12, and the third sub-pixel 13 are different from those of the first embodiment, but the positional relationship of the three sub-pixels 10 is the same as that of the first embodiment. Accordingly, the shapes of the first anode pattern 21, the second anode pattern 22, and the third anode pattern 23 are also different from those of the first embodiment, but the positional relationship is the same.

[0072] In this embodiment, taking the first anode pattern 21 as an example, the configuration of the main body 211 and the extension portion 212 is the same as that of the first embodiment, and the second anode pattern 22 and the third anode pattern 23 are the same, which will not be repeated here.

[0073] The anode pattern arrangement of this embodiment can achieve the same technical effect as that of the first embodiment, and will not be described in detail here.

[0074] Based on the same inventive concept, an embodiment of the present invention further provides a display panel, which uses any of the above array substrates. Specifically, the display panel can be an AMOLED display panel, an OLED display panel, or other display panels that can use the array substrate provided by the present invention. The display panel of the present invention is based on including any of the above array substrates, so it can achieve the same technical effects, and the repeated parts will not be repeated.

[0075] Based on the same inventive concept, an embodiment of the present invention further provides a display device, including the above-mentioned display panel provided in an embodiment of the present invention. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc. The technical effects of the implementation of the display device can be referred to the embodiment of the above-mentioned display panel, and the repeated parts will not be repeated.

[0076] In summary, the array substrate and the display panel of the present invention change the shape of the anode pattern so that the area of ​​the overlapping region between the anode pattern of the same-color sub-pixel and the gate of the driving transistor is the same, so that the anode of the same-color sub-pixel and the gate of the driving transistor form a parasitic capacitor with the same capacitance value, thereby avoiding the fine stripe problem of the display panel and improving the display effect of the display panel.

[0077] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. An array substrate, characterized in that: include: substrate; The thin film transistor layer is located on one side of the substrate and is provided with a plurality of driving transistors arranged in an array for driving sub-pixels to emit light. In adjacent pixels along the row direction or the column direction, the sub-pixels of the same color are arranged in a zigzag pattern. The anode layer is located on the side of the thin film transistor layer away from the substrate, and is provided with a plurality of anode patterns of different types arranged in an array and corresponding to the sub-pixels of different colors one by one. Among the pixels adjacent along the row direction or the column direction, the anode pattern of the sub-pixel at least partially away from the gate of the driving transistor includes an extension portion, and the extension portion extends to the gate of the driving transistor that drives the sub-pixel corresponding to the anode pattern and partially overlaps with the gate, so that the parasitic capacitance generated by the anode of the sub-pixel of the same color and the gate of the driving transistor are equal.

2. The array substrate according to claim 1, characterized in that: The anode pattern away from the gate of the driving transistor further includes a main body, and the anode pattern close to the gate of the driving transistor also includes a main body, and the projection of the sub-pixel on the substrate is included in the projection of the main body on the substrate.

3. The array substrate according to claim 2, characterized in that: In the anode patterns of the same category, the overlapping area between the extension portion of the anode pattern away from the gate of the driving transistor and the gate of the driving transistor is equal to the overlapping area between the main portion of the anode pattern close to the gate of the driving transistor and the gate of the driving transistor.

4. The array substrate according to claim 3, characterized in that: Among the anode patterns of the same category, the capacitance value of the parasitic capacitor formed by the anode patterns and the gate of the driving transistor with the same overlapping area is the same.

5. The array substrate according to claim 2, characterized in that: Among the anode patterns of the same type, the anode patterns far from the gate of the driving transistor have the same shape, and the anode patterns close to the gate of the driving transistor also have the same shape.

6. The array substrate according to claim 1, characterized in that: The direction in which the gate electrodes of the plurality of driving transistors driving the sub-pixels are sequentially arranged is parallel or perpendicular to the direction in which the pixels are arranged.

7. The array substrate according to claim 1, wherein: The projections of all the anode patterns on the substrate are separated from each other.

8. The array substrate according to claim 1, wherein: Among the anode patterns of the same category, the number of the anode patterns including the extension portion and the number of the other anode patterns are the same, and the two are respectively arranged in a uniform array on the anode layer.

9. The array substrate according to claim 1, wherein: Also includes: The light emitting layer is located on a side of the anode layer away from the thin film transistor layer. A plurality of sub-pixel arrays are arranged in the light emitting layer. The sub-pixels correspond to the anode patterns one by one.

10. A display panel, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 9.

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