Array substrate, visual angle control box and display device

Abstract

An array substrate (410) comprises a substrate (10), a first wiring layer (20), a second wiring layer (30), a first electrode layer (40) and a second electrode layer (60). The first wiring layer (20) comprises a plurality of grid lines (21) arranged at intervals in the first direction (Y), and the grid lines (21) extend in the second direction (X). The second wiring layer (30) comprises a plurality of data lines (31) arranged at intervals in the second direction (X), and the data lines (31) extend in the first direction (Y). Orthographic projections of the grid lines (21) and the data lines (31) on the substrate (10) intersect with each other, two adjacent grid lines (21) and two adjacent data lines (31) define a dimming area (401), and the dimming area (401) is configured to be switched between a sharing state and a peep-proof state. Each dimming area (401) is provided with a first electrode (41). The second electrode layer (60) includes a second electrode (61). The orthographic projection of the second electrode (61) on the substrate (10) at least partially does not coincide with the orthographic projection of the first electrode (41) on the substrate (10), and at least partially does not coincide with the orthographic projection of the thin film transistor (50) on the substrate (10).

Description

Array substrate, viewing angle control box and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a viewing angle control box, and a display device. Background Art

[0002] With the development of display technology, people have put forward higher requirements for the confidentiality and privacy of display devices. In order to prevent "visual intrusion" and "information leakage" when working in public places, display devices with anti-peeping functions have been developed. The anti-peeping function means that the display device has two display modes: sharing mode and anti-peeping mode. Existing anti-peeping display technology usually performs anti-peeping processing on the entire screen of the display device, that is, the display area of ​​the display device is displayed in the sharing mode, or the display area is displayed in the anti-peeping mode. However, with the increase in the size of the display device, the above-mentioned display technology that can only achieve full anti-peeping can no longer meet the needs of users.

[0003] Summary of the Invention

[0004] In one aspect, an array substrate is provided. The array substrate includes a substrate, a first routing layer, a second routing layer, a first electrode layer, and a second electrode layer. The first routing layer includes a plurality of gate lines spaced apart along a first direction, the gate lines extending along a second direction. The first direction intersects the second direction. The second routing layer is disposed on a side of the first routing layer away from the substrate and includes a plurality of data lines spaced apart along the second direction, the data lines extending along the first direction. The orthographic projections of the gate lines on the substrate intersect with the orthographic projections of the data lines on the substrate. Two adjacent gate lines and two adjacent data lines define a dimming zone, which is configured to switch between a shared state and an anti-peeping state. The first electrode layer is disposed on a side of the second routing layer away from the substrate and includes a plurality of first electrodes. Each dimming zone is provided with one of the first electrodes. The second electrode layer is disposed on a side of the first electrode layer away from the substrate and includes a second electrode. The orthographic projection of the second electrode on the substrate at least partially does not overlap with the orthographic projection of the first electrode on the substrate and at least partially does not overlap with the orthographic projection of the thin-film transistor on the substrate.

[0005] In some embodiments, each dimming zone is provided with a thin film transistor; the thin film transistor is electrically connected to the gate line, the data line, and the first electrode, and is configured to transmit a data signal from the data line to the first electrode under the control of a scan signal from the gate line. The second electrode includes a plurality of avoidance openings, one of which is provided in each dimming zone. The orthographic projection of the avoidance opening on the substrate at least partially overlaps with the orthographic projection of the thin film transistor on the substrate.

[0006] In some embodiments, the thin film transistor includes a gate pattern, a semiconductor pattern, a source pattern, and a drain pattern. The gate pattern is arranged on the first wiring layer and is connected to the gate line. The semiconductor pattern is arranged between the gate line layer and the second wiring layer. The source pattern is arranged on the second wiring layer and is connected to the data line. The drain pattern is arranged on the second wiring layer, spaced apart from the source pattern, and the orthographic projection of the drain pattern on the substrate does not overlap with the orthographic projection of the first electrode on the substrate. The orthographic projection of the gate pattern on the substrate covers the orthographic projections of the semiconductor pattern and the source pattern on the substrate, and partially overlaps with the orthographic projection of the drain pattern on the substrate; the orthographic projection of the avoidance opening on the substrate partially overlaps with the orthographic projections of the gate pattern, the semiconductor pattern, and the source pattern on the substrate, and covers the orthographic projection of the drain pattern on the substrate.

[0007] In some embodiments, the avoidance opening includes a first opening portion, wherein a boundary shape of the first opening portion is substantially the same as a boundary shape of the semiconductor pattern, and an orthographic projection of the first opening portion on the substrate is located within an orthographic projection of the semiconductor pattern on the substrate.

[0008] In some embodiments, the second electrode layer further includes a transfer block, the transfer block being located within the avoidance opening and spaced apart from a boundary of the avoidance opening, and the transfer block being electrically connected to the drain pattern and the first electrode, respectively.

[0009] In some embodiments, the avoidance opening further includes a second opening portion. The boundary shape of the second opening portion is substantially the same as the boundary shape of the adapter block, and the boundary of the second opening portion surrounds the adapter block.

[0010] In some embodiments, a distance between a boundary of the transfer block and a boundary of the second opening is 6 μm to 20 μm.

[0011] In some embodiments, the orthographic projection of the adapter block on the substrate does not overlap with the orthographic projections of the data line and the gate line on the substrate.

[0012] In some embodiments, the second electrode includes a plurality of third electrode strips and a plurality of fourth electrode strips. The plurality of third electrode strips are spaced apart along the second direction, and the third electrode strips extend along the first direction. The fourth electrode strips are connected to ends of the third electrode strips, and the extension direction of the fourth electrode strips is parallel to the extension direction of the gate lines. The orthographic projections of the fourth electrode strips on the substrate at least partially overlap with the orthographic projections of the gate lines on the substrate.

[0013] In some embodiments, the fourth electrode strip includes at least one protrusion and a straight portion connected to the protrusion; along the first direction, the size of the protrusion is larger than the size of the straight portion, and along the second direction, the size of the protrusion is larger than the size of the straight portion.

[0014] In some embodiments, the plurality of third electrode strips located in the same dimming zone include a first sub-electrode strip, a second sub-electrode strip, and a third sub-electrode strip. The first sub-electrode strip has two ends along the first direction connected to the straight portion, respectively. The second sub-electrode strip has one end along the first direction connected to the straight portion, and the other end connected to the protruding portion. The third sub-electrode strip has two ends along the first direction connected to the protruding portion, respectively. The first sub-electrode strip has a larger size in the first direction than the second sub-electrode strip, and the second sub-electrode strip has a larger size in the first direction than the third sub-electrode strip.

[0015] In some embodiments, the second electrode further includes a first slit located between two adjacent third electrode strips. The first electrode includes a plurality of first electrode strips spaced apart along the second direction, and a second slit located between two adjacent first electrode strips. The orthographic projections of the first and second slits on the substrate overlap, and the overlapping portion of the first and second slits forms a third slit. The dimension of the third slit in the second direction is smaller than the dimension of the first electrode strips in the second direction, and / or the dimension of the second electrode strips in the second direction.

[0016] In some embodiments, two adjacent first slits along the first direction are respectively a first sub-slit and a second sub-slit. The first sub-slit and the second sub-slit are located on either side of the fourth electrode strip and are connected to opposite sides of the fourth electrode strip. The end of the first sub-slit proximal to the fourth electrode strip is connected to the protruding portion, and the end of the second sub-slit proximal to the fourth electrode strip is connected to the straight portion. The dimension of the first sub-slit in the first direction is smaller than the dimension of the second sub-slit in the first direction.

[0017] In some embodiments, within the same dimming zone, the plurality of first slits include a third sub-slit, a fourth sub-slit, and a fifth sub-slit. The third sub-slit is connected to the straight portion at both ends along the first direction. The fourth sub-slit is connected to the straight portion at one end along the first direction and to the protruding portion at the other end. The fifth sub-slit is connected to the protruding portion at both ends along the first direction. The size of the third sub-slit in the first direction is larger than the size of the fourth sub-slit in the first direction, and the size of the fourth sub-slit in the first direction is larger than the size of the fifth sub-slit in the first direction.

[0018] In some embodiments, the first electrode includes a plurality of first electrode strips spaced apart along the second direction, and the second electrode includes a plurality of third electrode strips spaced apart along the second direction. The orthographic projections of the first and third electrode strips on the substrate are alternately arranged along the second direction, and a fourth slit is defined between adjacent first and third electrode strips. The dimension of the fourth slit in the second direction is smaller than the dimension of the first and third electrode strips in the second direction.

[0019] In some embodiments, in one of the dimming zones, the first electrode includes a plurality of first electrode strips spaced apart along the second direction, and second electrode strips connected end to end. The first electrode strips extend along the first direction. The second electrode strips are connected to both ends of the first electrode strips along the first direction, forming a structure in which the second electrode strips surround the plurality of first electrode strips.

[0020] In some embodiments, the second electrode strips include two fourth sub-electrode strips and two fifth sub-electrode strips. The two fourth sub-electrode strips are arranged opposite to each other along the first direction, and the extension direction of the first sub-electrode strips is parallel to the extension direction of the gate line. The two fifth sub-electrode strips are arranged opposite to each other along the second direction, and the extension direction of the second sub-electrode strips is parallel to the extension direction of the data line. The spacing between the fourth sub-electrode strip and the orthographic projection of the gate line on the substrate is equal to the spacing between the fifth sub-electrode strip and the orthographic projection of the data line on the substrate.

[0021] In some embodiments, the fourth sub-electrode strip has a sawtooth structure, or the fourth sub-electrode strip has a concave-convex structure.

[0022] In some embodiments, a first groove is provided on an edge of the fourth sub-electrode strip close to the gate line, and an orthographic projection of the first groove on the substrate is spaced apart from an orthographic projection of the gate line on the substrate.

[0023] In some embodiments, the gate line includes at least one light adjustment portion and a connection portion connected to the light adjustment portion, and a width of the light adjustment portion is greater than a width of the connection portion.

[0024] In some embodiments, a ratio of a maximum width of the light adjustment portion to a width of the connecting portion is 1.5-4.

[0025] In some embodiments, a ratio of the length of the connecting portion to the length of the light adjustment portion is 1.5-3.

[0026] In some embodiments, the orthographic projection of the light adjustment portion on the substrate is in a hexagonal or octagonal shape.

[0027] In some embodiments, the gate line is a zigzag line, comprising a plurality of extension segments sequentially connected along the second direction, wherein the extension segment comprises a plurality of the light adjustment portions and a plurality of connection portions alternately connected in sequence, and the two ends of the extension segment are the connection portions.

[0028] In some embodiments, the first electrode has a second groove on a side close to the light adjustment portion, the shape of the second groove is the same as the shape of the side of the light adjustment portion close to the first electrode, and the spacing between the second groove and the light adjustment portion is equal to the spacing between the first electrode and the connecting portion.

[0029] In some embodiments, an orthographic projection of the light adjustment portion on the substrate does not overlap with an orthographic projection of the thin film transistor on the substrate.

[0030] In some embodiments, the gate line includes multiple extension segments, and the multiple extension segments include multiple first extension segments and multiple second extension segments alternately connected; the interconnected first extension segments and the second extension segments are symmetrically arranged about a first reference line, and the angle between the first extension segment and the second extension segment and the second direction is 53° to 73°; the first reference line is parallel to the first direction.

[0031] In some embodiments, the data line is a zigzag line, including a plurality of third extension segments and a plurality of fourth extension segments that are alternately arranged and interconnected along the first direction; the interconnected third extension segments and the fourth extension segments are symmetrically arranged about a second reference line, and the angle between the third extension segment and the fourth extension segment and the first direction is 5° to 10°; the second reference line is parallel to the second direction.

[0032] In some embodiments, the second wiring layer further includes a plurality of common voltage signal lines spaced apart along the first direction. Along the second direction, the data lines and the common voltage signal lines are alternately arranged, and adjacent data lines and common voltage signal lines are symmetrically arranged.

[0033] In some embodiments, the common voltage signal line includes a widened portion, the widened portion is electrically connected to the second electrode, and an orthographic projection of the widened portion on the substrate is located within an orthographic projection of the gate line on the substrate.

[0034] In some embodiments, the array substrate includes a display area and a peripheral area surrounding the display area. The array substrate also includes a common voltage signal bus, a gate drive circuit, a fan-out trace, a chip-on-film, and a driver chip. The common voltage signal bus is located in the peripheral area and surrounds the display area; when the array substrate includes a common voltage signal line, the end of the common voltage signal line along the first direction is connected to the common voltage signal bus. The gate drive circuit is located in the peripheral area and is located on at least one side of the display area along the second direction, and is electrically connected to the gate line. The fan-out trace is located in the peripheral area and is located on one side of the display area along the first direction, and is electrically connected to the data line. The chip-on-film is connected to the fan-out trace. The driver chip is bound to the chip-on-film.

[0035] In another aspect, a viewing angle control box is provided, comprising the array substrate described in any of the above embodiments, an opposing substrate, and a first liquid crystal layer. The opposing substrate is disposed opposite the array substrate and, together with the array substrate, forms a liquid crystal box. The first liquid crystal layer is located within the liquid crystal box and is configured to adjust the deflection direction of the liquid crystal molecules within each dimming zone of the first liquid crystal layer under the control of the array substrate, thereby controlling light entering the liquid crystal layer to exit the liquid crystal layer in a scattered state or a perpendicular state.

[0036] In some embodiments, the viewing angle control box further includes a plurality of spacers. The spacers are located within the liquid crystal cell and are configured to support the array substrate and the opposing substrate. Each spacer includes a first end surface in contact with the array substrate, and an orthographic projection of the first end surface on the substrate is located within an orthographic projection of the light adjustment portion on the substrate.

[0037] In yet another aspect, a display device is provided. The display device includes a viewing angle control box as described in any of the above embodiments, a backlight module, and a liquid crystal display panel. The backlight module is disposed on a side of the viewing angle control box close to the array substrate and is configured to emit light perpendicular to the viewing angle control box in a direction close to the viewing angle control box. The liquid crystal display panel is disposed on a side of the viewing angle control box away from the backlight module.

[0038] In some embodiments, the liquid crystal display panel includes a plurality of sub-pixels, each sub-pixel having a size D1 in a first direction and a size D2 in a second direction. The array substrate includes a plurality of dimming zones, each having a size D3 in the first direction and a size D4 in the second direction; wherein D3 = N × D1 + M; D4 = O × D2 + P; 2 ≤ N ≤ 8, where N is a positive integer; 0.1 μm ≤ M ≤ 0.8 μm; 2 ≤ O ≤ 0.8, where O is a positive integer; and 0.1 μm ≤ P ≤ 0.8 μm. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0040] FIG1 is a structural diagram of a display device according to some embodiments;

[0041] FIG2 is a structural diagram of a liquid crystal display panel according to some embodiments;

[0042] FIG3A is a structural diagram of a viewing angle control box in a transparent state according to some embodiments;

[0043] FIG3B is a structural diagram of a viewing angle control box in a scattering state according to some embodiments;

[0044] FIG4 is a structural diagram of an array substrate according to some embodiments;

[0045] FIG5 is a structural diagram of a first routing layer according to some embodiments;

[0046] FIG6 is a partial enlarged view of the A1 area in FIG5 ;

[0047] FIG7 is a structural diagram of a second routing layer according to some embodiments;

[0048] FIG8A is a structural diagram of a dimming zone according to some embodiments;

[0049] FIG8B is another structural diagram of dimming zones according to some embodiments;

[0050] FIG9A is a diagram illustrating the positional relationship between a first electrode and a dimming zone according to some embodiments;

[0051] FIG9B is a partial enlarged view of the A2 area in FIG9A ;

[0052] FIG10 is a structural diagram of a first electrode according to some embodiments;

[0053] FIG11 is a partial enlarged view of the B1 region in FIG9B when the second electrode is not included;

[0054] FIG12 is a partial enlarged view of the B2 region in FIG9B when the second electrode is not included;

[0055] FIG13A is a partial enlarged view of the B3 region in FIG9B when the second electrode is not included;

[0056] FIG13B is a partial enlarged view of the B3 area in FIG9B ;

[0057] FIG14 is a structural diagram of a thin film transistor according to some embodiments;

[0058] FIG15 is a cross-sectional view taken along section line C1-C1 in FIG13B;

[0059] FIG16A is a structural diagram of a second electrode layer according to some embodiments;

[0060] FIG16B is a partial enlarged view of the A3 area in FIG16A ;

[0061] FIG17A is a partial enlarged view of area B1 in FIG9B ;

[0062] FIG17B is a cross-sectional view taken along section line C2-C2 in FIG17A;

[0063] FIG18 is a partial enlarged view of the B4 area in FIG9B ;

[0064] FIG19 is a cross-sectional view taken along section line C3-C3 in FIG18;

[0065] FIG20 is a partial enlarged view of the B2 area in FIG9B ;

[0066] FIG21 is a cross-sectional view taken along section line C4-C4 in FIG20;

[0067] FIG22 is a partial enlarged view of the B5 area in FIG9B ;

[0068] FIG23 is a cross-sectional view taken along section line C5-C5 in FIG22;

[0069] FIG24 is a structural diagram of a display device partitioned for anti-peeping display according to some embodiments;

[0070] FIG25 is a structural diagram of dimming zones and a display panel according to some embodiments;

[0071] FIG26 is a planar structural diagram of an array substrate according to some embodiments. DETAILED DESCRIPTION

[0072] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0073] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that a particular feature, structure, material or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0074] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0075] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0076] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0077] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0078] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0079] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0080] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0081] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0082] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0083] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0084] Some embodiments of the present disclosure provide a display device, which can be any device that displays either moving (e.g., video) or fixed (e.g., still images), and whether text or images. For example, the display device can be any product or component with a display function, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, an augmented reality (AR) device, or a virtual reality (VR) device.

[0085] The display device may be a liquid crystal display (LCD). The LCD may employ a vertical alignment (VA) display mode, a twisted nematic (TN) display mode, an advanced-super dimensional switching (ADS) display mode, or an in-plane switching (IPS) display mode, though the embodiments of the present disclosure are not limited thereto.

[0086] In the case where the display device is a liquid crystal display device, referring to FIG1 , the display device 1000 includes a liquid crystal display panel 100 and a backlight module 200. Typically, the liquid crystal display panel 100 includes a control substrate 110 (also referred to as an array substrate) and a color filter substrate 120 disposed opposite each other, with a second liquid crystal layer 130 disposed between the control substrate 110 and the color filter substrate 120.

[0087] Referring to FIG2 , a liquid crystal display panel 100 is provided with a plurality of sub-pixels P arranged in an array. The plurality of sub-pixels P may, for example, include a first sub-pixel P1 for emitting a first color light, a second sub-pixel P2 for emitting a second color light, and a third sub-pixel P3 for emitting a third color light. By way of example, the first color, the second color, and the third color are red, green, and blue, respectively. In FIG2 , each grid forms a sub-pixel P, and the grid lines may be signal lines (such as scan signal lines and data signal lines) of the liquid crystal display panel 100. The arrangement of the plurality of sub-pixels P is merely exemplary and may also be arranged in other ways. The embodiments of the present disclosure do not specifically limit this.

[0088] Each sub-pixel P includes a control circuit (not shown) located within a control substrate 110. Continuing with FIG1 , the control circuit may include, for example, a thin film transistor 112 and a pixel electrode 113 located on a first base substrate 111. The thin film transistor 112 includes an active layer, a source electrode, a drain electrode, a gate electrode, and a gate insulating layer. The source electrode and the drain electrode are respectively in contact with the active layer, and the pixel electrode 113 is electrically connected to the drain electrode of the thin film transistor 112.

[0089] In some embodiments, as shown in FIG1 , the control substrate 110 further includes a common electrode 114 disposed on the first base substrate 111. The pixel electrode 113 and the common electrode 114 may be disposed on different layers. In this case, as shown in FIG1 , a first insulating layer 115 is disposed between the pixel electrode 113 and the common electrode 114. A second insulating layer 116 is further disposed between the common electrode 114 and the thin film transistor 112.

[0090] When the common electrode 114 is disposed between the thin film transistor 112 and the pixel electrode 113, as shown in FIG1 , the color filter substrate 120 includes a color filter layer 122 disposed on a second base substrate 121. The color filter layer 122 includes at least red, green, and blue photoresist units. The red, green, and blue photoresist units are aligned with the sub-pixels on the control substrate 110, respectively. The color filter substrate 120 also includes a black matrix pattern 123 disposed on the second base substrate 121. The black matrix pattern 123 is used to separate the red, green, and blue photoresist units.

[0091] In some other embodiments, the pixel electrode 113 and the common electrode 114 may also be provided on the same layer. In this case, both the pixel electrode 113 and the common electrode 114 have a comb-tooth structure including a plurality of strip-shaped sub-electrodes (not shown in the figure). Alternatively, the common electrode 114 may also be provided on the color filter substrate 120 (not shown in the figure). This application does not impose any specific limitation on this.

[0092] In some embodiments, as shown in Figure 1, a first polarizer 140 is provided on the side of the control substrate 110 away from the second liquid crystal layer 130, and a second polarizer 150 is provided on the side of the color film substrate 120 away from the second liquid crystal layer 130. The polarization directions of the first polarizer 140 and the second polarizer 150 are perpendicular to each other. The liquid crystal display panel 100 may further include a protective cover 160 provided on the side of the color film substrate 120 away from the control substrate 110.

[0093] It is understood that the liquid crystal display panel 100 may also include other structures, which are not listed in detail in the embodiments of the present disclosure. For example, the liquid crystal display panel 100 may further include a third alignment film (not shown in the figure) disposed on the side of the control substrate 110 close to the second liquid crystal layer 130, a fourth alignment film (not shown in the figure) disposed on the side of the color filter substrate 120 close to the second liquid crystal layer 130, and the like.

[0094] The backlight module 200 is arranged on the non-display side of the liquid crystal display panel 100, and is used to provide a planar light source for the liquid crystal display panel 100. The backlight module 200 can be an edge-entry backlight module or a direct-type backlight module. In the embodiment of the present disclosure, as shown in Figure 1, the backlight module 200 is described as a direct-type backlight module. In the case where the backlight module 200 is a direct-type backlight module, as shown in Figure 1, the backlight module 200 may include a backlight source 210, a light guide plate 220 and a reflective sheet 230. The backlight source 210 is arranged on the side of the light guide plate 220 away from the liquid crystal display panel 100, and may include a plurality of point light sources (such as LED lights) arranged in an array. The light guide plate 220 is used to uniformize the light emitted by the backlight source 210. The reflective sheet 230 is disposed on a side of the backlight source 210 away from the LCD panel 100 to reflect the light emitted from the backlight source 210 toward the reflective sheet 230 , thereby increasing the light emitted from the backlight module 200 toward the LCD panel 100 and improving the light extraction efficiency of the display device.

[0095] In some embodiments, as shown in Figure 1, the backlight module 200 also includes an inverse prism 240 located on the side of the light guide plate 220 close to the liquid crystal display panel 100. The inverse prism 240 is used to refract at least part of the light emitted by the light guide plate 220 to a forward viewing angle (so that the light is emitted in a direction perpendicular to the surface of the light guide plate 220 close to the liquid crystal display panel 100) and improve the light output efficiency of the backlight module 200, that is, the inverse prism 240 can play a certain collimating role on the light emitted by the light guide plate 220.

[0096] In some embodiments, the display device 1000 can be a display device 1000 with an anti-peeping function. Referring to Figures 3A and 3B , the display device 1000 further includes a collimating film 300 and a viewing angle control box 400. The collimating film 300 and the viewing angle control box 400 are both disposed between the liquid crystal display panel 100 and the backlight module 200, with the collimating film 300 being closer to the backlight module 200 than the viewing angle control box 400. In other words, the collimating film 300 is located between the viewing angle control box 400 and the backlight module 200. In Figures 3A and 3B , the arrows indicate the propagation direction of light emitted from the backlight module 200.

[0097] The collimating film 300 is used to further collimate the light emitted by the backlight module 200 so that the light entering the collimating film 300 from the backlight module 200 can be emitted in a direction perpendicular to the surface of the collimating film 300 close to the liquid crystal display panel 100. That is to say, the collimating film 300 and the backlight module 200 cooperate to emit light in a direction perpendicular to the liquid crystal display panel 100 toward the viewing angle control box 400.

[0098] The viewing angle control box 400 may also be referred to as a Smart View Control Solution (SVC) or a viewing angle dimming box. The viewing angle control box 400 is configured to adjust the propagation direction of light passing through the viewing angle control box 400, thereby controlling the light emission direction of the liquid crystal display panel 100, so that the display device 1000 displays images in an anti-peeping display state (abbreviated as "anti-peeping state") and / or a shared display state (abbreviated as "shared state").

[0099] Illustratively, the viewing angle control box 400 can operate in a transparent state and / or a diffuse state. As shown in FIG3A , when the viewing angle control box 400 is operating in a transparent state, the long axis direction of the liquid crystal molecules in the first liquid crystal layer 430 can be, for example, parallel to the third direction Z (a direction perpendicular to the array substrate 410 ). The viewing angle control box 400 does not change the propagation direction of light passing through the viewing angle control box 400. Thus, light incident on the viewing angle control box 400 by the backlight module 200 still passes through the viewing angle control box 400 in a direction perpendicular to the liquid crystal display panel 100 and then enters and passes through the liquid crystal display panel 100. The propagation direction of light on the display side of the liquid crystal display panel 100 is perpendicular to the light emitting surface of the liquid crystal display panel 100. Only the area opposite to the liquid crystal display panel 100 (with the line of sight perpendicular to the liquid crystal display panel 100) can see the display content of the liquid crystal display panel 100. The area surrounding the liquid crystal display panel (the surrounding area) cannot see or cannot clearly see the display content of the liquid crystal display panel 100. In this case, the liquid crystal display panel 100 can prevent people from viewing it. In other words, the display device 1000 displays images in an anti-peeping state.

[0100] As shown in FIG3B , when the viewing angle control box 400 operates in a scattering state, the long axis direction of the liquid crystal molecules in the first liquid crystal layer 430 may, for example, form an angle with the third direction Z (a direction perpendicular to the array substrate 410). The viewing angle control box 400 may change the propagation direction of the light passing through the viewing angle control box 400 and cause the light to be emitted in a scattered state. In this way, the light from the backlight module 200 that enters the viewing angle control box 400 in a direction perpendicular to the viewing angle control box 400 passes through the viewing angle control box 400 and then enters and passes through the liquid crystal display panel 100 in a scattered state. The light on the display side of the liquid crystal display panel 100 is scattered in all directions. At this time, the area directly opposite the liquid crystal display panel 100 and the area located on the side of the liquid crystal display panel 100 can all see the display content of the liquid crystal display panel 100, and the display device 1000 displays in a shared state.

[0101] In some embodiments, referring to FIG3B , a viewing angle control box 400 includes an array substrate 410, an opposing substrate 420, and a first liquid crystal layer 430. The array substrate 410 and the opposing substrate 420 are disposed opposite each other, and a liquid crystal cell is formed between the array substrate 410 and the opposing substrate 420. The first liquid crystal layer 430 is located in the liquid crystal cell between the array substrate 410 and the opposing substrate 420.

[0102] In some embodiments, the first liquid crystal layer 430 may use a liquid crystal dimming film. For example, a polymer dispersed liquid crystal (PDLC) may be used. The polymer dispersed liquid crystal (PDLC) mainly works in a transparent state or a scattering state. For example, the polymer dispersed liquid crystal (PDLC) is a mixture of low-density liquid crystal molecules and prepolymer glue, which is polymerized to form micron-sized liquid crystal droplets uniformly dispersed in a polymer network, and then the dielectric anisotropy of the liquid crystal molecules is used to obtain a material with electro-optical corresponding properties. It should be noted that the material of the first liquid crystal layer 430 is not limited to this, as long as it is a liquid crystal that can be switched between a transparent state and a scattering state. For example, the liquid crystal in the first liquid crystal layer 430 may use a smectic phase liquid crystal, but is not limited to this.

[0103] For example, referring to FIG3B , the viewing angle control box 400 may further include a first alignment film 440 disposed on a side of the array substrate 410 close to the first liquid crystal layer 430, and a second alignment film 450 disposed on a side of the counter substrate 420 close to the first liquid crystal layer 430. The first alignment film 440 and the second alignment film 450 are used to control the deflection direction of the liquid crystal molecules in the first liquid crystal layer 430. For example, the first alignment film 440 and the second alignment film 450 may be used to control the deflection direction of the liquid crystal molecules when not subjected to an electric field. Alternatively, the first alignment film 440 and the second alignment film 450 may be used to define the pretilt angle of the liquid crystal molecules.

[0104] In some embodiments, referring to FIG4 , an array substrate 410 includes a substrate 10, a first wiring layer 20, a second wiring layer 30, a first electrode layer 40, a plurality of thin-film transistors 50, and a second electrode layer 60. The first wiring layer 20 is disposed on one side of the substrate 10, the second wiring layer 30 is disposed on a side of the first wiring layer 20 away from the substrate 10, the first electrode layer 40 is disposed on a side of the second wiring layer 30 away from the substrate 10, and the second electrode layer 60 is disposed on a side of the first electrode layer 40 away from the substrate 10. In other words, the first wiring layer 20, the second wiring layer 30, the first electrode layer 40, and the second electrode layer 60 are disposed in sequence along a square away from the substrate 10.

[0105] Referring to Figure 5, the first routing layer 20 includes a plurality of gate lines 21 spaced apart along a first direction Y, and the gate lines 21 extend as a whole along a second direction X. The first direction Y and the second direction X intersect, and illustratively, the first direction Y and the second direction X are perpendicular to each other. The gate lines 21 extending as a whole along the second direction X means that the gate lines 21 extend along the second direction X from a macroscopic perspective, but the gate lines 21 may have portions intersecting the second direction X from a microscopic perspective, for example, the gate lines 21 may be zigzag lines. It is understood that the gate lines 21 are used to transmit scan signals.

[0106] In some embodiments, as shown in FIG5 , the gate line 21 is a zigzag line and includes a plurality of extension segments 23 sequentially connected along the second direction X. A first angle α1 is formed between two interconnected extension segments 23. The first angle α1 may range from 34° to 74°.

[0107] In the liquid crystal display device 1000, when the two stacked layers each have a grid pattern and the grid patterns of the two layers are similar, moiré patterns are easily generated, that is, the human eye observes alternating light and dark stripes, which affects the visual experience. As shown in Figure 2, in the liquid crystal display panel 100, the projection shape of the plurality of sub-pixels P on the viewing angle control box 400 is roughly rectangular. The gate line 21 is set as a broken line, so that the extension direction of the gate line 21 and the grid forming the sub-pixel P have an angle, that is, the gate line 21 and the extension direction of the signal line in the liquid crystal display panel 100 have an angle. In this way, the grid formed by the gate line 21 and the grid formed by the sub-pixel P have different shapes, which is conducive to reducing the possibility of moiré patterns appearing in the display device 1000.

[0108] In some embodiments, referring to FIG. 5 , the plurality of extension segments 23 include first extension segments 24 and second extension segments 25 alternately arranged along the second direction X. The interconnected first extension segments 24 and second extension segments 25 are symmetrically arranged about the first reference line L3, and the second angle α2 between the first extension segments 24 and the second extension segments 25 and the second direction X is between 53° and 73°. It has been verified that when the second angle α2 is within this range, the risk of moiré patterns in the display device 1000 can be minimized. The first reference line L3 is parallel to the first direction Y and passes through the corner where the first extension segment 24 and the second extension segment 25 connect. The first extension segment 24 is the extension segment 23 extending along the first reference direction M1, and the second extension segment 25 is the extension segment 23 extending along the second reference direction M2. The first extension segment 24 and the second extension segment 25 are symmetrically arranged about the first reference line L3, such that the second angle α2 between the first extension segment 24 and the second extension segment 25 and the second direction X is the same. Exemplarily, the second angle α between the first extension section 24 and the second extension section 25 and the second direction X is 53°, 60°, 63.4° or 73°, etc. The embodiments of the present disclosure are not listed one by one.

[0109] As shown in Figure 5, the gate line 21 includes at least one light adjustment portion 231 and a connection portion 232 connected to the light adjustment portion 231. Exemplarily, each extension segment 23 (including the first extension segment 24 and the second extension segment 25) includes at least one light adjustment portion 231 and a connection portion 232 connected to the light adjustment portion 231.

[0110] Referring to FIG. 6 , the width D5 of the light modulating portion 231 is greater than the width D6 of the connecting portion 232 . The light modulating portion 231 can further increase the irregularity of the shape of the gate lines 21 , for example, by making the boundaries of the gate lines 21 substantially jagged. In other words, the light modulating portion 231 can increase the difference between the grid formed by the gate lines 21 and the grid on the liquid crystal display panel 100 , thereby improving the moiré problem of the display device 1000 .

[0111] It is understood that, as shown in FIG6 , the width D5 of the light adjustment portion 231 refers to the dimension of the light adjustment portion 231 in the third reference direction M3, and the width D6 of the connecting portion 232 refers to the dimension of the connecting portion 232 in the third reference direction M3. The third reference direction M3 is perpendicular to the extension direction of the extension section 23 in which the light adjustment portion 231 and the connecting portion 232 are located.

[0112] In some embodiments, the ratio D5 / D6 of the maximum width of the light adjustment portion 231 to the width of the connecting portion 232 is 1.5 to 4. As shown in FIG6 , the maximum width of the light adjustment portion 231 refers to the distance between two opposing boundaries of the light adjustment portion 231 along the third reference direction M3. For example, the ratio D1 / D2 of the maximum width of the light adjustment portion 231 to the width of the connecting portion 232 is 1.5, 2.0, 3.5, or 4, which are not listed in detail in the embodiments of the present disclosure.

[0113] Exemplarily, the width D6 of the connecting portion 232 can be 5μm to 15μm. On the one hand, the resistance of the connecting portion 232 is small and does not affect the signal transmission of the gate line 21. On the other hand, it can reduce the problem of light leakage (the deflection direction of the liquid crystal molecules is affected by the gate line and deflects unexpectedly) in the viewing angle control box 400 near the gate line 21 (connecting portion 232).

[0114] It is understandable that if the gate line 21 is too large, for example, greater than 15 μm, the voltage of the gate line 21 will form an electric field in a larger range and affect the deflection direction of the nearby liquid crystal molecules, thereby causing light leakage problems. In addition, the intervals between the dimming zones 401 may be too large, affecting the dimming effect of the viewing angle control box 400. If the width of the connecting portion 232 is too small (for example, less than 5 μm), the resistance of the connecting portion 232 will be relatively large, which is not conducive to signal transmission of the gate line 21 and may increase the difficulty of processing the gate line 21. For example, the width of the connecting portion 232 can be 5 μm, 8 μm, 15 μm, etc., which will not be listed one by one in the embodiments of the present disclosure.

[0115] In some embodiments, the difference (D5-D6) between the maximum width D5 of the light adjustment portion 231 and the width of the connecting portion 232 may be 8 μm to 18 μm. For example, the difference (D5-D6) between the width D5 of the light adjustment portion 231 and the width of the connecting portion 232 may be 8 μm, 13 μm, or 18 μm, which are not listed in detail in the embodiments of the present disclosure.

[0116] In a specific example, the width of the connecting portion 232 may be 8 μm, and the width of the light adjustment portion 231 may be 21 μm. In this case, the difference (D5-D6) between the width D5 of the light adjustment portion 231 and the width of the connecting portion 232 is 13 μm, and the ratio D5 / D6 of the maximum width of the light adjustment portion 231 to the width of the connecting portion 232 is 2.625.

[0117] In some embodiments, referring to FIG6 , the ratio L2 / L1 of the length L2 of the connecting portion 232 to the length L1 of the light adjustment portion 231 is 1.5 to 3.5, which is beneficial for the gate line 21 to reduce the moiré problem in the display device 1000. Exemplarily, the ratio L2 / L1 of the length L2 of the connecting portion 232 to the length L1 of the light adjustment portion 231 is 1.5, 2.2 or 3.5, which is not listed one by one in the embodiments of the present disclosure. Among them, the length L2 of the connecting portion 232 refers to the dimension of the connecting portion 232 in the fourth reference direction M4, and the length L1 of the light adjustment portion 231 refers to the dimension of the light adjustment portion 231 in the fourth reference direction M4. The fourth reference direction M4 is parallel to the extension direction of the extension section 23 where the connecting portion 232 and the light adjustment portion 231 are located.

[0118] Exemplarily, the length L2 of the connecting portion 232 may be 50 μm to 70 μm. For example, the length L2 of the connecting portion 232 may be 50 μm, 60 μm, or 70 μm. The length L1 of the light regulating portion 231 may be 20 μm to 36 μm. For example, the length of the light regulating portion 231 may be 20 μm, 28 μm, or 36 μm.

[0119] In some embodiments, the orthographic projection of the light adjustment portion 231 on the substrate 10 is in the shape of a hexagon (as shown in FIG6 ) or an octagon (not shown in the figure). In this way, the boundaries of the gate lines 21 do not form sharp angles, which helps to reduce the difficulty of preparing the gate lines 21. It is understandable that the light adjustment portion 231 can also be in other shapes, for example, the shape of the light adjustment portion 231 can be circular, elliptical or other shapes, which are not listed one by one in the embodiments of the present disclosure.

[0120] Referring to Figure 5 , each extension segment 23 includes a plurality of light adjustment portions 231 and a plurality of connection portions 232, which are alternately connected in sequence. The connection portions 232 are located at both ends of the extension segment 23. This prevents the formation of a large pattern at the junction between the first extension segment 24 and the second extension segment 25, which helps reduce the parasitic capacitance formed between the gate line 21 and the second wiring layer 30 (data line 31 and common voltage signal line 32), thereby reducing signal interference between the gate line 21 and the second wiring layer 30.

[0121] As shown in FIG5 , when the first extension segment 24 and the second extension segment 25 are symmetrically arranged about the first reference line L3 , the light adjustment portion 231 on the first extension segment 24 and the light adjustment portion 231 on the second extension segment 25 can also be symmetrically arranged about the first reference line L3 .

[0122] In some embodiments, the first wiring layer 20 further includes a gate pattern 51, which is connected to the gate line 21 and is used to form a control electrode of the thin film transistor 50. For example, the gate pattern 51 can be disposed at a corner between the first extension section 24 and the second extension section 25. The shape of the gate pattern 51 can be rectangular or other shapes, which is not specifically limited in the embodiments of the present disclosure.

[0123] Referring to Figure 7 , the second routing layer 30 includes a plurality of data lines 31 spaced apart along a second direction X. The data lines 31 generally extend along a first direction Y. "The data lines 31 generally extend along the first direction Y" means that, from a macroscopic perspective, the data lines 31 extend along the first direction Y. However, from a microscopic perspective, the data lines 31 may have portions intersecting the first direction Y, for example, the data lines 31 may be zigzag lines. It is understood that the data lines 31 are used to transmit data signals.

[0124] In some embodiments, referring to FIG. 7 , the plurality of data lines 31 are arranged as zigzag lines. The data lines 31 include a plurality of third extension segments 311 and a plurality of fourth extension segments 312 that are alternately arranged and interconnected along a first direction Y. Similar to the zigzag lines of the gate lines 21, the zigzag lines of the data lines 31 facilitate the viewing angle control box 400 in reducing or even eliminating moiré patterns on the display device 1000.

[0125] The interconnected third extension segment 311 and fourth extension segment 312 are symmetrically arranged about the second reference line L4, and a third angle β1 between the third extension segment 311 and the fourth extension segment 312 and the first direction Y is between 5° and 10°. It has been verified that when the third angle β1 between the third extension segment 311 and the fourth extension segment 312 and the first direction Y is within the above range, the risk of moiré patterns appearing on the display device 1000 can be minimized. The second reference line L4 is parallel to the second direction X and passes through the corner where the third extension segment 311 and the fourth extension segment 312 connect.

[0126] The third extension section 311 and the fourth extension section 312 are symmetrically arranged about the second reference line L4. Thus, the third angle β1 between the third extension section 311 and the fourth extension section 312 and the first direction Y is the same. For example, the third angle β1 between the third extension section 311 and the fourth extension section 312 and the first direction Y is 5°, 7°, or 10°, etc., and the embodiments of the present disclosure are not listed one by one.

[0127] In some embodiments, as shown in FIG7 , the second wiring layer 30 may further include a source pattern 53 and a drain pattern 54. The source pattern 53 and the drain pattern 54 are used to form the source and drain of the thin film transistor 50. The source pattern 53 is electrically connected to the data line 31 to receive the data signal transmitted by the data line 31. The source pattern 53 and the drain pattern 54 are arranged at intervals. For example, the source pattern 53 may have a "U"-shaped structure, which can increase the contact area between the source pattern 53 and the semiconductor pattern 52. The drain pattern 54 may have a "T"-shaped structure. It is understood that the shapes of the source pattern 53 and the drain pattern 54 can be adjusted according to actual needs.

[0128] In some embodiments, as shown in FIG7 , the second wiring layer 30 may further include a plurality of common voltage signal lines 32 spaced apart along the second direction X ( FIG7 exemplarily shows only one common voltage signal line 32 ). The common voltage signal line 32 may be used to transmit a common voltage signal. The common voltage signal line 32 extends along the first direction Y as a whole. The common voltage signal line 32 extends along the first direction Y as a whole means that the common voltage signal line 32 extends along the first direction Y from a macroscopic perspective, but the common voltage signal line 32 may have a portion intersecting the first direction Y from a microscopic perspective, for example, the common voltage signal line 32 may be a zigzag line.

[0129] In some embodiments, as shown in FIG7 , multiple data lines 31 and multiple common voltage signal lines 32 are alternately distributed along the second direction X. That is, along the second direction X, a common voltage signal line 32 is included between every two adjacent data lines 31, and a data line 31 is included between every two adjacent common voltage signal lines 32. Furthermore, adjacent data lines 31 and common voltage signal lines 32 are symmetrically arranged. This helps improve the uniformity of the wiring of the second wiring layer 30 and the uniformity of the display of the display device.

[0130] In some embodiments, adjacent data lines 31 and common voltage signal lines 32 may be symmetrically arranged. As shown in FIG7 , when the data lines 31 and common voltage signal lines 32 are alternately arranged and adjacent data lines 31 and common voltage signal lines 32 are symmetrically arranged, the plurality of common voltage signal lines 32 are zigzag lines, and the common voltage signal lines 32 include a plurality of fifth extension segments 321 and a plurality of sixth extension segments 322 that are alternately arranged and interconnected along the first direction Y. Similar to the reason why the gate lines 21 are zigzag lines, the zigzag lines of the common voltage signal lines 32 are beneficial for the viewing angle control box 400 to reduce or even eliminate the moiré problem of the display device 1000.

[0131] The interconnected fifth extension segment 321 and sixth extension segment 322 are symmetrically arranged about the second reference line L4, and a fourth angle β2 between the fifth extension segment 321 and the sixth extension segment 322 and the first direction Y is 5° to 10°. Because the data line 31 and the common voltage signal line 32 are symmetrically arranged, the fourth angle β2 between the fifth extension segment 321 and the sixth extension segment 322 and the first direction Y is the same as the third angle β1 between the third extension segment 311 and the fourth extension segment 312 and the first direction Y.

[0132] As shown in FIG7 , the common voltage signal line 32 may include a widened portion 323. The width of the widened portion 323 is greater than the width of other locations of the common voltage signal line 32 (excluding the widened portion 323). The widened portion 323 can increase the local area of ​​the common voltage signal line 32, thereby improving the stability and reliability of the subsequent connection between the second electrode 61 and the common voltage signal line 32.

[0133] In some embodiments, referring to Figures 8A and 8B , the orthographic projections of multiple gate lines 21 and multiple data lines 31 on the substrate 10 intersect with each other, and the orthographic projections of two adjacent gate lines and two adjacent data lines on the substrate define a dimming zone 401. Alternatively, the orthographic projections of any two adjacent data lines 31 on the substrate 10 intersect with the orthographic projections of any two adjacent gate lines 21 on the substrate to form a closed grid, which forms a dimming zone 401. Thus, the viewing angle control box 400 has multiple dimming zones 401 distributed in an array. It is understood that in embodiments of the present application, the dimming zone 401 may not include the area where the gate lines 21 and data lines 31 enclose the dimming zone 401. In other words, the gate lines 21 and data lines 31 do not fall within the dimming zone 401. The dimming zone 401 is configured to switch between a sharing state and an anti-peeping state. In other words, the dimming zone 401 is the smallest unit within which the viewing angle control box 400 can switch display states.

[0134] In some embodiments, referring to Figure 8B, when the gate line 21 and the data line 31 are both broken lines, the gate line 21 and the data line 31 can form two dimming areas 401 with different shapes. The two dimming areas 401 are respectively a first dimming area 4011 and a second dimming area 4012. Along the first direction Y, the first dimming areas 4011 and the second dimming areas 4012 are arranged alternately, and along the second direction X, the dimming areas 401 in the same row have the same shape.

[0135] For example, referring to FIG8A , the gate line 21 can coincide with the midpoint of the third extension 311 or the fourth extension 312 of the data line 31. This facilitates obtaining a regularly shaped data line 31. The data line 31 and the gate line 21 can coincide at the corner between the first extension 24 and the second extension 25. This facilitates obtaining a regularly shaped gate line 21. This results in a regular, uniform grid of dimming zones 401, which can improve the dimming uniformity of the viewing angle control box 400. Furthermore, the light interference conditions at each position of the viewing angle control box 400 are similar, which helps alleviate moiré issues in the display device 1000.

[0136] Referring to FIG9A , the first electrode layer 40 includes a plurality of first electrodes 41 , with one first electrode 41 located in each dimming zone 401 . In other words, each of the plurality of first electrodes 41 is located in a dimming zone 401 , and different first electrodes 41 are located in different dimming zones 401 . In other words, a single dimming zone 401 includes only one first electrode 41 . By way of example, the first electrode 41 may be a pixel electrode. FIG9A illustratively illustrates only one dimming zone 401 and one first electrode 41 .

[0137] In some embodiments, referring to Figures 10 and 11 , the first electrode 41 includes a plurality of first electrode strips 42 spaced apart along a second direction X, and second electrode strips 44 connected end to end. The first electrode strips 42 extend along a first direction Y. The second electrode strips 44 are connected to both ends of the first electrode strips 42 along the first direction Y, forming a structure in which the second electrode strips 44 surround the plurality of first electrode strips 42.

[0138] The second electrode strips 44 surround all the first electrode strips 42 (all included in one first electrode 41) and are connected to the (two) ends of the first electrode strips 42 along the first direction Y. In this way, the multiple first electrode strips 42 can be connected as a whole through the second electrode strips 44. When the first electrode 41 is electrically connected to the thin-film transistor 50, as long as one part of the first electrode strips 42 is electrically connected to the thin-film transistor 50, the multiple first electrode strips 42 can all be electrically connected to the thin-film transistor 50, thereby allowing the thin-film transistor 50 to charge the multiple first electrode strips 42. The second electrode strips 44 can also be considered as the portion formed by the edge of the first electrode 41, or the portion other than the first electrode strips 42.

[0139] In some embodiments, referring to FIG10 , the second electrode strips 44 include two fourth sub-electrode strips 441 disposed opposite each other along a first direction Y and two fifth sub-electrode strips 442 disposed opposite each other along a second direction X. Referring to FIG9B and FIG11 , the first sub-electrode strips 441 extend in a direction parallel to the gate lines 21 , and referring to FIG12 , the second sub-electrode strips 442 extend in a direction parallel to the data lines 31 .

[0140] Referring to FIG11 , a first spacing H1 is defined between the orthographic projection of the fourth sub-electrode strip 441 and the gate line 21 on the substrate 10. Referring to FIG12 , a second spacing H2 is defined between the orthographic projection of the fifth sub-electrode strip 442 and the data line 31 on the substrate 10. The first spacing H1 and the second spacing H2 may be equal or unequal, and are not specifically limited in the embodiments of the present disclosure. In other words, the outer boundary of the second electrode strip 44 is spaced from the boundary of the dimming region 401. This helps reduce signal interference between the first electrode 41 and the gate line 21 and data line 31, thereby ensuring that the electric field formed by the first electrode 41 and the second electrode layer 60 is evenly distributed within the dimming region 401.

[0141] In some embodiments, referring to FIG10 , the fourth sub-electrode strips 441 have a sawtooth structure, or a concave-convex structure. This helps to reduce the irregularity of the grid formed by the fourth sub-electrode strips 441, thereby helping the viewing angle control box 400 reduce or even eliminate the moiré problem of the display device 1000.

[0142] In some embodiments, referring to FIG. 10 and FIG. 11 , a first groove 45 is provided at an edge of the fourth sub-electrode strip 441 close to the gate line 21 , and an orthographic projection of the first groove 45 on the substrate is spaced apart from an orthographic projection of the gate line 21 on the substrate.

[0143] Exemplarily, the first electrode 41 is spaced apart from the boundary of the dimming zone 401 (as shown in FIG11 ). Referring to FIG11 , the orthographic projection of the first electrode 41 on the substrate 10 is spaced apart from the orthographic projection of the gate line 21 on the substrate 10 by a distance D7. Referring to FIG12 , the orthographic projection of the first electrode 41 on the substrate 10 is spaced apart from the orthographic projection of the data line 31 on the substrate 10 by a distance D8. Thus, along a direction perpendicular to the substrate 10, the first electrode 41 has no portion facing the gate line 21 or the data line 31. Consequently, no parasitic capacitance is generated between the first electrode 41 and the gate line 21 or the data line 31, thereby reducing the impact of voltage fluctuations of the gate line 21 or the data line 31 on the voltage of the first electrode 41.

[0144] In some embodiments, referring to FIG. 11 , in orthographic projection of the substrate 10, the first electrode 41 has a second groove 45' on a side near the light modulating portion 231. The shape of the second groove 45' is the same as the shape of the side of the light modulating portion 231 near the first electrode 41. Furthermore, the spacing between the second groove 45' and the light modulating portion 231 is equal to the spacing between the first electrode 41 and the connecting portion 232. In other words, the equal spacing between the first electrode 41, the light modulating portion 231, and the connecting portion 232 can reduce signal interference between the light modulating portion 231 of the gate line 21 and the first electrode 41.

[0145] In some embodiments, referring to FIG10 , a second slit 43 is included between two adjacent first electrode strips 42. The second slit 43 may also extend along the first direction Y. In the first direction Y, the end of the second slit 43 is spaced from the boundary of the first electrode 41. In other words, along the first direction Y, the second slit 43 does not penetrate the first electrode 41, and the two adjacent first electrode strips 42 can be connected as a whole through the edge of the first electrode 41 (the second electrode strip). The second slit 43 can not only increase the light transmittance of the first electrode layer 40, but also reduce the area of ​​the first electrode 42, thereby reducing the facing area of ​​the first electrode 42 and the common electrode layer 60, reducing the parasitic capacitance between the first electrode 42 and the common electrode layer 60, and thereby improving the charging efficiency of the first electrode 42.

[0146] Exemplarily, the orthographic projection of the first electrode strip 42 on the substrate 10 does not overlap with the orthographic projection of the second electrode layer 60 on the substrate 10. In this way, the risk of parasitic capacitance formed between the first electrode strip 42 and the second electrode layer 60 can be reduced, the influence of the second electrode layer 60 on the charging speed of the first electrode strip 42 can be reduced, and the charging efficiency of the first electrode strip 42 can be improved.

[0147] Referring to FIG8B , a thin film transistor 50 is provided in each dimming zone. That is, each of the multiple thin film transistors 50 is located in a dimming zone 401, and different thin film transistors 50 are located in different dimming zones 401. Referring to FIG13A and FIG13B , a thin film transistor 50 is electrically connected to a data line (one of the two data lines 31 that enclose the dimming zone 401 where the thin film transistor 50 is located), a gate line 21 (one of the two gate lines 21 that enclose the dimming zone 401 where the thin film transistor 50 is located), and a first electrode 41 (located in the dimming zone 401 where the thin film transistor 50 is located). The thin film transistor 50 is configured to transmit a data signal from the data line 31 to the first electrode 41 under the control of a scan signal from the gate line 21.

[0148] Referring to FIG. 13A , a thin film transistor 50 may include a gate pattern 51, a semiconductor pattern 52, a source pattern 53, and a drain pattern 54. The gate pattern 51 is disposed on the first wiring layer 20 and electrically connected to the gate line 21, and is configured to receive a scan signal from the gate line 21. The semiconductor pattern 52, also referred to as an active layer pattern, is located between the first wiring layer 20 and the second wiring layer 30. The source pattern 53 and the drain pattern 54 are located on the second wiring layer 30. The source pattern 53 is electrically connected to the data line 31, and the drain pattern 54 is spaced apart from the source pattern 53; that is, the drain pattern 54 and the source pattern 53 do not contact each other.

[0149] The orthographic projection of the gate pattern 51 on the substrate 10 covers the orthographic projections of the semiconductor pattern 52 and the source pattern 53 on the substrate 10, and partially overlaps with the orthographic projection of the drain pattern 54 on the substrate 10. The orthographic projection of the drain pattern on the substrate 10 does not overlap with the orthographic projection of the first electrode 41 on the substrate 10. Referring to FIG13A , the material of the semiconductor pattern 52 can be amorphous silicon (a-Si), oxide, or low-temperature polysilicon (LTPS), etc., and the embodiments of the present disclosure are not specifically limited to this.

[0150] 13B and 14 , the second electrode layer 60 includes a second electrode 61. Exemplarily, the second electrode 61 may be a common electrode 61, which may be electrically connected to a common voltage signal line (not shown). The orthographic projection of the second electrode 61 on the substrate 10 at least partially does not overlap with the orthographic projection of the first electrode 41 on the substrate 10, and the orthographic projection of the second electrode 61 on the substrate 10 at least partially does not overlap with the orthographic projection of the thin film transistor 50 on the substrate 10. In this way, the facing area between the second electrode 61 and the first electrode 41, as well as between the second electrode 61 and the thin film transistor 50, can be reduced, thereby reducing the parasitic capacitance generated between the second electrode 61 and the first electrode 41, as well as between the second electrode 61 and the thin film transistor 50, and reducing the adverse effects of the second electrode 61 on the first electrode 41 and the thin film transistor 50.

[0151] It is understandable that parasitic capacitance has a hysteresis effect on the transmission of signals. For example, the second electrode 61 and the first electrode 41 at least partially do not overlap, which can reduce the size of the parasitic capacitance generated between the two. In this way, in the process of the thin film transistor 50 charging the first electrode 41 (transmitting data signals), the charging efficiency of the first electrode 41 can be improved, that is, the first electrode 41 is charged faster and more fully. The second electrode 61 and the thin film transistor 50 at least partially do not overlap, which can reduce the risk of parasitic capacitance generated between the second electrode 61 and the thin film transistor 50, thereby improving the response speed of the thin film transistor 50.

[0152] In some embodiments, referring to FIG. 13B and FIG. 14 , the second electrode 61 includes a plurality of avoidance openings 62. Each dimming zone is provided with a avoidance opening 62, and the orthographic projection of the avoidance opening 62 on the substrate 10 at least partially overlaps with the orthographic projection of the thin-film transistor 50 on the substrate 10. In other words, the boundary of a avoidance opening 62 surrounds at least a portion of the thin-film transistor 50, and at least a portion of the thin-film transistor 50 is located within the avoidance opening 62. This helps reduce the area where the projections of the second electrode 61 and the thin-film transistor 50 overlap, reduces the parasitic capacitance generated between the second electrode 61 and the thin-film transistor 50, reduces the adverse effects of the second electrode 61 on the thin-film transistor 50, and thereby improves the response speed of the thin-film transistor 50.

[0153] For example, as shown in Figures 13B and 14 , the avoidance opening 62 includes a first opening portion 621. The boundary shape of the first opening portion 621 is substantially the same as the boundary shape of the semiconductor pattern 52, and the orthographic projection of the first opening portion 621 on the substrate 10 is located within the orthographic projection of the semiconductor pattern 52 on the substrate. The boundary of the first opening portion 621 surrounds the edge of the semiconductor pattern 52. This reduces the risk of the first opening portion 621 exposing the gate line 21 and the data line 31, thereby reducing the impact of the electric field formed by the gate line 21 and the data line 31 on the first liquid crystal layer.

[0154] For example, as shown in Figure 14, the boundary shape of the first opening portion 621 and the boundary shape of the semiconductor pattern 52 are approximately rectangular; the boundary of the first opening portion 621 is spaced apart from the semiconductor pattern 52, and along the circumference of the first opening portion 621, the spacing between the boundary of the first opening portion 621 and the semiconductor pattern 52 is approximately equal. In other words, the spacing between any position of the boundary of the first opening portion 621 and the semiconductor pattern 52 is approximately equal.

[0155] In some embodiments, as shown in FIG14 , when the orthographic projection of the first electrode 41 on the substrate 10 does not overlap with the orthographic projection of the drain pattern 54 on the substrate 10, the second electrode layer 60 further includes a transition block 63, which is electrically connected to the drain pattern 54 and the first electrode 41, respectively. In other words, the drain pattern 54 is electrically connected to the first electrode 41 via the transition block 63, which helps simplify the manufacturing process of the array substrate 410 and reduces the difficulty and cost of manufacturing the array substrate 410.

[0156] It is understood that, referring to FIG15 , the array substrate 410 further includes an insulating layer located between two adjacent conductive layers. For example, as shown in FIG15 , the control substrate 110 further includes a gate insulating layer 411 between the first wiring layer 20 and the semiconductor pattern 52, a first passivation layer (PVX1) 412 located between the second wiring layer 30 and the first electrode layer 40, and a second passivation layer (PVX2) 413 located between the first electrode layer 40 and the second electrode layer 60. The material of the first passivation layer 412 can be the same as that of the second passivation layer 413. For example, the material of the first passivation layer 412 and the material of the second passivation layer 413 can both include silicon nitride and / or silicon oxide.

[0157] Referring to FIG. 15 , the array substrate 410 further includes a second via 415 extending through the first passivation layer 412 and the second passivation layer 413, and a third via 416 extending through the second passivation layer 413. The orthographic projections of the second via 415 on the substrate 10 at least partially overlap with the drain pattern 54 and the adapter block 63, respectively. Thus, the adapter block 63 is electrically connected to the drain pattern 54 via the second via 415. The orthographic projections of the third via 416 on the substrate 10 at least partially overlap with the orthographic projections of the adapter block 63 and the first electrode 41 on the substrate 10. Thus, the adapter block 63 can be electrically connected to the first electrode 41 via the third via 416.

[0158] The design of the adapter block 63 allows, during the fabrication of the array substrate 410, the first electrode layer 40 and the second passivation layer 413 to be sequentially fabricated directly on the first passivation layer 412 after forming the first passivation layer 412. The second via 415 and the third via 416 can then be simultaneously formed through a single etching process. Compared to directly electrically connecting the first electrode 41 to the drain pattern 54 through a via (e.g., a via that only penetrates the first passivation layer), at least one via etching step can be omitted. This simplifies the fabrication process for the array substrate 410, thereby reducing the fabrication cost of the array substrate 410.

[0159] Illustratively, an embodiment of the present disclosure further provides a method for preparing an array substrate, the method comprising S100 to S500.

[0160] S100 , forming a first wiring layer, a gate insulating layer, a semiconductor layer and a second electrode layer in sequence on a substrate.

[0161] The structures of the first wiring layer, the gate insulating layer, the semiconductor layer and the first electrode layer are as described above and will not be described again here.

[0162] S200 , forming a first initial passivation layer on the second electrode layer.

[0163] The first initial passivation layer is a continuous whole-layer structure.

[0164] S300 , sequentially forming a first electrode layer and a second initial passivation layer on the first initial passivation layer.

[0165] The structure of the first electrode layer is as described above and will not be described again. The second initial passivation layer is a continuous whole layer structure.

[0166] S400 , patterning the second initial passivation layer and the first initial passivation layer to form a second passivation layer and a first passivation layer.

[0167] For example, the second via hole 415 and the third via hole 416 may be formed on the second initial passivation layer and the first initial passivation layer simultaneously by using the same etching process.

[0168] S500 , forming a second electrode layer on the second passivation layer.

[0169] The second electrode layer includes a transfer block, which is electrically connected to the drain electrode and the first electrode through the second via hole and the third via hole, respectively. Therefore, it is not necessary to separately provide via holes in the first initial passivation layer. The second via hole 415 and the third via hole 416 can be formed in a single step, which can simplify the manufacturing process of the array substrate 410 and thereby reduce the manufacturing cost of the array substrate 410.

[0170] For example, as shown in Figure 14, the boundary shape of the adapter block 63 and the boundary shape of the second opening portion 622 are substantially rectangular, and the corners of the rectangle are chamfered. The second opening portion 622 is spaced apart from the adapter block 63, and along the circumference of the second opening portion 622, the distance between the boundary of the second opening portion 622 and the adapter block 63 is substantially equal.

[0171] The spacing D9 between the boundary of the adapter block 63 and the boundary of the second opening portion 622 is 6μm to 20μm. In this way, it is possible to ensure that the adapter block 63 and the second electrode 61 are electrically isolated and reduce signal interference between the adapter block 63 and the second electrode 61. It is also possible to prevent the second opening portion 622 from being too large, resulting in a local area in the dimming zone 401 where the liquid crystal deflection cannot be controlled. Exemplarily, the spacing D9 between the boundary of the adapter block 63 and the boundary of the second opening portion 622 can be 6μm, 11.5μm, 18μm, or 20μm, etc., and the embodiments of the present disclosure do not specifically limit this.

[0172] It is understandable that if the spacing D9 between the boundary of the adapter block 63 and the boundary of the second opening portion 622 is too small, such as less than 6μm, on the one hand, it will increase the difficulty of the process of preparing the second electrode layer 60, and on the other hand, signal interference may occur between the adapter block 63 and the second electrode 61. If the spacing D9 between the boundary of the adapter block 63 and the boundary of the second opening portion 622 is too large, such as greater than 20μm, there will be a large area within the dimming zone 401 where the second electrode 61 does not exist. This area will not be able to generate an electric field with the first electrode 41, which will result in the inability to control the deflection direction of the liquid crystal molecules in this area, resulting in the inability to adjust the propagation direction of light in this area. Therefore, the spacing D9 between the boundary of the adapter block 63 and the boundary of the second opening portion 622 is set to 6μm to 20μm.

[0173] In some embodiments, referring to FIG. 14 , the orthographic projection of the adapter block 63 on the substrate 10 does not overlap with the orthographic projections of the data line 31 and the gate line 21 on the substrate 10. This reduces the risk of parasitic capacitance between the adapter block 63 and the data line 31 and the gate line 21, thereby reducing voltage fluctuations on the data line 31 and the gate line 21 that would otherwise affect the voltage of the adapter block 63. This improves the voltage stability of the first electrode 41, thereby improving the stability of the light-transmitting state within the dimming zone 401.

[0174] In some embodiments, referring to FIG. 16A , the second electrode 61 includes a plurality of third electrode strips 64 spaced apart along a second direction X, and fourth electrode strips 66 connected to ends of the third electrode strips 64. The third electrode strips 64 extend along a first direction Y. The fourth electrode strips 66 extend in a direction parallel to the direction of the gate lines 21, and their orthographic projections on the substrate 10 at least partially overlap with the orthographic projections of the gate lines 21 on the substrate 10. Along the first direction Y, the ends of the third electrode strips 64 are respectively connected to the fourth electrode strips 66. In this way, the third electrode strips 64 located in different dimming zones 401 are connected via the fourth electrode strips 66.

[0175] Exemplarily, in the orthographic projection of the gate line 21 on the substrate 10, except for a portion exposed by the avoidance opening 62, the rest of the gate line 21 is located within the fourth electrode strip 66. Exemplarily, referring to Figures 17A and 17B, the boundary of the orthographic projection of the gate line 21 on the substrate 10 is located within the boundary of the orthographic projection of the fourth electrode strip 66 on the substrate 10, and is spaced apart from the boundary of the fourth electrode strip 66. In other words, the width of the fourth electrode strip 66 (the dimension in the direction perpendicular to the extension of the fourth electrode strip 66) is greater than the width of the gate line 21. In this way, the fourth electrode strip 66 can completely cover the gate line 21 and completely shield the electric field generated by the gate line 21.

[0176] In some embodiments, referring to FIG. 16B , the fourth electrode strips 66 include at least one protruding portion 661 and a straight portion 662 connected to the protruding portion 661. Exemplarily, the fourth electrode strips 66 are formed by alternatingly connecting multiple protruding portions 661 and multiple straight portions 662. A dimension D10 of the protruding portion 661 in the first direction Y is greater than a dimension D11 of the straight portion 662 in the first direction Y. A dimension D12 of the protruding portion 661 in the second direction X is greater than a dimension D13 of the straight portion 662 in the second direction X. The boundaries of the fourth electrode strips 66 can be serrated or have a concave-convex structure to better shield the gate lines 21 and reduce the impact of the electric field formed by the gate lines 21 on the first liquid crystal layer.

[0177] For example, referring to FIG. 17A , when the gate line 21 includes multiple light modulation portions 231, the shape of the protrusion 661 can be the same as that of the light modulation portion 231, with each protrusion 661 corresponding to one light modulation portion 231. The orthographic projection of the protrusion 661 on the substrate 10 overlaps the orthographic projection of the light modulation portion 231 corresponding to the protrusion 661. Furthermore, the spacing D14 between the orthographic projections of the protrusion 661 and the light modulation portion 231 on the substrate can be equal to the spacing D15 between the orthographic projections of the connecting portion 232 and the straight portion 662 on the substrate. In other words, the spacing between different portions of the orthographic projection of the fourth electrode strip 66 on the substrate 10 and the orthographic projection of the gate line 21 on the substrate 10 is substantially equal. In this way, the fourth electrode strip 66 can shield the electric field generated by the gate line 21, reducing the risk that the electric field generated by the light modulation portion 231 affects the first liquid crystal layer.

[0178] Referring to FIG. 16B , the plurality of third electrode strips 64 within the same dimming zone include a first sub-electrode strip 641, a second sub-electrode strip 642, and a third sub-electrode strip 643. The first sub-electrode strip 641 is connected to the straight portion 662 at both ends along the first direction Y. The second sub-electrode strip 642 is connected to the straight portion 662 at one end along the first direction Y, and to the protruding portion 661 at the other end. The third sub-electrode strip 643 is connected to the protruding portion 661 at both ends along the first direction Y. A dimension L5 of the first sub-electrode strip 641 in the first direction Y is greater than a dimension L6 of the second sub-electrode strip 642 in the first direction Y. Furthermore, the dimension L6 of the second sub-electrode strip 642 in the first direction Y is greater than a dimension L7 of the third sub-electrode strip 643 in the first direction Y.

[0179] Referring to FIG. 16B , the second electrode 61 further includes a first slit 65 located between two adjacent third electrode strips 64. The two adjacent first slits 65 along the first direction Y are respectively a first sub-slit 651 and a second sub-slit 652. The first sub-slit 651 and the second sub-slit 652 are located on opposite sides of the fourth electrode strip 66 and connected to opposite sides of the fourth electrode strip 66. The dimension L8 between the first sub-slit 651 and the second sub-slit 652 on either side of the straight portion 662 in the first direction Y is smaller than the dimension L9 between the first sub-slit 651 and the second sub-slit 652 on either side of the protruding portion 661 in the first direction Y. Continuing with FIG. 16B , within the same dimming zone, the multiple first slits 65 include a third sub-slit 653, a fourth sub-slit 654, and a fifth sub-slit 655. The third sub-slit 653 is connected to the straight portion 662 at both ends along the first direction Y. One end of the fourth sub-slit 654 along the first direction Y is connected to the straight portion 662, and the other end is connected to the protruding portion 661. The fifth sub-slit 655 is connected to the protruding portion 661 at both ends along the first direction Y. A dimension L10 of the third sub-slit 653 in the first direction Y is greater than a dimension L11 of the fourth sub-slit 654 in the first direction Y, and a dimension L11 of the fourth sub-slit 654 in the first direction Y is greater than a dimension L12 of the fifth sub-slit 655 in the first direction Y.

[0180] Referring to Figures 18 and 19 , the second electrode 61 further includes a first slit 65 located between two adjacent third electrode strips 64. The first electrode 41 includes a plurality of first electrode strips 42 spaced apart along the second direction X, and a second slit 43 located between two adjacent first electrode strips 42. The orthographic projections of the first slit 65 and the second slit 43 on the substrate overlap, and the overlapping portion of the first slit 65 and the second slit 43 forms a third slit 68. A dimension D16 of the third slit 68 in the second direction X is smaller than a dimension D17 of the first electrode strip 42 in the second direction X and a dimension D18 of the third electrode strip 64 in the second direction X.

[0181] It is understood that the extension direction of the second slit 43 is parallel to the extension direction of the first slit 65 and extends along the first direction Y. This helps to improve the light transmittance of the viewing angle control box 400. However, in other embodiments, the extension direction of the second slit 43 and the extension direction of the first slit 65 may also have a certain angle with the first direction Y, and the embodiments of the present disclosure are not specifically limited to this.

[0182] In some embodiments, as shown in FIG18 , a fourth slit 68 ′ is included between the orthographic projections of adjacent first electrode strips 42 and third electrode strips 64 on the substrate 10. The fourth slit 68 ′ is located within the second slit 43 and the first slit 65 . For example, the dimensions D16 of the plurality of fourth slits 68 ′ in the second direction X are equal, meaning that the plurality of first electrode strips 42 and third electrode strips 64 are equally spaced along the second direction X. Alternatively, the orthographic projections of the first electrode strips 42 and the orthographic projections of the third electrode strips 64 on the substrate 10 are alternately arranged along the second direction X, and the first electrode strips 42 and third electrode strips 64 do not overlap. For example, a third electrode strip 64 is included between every two adjacent first electrode strips 42, and a first electrode strip 42 is included between every two adjacent third electrode strips 64. This allows for a more uniform distribution of the electric field formed by the first electrode 41 and the second electrode 61. Moreover, the overlapping area of ​​the first electrode 41 and the second electrode 61 on the substrate 10 can be minimized, the parasitic capacitance generated between the first electrode 41 and the second electrode 61 can be reduced, and the influence of the second electrode 61 on the charging efficiency of the first electrode 41 can be reduced.

[0183] In some embodiments, as shown in FIG16B , the second electrode 61 further includes a fifth electrode strip 67. As shown in FIG20 and FIG21 , the extension direction of the fifth electrode strip 67 is parallel to the extension direction of the data line 31, and the orthographic projection of the fifth electrode strip 67 on the substrate 10 covers at least a portion of the orthographic projection of the data line 31 on the substrate 10.

[0184] Exemplarily, in the orthographic projection of the data line 31 on the substrate 10 , except for a portion exposed by the avoidance opening 62 , the rest of the portion is located within the fifth electrode strip 67 .

[0185] 20 and 21 , the boundary of the orthographic projection of the data line 31 on the substrate 10 is located within the boundary of the orthographic projection of the fifth electrode strip 67 on the substrate 10, and is spaced apart from the boundary of the orthographic projection of the fifth electrode strip 67 on the substrate 10. In other words, the width of the fifth electrode strip 67 (the dimension in the direction perpendicular to the extension of the fifth electrode strip 67) is greater than the width of the data line 31. In this way, the fifth electrode strip 67 can completely cover the data line 31 and completely shield the electric field generated by the data line 31.

[0186] In some embodiments, since the common voltage signal line 32 and the second electrode 61 (second electrode layer 60) are electrically connected, that is, there is no voltage difference between the common voltage signal line 32 and the second electrode 61, therefore, there is no voltage difference and no parasitic capacitance between the two. Based on this, the orthographic projection of the second electrode 61 on the substrate 10 can overlap with the common voltage signal line 32 or be separated and non-overlapping, without affecting the electric field distribution within the dimming zone 401. For example, as shown in Figure 22, the orthographic projection of the second electrode 61 on the substrate 10 partially overlaps with the common voltage signal line 32 and is separated and non-overlapping with part of the common voltage signal line 32.

[0187] As shown in Figures 22 and 23, the array substrate 410 also includes a first via 414 that penetrates the first passivation layer 412 and the second passivation layer 413. The orthographic projection of the first via 414 on the substrate 10 at least partially overlaps with the orthographic projection of the common voltage signal line 32 and the second electrode 61 on the substrate 10, respectively. In this way, the second electrode 61 is electrically connected to the common voltage signal line 32 through the first via 414.

[0188] When the common voltage signal line 32 includes a widened portion 323, the widened portion 323 is electrically connected to the second electrode 61. The first via 414 exposes the widened portion 323 of the common voltage signal line 32. The widened portion 323 can increase the contact area between the second electrode 61 and the common voltage signal line 32, thereby improving the connection stability between the common voltage signal line 32 and the second electrode 61. The orthographic projection of the widened portion 323 on the substrate 10 is located within the orthographic projection of the gate line 21 on the substrate. This helps reduce light obstruction caused by the widened portion 323 and improves the light transmittance of the array substrate 410.

[0189] When the display device 1000 is in operation, the first liquid crystal layer 430 of the viewing angle control box 400 is configured to adjust the deflection direction of the liquid crystal molecules located in each dimming zone 401 in the first liquid crystal layer 430 under the control of the thin-film transistor 50 of the array substrate 410. For example, when the display device 1000 is in operation, the viewing angle control box 400 transmits a voltage signal to the first electrode 41 via the thin-film transistor 50, and the common voltage signal line 32 provides a common voltage to the second electrode 61. This generates a voltage difference between the first electrode 41 and the second electrode 61, thereby forming an electric field within the dimming zone 401. The liquid crystal molecules located in the dimming zone 401 are deflected by this electric field. Based on this, the light entering each dimming zone 401 is controlled to exit the first liquid crystal layer 430 in a scattered state or a perpendicular state. In other words, the light entering each dimming zone 401 is adjusted. The viewing angle control box 400 provided herein can precisely control the deflection direction of the liquid crystal molecules within each dimming zone 401, thereby controlling the light propagation direction of each dimming zone 401 and precisely controlling the light transmittance state (transparent state or heat dissipation state) of each dimming zone 401. In this way, the viewing angle control box 400 can adjust the display state (shared state or anti-peeping state) of the area corresponding to each dimming zone 401 in the liquid crystal display panel 100.

[0190] Among them, the deflection directions of the liquid crystal molecules in different dimming zones 401 can be the same or different, that is, the propagation directions of the light passing through different dimming zones 401 can be the same or different. Based on this, the display state of the areas in the liquid crystal display panel 100 with different dimming zones 401 can be adjusted, that is, different areas of the liquid crystal display panel 100 can display images in a sharing state and an anti-peeping state respectively. Especially in large-scale display devices, users can adjust the display state of different areas as needed. For example, referring to Figure 24, different areas can be displayed in an anti-peeping state and a sharing state at the same time, which is conducive to improving the user experience. Among them, in Figure 24, the display device 1000 includes an anti-peeping display area 1001 and a sharing display area 1002. The anti-peeping display area 1001 and the sharing display area 1002 can be arranged in any shape, number and relative position relationship, and the embodiments of the present disclosure are not specifically limited to this.

[0191] In the embodiments of the present disclosure, the dimming zone 401 is the smallest dimming unit of the viewing angle control box 400. By adjusting the size (area) of the dimming zone 401, the dimming accuracy of the viewing angle control box 400 can be adjusted. This, in turn, adjusts the minimum area within which the display device 1000 can perform partitioned display. In other words, the accuracy of the partitioned display of the display device 1000 is related to the size of the dimming zone 401. Dimming refers to adjusting the propagation direction of light passing through the viewing angle control box 400, and partitioned display refers to different display states (shared or private) for different areas. For example, if each dimming zone 401 of the viewing angle control box 400 is positioned opposite 10 sub-pixels of the liquid crystal display panel 100, the minimum area within which the liquid crystal display panel 100 performs partitioned display is 10 sub-pixels. Based on this, for example, the size of the dimming zone 401 and the sub-pixel size can be set to the same order of magnitude (e.g., a difference of less than 10 times in the length of a single side). This allows the display device 1000 to achieve pixel-level dimming. This enables the display device to achieve anti-peeping display in any partition, improves the display flexibility of the display device, and further enhances the user experience.

[0192] In some embodiments, referring to FIG. 25 , each subpixel P has a size D1 in the first direction Y and a size D2 in the second direction X. The dimming zone 401 has a size D3 in the first direction Y and a size D4 in the second direction X. D3 = N × D1 + M; D4 = O × D2 + P; 2 ≤ N ≤ 8, where N is a positive integer; 0.1 μm ≤ M ≤ 8 μm; 2 ≤ O ≤ 8, where O is a positive integer; 0.1 μm ≤ P ≤ 0.8 μm. In other words, the size of the dimming zone 401 in the first direction Y is (2 to 8) times the size of the subpixel P in the first direction Y + (0.1 to 0.8) μm, and the size of the dimming zone 401 in the second direction X is (2 to 8) times the size of the subpixel P in the second direction X + (0.1 to 0.8) μm. N and O may be the same or different, and M and P may be the same or different, and this is not limited in the presently disclosed embodiments. Illustratively, D3 = 4× D1 + 0.2 μm; and D4 = 4× D2 + 0.2 μm.

[0193] Based on the above-mentioned size setting, on the one hand, the display device 1000 can achieve pixel-level dimming, which is beneficial to improving the dimming accuracy of the display device 1000. On the other hand, the dimming zone 401 is an integer multiple of the sub-pixel P plus (0.1~0.8) μm, which can avoid the positive projection of the dimming zone 401 on the liquid crystal display panel 100 and the periodic distribution of multiple sub-pixels P. This can reduce or even eliminate the problem of rainbow patterns on the liquid crystal display panel 100.

[0194] In some embodiments, the viewing angle control box 400 further includes a plurality of spacers (not shown in the figure), which are located within the liquid crystal box formed between the array substrate 410 and the opposing substrate 420 and are configured to support the array substrate 410 and the opposing substrate 420 to improve the uniformity of the thickness of the liquid crystal box. Each spacer includes a first end face in contact with the array substrate 410, and the orthographic projection of the first end face on the substrate 10 is located within the orthographic projection of the light adjustment portion 231 on the substrate 10. In other words, the light adjustment portion 231 can also be used to set spacers, which helps to improve the flatness of the area on the array substrate 410 where the spacers are set, and increases the pressure bearing capacity of the array substrate 410, thereby reducing the possibility of the spacers crushing the array substrate 410.

[0195] In some embodiments, referring to FIG. 26 , an array substrate 410 includes a display area 407 and a peripheral area 408 surrounding the display area 407. Multiple dimming zones 401 are located within the display area 407. Exemplarily, the display area 407 is configured to emit light toward the liquid crystal display panel 100. The array substrate 410 may further include a common voltage signal bus 402, a gate driver circuit 403, fan-out traces 404, a chip-on-film (COF) 405, and a driver chip 406.

[0196] The common voltage signal bus 402 is located in the peripheral area 408 and surrounds the display area 407. When the array substrate 410 includes the common voltage signal line 32, the end of the common voltage signal line 32 along the first direction Y is connected to the common voltage signal bus 402. The annular common voltage signal bus 402 helps reduce the resistance of the common voltage signal line 32.

[0197] The gate drive circuit 403 is located in the peripheral area 408 and is located on at least one side of the display area 407 along the second direction X. For example, as shown in FIG26 , the gate drive circuit 403 is located on two opposite sides of the display area 407 along the second direction X. In other words, the gate drive circuit 403 adopts a double-sided drive method. The gate drive circuit 403 is electrically connected to the plurality of gate lines 21 and is configured to transmit scan signals to the plurality of gate lines 21.

[0198] In some other embodiments, multiple gate lines 21 can also be driven by an integrated chip, that is, multiple gate lines 21 can be connected to the integrated chip through a flip chip film, and the integrated chip is connected to the multiple gate lines 21 through the flip chip film to transmit scanning signals to the multiple gate lines 21.

[0199] The fan-out traces 404 are located in the peripheral area 408 and on one side of the display area 407 along the first direction Y. The fan-out traces 404 are connected to the multiple data lines 31 and to the chip-on-film 405. The driver chip 406 is bonded to the chip-on-film 405. The driver chip 406 is connected to the multiple data lines 31 through the chip-on-film 405 and the fan-out traces 404, and is used to transmit data signals to the multiple data lines 31. In other words, the array substrate 410 adopts a COF (Chip On Film) module structure.

[0200] In some other embodiments, the driver chip 406 may also be directly bonded to the peripheral region 408 of the array substrate 410 . That is, the array substrate 410 adopts a COG (Chip On Glass) module structure.

[0201] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate, comprising: A substrate and a first wiring layer arranged on one side of the substrate, wherein the first wiring layer includes a plurality of gate lines arranged at intervals along a first direction, at least one of the gate lines extends along a second direction; the first direction intersects the second direction; A second wiring layer is arranged on a side of the first wiring layer away from the substrate, comprising a plurality of data lines spaced apart along the second direction, at least one of the data lines extending along the first direction; an orthographic projection of the gate line on the substrate intersects with an orthographic projection of the data line on the substrate, two adjacent gate lines and two adjacent data lines define a dimming zone, and the dimming zone is configured to switch between a sharing state and an anti-peeping state; A first electrode layer, disposed on a side of the second wiring layer away from the substrate, comprising a plurality of first electrodes, one of the first electrodes being at least partially located in one of the dimming zones; The second electrode layer is arranged on a side of the first electrode layer away from the substrate, and comprises a second electrode; the orthographic projection of the second electrode on the substrate at least partially does not overlap with the orthographic projection of the first electrode on the substrate.

2. The array substrate according to claim 1, wherein: Each dimming area is provided with a thin film transistor; the thin film transistor is electrically connected to the gate line, the data line and the first electrode, and is configured to transmit a data signal from the data line to the first electrode under the control of a scan signal from the gate line; The second electrode comprises a plurality of avoidance openings, wherein each of the dimming regions is provided with one avoidance opening; the orthographic projection of the avoidance opening on the substrate at least partially overlaps with the orthographic projection of the thin film transistor on the substrate.

3. The array substrate according to claim 2, wherein: The thin film transistor comprises: A gate pattern, disposed on the first wiring layer and connected to the gate line; A semiconductor pattern is arranged between the gate line layer and the second wiring layer; A source pattern, disposed on the second wiring layer and connected to the data line; a drain pattern, arranged on the second wiring layer, spaced apart from the source pattern, and an orthographic projection of the drain pattern on the substrate does not overlap with an orthographic projection of the first electrode on the substrate; The orthographic projection of the gate pattern on the substrate covers the orthographic projections of the semiconductor pattern and the source pattern on the substrate, and partially overlaps with the orthographic projection of the drain pattern on the substrate; the orthographic projection of the avoidance opening on the substrate partially overlaps with the orthographic projections of the gate pattern, the semiconductor pattern and the source pattern on the substrate, and covers the orthographic projection of the drain pattern on the substrate.

4. The array substrate according to claim 3, wherein: The avoidance opening comprises: A first opening portion, wherein a boundary shape of the first opening portion is substantially the same as a boundary shape of the semiconductor pattern, and an orthographic projection of the first opening portion on the substrate is located within an orthographic projection of the semiconductor pattern on the substrate.

5. The array substrate according to claim 3 or 4, wherein: The second electrode layer further comprises: The adapter block is located in the avoidance opening and is spaced apart from the boundary of the avoidance opening; the adapter block is respectively The drain pattern is electrically connected to the first electrode.

6. The array substrate according to claim 5, wherein: The avoidance opening also includes: A second opening portion, wherein a boundary shape of the second opening portion is substantially the same as a boundary shape of the adapter block, and a boundary of the second opening portion surrounds the adapter block.

7. The array substrate according to claim 6, wherein: The distance between the boundary of the transfer block and the boundary of the second opening is 6 μm to 20 μm.

8. The array substrate according to any one of claims 5 to 7, wherein: The orthographic projection of the adapter block on the substrate does not overlap with the orthographic projections of the data line and the gate line on the substrate.

9. The array substrate according to any one of claims 1 to 8, wherein: The second electrode comprises: a plurality of third electrode strips arranged at intervals along the second direction, the third electrode strips extending along the first direction; A fourth electrode strip connected to the end of the third electrode strip has an extension direction parallel to an extension direction of the gate line, and an orthographic projection of the fourth electrode strip on the substrate at least partially overlaps with an orthographic projection of the gate line on the substrate.

10. The array substrate according to claim 9, wherein: The fourth electrode strip comprises at least one protruding portion and a straight portion connected to the protruding portion; The size of the protruding portion in the first direction is larger than the size of the straight portion in the first direction, and the size of the protruding portion in the second direction is larger than the size of the straight portion in the second direction.

11. The array substrate according to claim 10, wherein: The plurality of third electrode strips located in the same dimming zone include: a first sub-electrode strip, wherein two ends of the first sub-electrode strip along the first direction are respectively connected to the straight portion; a second sub-electrode strip, wherein one end of the second sub-electrode strip along the first direction is connected to the straight portion, and the other end of the second sub-electrode strip is connected to the protruding portion; a third sub-electrode strip, wherein two ends of the third sub-electrode strip along the first direction are respectively connected to the protruding portions; The size of the first sub-electrode strip in the first direction is larger than the size of the second sub-electrode strip in the first direction, and the size of the second sub-electrode strip in the first direction is larger than the size of the third sub-electrode strip in the first direction.

12. The array substrate according to any one of claims 9 to 11, wherein: The second electrode also includes a first slit located between two adjacent third electrode strips; the first electrode includes a plurality of first electrode strips spaced apart along the second direction, and a second slit located between two adjacent first electrode strips; the orthographic projections of the first slit and the second slit on the substrate overlap, and the overlapping portion of the first slit and the second slit forms a third slit, and a size of the third slit in the second direction is smaller than a size of the first electrode strip in the second direction, and / or smaller than a size of the second electrode strip in the second direction.

13. The array substrate according to claim 12, wherein: In the same dimming zone, the plurality of first slits include: a third sub-slit, wherein two ends of the third sub-slit along the first direction are respectively connected to the straight portion; a fourth sub-slit, wherein one end of the fourth sub-slit along the first direction is connected to the straight portion, and the other end of the fourth sub-slit is connected to the protruding portion; a fifth sub-slit, wherein two ends of the fifth sub-slit along the first direction are respectively connected to the protruding portions; The size of the third sub-slit in the first direction is greater than the size of the fourth sub-slit in the first direction, and the size of the fourth sub-slit in the first direction is greater than the size of the fifth sub-slit in the first direction.

14. The array substrate according to any one of claims 1 to 11, wherein: The first electrode includes a plurality of first electrode strips spaced apart along the second direction, and the second electrode includes a plurality of third electrode strips spaced apart along the second direction; the orthographic projections of the first electrode strips and the third electrode strips on the substrate are alternately arranged along the second direction, and fourth slits are provided between adjacent first electrode strips and third electrode strips; a size of the fourth slit in the second direction is smaller than a size of the first electrode strips and the third electrode strips in the second direction.

15. The array substrate according to any one of claims 1 to 14, wherein: In one of the dimming zones, the first electrode comprises: a plurality of first electrode strips arranged at intervals along the second direction, wherein the first electrode strips extend along the first direction; The second electrode strips are connected end to end, and the second electrode strips are connected to two ends of the first electrode strips along the first direction to form a structure in which the second electrode strips surround the plurality of first electrode strips.

16. The array substrate according to claim 15, wherein: The second electrode strip comprises: two fourth sub-electrode strips arranged opposite to each other along the first direction, wherein the extension direction of the first sub-electrode strips is parallel to the extension direction of the gate line, and a first interval exists between the orthographic projections of the fourth sub-electrode strips and the gate line on the substrate; Two fifth sub-electrode strips are arranged opposite to each other along the second direction, the extension direction of the second sub-electrode strips is parallel to the extension direction of the data line, and there is a second interval between the orthographic projections of the fifth sub-electrode strips and the data line on the substrate; the first interval is less than or equal to the second interval.

17. The array substrate according to claim 16, wherein: The fourth sub-electrode strip has a sawtooth structure, or the fourth sub-electrode strip has a concave-convex structure.

18. The array substrate according to claim 17, wherein: The fourth sub-electrode strip is provided with a first groove near the edge of the gate line, and the orthographic projection of the first groove on the substrate is spaced apart from the orthographic projection of the gate line on the substrate.

19. The array substrate according to any one of claims 1 to 18, wherein: The gate line includes at least one light adjustment portion and a connection portion connected to the light adjustment portion, and a width of the light adjustment portion is greater than a width of the connection portion.

20. The array substrate according to claim 19, wherein: The ratio of the maximum width of the light adjustment portion to the width of the connection portion is 1.5-4.

21. The array substrate according to claim 19 or 20, wherein: The ratio of the length of the connecting portion to the length of the light adjusting portion is 1.5-3.

22. The array substrate according to any one of claims 19 to 21, wherein: The orthographic projection of the light adjustment portion on the substrate has a hexagonal or octagonal shape.

23. The array substrate according to any one of claims 19 to 22, wherein: The gate line is a zigzag line, including a plurality of extension segments connected in sequence along the second direction; The extension section includes a plurality of the light adjustment parts and a plurality of connection parts which are alternately connected in sequence; and both ends of the extension section are the connection parts respectively.

24. The array substrate according to any one of claims 19 to 23, wherein: The first electrode has a second groove on one side close to the light adjustment part, the shape of the second groove is the same as the shape of the light adjustment part on one side close to the first electrode, and the interval between the second groove and the light adjustment part is equal to the interval between the first electrode and the connecting part.

25. The array substrate according to any one of claims 19 to 24, wherein: An orthographic projection of the light adjustment portion on the substrate does not overlap with an orthographic projection of the thin film transistor on the substrate.

26. The array substrate according to any one of claims 1 to 25, wherein: The gate line includes a plurality of extension segments, and the plurality of extension segments include a plurality of first extension segments and a plurality of second extension segments that are alternately connected; the first extension segments and the second extension segments that are connected to each other are symmetrically arranged about a first reference line, and the angles between the first extension segments and the second extension segments and the second direction are 53° to 73°; the first reference line is parallel to the first direction.

27. The array substrate according to any one of claims 1 to 26, wherein: The data line is a zigzag line, including a plurality of third extension segments and a plurality of fourth extension segments that are alternately arranged in sequence and interconnected along the first direction; the interconnected third extension segments and the fourth extension segments are symmetrically arranged about a second reference line, and the angle between the third extension segments and the fourth extension segments and the first direction is 5° to 10°; the second reference line is parallel to the second direction.

28. The array substrate according to any one of claims 1 to 27, wherein: The second wiring layer further includes a plurality of common voltage signal lines spaced apart along the first direction; Along the second direction, the data lines and the common voltage signal lines are arranged alternately, and adjacent data lines and common voltage signal lines are arranged symmetrically.

29. The array substrate according to claim 28, wherein: The common voltage signal line comprises: A widened portion, wherein the widened portion is electrically connected to the second electrode, and an orthographic projection of the widened portion on the substrate is located within an orthographic projection of the gate line on the substrate.

30. The array substrate according to any one of claims 1 to 29, wherein: The array substrate comprises a display area and a peripheral area surrounding the display area; the array substrate further comprises: a common voltage signal bus located in the peripheral area and surrounding the display area; when the array substrate includes a common voltage signal line, an end of the common voltage signal line along the first direction is connected to the common voltage signal bus; a gate driving circuit, located in the peripheral area and at least on one side of the display area along the second direction, and electrically connected to the gate line; A fan-out wiring, located in the peripheral area and on one side of the display area along the first direction, the fan-out wiring being electrically connected to the data line; A flip chip film connected to the fan-out wiring; The driving chip is bound to the chip-on-chip film.

31. A viewing angle control box, comprising: The array substrate according to any one of claims 1 to 30; The array substrate comprises a plurality of thin film transistors, each dimming area is provided with one thin film transistor, and the thin film transistor is configured to control the dimming area of ​​the viewing angle control box to switch between a sharing state and an anti-peeping state; an opposing substrate, arranged opposite to the array substrate, and forming a liquid crystal box with the array substrate; The first liquid crystal layer is located in the liquid crystal box and is configured to adjust the deflection direction of the liquid crystal molecules located in each dimming zone in the first liquid crystal layer under the control of the driving circuit of the array substrate, thereby controlling the light entering each dimming zone to exit the liquid crystal layer in an anti-peeping state or a sharing state.

32. The viewing angle control box according to claim 31, further comprising: A plurality of spacers are located in the liquid crystal box and are configured to support the array substrate and the opposing substrate. The spacers include a first end surface in contact with the array substrate, and the orthographic projection of the first end surface on the substrate is located within the orthographic projection of the light adjustment part on the substrate.

33. A display device comprising: The viewing angle control box as claimed in claim 31 or 32; A backlight module is disposed on a side of the viewing angle control box close to the array substrate and is configured to emit light perpendicular to the viewing angle control box in a direction close to the viewing angle control box; The liquid crystal display panel is arranged on a side of the viewing angle control box away from the backlight module.

34. The display device according to claim 33, wherein: The liquid crystal display panel includes a plurality of sub-pixels, wherein the size of the sub-pixels in the first direction is D1 and the size of the sub-pixels in the second direction is D2; The array substrate includes multiple dimming areas, each of which has a size D3 in the first direction and a size D4 in the second direction; wherein, D3=N×D1+M; D4=O×D2+P; 2≤N≤8, and N is a positive integer; 0.1μm≤M≤0.8μm; 2≤O≤0.8, and O is a positive integer; 0.1μm≤P≤0.8μm.

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