Array substrate, viewing angle control box and display device

Abstract

An array substrate (410) includes a substrate (10), a first wiring layer (20), a second wiring layer (30), a first electrode layer (40), and a second electrode layer (60). The first wiring layer (20) includes a plurality of gate lines (21) spaced apart along a first direction (Y) and extending along a second direction (X). The second wiring layer (30) includes a plurality of data lines (31) spaced apart along the second direction (X) and extending along the first direction (Y). The orthographic projections of the gate lines (21) and data lines (31) onto the substrate (10) intersect each other, and two adjacent gate lines (21) and two adjacent data lines (31) define a dimming region (401), which is configured to switch between a sharing state and a privacy state. Each dimming region (401) is provided with a first electrode (41). The second electrode layer (60) includes a second electrode (61). The orthographic projection of the second electrode (61) onto the substrate (10) is at least partially different from the orthographic projection of the first electrode (41) onto the substrate (10) and at least partially different from the orthographic projection of the thin-film transistor (50) onto the substrate (10).

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a viewing angle control box, and a display device. Background Technology

[0002] With the development of display technology, people have placed higher demands on the confidentiality and privacy of display devices. To prevent "visual intrusion" and "information leakage" in public offices, display devices with privacy features have been developed. Privacy functionality refers to a display device having both a shared mode and a privacy mode. Existing privacy display technologies typically process the entire screen of the device for privacy, meaning the entire display area is either in shared mode or entirely in privacy mode. However, as the size of display devices increases, the aforementioned technologies that only provide comprehensive privacy protection can no longer meet user needs. Summary of the Invention

[0003] On one hand, an array substrate is provided. The array substrate includes a substrate, a first wiring layer, a second wiring layer, a first electrode layer, and a second electrode layer. The first wiring layer includes a plurality of gate lines spaced apart along a first direction, the gate lines extending along a second direction. The first direction intersects the second direction. The second wiring layer is disposed on the side of the first wiring layer away from the substrate and includes a plurality of data lines spaced apart along the second direction, the data lines extending along the first direction. The orthographic projections of the gate lines on the substrate intersect each other, and two adjacent gate lines and two adjacent data lines define a dimming zone, the dimming zone being configured to switch between a sharing state and a privacy state. The first electrode layer is disposed on the side of the second wiring layer away from the substrate and includes a plurality of first electrodes. Each dimming zone has one first electrode. The second electrode layer is disposed on the side of the first electrode layer away from the substrate and includes a second electrode. The orthographic projection of the second electrode on the substrate does not at least partially coincide with the orthographic projection of the first electrode on the substrate, and does not at least partially coincide with the orthographic projection of the thin-film transistor on the substrate.

[0004] In some embodiments, each dimming region comprises a thin-film transistor; the thin-film transistor is electrically connected to the gate line, the data line, and the first electrode, and is configured to transmit a data signal from the data line to the first electrode under the control of a scan signal from the gate line. The second electrode includes a plurality of clearance openings, with one clearance opening located within each dimming region. The orthographic projection of the clearance opening onto the substrate at least partially coincides with the orthographic projection of the thin-film transistor onto the substrate.

[0005] In some embodiments, the thin-film transistor includes a gate pattern, a semiconductor pattern, a source pattern, and a drain pattern. The gate pattern is disposed on the first wiring layer and connected to the gate line. The semiconductor pattern is disposed between the gate line layer and the second wiring layer. The source pattern is disposed on the second wiring layer and connected to the data line. The drain pattern is disposed on the second wiring layer, spaced apart from the source pattern, and the orthographic projection of the drain pattern on the substrate does not coincide with the orthographic projection of the first electrode on the substrate. The orthographic projection of the gate pattern on the substrate covers the orthographic projections of the semiconductor pattern and the source pattern on the substrate, and partially coincides with the orthographic projection of the drain pattern on the substrate; the orthographic projection of the clearance opening on the substrate coincides with the partial orthographic projections of the gate pattern, the semiconductor pattern, and the source pattern on the substrate, and covers the orthographic projection of the drain pattern on the substrate.

[0006] In some embodiments, the clearance opening includes a first opening. The boundary shape of the first opening is substantially the same as the boundary shape of the semiconductor pattern, and the orthographic projection of the first opening onto the substrate lies within the orthographic projection of the semiconductor pattern onto the substrate.

[0007] In some embodiments, the second electrode layer further includes a transition block. The transition block is located within the clearance opening and is spaced from the boundary of the clearance opening. The transition block is electrically connected to both the drain pattern and the first electrode.

[0008] In some embodiments, the clearance opening further includes a second opening. The boundary shape of the second opening is substantially the same as the boundary shape of the adapter block, and the boundary of the second opening surrounds the adapter block.

[0009] In some embodiments, the interval between the boundary of the adapter block and the boundary of the second opening is 6 μm to 20 μm.

[0010] In some embodiments, the orthographic projection of the adapter block on the substrate does not coincide with the orthographic projection of the data line and the gate line on the substrate.

[0011] In some embodiments, the second electrode includes a plurality of third electrode strips and a plurality of fourth electrode strips. The plurality of third electrode strips are spaced apart along the second direction and extend along the first direction. The fourth electrode strips are connected to the ends of the third electrode strips, and the extending direction of the fourth electrode strips is parallel to the extending direction of the gate line. The orthographic projection of the fourth electrode strip onto the substrate at least partially overlaps with the orthographic projection of the gate line onto the substrate.

[0012] In some embodiments, the fourth electrode strip includes at least one protrusion and a straight portion connected to the protrusion; the size of the protrusion is larger than the size of the straight portion along the first direction, and the size of the protrusion is larger than the size of the straight portion along the second direction.

[0013] In some embodiments, the plurality of third electrode strips located within the same dimming area include a first sub-electrode strip, a second sub-electrode strip, and a third sub-electrode strip. The first sub-electrode strip is connected to the straight portion at both ends along the first direction. The second sub-electrode strip is connected to the straight portion at one end along the first direction and to the protrusion at the other end. The third sub-electrode strip is connected to the protrusion at both ends along the first direction. The dimension of the first sub-electrode strip in the first direction is larger than the dimension of the second sub-electrode strip in the first direction, and the dimension of the second sub-electrode strip in the first direction is larger than the dimension of the third sub-electrode strip in the first direction.

[0014] In some embodiments, the second electrode further includes a first slit located between two adjacent third electrode strips. The first electrode includes a plurality of first electrode strips spaced apart along a second direction, and a second slit located between two adjacent first electrode strips. The orthographic projections of the first slit and the second slit on the substrate overlap, and the overlapping portion of the first slit and the second slit forms a third slit, the dimension of the third slit in the second direction being smaller than the dimension of the first electrode strip in the second direction, and / or the dimension of the second electrode strip in the second direction.

[0015] In some embodiments, two adjacent first slits along a first direction are respectively a first sub-slit and a second sub-slit. The first sub-slit and the second sub-slit are located on opposite sides of the fourth electrode strip and are connected to the opposite sides of the fourth electrode strip, respectively. The end of the first sub-slit near the fourth electrode strip is connected to the protrusion, and the end of the second sub-slit near the fourth electrode strip is connected to the straight portion. The dimension of the first sub-slit in the first direction is smaller than the dimension of the second sub-slit in the first direction.

[0016] In some embodiments, within the same dimming area, the plurality of first slits include a third sub-slit, a fourth sub-slit, and a fifth sub-slit. The third sub-slit is connected to the straight portion at both ends along the first direction. The fourth sub-slit is connected to the straight portion at one end along the first direction and to the protrusion at the other end. The fifth sub-slit is connected to the protrusion at both ends along the first direction. The dimension of the third sub-slit in the first direction is larger than the dimension of the fourth sub-slit in the first direction, and the dimension of the fourth sub-slit in the first direction is larger than the dimension of the fifth sub-slit in the first direction.

[0017] In some embodiments, the first electrode includes a plurality of first electrode strips spaced apart along the second direction, and the second electrode includes a plurality of third electrode strips spaced apart along the second direction. The orthographic projections of the first and third electrode strips onto the substrate are alternately arranged along the second direction, and a fourth slit is formed between adjacent first and third electrode strips. The dimension of the fourth slit in the second direction is smaller than the dimensions of the first and third electrode strips in the second direction.

[0018] In some embodiments, within one of the dimming areas, the first electrode includes a plurality of first electrode strips spaced apart along the second direction, and a second electrode strip connected end-to-end. The first electrode strips extend along the first direction. The second electrode strips are connected to the two ends of the first electrode strips along the first direction to form a structure in which the second electrode strips surround the plurality of first electrode strips.

[0019] In some embodiments, the second electrode strip includes two fourth sub-electrode strips and two fifth sub-electrode strips. The two fourth sub-electrode strips are arranged opposite each other along the first direction, and the extension direction of the first sub-electrode strip is parallel to the extension direction of the gate line. The two fifth sub-electrode strips are arranged opposite each other along the second direction, and the extension direction of the second sub-electrode strip is parallel to the extension direction of the data line. The interval between the orthographic projections of the fourth sub-electrode strips and the gate line onto the substrate is equal to the interval between the orthographic projections of the fifth sub-electrode strips and the data line onto the substrate.

[0020] In some embodiments, the fourth sub-electrode strip has a serrated structure, or the fourth sub-electrode strip has a concave-convex structure.

[0021] In some embodiments, the fourth sub-electrode strip has a first groove near the edge of the gate line, and the orthographic projection of the first groove on the substrate is spaced apart from the orthographic projection of the gate line on the substrate.

[0022] In some embodiments, the grid line includes at least one light adjustment portion and a connecting portion connected to the light adjustment portion, wherein the width of the light adjustment portion is greater than the width of the connecting portion.

[0023] In some embodiments, the ratio of the maximum width of the light adjustment portion to the width of the connecting portion is 1.5 to 4.

[0024] In some embodiments, the ratio of the length of the connecting portion to the length of the light-adjusting portion is 1.5 to 3.

[0025] In some embodiments, the shape of the orthographic projection of the light-adjusting portion onto the substrate is hexagonal or octagonal.

[0026] In some embodiments, the gate line is a zigzag line, including a plurality of extension segments connected sequentially along a second direction. Each extension segment includes a plurality of light-adjusting portions and a plurality of connecting portions connected alternately in sequence; and each end of the extension segment is a connecting portion.

[0027] In some embodiments, the first electrode has a second groove on the side near the light adjustment portion, the shape of the second groove is the same as the shape of the side of the light adjustment portion near the first electrode, and the interval between the second groove and the light adjustment portion is equal to the interval between the first electrode and the connection portion.

[0028] In some embodiments, the orthographic projection of the light-adjusting portion onto the substrate does not coincide with the orthographic projection of the thin-film transistor onto the substrate.

[0029] In some embodiments, the gate line includes a plurality of extension segments, the plurality of extension segments including a plurality of alternating first extension segments and a plurality of second extension segments; the interconnected first extension segments and second extension segments are symmetrically arranged about a first reference line, and the angle between the first extension segments and the second extension segments and the second direction is 53° to 73°; the first reference line is parallel to the first direction.

[0030] In some embodiments, the data line is a zigzag line, including a plurality of third extension segments and a plurality of fourth extension segments that are alternately arranged and interconnected along the first direction; the interconnected third extension segments and fourth extension segments are symmetrically arranged about a second reference line, and the angle between the third extension segments and the fourth extension segments and the first direction is 5° to 10°; the second reference line is parallel to the second direction.

[0031] In some embodiments, the second routing layer further includes a plurality of common voltage signal lines spaced apart along the first direction. Along the second direction, the data lines and the common voltage signal lines are arranged alternately, and adjacent data lines and common voltage signal lines are symmetrically arranged.

[0032] In some embodiments, the common voltage signal line includes a widened portion electrically connected to the second electrode, and the orthographic projection of the widened portion on the substrate lies within the orthographic projection of the gate line on the substrate.

[0033] In some embodiments, the array substrate includes a display area and a peripheral area surrounding the display area. The array substrate further includes a common voltage signal bus, a gate driving circuit, a fan-out trace, a die-capped film, and a driver chip. The common voltage signal bus is located in the peripheral area and surrounds the display area; in the case where the array substrate includes a common voltage signal line, the end of the common voltage signal line along the first direction is connected to the common voltage signal bus. The gate driving circuit is located in the peripheral area and at least one side of the display area along the second direction, and is electrically connected to the gate line. The fan-out trace is located in the peripheral area and one side of the display area along the first direction, and is electrically connected to the data line. The die-capped film is connected to the fan-out trace. The driver chip is bonded to the die-capped film.

[0034] On the other hand, a viewing angle control box is provided, including the array substrate, the opposing substrate, and the first liquid crystal layer as described in any of the above embodiments. The opposing substrate is disposed opposite to the array substrate and together with the array substrate forms a liquid crystal cell. The first liquid crystal layer is located within the liquid crystal cell and is configured to, under the control of the array substrate, adjust the deflection direction of liquid crystal molecules located in each dimming region of the first liquid crystal layer, thereby controlling the light incident on the liquid crystal layer to exit the liquid crystal layer in a scattered state or a perpendicular state.

[0035] In some embodiments, the viewing angle control box further includes a plurality of spacers. The spacers are located within the liquid crystal cell and are configured to support the array substrate and the opposing substrate. Each spacer includes a first end face that contacts the array substrate. The orthographic projection of the first end face onto the substrate is located within the orthographic projection of the light adjustment portion onto the substrate.

[0036] In another aspect, a display device is also provided. The display device includes a viewing angle control box, a backlight module, and a liquid crystal display panel as described in any of the above embodiments. The backlight module is disposed on the side of the viewing angle control box near the array substrate and is configured to emit light perpendicular to the viewing angle control box in a direction close to the viewing angle control box. The liquid crystal display panel is disposed on the side of the viewing angle control box away from the backlight module.

[0037] In some embodiments, the liquid crystal display panel includes a plurality of sub-pixels, each sub-pixel having a size D1 in a first direction and a size D2 in a second direction. The array substrate includes a plurality of dimming areas, each dimming area having a size D3 in the first direction and a size D4 in the second direction; wherein, D3 = N × D1 + M; D4 = 0 × D2 + P; 2 ≤ N ≤ 8, and N is a positive integer; 0.1 μm ≤ M ≤ 0.8 μm; 2 ≤ 0 ≤ 0.8, and 0 is a positive integer; 0.1 μm ≤ P ≤ 0.8 μm. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0039] Figure 1 This is a structural diagram of a display device according to some embodiments;

[0040] Figure 2 This is a structural diagram of a liquid crystal display panel according to some embodiments;

[0041] Figure 3A This is a structural diagram of the view control box in a transparent state according to some embodiments;

[0042] Figure 3B This is a structural diagram of the view control box in a scattering state according to some embodiments;

[0043] Figure 4 This is a structural diagram of an array substrate according to some embodiments;

[0044] Figure 5 This is a structural diagram of the first wiring layer according to some embodiments;

[0045] Figure 6 for Figure 5 A magnified view of a portion of region A1 in the middle;

[0046] Figure 7 This is a structural diagram of the second wiring layer according to some embodiments;

[0047] Figure 8A This is a structural diagram of a dimming area according to some embodiments;

[0048] Figure 8B This is another structural diagram of the dimming area according to some embodiments;

[0049] Figure 9A This is a diagram showing the positional relationship between the first electrode and the dimming area according to some embodiments;

[0050] Figure 9B for Figure 9A A magnified view of a portion of region A2 in the middle;

[0051] Figure 10 This is a structural diagram of the first electrode according to some embodiments;

[0052] Figure 11 for Figure 9B A magnified view of region B1 excluding the second electrode;

[0053] Figure 12 for Figure 9B A magnified view of region B2 excluding the second electrode;

[0054] Figure 13A for Figure 9B A magnified view of region B3 excluding the second electrode;

[0055] Figure 13B for Figure 9B A magnified view of a portion of region B3 in the middle;

[0056] Figure 14 A structural diagram of a thin-film transistor according to some embodiments;

[0057] Figure 15 For along Figure 13B Cross-sectional view along section line C1-C1;

[0058] Figure 16A This is a structural diagram of the second electrode layer according to some embodiments;

[0059] Figure 16B for Figure 16A A magnified view of a portion of area A3 in the middle;

[0060] Figure 17A for Figure 9B A magnified view of a portion of region B1;

[0061] Figure 17B For along Figure 17A Cross-sectional view along section line C2-C2;

[0062] Figure 18 for Figure 9B A magnified view of a portion of region B4 in the middle;

[0063] Figure 19 For along Figure 18 Cross-sectional view along section line C3-C3;

[0064] Figure 20 for Figure 9B A magnified view of a portion of region B2 in the middle;

[0065] Figure 21 For along Figure 20 Cross-sectional view along section line C4-C4;

[0066] Figure 22 for Figure 9B A magnified view of a portion of region B5 in the middle;

[0067] Figure 23 For along Figure 22 Cross-sectional view along section line C5-C5;

[0068] Figure 24 This is a structural diagram of a display partition for privacy display according to some embodiments;

[0069] Figure 25 This is a structural diagram of the dimming area and display panel according to some embodiments;

[0070] Figure 26 This is a planar structural diagram of an array substrate according to some embodiments. Detailed Implementation

[0071] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0072] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0073] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0074] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0075] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0076] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0077] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0078] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0079] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0080] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0081] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0082] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0083] Some embodiments of this disclosure provide a display device, which can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images), and whether text or images. Exemplarily, the display device can be any product or component with display functionality, such as a television, laptop computer, tablet computer, mobile phone, personal digital assistant (PDA), navigator, wearable device, augmented reality (AR) device, virtual reality (VR) device, etc.

[0084] The aforementioned display device may be a liquid crystal display (LCD). The LCD may be a vertical alignment (VA) type display, or a twisted nematic (TN) type display, an advanced-super dimensionalal switching (ADS) type display, or an in-plane switching (IPS) type display; the embodiments disclosed herein do not limit this.

[0085] If the display device is a liquid crystal display device, refer to Figure 1 The display device 1000 includes a liquid crystal display panel 100 and a backlight module 200. Typically, the liquid crystal display panel 100 includes a control substrate 110 (also referred to as an array substrate) and a color filter substrate 120 disposed opposite each other, with a second liquid crystal layer 130 between the control substrate 110 and the color filter substrate 120.

[0086] See Figure 2 The liquid crystal display panel 100 array comprises multiple sub-pixels P, which may include, for example, a first sub-pixel P1 for emitting a first color light, a second sub-pixel P2 for emitting a second color light, and a third sub-pixel P3 for emitting a third color light. For example, the first color, the second color, and the third color are red, green, and blue, respectively. Figure 2 In this process, each grid forms a sub-pixel P. The grid lines can be signal lines of the liquid crystal display panel 100 (such as scan signal lines and data signal lines). The arrangement of multiple sub-pixels P is only exemplary and can also be arranged in other ways. The embodiments disclosed herein do not specifically limit this arrangement.

[0087] Each sub-pixel P includes a control circuit (not shown in the figure) located within the control substrate 110, see further. Figure 1 The control circuit may include, for example, a thin-film transistor 112 and a pixel electrode 113 located on the first substrate 111. The thin-film transistor 112 includes an active layer, a source, a drain, a gate, and a gate insulating layer. The source and drain are respectively in contact with the active layer, and the pixel electrode 113 is electrically connected to the drain of the thin-film transistor 112.

[0088] In some embodiments, such as Figure 1 As shown, the control substrate 110 also includes a common electrode 114 disposed on the first substrate 111. The pixel electrode 113 and the common electrode 114 can be disposed on different layers; in this case, as shown... Figure 1 As shown, a first insulating layer 115 is disposed between the pixel electrode 113 and the common electrode 114. A second insulating layer 116 is also disposed between the common electrode 114 and the thin-film transistor 112.

[0089] When the common electrode 114 is disposed between the thin-film transistor 112 and the pixel electrode 113, such as Figure 1 As shown, the color filter substrate 120 includes a color filter layer 122 disposed on a second substrate 121. The color filter layer 122 includes at least red photoresist units, green photoresist units, and blue photoresist units, which are respectively aligned with sub-pixels on the control substrate 110. The color filter substrate 120 also includes a black matrix pattern 123 disposed on the second substrate 121, which is used to separate the red, green, and blue photoresist units.

[0090] In some other embodiments, the pixel electrode 113 and the common electrode 114 may also be disposed on the same layer. In this case, both the pixel electrode 113 and the common electrode 114 are comb-shaped structures including multiple strip-shaped sub-electrodes (not shown in the figure). Alternatively, the common electrode 114 may also be disposed on the color filter substrate 120 (not shown in the figure). This application does not specifically limit this.

[0091] In some embodiments, such as Figure 1 As shown, a first polarizer 140 is disposed on the side of the control substrate 110 away from the second liquid crystal layer 130, and a second polarizer 150 is disposed on the side of the color filter substrate 120 away from the second liquid crystal layer 130. The polarization directions of the first polarizer 140 and the second polarizer 150 are perpendicular to each other. The liquid crystal display panel 100 may also include a protective cover plate 160 disposed on the side of the color filter substrate 120 away from the control substrate 110.

[0092] It is understood that the liquid crystal display panel 100 may also include other structures, which will not be listed one by one in the embodiments of this disclosure. For example, the liquid crystal display panel 100 may also include a third alignment film (not shown in the figure) disposed on the side of the control substrate 110 near the second liquid crystal layer 130, a fourth alignment film (not shown in the figure) disposed on the side of the color filter substrate 120 near the second liquid crystal layer 130, etc.

[0093] A backlight module 200 is disposed on the non-display side of the liquid crystal display panel 100 and is used to provide a planar light source for the liquid crystal display panel 100. The backlight module 200 can be an edge-lit backlight module or a direct-lit backlight module. In embodiments of this disclosure, such as... Figure 1 As shown, the description takes a direct-lit backlight module 200 as an example. When the backlight module 200 is a direct-lit backlight module, as... Figure 1 As shown, the backlight module 200 may include a backlight source 210, a light guide plate 220, and a reflector 230. The backlight source 210 is located on the side of the light guide plate 220 away from the liquid crystal display panel 100, and may include multiple point light sources (such as LEDs) arranged in an array. The light guide plate 220 is used to homogenize the light emitted from the backlight source 210. The reflector 230 is located on the side of the backlight source 210 away from the liquid crystal display panel 100, and is used to reflect the light emitted from the backlight source 210 towards the reflector 230, thereby increasing the light emitted from the backlight module 200 towards the liquid crystal display panel 100 and improving the light extraction efficiency of the display device.

[0094] In some embodiments, such as Figure 1 As shown, the backlight module 200 also includes an inverted prism 240 located on the side of the light guide plate 220 near the liquid crystal display panel 100. The inverted prism 240 is used to refract at least part of the light emitted from the light guide plate 220 to the forward viewing angle (so that the light is emitted in a direction perpendicular to the surface of the light guide plate 220 near the liquid crystal display panel 100) and improve the light output efficiency of the backlight module 200. That is, the inverted prism 240 can play a certain collimation role on the light emitted from the light guide plate 220.

[0095] In some embodiments, the display device 1000 may be a display device 1000 with a privacy function, see reference. Figure 3A and Figure 3B The display device 1000 also includes a collimation film 300 and a viewing angle control box 400. Both the collimation film 300 and the viewing angle control box 400 are disposed between the liquid crystal display panel 100 and the backlight module 200, with the collimation film 300 being closer to the backlight module 200 than the viewing angle control box 400; that is, the collimation film 300 is located between the viewing angle control box 400 and the backlight module 200. In this context... Figure 3A and Figure 3B In the image, the arrow indicates the direction of light propagation emitted by the backlight module 200.

[0096] The collimating film 300 is used to further collimate the light emitted from the backlight module 200 so that the light entering the collimating film 300 from the backlight module 200 can be emitted in a direction perpendicular to the collimating film 300 and close to the surface of the liquid crystal display panel 100. In other words, the collimating film 300 and the backlight module 200 cooperate to emit light perpendicular to the liquid crystal display panel 100 into the viewing angle control box 400.

[0097] The viewing angle control box 400 can also be called a Smart View Control Solution (SVC) or a viewing angle dimming box. The viewing angle control box 400 is configured to adjust the propagation direction of light passing through the viewing angle control box 400, thereby controlling the light emission direction of the liquid crystal display panel 100, so that the display device 1000 displays images in a privacy display state (hereinafter referred to as: privacy state) and / or a shared display state (hereinafter referred to as: shared state).

[0098] For example, the view control box 400 can operate in a transparent state and / or a scattering state. Figure 3A As shown, when the viewing angle control box 400 is in a transparent state, the long axis direction of the liquid crystal molecules in the first liquid crystal layer 430 can be parallel to the third direction Z (perpendicular to the array substrate 410). The viewing angle control box 400 does not change the propagation direction of the light passing through the viewing angle control box 400. In this way, the light from the backlight module 200 entering the viewing angle control box 400 still passes through the viewing angle control box 400 in a direction perpendicular to the liquid crystal display panel 100, and then enters and passes through the liquid crystal display panel 100. The propagation direction of the light on the display side of the liquid crystal display panel 100 is perpendicular to the light emitting surface of the liquid crystal display panel 100. Only the area opposite to the liquid crystal display panel 100 (where the line of sight is perpendicular to the liquid crystal display panel 100) can see the display content of the liquid crystal display panel 100. The peripheral area (surrounding area) of the liquid crystal display panel cannot see or cannot clearly see the content displayed by the liquid crystal display panel 100. At this time, the liquid crystal display panel 100 can prevent people in the surrounding area from watching. That is to say, the display device 1000 displays images in a privacy mode.

[0099] like Figure 3BAs shown, when the viewing angle control box 400 operates in the scattering state, the long axis direction of the liquid crystal molecules in the first liquid crystal layer 430 can, for example, have an angle with the third direction Z (the direction perpendicular to the array substrate 410). The viewing angle control box 400 can change the propagation direction of the light passing through the viewing angle control box 400 and make the light emitted in a scattered state. In this way, the light from the backlight module 200 that enters the viewing angle control box 400 in a direction perpendicular to the viewing angle control box 400 passes through the viewing angle control box 400 and then enters and passes through the liquid crystal display panel 100 in a scattered state. The light from the display side of the liquid crystal display panel 100 scatters in all directions. At this time, the area directly opposite the liquid crystal display panel 100 and the area around the liquid crystal display panel 100 can both see the display content of the liquid crystal display panel 100, and the display device 1000 displays in a shared state.

[0100] In some embodiments, see Figure 3B The viewing angle control box 400 includes an array substrate 410, an opposing substrate 420, and a first liquid crystal layer 430. The array substrate 410 and the opposing substrate 420 are disposed opposite to each other, and a liquid crystal cell is formed between the array substrate 410 and the opposing substrate 420. The first liquid crystal layer 430 is located in the liquid crystal cell between the array substrate 410 and the opposing substrate 420.

[0101] In some embodiments, the first liquid crystal layer 430 may be a liquid crystal dimming film. For example, it may be a polymer-dispersed liquid crystal (PDLC). PDLC primarily operates in a transparent or scattering state. For instance, PDLC is formed by mixing liquid crystal molecules with a prepolymer adhesive, undergoing a polymerization reaction to form micron-sized liquid crystal droplets uniformly dispersed in a polymer network, and then utilizing the dielectric anisotropy of the liquid crystal molecules to obtain a material with electro-optical response properties. It should be noted that the material of the first liquid crystal layer 430 is not limited to this; any liquid crystal capable of switching between a transparent and scattering state is acceptable. For example, the liquid crystal in the first liquid crystal layer 430 may be a smectic liquid crystal, but it is not limited to this.

[0102] For example, see Figure 3B The viewing angle control box 400 may further include a first alignment film 440 disposed on the side of the array substrate 410 near the first liquid crystal layer 430, and a second alignment film 450 disposed on the side of the opposing substrate 420 near the first liquid crystal layer 430. The first alignment film 440 and the second alignment film 450 are used to control the deflection direction of the liquid crystal molecules in the first liquid crystal layer 430. For example, the first alignment film 440 and the second alignment film 450 can be used to control the deflection direction of the liquid crystal molecules when there is no electric field. It can also be understood that the first alignment film 440 and the second alignment film 450 are used to define the pretilt angle of the liquid crystal molecules.

[0103] In some embodiments, see Figure 4 The array substrate 410 includes a substrate 10, a first wiring layer 20, a second wiring layer 30, a first electrode layer 40, a plurality of thin-film transistors 50, and a second electrode layer 60. The first wiring layer 20 is disposed on one side of the substrate 10, the second wiring layer 30 is disposed on the side of the first wiring layer 20 away from the substrate 10, the first electrode layer 40 is disposed on the side of the second wiring layer 30 away from the substrate 10, and the second electrode layer 60 is disposed on the side of the first electrode layer 40 away from the substrate 10. That is, the first wiring layer 20, the second wiring layer 30, the first electrode layer 40, and the second electrode layer 60 are arranged sequentially in a square shape away from the substrate 10.

[0104] See Figure 5 The first trace layer 20 includes a plurality of gate lines 21 spaced apart along a first direction Y, and the gate lines 21 generally extend along a second direction X. The first direction Y and the second direction X intersect; exemplarily, the first direction Y and the second direction X are perpendicular to each other. "The gate lines 21 generally extend along the second direction X" means that while the gate lines 21 appear to extend along the second direction X macroscopically, they may have portions intersecting with the second direction X microscopically; for example, the gate lines 21 may be zigzag traces. It is understood that the gate lines 21 are used to transmit scan signals.

[0105] In some embodiments, such as Figure 5 As shown, the gate line 21 is a broken line, and the gate line 21 includes a plurality of extension segments 23 connected sequentially along the second direction X. There is a first included angle α1 between two interconnected extension segments 23. The range of the first included angle α1 can be 34° to 74°.

[0106] In a liquid crystal display device 1000, when two stacked layers each have a grid pattern, and the grid patterns of the two layers are similar, moiré patterns are easily generated, which are stripes of alternating light and dark observed by the human eye, affecting the visual experience. For example... Figure 2 As shown, in the liquid crystal display panel 100, the projection shape of multiple sub-pixels P on the viewing angle control box 400 is approximately rectangular. By setting the gate line 21 as a broken line, the extension direction of the gate line 21 can form an angle with the grid forming the sub-pixel P. That is, the gate line 21 forms an angle with the extension direction of the signal lines in the liquid crystal display panel 100. In this way, the grid formed by the gate line 21 has a different shape from the grid formed by the sub-pixel P, which helps to reduce the possibility of moiré patterns appearing in the display device 1000.

[0107] In some embodiments, see Figure 5The multiple extension segments 23 include alternating first extension segments 24 and second extension segments 25 arranged along the second direction X. The interconnected first extension segments 24 and second extension segments 25 are symmetrically arranged about a first reference line L3, and the second included angle α2 between the first extension segments 24 and second extension segments 25 and the second direction X is 53° to 73°. It has been verified that when the second included angle α2 is within the above range, the risk of moiré patterns appearing in the display device 1000 can be minimized. The first reference line L3 is parallel to the first direction Y and passes through the corner where the first extension segments 24 and second extension segments 25 connect. The first extension segment 24 is an extension segment 23 extending along the first reference direction M1, and the second extension segment 25 is an extension segment 23 extending along the second reference direction M2. The first extension segments 24 and second extension segments 25 are symmetrically arranged about the first reference line L3, such that the second included angle α2 between the first extension segments 24 and second extension segments 25 and the second direction X is the same. For example, the second included angle α between the first extension segment 24 and the second extension segment 25 and the second direction X is 53°, 60°, 63.4° or 73°, etc., and the embodiments of this disclosure will not be listed one by one.

[0108] like Figure 5 As shown, the grid line 21 includes at least one light adjustment section 231 and a connecting section 232 connected to the light adjustment section 231. Exemplarily, each extension segment 23 (including the first extension segment 24 and the second extension segment 25) includes at least one light adjustment section 231 and a connecting section 232 connected to the light adjustment section 231.

[0109] See Figure 6 The width D5 of the light adjustment section 231 is greater than the width D6 of the connecting section 232. The light adjustment section 231 can further increase the irregularity of the shape of the grid lines 21, for example, the boundaries of the grid lines 21 are roughly serrated. In other words, the light adjustment section 231 can increase the difference between the grid formed by the grid lines 21 and the grid on the liquid crystal display panel 100, which is beneficial to improving the moiré pattern problem of the display device 1000.

[0110] It is understandable that, such as Figure 6 As shown, the width D5 of the light adjustment section 231 refers to the dimension of the light adjustment section 231 in the third reference direction M3, and the width D6 of the connecting section 232 refers to the dimension of the connecting section 232 in the third reference direction M3. The third reference direction M3 is perpendicular to the extension direction of the extension segment 23 where the light adjustment section 231 and the connecting section 232 are located.

[0111] In some embodiments, the ratio D5 / D6 of the maximum width of the light adjustment section 231 to the width of the connecting section 232 is 1.5 to 4. Wherein, for example... Figure 6As shown, the maximum width of the light adjustment section 231 refers to the interval between two opposite boundaries of the light adjustment section 231 along the third reference direction M3. For example, the ratio D1 / D2 of the maximum width of the light adjustment section 231 to the width of the connecting section 232 is 1.5, 2.0, 3.5, or 4; however, the embodiments of this disclosure will not list all of these.

[0112] For example, the width D6 of the connection portion 232 can be 5μm to 15μm. On the one hand, the resistance of the connection portion 232 is small and does not affect the signal transmission of the gate line 21. On the other hand, it can reduce the problem of light leakage (the deflection direction of liquid crystal molecules is affected by the gate line and deflects unexpectedly) in the vicinity of the viewing angle control box 400 near the gate line 21 (connection portion 232).

[0113] Understandably, if the gate line 21 is too large, for example, greater than 15 μm, the voltage of the gate line 21 will create a large-scale electric field, affecting the deflection direction of nearby liquid crystal molecules and thus causing light leakage. Furthermore, it may lead to excessively large spacing between the dimming areas 401, affecting the dimming effect of the viewing angle control box 400. If the width of the connection portion 232 is too small (for example, less than 5 μm), the resistance of the connection portion 232 will be relatively high, which is not conducive to signal transmission through the gate line 21 and may increase the processing difficulty of the gate line 21. For example, the width of the connection portion 232 can be 5 μm, 8 μm, 15 μm, etc., and the embodiments of this disclosure will not list them all.

[0114] In some embodiments, the difference (D5-D6) between the maximum width D5 of the light adjustment part 231 and the width of the connecting part 232 can be 8μm to 18μm. Exemplarily, the difference (D5-D6) between the width D5 of the light adjustment part 231 and the width of the connecting part 232 can be 8μm, 13μm or 18μm, and the embodiments of this disclosure will not be listed one by one.

[0115] In a specific example, the width of the connecting portion 232 can be 8 μm, and the width of the light adjustment portion 231 can be 21 μm. In this case, the difference between the width D5 of the light adjustment portion 231 and the width of the connecting portion 232 (D5-D6) is 13 μm, and the ratio D5 / D6 of the maximum width of the light adjustment portion 231 to the width of the connecting portion 232 is 2.625.

[0116] In some embodiments, see Figure 6The ratio L2 / L1 of the length L2 of the connecting portion 232 to the length L1 of the light-adjusting portion 231 is 1.5 to 3.5, which helps to reduce moiré patterns in the display device 1000. For example, the ratio L2 / L1 of the length L2 of the connecting portion 232 to the length L1 of the light-adjusting portion 231 is 1.5, 2.2, or 3.5, and these will not be listed individually in the embodiments of this disclosure. The length L2 of the connecting portion 232 refers to its dimension in the fourth reference direction M4, and the length L1 of the light-adjusting portion 231 refers to its dimension in the fourth reference direction M4. The fourth reference direction M4 is parallel to the extension direction of the extension segment 23 where the connecting portion 232 and the light-adjusting portion 231 are located.

[0117] For example, the length L2 of the connecting portion 232 can be 50μm to 70μm. For instance, the length L2 of the connecting portion 232 can be 50μm, 60μm, or 70μm. The length L1 of the light adjustment portion 231 can be 20μm to 36μm. For instance, the length of the light adjustment portion 231 can be 20μm, 28μm, or 36μm.

[0118] In some embodiments, the orthographic projection of the light-adjusting portion 231 onto the substrate 10 is hexagonal (e.g., ...). Figure 6 (as shown) or octagonal (not shown in the figure). In this way, the boundaries of the gate line 21 will not form sharp angles, which helps to reduce the fabrication difficulty of the gate line 21. It is understood that the light adjustment part 231 can also be other shapes, such as circular, elliptical or other shapes, and the embodiments of this disclosure will not be listed one by one.

[0119] See Figure 5 Each extension segment 23 includes a plurality of light adjustment sections 231 and a plurality of connecting sections 232 connected alternately in sequence. The two ends of the extension segment 23 are both connecting sections 232. This prevents the formation of a large pattern at the connection between the first extension segment 24 and the second extension segment 25, which helps reduce the parasitic capacitance formed between the gate line 21 and the second routing layer 30 (data line 31 and common voltage signal line 32), and reduces signal interference between the gate line 21 and the second routing layer 30.

[0120] like Figure 5 As shown, when the first extension segment 24 and the second extension segment 25 are symmetrically arranged about the first reference line L3, the light adjustment part 231 on the first extension segment 24 and the light adjustment part 231 on the second extension segment 25 can also be symmetrically arranged about the first reference line L3.

[0121] In some embodiments, the first wiring layer 20 further includes a gate pattern 51 connected to the gate line 21 for forming the control electrode of the thin-film transistor 50. Exemplarily, the gate pattern 51 may be disposed at the corner of the first extension 24 and the second extension 25. The shape of the gate pattern 51 may be rectangular or other shapes, and the embodiments disclosed herein are not specifically limited thereto.

[0122] See Figure 7 The second routing layer 30 includes multiple data lines 31 spaced apart along the second direction X. The data lines 31 generally extend along the first direction Y. This means that while the data lines 31 appear to extend along the first direction Y macroscopically, they may have portions intersecting with the first direction Y microscopically; for example, the data lines 31 may be zigzag lines. Understandably, the data lines 31 are used to transmit data signals.

[0123] In some embodiments, see Figure 7 The multiple data lines 31 are zigzag lines, and each data line 31 includes multiple third extension segments 311 and multiple fourth extension segments 312 that are alternately arranged and interconnected along the first direction Y. Similar to the zigzag lines 21, the zigzag lines of the data lines 31 help the viewing angle control box 400 to reduce or even eliminate the moiré pattern problem of the display device 1000.

[0124] The interconnected third extension segment 311 and fourth extension segment 312 are symmetrically arranged about the second reference line L4, and the third included angle β1 between the third extension segment 311 and fourth extension segment 312 and the first direction Y is 5° to 10°. It has been verified that when the third included angle β1 between the third extension segment 311 and fourth extension segment 312 and the first direction Y is within the above range, the risk of moiré patterns appearing in the display device 1000 can be minimized. The second reference line L4 is parallel to the second direction X and passes through the corner where the third extension segment 311 and fourth extension segment 312 connect.

[0125] The third extension segment 311 and the fourth extension segment 312 are symmetrically arranged about the second reference line L4, so that the third included angle β1 between the third extension segment 311 and the fourth extension segment 312 and the first direction Y is the same. For example, the third included angle β1 between the third extension segment 311 and the fourth extension segment 312 and the first direction Y is 5°, 7° or 10°, etc., and the embodiments of this disclosure will not be listed one by one.

[0126] In some embodiments, such as Figure 7As shown, the second wiring layer 30 may further include a source pattern 53 and a drain pattern 54, which are used to form the source and drain of the thin-film transistor 50. The source pattern 53 is electrically connected to the data line 31 to receive data signals transmitted by the data line 31. The source pattern 53 and drain pattern 54 are spaced apart; for example, the source pattern 53 can be a "U"-shaped structure, which increases the contact area between the source pattern 53 and the semiconductor pattern 52. The drain pattern 54 can be a "T"-shaped structure. It is understood that the shapes of the source pattern 53 and drain pattern 54 can be adjusted according to actual needs.

[0127] In some embodiments, such as Figure 7 As shown, the second routing layer 30 may further include multiple common voltage signal lines 32 spaced apart along the second direction X. Figure 7 The example only shows one common voltage signal line 32. The common voltage signal line 32 can be used to transmit a common voltage signal. The common voltage signal line 32 extends generally along the first direction Y. This means that while the common voltage signal line 32 appears to extend along the first direction Y macroscopically, it may have portions intersecting the first direction Y microscopically; for example, the common voltage signal line 32 may be a zigzag line.

[0128] In some embodiments, such as Figure 7 As shown, multiple data lines 31 and multiple common voltage signal lines 32 are alternately distributed along the second direction X. That is, along the second direction X, there is a common voltage signal line 32 between every two adjacent data lines 31, and a data line 31 between every two adjacent common voltage signal lines 32, and the adjacent data lines 31 and common voltage signal lines 32 are symmetrically arranged. This helps to improve the uniformity of the wiring in the second wiring layer 30 and improve the uniformity of the display on the display device.

[0129] In some embodiments, adjacent data lines 31 and common voltage signal lines 32 can be arranged symmetrically, such as... Figure 7 As shown, with data lines 31 and common voltage signal lines 32 arranged alternately, and adjacent data lines 31 and common voltage signal lines 32 symmetrically arranged, the multiple common voltage signal lines 32 are zigzag lines. Each common voltage signal line 32 includes multiple fifth extension segments 321 and multiple sixth extension segments 322 that are alternately arranged and interconnected along the first direction Y. Similar to the zigzag line arrangement of the gate line 21, the zigzag arrangement of the common voltage signal lines 32 helps the viewing angle control box 400 reduce or even eliminate moiré patterns on the display device 1000.

[0130] The interconnected fifth extension segment 321 and sixth extension segment 322 are symmetrically arranged about the second reference line L4, and the fourth included angle β2 between the fifth extension segment 321 and the sixth extension segment 322 and the first direction Y is 5° to 10°. Since the data line 31 and the common voltage signal line 32 are symmetrically arranged, the fourth included angle β2 between the fifth extension segment 321 and the sixth extension segment 322 and the first direction Y is the same as the third included angle β1 between the third extension segment 311 and the fourth extension segment 312 and the first direction Y.

[0131] like Figure 7 As shown, the common voltage signal line 32 may include a widened portion 323, the width of which is greater than the width of other parts of the common voltage signal line 32 (excluding the widened portion 323). The widened portion 323 can increase the local area of ​​the common voltage signal line 32, thereby improving the stability and reliability of the subsequent connection between the second electrode 61 and the common voltage signal line 32.

[0132] In some embodiments, see Figure 8A and Figure 8B The orthographic projections of multiple gate lines 21 and multiple data lines 31 on the substrate 10 intersect each other, and the orthographic projections of two adjacent gate lines and two adjacent data lines on the substrate define a dimming area 401. Alternatively, the orthographic projections of any two adjacent data lines 31 on the substrate 10, intersecting with the orthographic projections of any two adjacent gate lines 21 on the substrate, form a closed grid, which constitutes a dimming area 401. Thus, the viewing angle control box 400 has multiple arrayed dimming areas 401. It is understood that in the embodiments of this application, the range of the dimming area 401 may not include the area containing the gate lines 21 and data lines 31 that enclose the dimming area 401; that is, the gate lines 21 and data lines 31 are not within the range of the dimming area 401. The dimming area 401 is configured to switch between a sharing state and a privacy state; that is, the dimming area 401 is the smallest unit within which the viewing angle control box 400 can switch display states.

[0133] In some embodiments, see Figure 8B When both the grid line 21 and the data line 31 are broken lines, the grid line 21 and the data line 31 can form two dimming areas 401 with different shapes. The two dimming areas 401 are the first dimming area 4011 and the second dimming area 4012, respectively. Along the first direction Y, the first dimming area 4011 and the second dimming area 4012 are arranged alternately, and along the second direction X, the dimming areas 401 in the same row have the same shape.

[0134] For example, see Figure 8AThe grid line 21 can coincide with the midpoint of the third extension segment 311 or the fourth extension segment 312 of the data line 31, which is beneficial for obtaining a data line 31 with a regular shape. The data line 31 coincides with the grid line 21 at the corner between the first extension segment 24 and the second extension segment 25, which is beneficial for obtaining a grid line 21 with a regular shape. Based on this, a regular and uniform dimming area 401 grid is obtained, which can improve the dimming uniformity of the viewing angle control box 400. Furthermore, it makes the interference of light at various positions of the viewing angle control box 400 similar, which is beneficial for improving the moiré pattern problem of the display device 1000.

[0135] See Figure 9A The first electrode layer 40 includes a plurality of first electrodes 41, with one first electrode 41 located within each dimming region 401. Alternatively, each of the plurality of first electrodes 41 is located within a dimming region 401, and different first electrodes 41 are located within different dimming regions 401; in other words, only one first electrode 41 is included within the same dimming region 401. For example, the first electrode 41 can be a pixel electrode. Figure 9A The image only shows one dimming zone 401 and one first electrode 41 as an example.

[0136] In some embodiments, see Figure 10 and Figure 11 The first electrode 41 includes a plurality of first electrode strips 42 spaced apart along a second direction X, and a second electrode strip 44 connected end to end. The first electrode strips 42 extend along a first direction Y. The second electrode strips 44 are connected to the two ends of the first electrode strips 42 along the first direction Y to form a structure in which the second electrode strips 44 surround the plurality of first electrode strips 42.

[0137] The second electrode strip 44 surrounds all the first electrode strips 42 (including one first electrode 41) and is connected to the two ends of the first electrode strips 42 along the first direction Y. In this way, multiple first electrode strips 42 can be connected as a whole through the second electrode strip 44. When the first electrode 41 is electrically connected to the thin-film transistor 50, as long as one part is electrically connected to the thin-film transistor 50, all the multiple first electrode strips 42 can be electrically connected to the thin-film transistor 50, thereby allowing the thin-film transistor 50 to charge the multiple first electrode strips 42. The second electrode strip 44 can also be considered as the portion formed by the edge of the first electrode 41, or the portion excluding the first electrode strips 42.

[0138] In some embodiments, see Figure 10 The second electrode strip 44 includes two fourth sub-electrode strips 441 arranged opposite each other along the first direction Y and two fifth sub-electrode strips 442 arranged opposite each other along the second direction X. (See reference...) Figure 9B and Figure 11The extension direction of the first sub-electrode strip 441 is parallel to the extension direction of the grid line 21, see reference. Figure 12 The extension direction of the second sub-electrode strip 442 is parallel to the extension direction of the data line 31.

[0139] See Figure 11 The fourth sub-electrode strip 441 and the gate line 21 have a first spacing H1 between their orthogonal projections on the substrate 10, see reference. Figure 12 The fifth sub-electrode strip 442 and the data line 31 have a second interval H2 between their orthogonal projections on the substrate 10. The first interval H1 and the second interval H2 may be equal or unequal, and the embodiments of this disclosure do not specifically limit this. That is, the outer boundary of the second electrode strip 44 is spaced from the boundary of the dimming area 401. This helps to reduce signal interference between the first electrode 41 and the gate line 21 and the data line 31, thereby making the electric field formed by the first electrode 41 and the second electrode layer 60 uniformly distributed within the dimming area 401.

[0140] In some embodiments, see Figure 10 The fourth sub-electrode strip 441 has a serrated structure, or it has a concave-convex structure. This helps to increase the irregularity of the grid formed by the fourth sub-electrode strip 441, which in turn helps the viewing angle control box 400 to reduce or even eliminate the moiré pattern problem of the display device 1000.

[0141] In some embodiments, see Figure 10 and Figure 11 The fourth sub-electrode strip 441 has a first groove 45 near the edge of the gate line 21. The orthographic projection of the first groove 45 on the substrate is spaced from the orthographic projection of the gate line 21 on the substrate.

[0142] For example, the boundary between the first electrode 41 and the dimming area 401 is spaced (e.g., Figure 11 (As shown). See also Figure 11 The orthographic projection of the first electrode 41 onto the substrate 10 is spaced D7 from the orthographic projection of the gate line 21 onto the substrate 10. (See reference...) Figure 12 The orthographic projection of the first electrode 41 on the substrate 10 is spaced D8 from the orthographic projection of the data line 31 on the substrate 10. Thus, along the direction perpendicular to the substrate 10, there is no portion where the first electrode 41 is positioned opposite the gate line 21 and the data line 31, and no parasitic capacitance is generated between the first electrode 41 and the gate line 21 and the data line 31. This reduces the impact of voltage fluctuations in the gate line 21 and the data line 31 on the voltage of the first electrode 41.

[0143] In some embodiments, see Figure 11In the orthographic projection of the substrate 10, the first electrode 41 has a second groove 45' on the side near the light adjustment section 231. The shape of the second groove 45' is the same as the shape of the side of the light adjustment section 231 near the first electrode 41, and the interval between the second groove 45' and the light adjustment section 231 is equal to the interval between the first electrode 41 and the connecting section 232. That is, the first electrode 41 is equally spaced from the light adjustment section 231 and the connecting section 232, which can reduce the signal interference problem between the light adjustment section 231 of the gate line 21 and the first electrode 41.

[0144] In some embodiments, see Figure 10 A second slit 43 is included between two adjacent first electrode strips 42. The second slit 43 may also extend along a first direction Y. In the first direction Y, the end of the second slit 43 is spaced from the boundary of the first electrode 41. In other words, along the first direction Y, the second slit 43 does not penetrate the first electrode 41, and two adjacent first electrode strips 42 can be connected as a whole through the edge of the first electrode 41 (the second electrode strip). The second slit 43 can not only increase the light transmittance of the first electrode layer 40, but also reduce the area of ​​the first electrode 42, thereby reducing the facing area between the first electrode 42 and the common electrode layer 60, reducing the parasitic capacitance between the first electrode 42 and the common electrode layer 60, and thus improving the charging efficiency of the first electrode 42.

[0145] For example, the orthographic projection of the first electrode strip 42 on the substrate 10 does not coincide with the orthographic projection of the second electrode layer 60 on the substrate 10. This can reduce the risk of parasitic capacitance forming between the first electrode strip 42 and the second electrode layer 60, reduce the impact of the second electrode layer 60 on the charging speed of the first electrode strip 42, and improve the charging efficiency of the first electrode strip 42.

[0146] See Figure 8B Each dimming zone contains one thin-film transistor 50. That is, each of the multiple thin-film transistors 50 is located within a dimming zone 401, and different thin-film transistors 50 are located in different dimming zones 401. See also... Figure 13A and Figure 13B A thin-film transistor 50 is electrically connected to a data line (one of the two data lines 31 that form the dimming area 401 where the thin-film transistor 50 is located), a gate line 21 (one of the two gate lines 21 that form the dimming area 401 where the thin-film transistor 50 is located), and a first electrode 41 (located within the dimming area 401 where the thin-film transistor 50 is located). The thin-film transistor 50 is configured to transmit data signals from the data line 31 to the first electrode 41 under the control of a scan signal from the gate line 21.

[0147] See Figure 13A The thin-film transistor 50 may include a gate pattern 51, a semiconductor pattern 52, a source pattern 53, and a drain pattern 54. The gate pattern 51 is disposed on the first wiring layer 20 and electrically connected to the gate line 21, and is configured to receive a scan signal from the gate line 21. The semiconductor pattern 52, also referred to as the active layer pattern, is located between the first wiring layer 20 and the second wiring layer 30. The source pattern 53 and the drain pattern 54 are located on the second wiring layer 30. The source pattern 53 is electrically connected to the data line 31, and the drain pattern 54 is spaced apart from the source pattern 53, meaning that the drain pattern 54 and the source pattern 53 do not contact each other.

[0148] The orthogonal projection of the gate pattern 51 onto the substrate 10 covers the orthogonal projections of the semiconductor pattern 52 and the source pattern 53 onto the substrate 10, and partially coincides with the orthogonal projection of the drain pattern 54 onto the substrate 10. The orthogonal projection of the drain pattern onto the substrate 10 does not coincide with the orthogonal projection of the first electrode 41 onto the substrate 10. (See also...) Figure 13A The material of the semiconductor pattern 52 can be amorphous silicon (a-Si), oxide, or low-temperature polycrystalline silicon (LTPS), etc., and the embodiments disclosed herein do not specifically limit this.

[0149] See Figure 13B and Figure 14 The second electrode layer 60 includes a second electrode 61. Exemplarily, the second electrode 61 can be a common electrode 61, for example, electrically connected to a common voltage signal line (not shown). The orthographic projection of the second electrode 61 onto the substrate 10 does not at least partially coincide with the orthographic projection of the first electrode 41 onto the substrate 10, and the orthographic projection of the second electrode 61 onto the substrate 10 does not at least partially coincide with the orthographic projection of the thin-film transistor 50 onto the substrate 10. This reduces the facing area between the second electrode 61 and the first electrode 41, and between the second electrode 61 and the thin-film transistor 50, thereby reducing the parasitic capacitance generated between the second electrode 61 and the first electrode 41, and between the second electrode 61 and the thin-film transistor 50, and reducing the adverse effects of the second electrode 61 on the first electrode 41 and the thin-film transistor 50.

[0150] Understandably, parasitic capacitance can lag signal transmission. For example, by at least partially decoupling the second electrode 61 from the first electrode 41, the magnitude of the parasitic capacitance between them can be reduced. This improves the charging efficiency of the first electrode 41 during the charging process (data signal transmission) of the thin-film transistor 50, meaning the first electrode 41 charges faster and more fully. The fact that the second electrode 61 does not partially overlap with the thin-film transistor 50 further reduces the risk of parasitic capacitance between them, thereby improving the response speed of the thin-film transistor 50.

[0151] In some embodiments, see Figure 13B and Figure 14 The second electrode 61 includes multiple clearance openings 62. Each dimming area has one clearance opening 62. The orthographic projection of the clearance opening 62 onto the substrate 10 at least partially coincides with the orthographic projection of the thin-film transistor 50 onto the substrate 10. That is, the boundary of one clearance opening 62 surrounds at least a portion of the thin-film transistor 50, and at least a portion of the thin-film transistor 50 is located within the clearance opening 62. This helps to reduce the area of ​​overlapping projections between the second electrode 61 and the thin-film transistor 50, reducing the parasitic capacitance generated by the second electrode 61 and the thin-film transistor 50, reducing the adverse effects of the second electrode 61 on the thin-film transistor 50, and thereby improving the response speed of the thin-film transistor 50.

[0152] For example, such as Figure 13B and Figure 14 As shown, the clearance opening 62 includes a first opening 621. The boundary shape of the first opening 621 is approximately the same as the boundary shape of the semiconductor pattern 52, and the orthographic projection of the first opening 621 on the substrate 10 lies within the orthographic projection of the semiconductor pattern 52 on the substrate. The boundary of the first opening 621 surrounds the edge of the semiconductor pattern 52. In this way, the risk of the first opening 621 exposing the gate line 21 and the data line 31 can be reduced, and the influence of the electric field formed by the gate line 21 and the data line 31 on the first liquid crystal layer can be reduced.

[0153] For example, such as Figure 14 As shown, the boundary shape of the first opening 621 and the boundary shape of the semiconductor pattern 52 are approximately rectangular; the boundary of the first opening 621 is spaced from the semiconductor pattern 52, and the spacing between the boundary of the first opening 621 and the semiconductor pattern 52 is approximately equal along the circumference of the first opening 621. In other words, the spacing between any position of the boundary of the first opening 621 and the semiconductor pattern 52 is approximately equal.

[0154] In some embodiments, such as Figure 14As shown, when the orthographic projection of the first electrode 41 on the substrate 10 does not coincide with the orthographic projection of the drain pattern 54 on the substrate 10, the second electrode layer 60 further includes a transition block 63, which is electrically connected to both the drain pattern 54 and the first electrode 41. In other words, the drain pattern 54 is electrically connected to the first electrode 41 via the transition block 63. This simplifies the fabrication process of the array substrate 410 and reduces its fabrication difficulty and cost.

[0155] Understandably, see Figure 15 The array substrate 410 also includes an insulating layer located between two adjacent conductive layers. For example, as... Figure 15 As shown, the control substrate 110 further includes a gate insulating layer 411 between the first wiring layer 20 and the semiconductor pattern 52, a first passivation layer (PVX1) 412 between the second wiring layer 30 and the first electrode layer 40, and a second passivation layer (PVX2) 413 between the first electrode layer 40 and the second electrode layer 60. The material of the first passivation layer 412 can be the same as the material of the second passivation layer 413; for example, both the materials of the first passivation layer 412 and the second passivation layer 413 can include silicon nitride and / or silicon oxide.

[0156] See Figure 15 The array substrate 410 further includes a second via 415 penetrating the first passivation layer 412 and the second passivation layer 413, and a third via 416 penetrating the second passivation layer 413. The orthographic projection of the second via 415 on the substrate 10 at least partially coincides with the drain pattern 54 and the transition block 63, respectively, so that the transition block 63 is electrically connected to the drain pattern 54 through the second via 415. The orthographic projection of the third via 416 on the substrate 10 at least partially coincides with the orthographic projections of the transition block 63 and the first electrode 41 on the substrate 10, so that the transition block 63 is electrically connected to the first electrode 41 through the third via 416.

[0157] With the design of the aforementioned adapter block 63, during the fabrication of the array substrate 410, after forming the first passivation layer 412, the first electrode layer 40 and the second passivation layer 413 can be sequentially fabricated on the first passivation layer 412. Then, the second via 415 and the third via 416 can be formed simultaneously through a one-step etching process. Compared to the first electrode 41 being directly electrically connected to the drain pattern 54 through a via (e.g., a via that only penetrates the first passivation layer), at least one via etching process can be saved. In other words, the fabrication process of the array substrate 410 can be simplified, thereby reducing the fabrication cost of the array substrate 410.

[0158] By way of example, embodiments of this disclosure also provide a method for fabricating an array substrate, the method comprising steps S100 to S500.

[0159] S100, a first wiring layer, a gate insulating layer, a semiconductor layer, and a second electrode layer are sequentially formed on the substrate.

[0160] The structure of the first wiring layer, gate insulating layer, semiconductor layer and first electrode layer is described above and will not be repeated here.

[0161] S200, a first initial passivation layer is formed on the second electrode layer.

[0162] The first initial passivation layer is a continuous, monolithic structure.

[0163] S300, a first electrode layer and a second initial passivation layer are sequentially formed on the first initial passivation layer.

[0164] The structure of the first electrode layer is described above and will not be repeated here. The second initial passivation layer is a continuous monolayer structure.

[0165] S400, pattern the second initial passivation layer and the first initial passivation layer to form the second passivation layer and the first passivation layer.

[0166] For example, the same etching process can be used to form a second via 415 and a third via 416 on the second initial passivation layer and the first initial passivation layer.

[0167] S500, a second electrode layer is formed on the second passivation layer.

[0168] The second electrode layer includes a transition block, which is electrically connected to the drain and the first electrode through a second via and a third via, respectively. Therefore, it is not necessary to separately create vias on the first initial passivation layer; the second via 415 and the third via 416 can be formed in a single process, simplifying the fabrication process of the array substrate 410 and thus reducing its fabrication cost.

[0169] For example, such as Figure 14 As shown, the boundary shape of the adapter block 63 and the boundary shape of the second opening 622 are approximately rectangular, and the corners of the rectangles are chamfered. The second opening 622 is spaced from the adapter block 63, and the distance between the boundary of the second opening 622 and the adapter block 63 is approximately equal along the circumference of the second opening 622.

[0170] The distance D9 between the boundary of the adapter block 63 and the boundary of the second opening 622 is 6μm to 20μm. This ensures electrical insulation between the adapter block 63 and the second electrode 61, reducing signal interference between them, and also prevents an excessively large second opening 622 from creating uncontrollable localized areas of liquid crystal deflection within the dimming area 401. For example, the distance D9 between the boundary of the adapter block 63 and the boundary of the second opening 622 can be 6μm, 11.5μm, 18μm, or 20μm, etc., and the embodiments of this disclosure do not specifically limit this.

[0171] Understandably, if the distance D9 between the boundary of the transition block 63 and the boundary of the second opening 622 is too small, for example, less than 6 μm, it will increase the difficulty of fabricating the second electrode layer 60, and may also cause signal interference between the transition block 63 and the second electrode 61. If the distance D9 between the boundary of the transition block 63 and the boundary of the second opening 622 is too large, for example, greater than 20 μm, a large area within the dimming area 401 will lack the second electrode 61. This area will not be able to generate an electric field with the first electrode 41, thus making it impossible to control the deflection direction of the liquid crystal molecules in this area, and consequently, unable to adjust the propagation direction of light in this area. Therefore, the distance D9 between the boundary of the transition block 63 and the boundary of the second opening 622 is set to 6 μm to 20 μm.

[0172] In some embodiments, see Figure 14 The orthographic projection of the adapter block 63 on the substrate 10 does not coincide with the orthographic projections of the data line 31 and the gate line 21 on the substrate 10. This reduces the risk of parasitic capacitance between the adapter block 63 and the data line 31 and the gate line 21, thereby reducing voltage fluctuations in the adapter block 63 caused by voltage fluctuations on the data line 31 and the gate line 21, improving the voltage stability of the first electrode 41, and thus improving the stability of the light transmission state within the dimming area 401.

[0173] In some embodiments, see Figure 16A The second electrode 61 includes a plurality of third electrode strips 64 spaced apart along a second direction X, and a fourth electrode strip 66 connected to the ends of the third electrode strips 64. The third electrode strips 64 extend along a first direction Y. The extending direction of the fourth electrode strip 66 is parallel to the extending direction of the gate line 21, and its orthographic projection on the substrate 10 at least partially overlaps with the orthographic projection of the gate line 21 on the substrate 10. Along the first direction Y, the ends of the third electrode strips 64 are respectively connected to the fourth electrode strips 66, so that the third electrode strips 64 located in different dimming areas 401 are connected through the fourth electrode strips 66.

[0174] Exemplarily, in the orthogonal projection of the gate line 21 onto the substrate 10, the remainder is located within the fourth electrode strip 66, except for a portion exposed by the clearance opening 62. Exemplarily, see [reference needed]. Figure 17A and Figure 17B The boundary of the orthographic projection of the gate line 21 onto the substrate 10 lies within the boundary of the orthographic projection of the fourth electrode strip 66 onto the substrate 10, and is spaced apart from the boundary of the fourth electrode strip 66. In other words, the width of the fourth electrode strip 66 (the dimension in the direction perpendicular to the extension of the fourth electrode strip 66) is greater than the width of the gate line 21, so that the fourth electrode strip 66 can completely cover the gate line 21 and completely shield the electric field generated by the gate line 21.

[0175] In some embodiments, see Figure 16B The fourth electrode strip 66 includes at least one protrusion 661 and a straight portion 662 connected to the protrusion 661. Exemplarily, the fourth electrode strip 66 consists of a plurality of protrusions 661 and a plurality of straight portions 662 connected alternately in sequence. The dimension D10 of the protrusion 661 in the first direction Y is greater than the dimension D11 of the straight portion 662 in the first direction Y, and the dimension D12 of the protrusion 661 in the second direction X is greater than the dimension D13 of the straight portion 662 in the second direction X. The boundary shape of the fourth electrode strip 66 can be serrated or have an uneven structure to better shield the gate line 21 and reduce the influence of the electric field formed by the gate line 21 on the first liquid crystal layer.

[0176] For example, see Figure 17A When the gate line 21 includes multiple light-adjusting portions 231, the shape of the protrusion 661 can be the same as the shape of the light-adjusting portion 231, with each protrusion 661 corresponding to one light-adjusting portion 231. The orthographic projection of the protrusion 661 on the substrate 10 covers the orthographic projection of the light-adjusting portion 231 corresponding to the protrusion 661 on the substrate 10. Furthermore, the interval D14 between the orthographic projections of the protrusion 661 and the light-adjusting portion 231 on the substrate can be equal to the interval D15 between the orthographic projections of the connecting portion 232 and the straight portion 662 on the substrate. In other words, the different portions of the orthographic projection of the fourth electrode strip 66 on the substrate 10 are approximately equal to the intervals of the orthographic projections of the gate line 21 on the substrate 10. Thus, the fourth electrode strip 66 can shield the electric field generated by the gate line 21, reducing the risk of the electric field generated by the light-adjusting portion 231 affecting the first liquid crystal layer.

[0177] See Figure 16BThe plurality of third electrode strips 64 located within the same dimming zone include a first sub-electrode strip 641, a second sub-electrode strip 642, and a third sub-electrode strip 643. The first sub-electrode strip 641 is connected to a straight portion 662 at both ends along the first direction Y. The second sub-electrode strip 642 is connected to the straight portion 662 at one end along the first direction Y, and to a protrusion 661 at the other end. The third sub-electrode strip 643 is connected to the protrusion 661 at both ends along the first direction Y. The dimension L5 of the first sub-electrode strip 641 in the first direction Y is greater than the dimension L6 of the second sub-electrode strip 642 in the first direction Y, and the dimension L6 of the second sub-electrode strip 642 in the first direction Y is greater than the dimension L7 of the third sub-electrode strip 643 in the first direction Y.

[0178] See Figure 16B The second electrode 61 also includes a first slit 65 located between two adjacent third electrode strips 64. The two adjacent first slits 65 along the first direction Y are respectively a first sub-slit 651 and a second sub-slit 652, which are located on both sides of the fourth electrode strip 66 and connected to the opposite sides of the fourth electrode strip 66. The dimension L8 between the first sub-slits 651 and the second sub-slits 652 on both sides of the straight portion 662 in the first direction Y is smaller than the dimension L9 between the first sub-slits 651 and the second sub-slits 652 on both sides of the protruding portion 661 in the first direction Y. (Continue reading) Figure 16B Within the same dimming zone, multiple first slits 65 include a third sub-slit 653, a fourth sub-slit 654, and a fifth sub-slit 655. The third sub-slit 653 is connected to a straight portion 662 at both ends along the first direction Y. The fourth sub-slit 654 is connected to the straight portion 662 at one end along the first direction Y, and to a protrusion 661 at the other end. The fifth sub-slit 655 is connected to the protrusion 661 at both ends along the first direction Y. The dimension L10 of the third sub-slit 653 in the first direction Y is greater than the dimension L11 of the fourth sub-slit 654 in the first direction Y, and the dimension L11 of the fourth sub-slit 654 in the first direction Y is greater than the dimension L12 of the fifth sub-slit 655 in the first direction Y.

[0179] See Figure 18 and Figure 19The second electrode 61 also includes a first slit 65 located between two adjacent third electrode strips 64. The first electrode 41 includes a plurality of first electrode strips 42 spaced apart along the second direction X, and a second slit 43 located between two adjacent first electrode strips 42. The orthographic projections of the first slit 65 and the second slit 43 on the substrate overlap, and the overlapping portion of the first slit 65 and the second slit 43 forms a third slit 68. The dimension D16 of the third slit 68 in the second direction X is smaller than the dimension D17 of the first electrode strip 42 in the second direction X and the dimension D18 of the third electrode strip 64 in the second direction X.

[0180] It is understood that the extension direction of the second slit 43 is parallel to the extension direction of the first slit 65 and extends along the first direction Y. This is beneficial to improving the light transmittance of the viewing angle control box 400. However, in some other embodiments, the extension directions of the second slit 43 and the first slit 65 may also have a certain angle with the first direction Y. The embodiments disclosed herein do not specifically limit this.

[0181] In some embodiments, such as Figure 18 As shown, a fourth slit 68' is included between the orthographic projections of adjacent first electrode strips 42 and third electrode strips 64 on the substrate 10. The fourth slit 68' is located within the second slit 43 and the first slit 65. Exemplarily, the dimensions D16 of the plurality of fourth slits 68' in the second direction X are equal, that is, the plurality of first electrode strips 42 and third electrode strips 64 are equally spaced along the second direction X. Alternatively, the orthographic projections of the first electrode strips 42 and the third electrode strips 64 on the substrate 10 are alternately arranged along the second direction X, and the first electrode strips 42 and third electrode strips 64 do not overlap. For example, a third electrode strip 64 is included between every two adjacent first electrode strips 42, and a first electrode strip 42 is included between every two adjacent third electrode strips 64. This allows for a more uniform electric field distribution formed by the first electrode 41 and the second electrode 61. Moreover, it can minimize the area of ​​the overlapping projection of the first electrode 41 and the second electrode 61 on the substrate 10, reduce the size of the parasitic capacitance generated between the first electrode 41 and the second electrode 61, and reduce the impact of the second electrode 61 on the charging efficiency of the first electrode 41.

[0182] In some embodiments, such as Figure 16B As shown, the second electrode 61 also includes a fifth electrode strip 67. (As indicated...) Figure 20 and Figure 21 As shown, the extension direction of the fifth electrode strip 67 is parallel to the extension direction of the data line 31, and the orthogonal projection of the fifth electrode strip 67 on the substrate 10 covers at least a portion of the orthogonal projection of the data line 31 on the substrate 10.

[0183] For example, in the orthogonal projection of the data line 31 onto the substrate 10, the rest is located within the fifth electrode strip 67, except for a portion that is exposed by the clearance opening 62.

[0184] For example, see Figure 20 and Figure 21 The boundary of the orthographic projection of the data line 31 onto the substrate 10 lies within the boundary of the orthographic projection of the fifth electrode strip 67 onto the substrate 10, and is spaced apart from the boundary of the orthographic projection of the fifth electrode strip 67 onto the substrate 10. In other words, the width of the fifth electrode strip 67 (the dimension in the direction perpendicular to the extension of the fifth electrode strip 67) is greater than the width of the data line 31, so that the fifth electrode strip 67 can completely cover the data line 31 and completely shield the electric field generated by the data line 31.

[0185] In some embodiments, since the common voltage signal line 32 and the second electrode 61 (second electrode layer 60) are electrically connected, meaning there is no voltage difference between the common voltage signal line 32 and the second electrode 61, there will be no voltage difference or parasitic capacitance between them. Based on this, the orthogonal projection of the second electrode 61 onto the substrate 10 may coincide with or be separate from the common voltage signal line 32, without affecting the electric field distribution within the dimming area 401. For example, as... Figure 22 As shown, the orthogonal projection of the second electrode 61 on the substrate 10 partially coincides with the common voltage signal line 32, and the portion of the common voltage signal line 32 is separated from and does not coincide with the common voltage signal line 32.

[0186] like Figure 22 and Figure 23 As shown, the array substrate 410 also includes a first via 414 penetrating the first passivation layer 412 and the second passivation layer 413. The orthographic projection of the first via 414 on the substrate 10 at least partially overlaps with the orthographic projection of the common voltage signal line 32 and the second electrode 61 on the substrate 10. Thus, the second electrode 61 is electrically connected to the common voltage signal line 32 through the first via 414.

[0187] When the common voltage signal line 32 includes a widened portion 323, the widened portion 323 is electrically connected to the second electrode 61. The first via 414 exposes the widened portion 323 of the common voltage signal line 32. The widened portion 323 can increase the contact area between the second electrode 61 and the common voltage signal line 32, which is beneficial to improving the connection stability between the common voltage signal line 32 and the second electrode 61. The orthographic projection of the widened portion 323 on the substrate 10 is located within the orthographic projection of the gate line 21 on the substrate. This is beneficial to reduce the light shading of the widened portion 323 and improve the light transmittance of the array substrate 410.

[0188] When the display device 1000 is operating, the first liquid crystal layer 430 of the viewing angle control box 400 is configured to adjust the deflection direction of liquid crystal molecules located in each dimming region 401 within the first liquid crystal layer 430 under the control of the thin-film transistor 50 of the array substrate 410. For example, when the display device 1000 is operating, the viewing angle control box 400 transmits a voltage signal to the first electrode 41 via the thin-film transistor 50, and a common voltage signal line 32 provides a common voltage to the second electrode 61, generating a voltage difference between the first electrode 41 and the second electrode 61, thereby forming an electric field within the dimming region 401. The liquid crystal molecules located within the dimming region 401 are deflected under the action of this electric field. Based on this, the light incident into each dimming region 401 is controlled to exit the first liquid crystal layer 430 in a scattered or perpendicular state; that is, the light incident into each dimming region 401 is adjusted. The viewing angle control box 400 provided in this application can precisely control the deflection direction of liquid crystal molecules in each dimming zone 401, thereby controlling the light propagation direction of each dimming zone 401 and precisely controlling the light transmission state (transparent state or heat dissipation state) of each dimming zone 401. In this way, the viewing angle control box 400 can adjust the display state (sharing state or privacy state) of the area in the liquid crystal display panel 100 corresponding to each dimming zone 401.

[0189] In this design, the deflection directions of liquid crystal molecules in different dimming areas 401 can be the same or different, meaning that the propagation directions of light passing through different dimming areas 401 can be the same or different. Based on this, the display state of areas in the liquid crystal display panel 100 corresponding to different dimming areas 401 can be adjusted. That is, different areas of the liquid crystal display panel 100 can display images in a sharing state and a privacy state, respectively. Especially in large-size display devices, users can adjust the display state of different areas as needed. For example, see [reference needed]. Figure 24 It can be displayed in both privacy and sharing modes simultaneously in different areas, which improves the user experience. Specifically, in... Figure 24 In the display device 1000, there are privacy display area 1001 and sharing display area 1002. The privacy display area 1001 and sharing display area 1002 can be arranged in any shape, number and relative position relationship. The embodiments of this disclosure do not specifically limit this.

[0190] In the embodiments of this disclosure, the dimming zone 401 is the smallest dimming unit of the viewing angle control box 400. The dimming accuracy of the viewing angle control box 400 can be adjusted by adjusting the area size (area) of the dimming zone 401. This, in turn, adjusts the smallest area where the display device 1000 can perform partitioned display; that is, the partitioned display accuracy of the display device 1000 is related to the area size of the dimming zone 401. Dimming refers to adjusting the propagation direction of light passing through the viewing angle control box 400, and partitioned display refers to different display states (sharing state or privacy state) for different areas. For example, when each dimming zone 401 of the viewing angle control box 400 is positioned relative to 10 sub-pixels of the liquid crystal display panel 100, the smallest area for partitioned display of the liquid crystal display panel 100 is 10 sub-pixels. Based on this, for example, the area size of the dimming zone 401 and the size of the sub-pixels can be set to the same order of magnitude (e.g., the difference in length on one side is less than 10 times), thus enabling the display device 1000 to achieve pixel-level dimming. This enables display devices to achieve privacy-protected display in any partition, improving the flexibility of the display and thus enhancing the user experience.

[0191] In some embodiments, see Figure 25 Each sub-pixel P has a size of D1 in the first direction Y and a size of D2 in the second direction X. The dimming area 401 has a size of D3 in the first direction Y and a size of D4 in the second direction X. D3 = N × D1 + M; D4 = 0 × D2 + P; 2 ≤ N ≤ 8, and N is a positive integer; 0.1 μm ≤ M ≤ 8 μm; 2 ≤ 0 ≤ 8, and 0 is a positive integer; 0.1 μm ≤ P ≤ 0.8 μm. That is, the size of the dimming area 401 in the first direction Y is (2 to 8) times the size of the sub-pixel P in the first direction Y + (0.1 to 0.8) μm, and the size of the dimming area 401 in the second direction X is (2 to 8) times the size of the sub-pixel P in the second direction X + (0.1 to 0.8) μm. Wherein, N and O can be the same or different, and M and P can be the same or different; the embodiments of this disclosure do not limit this. For example, D3 = 4 × D1 + 0.2 μm; and D4 = 4 × D2 + 0.2 μm.

[0192] Based on the above size settings, on the one hand, the display device 1000 can achieve pixel-level dimming, which is beneficial to improving the dimming accuracy of the display device 1000. On the other hand, the dimming area 401 being an integer multiple of the sub-pixel P plus (0.1~0.8) μm can avoid the situation where the orthographic projection of the dimming area 401 on the liquid crystal display panel 100 and multiple sub-pixels P are periodically distributed. This can reduce or even eliminate the problem of rainbow patterns appearing on the liquid crystal display panel 100.

[0193] In some embodiments, the viewing angle control cell 400 further includes a plurality of spacers (not shown) located within a liquid crystal cell formed between the array substrate 410 and the opposing substrate 420. These spacers are configured to support the array substrate 410 and the opposing substrate 420, improving the uniformity of the liquid crystal cell thickness. Each spacer includes a first end face that contacts the array substrate 410. The orthographic projection of the first end face onto the substrate 10 lies within the orthographic projection of the light adjustment section 231 onto the substrate 10. In other words, the light adjustment section 231 can also be used to provide spacers. The light adjustment section 231 helps improve the flatness of the area on the array substrate 410 where the spacers are provided, increases the pressure bearing capacity of the array substrate 410, and reduces the possibility of the spacers damaging the array substrate 410.

[0194] In some embodiments, see Figure 26 The array substrate 410 includes a display area 407 and a peripheral area 408 surrounding the display area 407. A plurality of dimming areas 401 are located within the display area 407. Exemplarily, the display area 407 is used to emit light to the liquid crystal display panel 100. The array substrate 410 may also include a common voltage signal bus 402, a gate driving circuit 403, fan-out traces 404, a flip-chip film 405, and a driver chip 406.

[0195] A common voltage signal bus 402 is located in the peripheral area 408 and surrounds the display area 407. When the array substrate 410 includes a common voltage signal line 32, the end of the common voltage signal line 32 along the first direction Y is connected to the common voltage signal bus 402. The ring-shaped common voltage signal bus 402 helps to reduce the resistance of the common voltage signal line 32.

[0196] The gate driving circuit 403 is located in the peripheral region 408 and at least on one side of the display region 407 along the second direction X, for example, as shown in the example. Figure 26 As shown, the gate driving circuit 403 is located on opposite sides of the display area 407 along the second direction X, that is, the gate driving circuit 403 adopts a dual-side driving method. The gate driving circuit 403 is electrically connected to multiple gate lines 21 and is configured to transmit scan signals to the multiple gate lines 21.

[0197] In other embodiments, the multiple gate lines 21 can also be driven by an integrated chip. That is, the multiple gate lines 21 can be connected to the integrated chip through a flip-chip film, and the integrated chip can be connected to the multiple gate lines 21 through the flip-chip film to transmit scanning signals to the multiple gate lines 21.

[0198] Fan-out trace 404 is located in the peripheral area 408 and on one side of the display area 407 along the first direction Y. Fan-out trace 404 is connected to multiple data lines 31 and to the chip-on-film 405. Driver chip 406 is bonded to the chip-on-film 405. Driver chip 406 is connected to multiple data lines 31 through chip-on-film 405 and fan-out trace 404, and is used to transmit data signals to multiple data lines 31. That is to say, the array substrate 410 adopts a COF (Chip On Film) module structure.

[0199] In some other embodiments, the driver chip 406 can also be directly bonded to the peripheral area 408 of the array substrate 410. That is, the array substrate 410 adopts a COG (Chip On Glass) module structure.

[0200] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, comprising: A substrate and a first wiring layer disposed on one side of the substrate, the first wiring layer including a plurality of gate lines spaced apart along a first direction, at least one of the gate lines extending along a second direction; the first direction and the second direction intersect. The second wiring layer is disposed on the side of the first wiring layer away from the substrate, and includes a plurality of data lines spaced apart along the second direction, at least one of the data lines extending along the first direction; the orthographic projection of the gate line on the substrate and the orthographic projection of the data line on the substrate intersect each other, and two adjacent gate lines and two adjacent data lines define a dimming zone, which is configured to switch between a sharing state and a privacy state; A first electrode layer is disposed on the side of the second wiring layer away from the substrate, and includes a plurality of first electrodes, wherein at least a portion of one of the first electrodes is located in one of the dimming areas; A second electrode layer is disposed on the side of the first electrode layer away from the substrate, and includes a second electrode; the orthographic projection of the second electrode on the substrate does not at least partially coincide with the orthographic projection of the first electrode on the substrate. The second electrode includes a plurality of third electrode strips spaced apart along the second direction, and a fourth electrode strip connected to the end of the third electrode strips; the third electrode strips extend along the first direction, the extension direction of the fourth electrode strips is parallel to the extension direction of the gate line, and the orthographic projection of the fourth electrode strip on the substrate at least partially overlaps with the orthographic projection of the gate line on the substrate; the fourth electrode strip includes at least one protrusion and a straight portion connected to the protrusion. The protrusion in the first direction is larger than the straight portion in the first direction, and the protrusion in the second direction is larger than the straight portion in the second direction.

2. The array substrate according to claim 1, wherein, Each of the dimming areas is provided with a thin-film transistor; the thin-film transistor is electrically connected to the gate line, the data line and the first electrode, and is configured to transmit data signals from the data line to the first electrode under the control of a scan signal from the gate line; The second electrode includes a plurality of clearance openings, and each dimming area has one clearance opening; the orthographic projection of the clearance opening on the substrate at least partially overlaps with the orthographic projection of the thin-film transistor on the substrate.

3. The array substrate according to claim 2, wherein, The thin-film transistor includes: A gate pattern is disposed on the first wiring layer and connected to the gate line; A semiconductor pattern is disposed between the first wiring layer and the second wiring layer; The source pattern is disposed on the second trace layer and connected to the data line; A drain pattern is disposed on the second wiring layer, spaced apart from the source pattern, and the orthographic projection of the drain pattern on the substrate does not coincide with the orthographic projection of the first electrode on the substrate; The orthographic projection of the gate pattern on the substrate covers the orthographic projections of the semiconductor pattern and the source pattern on the substrate, and partially coincides with the orthographic projection of the drain pattern on the substrate; the orthographic projection of the clearance opening on the substrate coincides with the orthographic projections of the gate pattern, the semiconductor pattern and the source pattern on the substrate, and covers the orthographic projection of the drain pattern on the substrate.

4. The array substrate according to claim 3, wherein, The clearance opening includes: A first opening, the boundary shape of which is approximately the same as the boundary shape of the semiconductor pattern, and the orthographic projection of the first opening onto the substrate lies within the orthographic projection of the semiconductor pattern onto the substrate.

5. The array substrate according to claim 3, wherein, The second electrode layer further includes: The adapter block is located within the clearance opening and is spaced from the boundary of the clearance opening; the adapter block is electrically connected to the drain pattern and the first electrode respectively.

6. The array substrate according to claim 5, wherein, The clearance opening also includes: The second opening has a boundary shape that is approximately the same as the boundary shape of the adapter block, and the boundary of the second opening surrounds the adapter block.

7. The array substrate according to claim 6, wherein, The distance between the boundary of the adapter block and the boundary of the second opening is 6μm to 20μm.

8. The array substrate according to claim 5, wherein, The orthographic projection of the adapter block on the substrate does not coincide with the orthographic projection of the data line and the gate line on the substrate.

9. The array substrate according to claim 1, wherein, The plurality of third electrode strips located within the same dimming area include: The first sub-electrode strip is connected to the straight portion at both ends along the first direction; The second sub-electrode strip has one end connected to the straight portion along the first direction and the other end connected to the protruding portion; The third sub-electrode strip, wherein both ends of the third sub-electrode strip along the first direction are respectively connected to the protrusion; Wherein, the size of the first sub-electrode strip in the first direction is greater than the size of the second sub-electrode strip in the first direction, and the size of the second sub-electrode strip in the first direction is greater than the size of the third sub-electrode strip in the first direction.

10. The array substrate according to claim 1, wherein, The second electrode further includes a first slit located between two adjacent third electrode strips; the first electrode includes a plurality of first electrode strips spaced apart along a second direction, and a second slit located between two adjacent first electrode strips; the orthographic projections of the first slit and the second slit on the substrate overlap, and the overlapping portion of the first slit and the second slit forms a third slit, the size of the third slit in the second direction being smaller than the size of the first electrode strip in the second direction, and / or smaller than the size of the third electrode strip in the second direction.

11. The array substrate according to claim 10, wherein, Within the same dimming zone, a plurality of the first slits include: The third sub-slit, wherein both ends of the third sub-slit along the first direction are respectively connected to the straight portion; A fourth sub-slit, one end of which is connected to the straight portion along the first direction, and the other end of which is connected to the protrusion; The fifth sub-slit is connected to the protrusion at both ends along the first direction; Wherein, the size of the third sub-slit in the first direction is greater than the size of the fourth sub-slit in the first direction, and the size of the fourth sub-slit in the first direction is greater than the size of the fifth sub-slit in the first direction.

12. The array substrate according to claim 1, wherein, The first electrode includes a plurality of first electrode strips spaced apart along the second direction, and the second electrode includes a plurality of third electrode strips spaced apart along the second direction; the orthographic projections of the first electrode strips and the third electrode strips on the substrate are alternately arranged along the second direction, and a fourth slit is provided between adjacent first electrode strips and third electrode strips; the size of the fourth slit in the second direction is smaller than the size of the first electrode strips and the third electrode strips in the second direction.

13. The array substrate according to claim 1, wherein, In one of the dimming areas, the first electrode includes: A plurality of first electrode strips are spaced apart along the second direction, and the first electrode strips extend along the first direction; A second electrode strip is connected end to end, and the second electrode strip is connected to the two ends of the first electrode strip along the first direction to form a structure in which the second electrode strip surrounds the plurality of first electrode strips.

14. The array substrate according to claim 13, wherein, The second electrode strip includes: Two fourth sub-electrode strips are arranged opposite each other along the first direction, the extension direction of the fourth sub-electrode strips is parallel to the extension direction of the gate line, and there is a first gap between the orthogonal projection of the fourth sub-electrode strips and the gate line on the substrate; Two fifth sub-electrode strips are arranged opposite each other along the second direction, the extension direction of the fifth sub-electrode strips is parallel to the extension direction of the data line, and there is a second gap between the orthogonal projection of the fifth sub-electrode strips and the data line on the substrate; the first gap is less than or equal to the second gap.

15. The array substrate according to claim 14, wherein, The fourth sub-electrode strip has a serrated structure, or the fourth sub-electrode strip has a concave-convex structure.

16. The array substrate according to claim 15, wherein, The fourth sub-electrode strip has a first groove near the edge of the gate line, and the orthographic projection of the first groove on the substrate is spaced apart from the orthographic projection of the gate line on the substrate.

17. The array substrate according to any one of claims 1 to 16, wherein, The grid line includes at least one light adjustment section and a connecting section connected to the light adjustment section, wherein the width of the light adjustment section is greater than the width of the connecting section.

18. The array substrate according to claim 17, wherein, The ratio of the maximum width of the light adjustment part to the width of the connecting part is 1.5 to 4.

19. The array substrate according to claim 17, wherein, The ratio of the length of the connecting part to the length of the light adjustment part is 1.5 to 3.

20. The array substrate according to claim 17, wherein, The shape of the orthographic projection of the light-adjusting part onto the substrate is hexagonal or octagonal.

21. The array substrate according to claim 17, wherein, The grid line is a broken line, including multiple extension segments connected sequentially along the second direction; The extension section includes a plurality of light adjustment parts and a plurality of connecting parts that are alternately connected in sequence; and the two ends of the extension section are the connecting parts respectively.

22. The array substrate according to claim 17, wherein, The first electrode has a second groove on the side near the light adjustment part. The shape of the second groove is the same as the shape of the side of the light adjustment part near the first electrode, and the interval between the second groove and the light adjustment part is equal to the interval between the first electrode and the connecting part.

23. The array substrate according to claim 17, wherein, Each of the dimming areas is provided with a thin-film transistor; the orthographic projection of the light adjustment unit on the substrate does not coincide with the orthographic projection of the thin-film transistor on the substrate.

24. The array substrate according to any one of claims 1 to 16, wherein, The grid line includes multiple extension segments, which include multiple alternating first extension segments and multiple second extension segments; the interconnected first extension segments and second extension segments are symmetrically arranged about a first reference line, and the angle between the first extension segment and the second extension segment and the second direction is 53°~73°; the first reference line is parallel to the first direction.

25. The array substrate according to any one of claims 1 to 16, wherein, The data line is a zigzag line, including a plurality of third extension segments and a plurality of fourth extension segments that are alternately arranged and interconnected along the first direction; the interconnected third extension segments and fourth extension segments are symmetrically arranged about the second reference line, and the angle between the third extension segment and the fourth extension segment and the first direction is 5°~10°; the second reference line is parallel to the second direction.

26. The array substrate according to any one of claims 1 to 16, wherein, The second routing layer also includes a plurality of common voltage signal lines spaced apart along the first direction; Along the second direction, the data lines and the common voltage signal lines are arranged alternately, and adjacent data lines and common voltage signal lines are symmetrically arranged.

27. The array substrate according to claim 26, wherein, The common voltage signal line includes: The widened portion is electrically connected to the second electrode, and the orthographic projection of the widened portion on the substrate is located within the orthographic projection of the gate line on the substrate.

28. The array substrate according to any one of claims 1 to 16, wherein, The array substrate includes a display area and a peripheral area surrounding the display area; the array substrate further includes: A common voltage signal bus is located in the peripheral area and surrounds the display area; when the array substrate includes a common voltage signal line, the end of the common voltage signal line along the first direction is connected to the common voltage signal bus. A gate driving circuit is located in the peripheral region and at least on one side of the display area along the second direction, and is electrically connected to the gate line; The fan-out trace is located in the peripheral area and on one side of the display area along the first direction; the fan-out trace is electrically connected to the data line. A flip-chip film is connected to the fan-out trace; The driver chip is bonded to the flip-chip film.

29. A view control box, comprising: The array substrate as described in any one of claims 1 to 28; The array substrate includes a plurality of thin-film transistors, each of the dimming zones is provided with a thin-film transistor, and the thin-film transistor is configured to control the dimming zone of the viewing angle control box to switch between a sharing state and a privacy state; A counter substrate is disposed opposite to the array substrate and together with the array substrate forms a liquid crystal cell; The first liquid crystal layer, located within the liquid crystal cell, is configured to, under the control of the driving circuit of the array substrate, adjust the deflection direction of the liquid crystal molecules located in each dimming zone of the first liquid crystal layer, thereby controlling the light incident into each dimming zone to prevent the liquid crystal layer from being emitted in a spy state or a sharing state.

30. The viewing angle control box according to claim 29, further comprising: Multiple spacers are located within the liquid crystal cell and are configured to support the array substrate and the opposing substrate. Each spacer includes a first end face that contacts the array substrate. The orthographic projection of the first end face onto the substrate is located within the orthographic projection of the light adjustment portion onto the substrate.

31. A display device, comprising: The view control box as described in claim 29 or 30; The backlight module is disposed on the side of the viewing angle control box near the array substrate and is configured to emit light perpendicular to the viewing angle control box in a direction close to the viewing angle control box. The liquid crystal display panel is located on the side of the viewing angle control box away from the backlight module.

32. The display device according to claim 31, wherein, The liquid crystal display panel includes a plurality of sub-pixels, wherein the size of the sub-pixels is D1 in a first direction and D2 in a second direction; The array substrate includes multiple dimming areas, each dimming area having a dimension D3 in a first direction and a dimension D4 in a second direction; wherein, D3 = N × D1 + M; D4 = 0 × D2 + P; 2 ≤ N ≤ 8, and N is a positive integer; 0.1 μm ≤ M ≤ 0.8 μm; 2 ≤ 0 ≤ 0.8, and 0 is a positive integer; 0.1 μm ≤ P ≤ 0.8 μm.

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