Array substrate and touch display device

Abstract

The invention provides an array substrate and a touch display device. The array substrate comprises: a substrate comprising a plurality of pixels; a pixel electrode; the touch sensing block comprises a plurality of touch electrodes; each touch control sensing block is connected with at least one touch control signal line; the two adjacent rows of touch electrodes in each touch sensing block are connected through the first connecting line; the second connecting lines are not overlapped with the touch signal lines, and the pixel electrodes are connected with the TFTs through the second connecting lines. And the pixel structure is a Z framework pixel. Every four adjacent pixels form a repetitive unit, each repetitive unit comprises four adjacent sub-pixels arranged in two rows and two columns, pixel electrodes of two obliquely opposite sub-pixels are connected with the TFTs through second connecting lines, and touch electrodes of the other two obliquely opposite sub-pixels are connected through first connecting lines.

Description

Array substrate, touch display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a touch display device including the array substrate. Background Art

[0002] As an important tool for human-computer interaction, touch display panels are widely used in display products such as smartphones, tablets, laptops, and monitors. Among various touch display panels, capacitive touch display panels are widely used due to their advantages such as greater sensitivity and multi-touch capabilities.

[0003] Summary of the Invention

[0004] According to one aspect of the present disclosure, an array substrate is provided, comprising: a base substrate comprising a plurality of pixels arranged in an array, the plurality of pixels comprising a plurality of sub-pixels arranged in an array, each of the plurality of sub-pixels comprising a pixel electrode, a touch electrode, and a thin film transistor; a plurality of touch sensing blocks located on the base substrate and electrically insulated from one another, each touch sensing block comprising a plurality of touch electrodes, the plurality of touch electrodes of each touch sensing block being electrically connected to one another and arranged in an array; a plurality of gate lines extending along a first direction, each row of sub-pixels being associated with two of the plurality of gate lines; a plurality of gate lines extending along a second direction A touch signal line and multiple data lines, the touch signal line and the data lines are located in the same layer, each of the touch sensing blocks is electrically connected to at least one of the multiple touch signal lines, and the first direction and the second direction are arranged to intersect; a first connecting line, two adjacent rows of touch electrodes in each touch sensing block are electrically connected through the first connecting line; and a second connecting line, each of at least a portion of the multiple pixel electrodes is electrically connected to the drain of a corresponding thin film transistor through the second connecting line, and the orthographic projection of the second connecting line on the base substrate does not overlap with the orthographic projection of the touch signal line on the base substrate. The gate electrode of the thin film transistor of each sub-pixel is electrically connected to the gate line, the drain electrode of the thin film transistor of each sub-pixel is electrically connected to the pixel electrode of the sub-pixel, and the source electrode of the thin film transistor of each sub-pixel is electrically connected to the data line. Every two adjacent sub-pixels in the same row of sub-pixels constitute a unit group. The source electrode of the thin film transistor of each unit group is electrically connected to the same data line, the gate electrode of the thin film transistor of each unit group is electrically connected to a different gate line, and the source electrode of the thin film transistor of two adjacent sub-pixels in the same column of sub-pixels is electrically connected to a different data line. Every four adjacent pixels in the plurality of pixels constitute a repeating unit. Each repeating unit includes four adjacent sub-pixels. The four adjacent sub-pixels are arranged in two rows and two columns. The pixel electrodes of two sub-pixels in different rows and diagonally opposite to each other among the four adjacent sub-pixels are respectively electrically connected to the drain electrode of a corresponding thin film transistor via the second connecting line. The touch electrodes of the other two sub-pixels in different rows and diagonally opposite to each other among the four adjacent sub-pixels are electrically connected via the first connecting line.

[0005] In some embodiments, the array substrate further includes a third connecting line, each of a portion of the plurality of pixel electrodes is electrically connected to the drain of a corresponding thin film transistor through the second connecting line, and each of the remaining plurality of pixel electrodes is electrically connected to the drain of a corresponding thin film transistor through the third connecting line, and the orthographic projection of the third connecting line on the base substrate partially overlaps with the orthographic projection of the touch signal line on the base substrate.

[0006] In some embodiments, an orthographic projection of the third connecting line on the substrate does not overlap with an orthographic projection of the first connecting line on the substrate.

[0007] In some embodiments, the overlapping portion of the orthographic projection of the third connection line on the base substrate and the orthographic projection of the touch signal line on the base substrate constitutes a first overlapping region, and areas of all first overlapping regions are equal to each other.

[0008] In some embodiments, the array substrate further includes a plurality of common connection lines extending along the first direction. Each of the plurality of common connection lines is arranged between two adjacent rows of sub-pixels, and touch electrodes in the same row within each touch sensing block are electrically connected to each other via the common connection line. Each common connection line is disconnected at a region between two adjacent touch sensing blocks.

[0009] In some embodiments, a data line is provided at the interval area between any two adjacent touch sensing blocks along the first direction, the disconnected portion of the common connection line at the interval area is located on the first side of the data line, the continuous portion of the common connection line includes a first sub-portion, a second sub-portion and a third sub-portion connected in sequence, the first sub-portion is located on the second side of the data line, the third sub-portion is located on the first side of the data line, the second sub-portion is located between the first sub-portion and the third sub-portion, and the orthographic projection of the second sub-portion on the base substrate falls within the orthographic projection of the data line on the base substrate.

[0010] In some embodiments, a length of the third subsection along the first direction is greater than or equal to a first threshold.

[0011] In some embodiments, the array substrate further includes a fourth connecting line, wherein a first end of the fourth connecting line is electrically connected to a touch electrode of one of two touch sensing blocks arbitrarily adjacent along the second direction, and a second end of the fourth connecting line is disconnected from a touch electrode of the other of the two touch sensing blocks arbitrarily adjacent along the second direction, so that the two touch sensing blocks arbitrarily adjacent along the second direction are electrically insulated from each other.

[0012] In some embodiments, the orthographic projection of the fourth connecting line on the substrate spans the orthographic projections of two gate lines located between any two adjacent touch sensing blocks along the second direction on the substrate, and the distance by which the second end of the fourth connecting line extends beyond the gate line closest to the second end of the two gate lines is greater than or equal to a second threshold.

[0013] In some embodiments, the orthographic projection of the first connecting line on the base substrate partially overlaps with the orthographic projection of the touch signal line on the base substrate, and an extension direction of the first connecting line at the overlap is perpendicular to an extension direction of the touch signal line at the overlap.

[0014] In some embodiments, each touch sensing block is electrically connected to at least one of the plurality of touch signal lines via a via, and an orthographic projection of the via on the base substrate does not overlap with an orthographic projection of the first connection line on the base substrate.

[0015] In some embodiments, an orthographic projection of the first connection line on the base substrate partially overlaps with an orthographic projection of the touch signal line on the base substrate, and one first connection line is provided between two adjacent rows of sub-pixels in each repeating unit.

[0016] In some embodiments, each repeating unit is further provided with a compensation line, the orthographic projection of the compensation line on the substrate partially overlaps with the orthographic projection of the touch signal line on the substrate, and the touch signal line overlapping with the compensation line and the touch signal line overlapping with the first connecting line in each repeating unit are two different touch signal lines.

[0017] In some embodiments, the compensation line includes a sub-portion extending along the first direction, the orthographic projection of the sub-portion on the base substrate partially overlaps with the orthographic projection of the touch signal line on the base substrate, and both opposite ends of the sub-portion in the first direction extend beyond the touch signal line.

[0018] In some embodiments, an orthographic projection of the compensation line on the base substrate does not overlap with an orthographic projection of the gate line and the common connection line on the base substrate.

[0019] In some embodiments, the line width of the compensation line is equal to the line width of the first connection line.

[0020] In some embodiments, the overlapping portion of the orthographic projection of the compensation line on the base substrate and the orthographic projection of the touch signal line on the base substrate constitutes a second overlapping region, and areas of all the second overlapping regions are equal to each other.

[0021] In some embodiments, the touch signal line has a width greater than that of the data line.

[0022] In some embodiments, the touch signal line includes a first portion and a second portion, and a line width of the first portion is smaller than a line width of the second portion.

[0023] In some embodiments, the array substrate further includes a light shielding layer located on a side of the touch signal line and the data line away from the base substrate. The light shielding layer includes a first light shielding portion and a second light shielding portion, the orthographic projection of the data line on the base substrate falls within the orthographic projection of the first light shielding portion on the base substrate, the orthographic projection of the touch signal line on the base substrate falls within the orthographic projection of the second light shielding portion on the base substrate, the width of the first light shielding portion along the first direction is a first width, the width of the second light shielding portion along the first direction is a second width, the width of each sub-pixel along the first direction is a third width, and the first width, the second width, and the third width satisfy the following condition: the ratio of the absolute value of the difference between the first width and the second width to twice the third width is less than or equal to 5%.

[0024] In some embodiments, the orthographic projection of the data line on the base substrate does not overlap with the orthographic projection of the touch electrode on the base substrate, and the orthographic projection of the touch signal line on the base substrate does not overlap with the orthographic projection of the touch electrode on the base substrate.

[0025] In some embodiments, a data line is arranged for every two columns of sub-pixels, and each of at least some of the multiple data lines is arranged between two adjacent columns of sub-pixels; and a touch signal line is arranged for every two columns of sub-pixels, and each touch signal line is arranged between two adjacent columns of sub-pixels and located between two adjacent data lines.

[0026] In some embodiments, the orthographic projection of the touch electrode in each sub-pixel on the substrate at least partially overlaps with the orthographic projection of the pixel electrode in the sub-pixel on the substrate. For each data line and two columns of sub-pixels located on both sides of the data line, the distance between the orthographic projection of the touch electrode in each of the two columns of sub-pixels on the substrate and the orthographic projection of the data line on the substrate is a first distance, and the distance between the orthographic projection of the pixel electrode in each of the two columns of sub-pixels on the substrate and the orthographic projection of the data line on the substrate is a second distance, wherein the second distance is greater than the first distance, and the difference between the second distance and the first distance is greater than or equal to a third threshold.

[0027] In some embodiments, for each touch signal line and the two columns of sub-pixels located on both sides of the touch signal line, the distance between the orthographic projection of the touch electrode in each column of sub-pixels in the two columns of sub-pixels on the substrate and the orthographic projection of the touch signal line on the substrate is a third distance, and the distance between the orthographic projection of the pixel electrode in each column of sub-pixels in the two columns of sub-pixels on the substrate and the orthographic projection of the touch signal line on the substrate is a fourth distance, and the fourth distance is greater than the third distance and the difference between the fourth distance and the third distance is greater than or equal to the third threshold.

[0028] In some embodiments, the ratio of the number of data lines to the number of touch signal lines is 1:2, one data line is arranged for every two columns of sub-pixels, two touch signal lines are arranged for every two columns of sub-pixels, and the two touch signal lines are arranged between two adjacent columns of sub-pixels.

[0029] In some embodiments, the touch electrode is located on the base substrate, the gate line is located on the side of the touch electrode away from the base substrate, the data line and the touch signal line are located on the side of the gate line away from the base substrate, and the pixel electrode and the first connecting line are located on the same layer and both are located on the side of the data line away from the base substrate.

[0030] In some embodiments, the pixel electrode is located on the base substrate, the gate line is located on the side of the pixel electrode away from the base substrate, the data line and the touch signal line are located on the side of the gate line away from the base substrate, and the touch electrode and the first connecting line are located on the same layer and both are located on the side of the data line away from the base substrate.

[0031] In some embodiments, an extension direction of the first connection line is different from an extension direction of the touch signal line, and an orthographic projection of the first connection line on the base substrate overlaps at most a portion with an orthographic projection of the touch signal line on the base substrate.

[0032] In some embodiments, each touch sensing block is electrically connected to at least one of the plurality of touch signal lines via a via, and an orthographic projection of the via on the substrate is located between orthographic projections of two gate lines between two adjacent rows of sub-pixels on the substrate.

[0033] In some embodiments, the first connection line and the touch signal line extend in the same direction, and an orthographic projection of the first connection line on the base substrate falls within an orthographic projection of the touch signal line on the base substrate.

[0034] In some embodiments, the array substrate further includes a liquid crystal layer, the touch electrode and the pixel electrode are located on the same side of the liquid crystal layer, and the touch electrode and the pixel electrode are made of indium tin oxide.

[0035] In some embodiments, each pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged in sequence along the first direction, and the four adjacent pixels of each repeating unit are arranged into two rows and two columns and include a first pixel, a second pixel, a third pixel, and a fourth pixel, the first pixel and the second pixel are located in the same row and the first pixel and the third pixel are located in the same column, the third pixel and the fourth pixel are located in the same row and the second pixel and the fourth pixel are located in the same column. The sources of the thin film transistors of the first subpixel and the second subpixel of the first pixel are electrically connected to the first data line among the multiple data lines, the sources of the thin film transistors of the third subpixel of the first pixel and the first subpixel of the second pixel are electrically connected to the second data line among the multiple data lines, the sources of the thin film transistors of the second subpixel and the third subpixel of the second pixel are electrically connected to the third data line among the multiple data lines, the sources of the thin film transistors of the first subpixel and the second subpixel of the third pixel are electrically connected to the second data line, the sources of the thin film transistors of the third subpixel of the third pixel and the first subpixel of the fourth pixel are electrically connected to the third data line, and the sources of the thin film transistors of the second subpixel and the third subpixel of the fourth pixel are electrically connected to the fourth data line among the multiple data lines.

[0036] In some embodiments, the gates of the thin film transistors of all first sub-pixels in the same row of pixels are electrically connected to the first gate line of the two gate lines, the gates of the thin film transistors of all second sub-pixels in the same row of pixels are electrically connected to the second gate line of the two gate lines, and the gates of the thin film transistors of the third sub-pixels of two adjacent pixels in the same row of pixels are electrically connected to the first gate line and the second gate line, respectively.

[0037] According to another aspect of the present disclosure, a touch display device is provided. The touch display device includes the array substrate described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly describe the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0039] FIG1 is a schematic diagram showing an arrangement of a pixel structure of an array substrate according to an embodiment of the present disclosure;

[0040] FIG2 shows an arrangement of touch sensing blocks according to an embodiment of the present disclosure;

[0041] FIG3 shows a partial enlarged view of region I in FIG2 ;

[0042] FIG4 is a schematic plan view showing a partial structure of an array substrate according to an embodiment of the present disclosure;

[0043] FIG5 shows a partial enlarged view of region II of FIG4 ;

[0044] FIG6 shows a partial enlarged view of region III of FIG4 ;

[0045] FIG7 shows a partial enlarged view of region IV of FIG4 ;

[0046] FIG8 shows a structural design of adjacent touch sensing blocks at a disconnection point according to an embodiment of the present disclosure;

[0047] FIG9 is a schematic diagram showing the arrangement of a partial structure of an array substrate according to an embodiment of the present disclosure;

[0048] FIG10 shows a partial enlarged view of region V in FIG4 ;

[0049] FIG11 shows a partial enlarged view of a touch sensing block in FIG2 ;

[0050] FIG12 shows a schematic cross-sectional view taken along line AA′ of FIG4 ;

[0051] FIG13 shows a schematic cross-sectional view taken along line BB′ of FIG4 ;

[0052] FIG14 is a plan view showing a partial structure of an array substrate according to another embodiment of the present disclosure;

[0053] FIG15 shows a partial enlarged view of region VI of FIG14 ;

[0054] FIG16 shows a partial enlarged view of region VII of FIG14; and

[0055] FIG17 shows a block diagram of a touch display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present disclosure.

[0057] Touch display devices have a more humane interaction mode, which can greatly improve the user's operating efficiency and comfort. Therefore, they have become one of the mainstream displays in the display field.

[0058] FIG1 is a schematic diagram of the arrangement of the pixel structure of the array substrate 100 provided according to an embodiment of the present disclosure, FIG2 is a schematic diagram of the arrangement of multiple touch sensing blocks of the array substrate 100, FIG3 is a partial enlarged view of the area I circled by the dotted rectangular frame in FIG2, FIG4 is a planar schematic diagram of the partial structure of the array substrate 100, and FIG5 is a partial enlarged view of the area II circled by the dotted rectangular frame in FIG4. As shown in FIG1 to FIG5, the array substrate 100 includes: a base substrate 101, which includes a plurality of pixels arranged in an array, each pixel including a first sub-pixel SP1, a second sub-pixel SP2 and a third sub-pixel SP3 arranged in sequence along a first direction D1, the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 can be configured to emit light of different colors. In one example, the first sub-pixel SP1 can be configured to emit red light, the second sub-pixel SP2 can be configured to emit green light, and the third sub-pixel SP3 can be configured to emit red light. blue light; a plurality of pixel electrodes 102 located on the base substrate 101, wherein one pixel electrode 102 is disposed in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3; a plurality of touch sensing blocks 103 located on the base substrate 101 and electrically insulated from each other, wherein each touch sensing block 103 includes a plurality of touch electrodes 104 electrically connected to each other and arranged in a plurality of rows, wherein one touch electrode 104 ...; a plurality of touch sensing blocks 103 located along a direction intersecting the first direction D1 a plurality of touch signal lines TX extending in the second direction D2 of the cross, each touch sensing block 103 is electrically connected to at least one of the plurality of touch signal lines TX; a plurality of thin film transistors 111 located on the base substrate 101, each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 includes at least one thin film transistor 111; a plurality of data lines Data extending along the second direction D2, the touch signal lines TX and the data lines Data are located in the same layer; a plurality of gate lines Gate extending along the first direction D1, each row of sub-pixels Associated with two gate lines Gate among the multiple gate lines Gate; a first connecting line 107, two adjacent rows of touch electrodes 104 in each touch sensing block 103 are electrically connected through the first connecting line 107; and a second connecting line 109, each of at least a portion of the multiple pixel electrodes 102 is electrically connected to the drain 111B of one of the multiple thin film transistors 111 through the second connecting line 109, and the orthographic projection of the second connecting line 109 on the base substrate 101 does not overlap with the orthographic projection of the touch signal line TX on the base substrate 101.

[0059] The gate electrode 111A of the thin-film transistor 111 of each sub-pixel is electrically connected to the gate line Gate, the drain electrode 111B of the thin-film transistor 111 of each sub-pixel is electrically connected to the pixel electrode 102 of the sub-pixel, and the source electrode 111C of the thin-film transistor 111 of each sub-pixel is electrically connected to the data line Data. Every two adjacent sub-pixels in the same row of sub-pixels constitute a unit group. The source electrode 111C of the thin-film transistor 111 of each unit group is electrically connected to the same data line Data, the gate electrode 111A of the thin-film transistor 111 of each unit group is electrically connected to a different gate line Gate, and the source electrode 111C of the thin-film transistor 111 of two adjacent sub-pixels in the same column of sub-pixels is electrically connected to a different data line Data. This pixel arrangement of the array substrate 100 can be referred to as a Z-architecture pixel. With the Z-architecture pixel, even if there is a difference in the charging status of adjacent data lines Data, there will be no display difference between adjacent pixel columns, thereby avoiding undesirable phenomena such as vertical stripes or shaking head lines.

[0060] Every four adjacent pixels in a plurality of pixels constitute a repeating unit, and each repeating unit includes four adjacent sub-pixels, which are arranged in two rows and two columns. The pixel electrodes 102 of two sub-pixels located in different rows and diagonally opposite each other among the four adjacent sub-pixels are respectively electrically connected to the drain electrode 111B of a corresponding thin-film transistor 111 via a second connecting line 109, and the touch electrodes 104 of another two sub-pixels located in different rows and diagonally opposite each other among the four adjacent sub-pixels are electrically connected via a first connecting line 107. For example, FIG5 shows a partial structure of four adjacent sub-pixels within a repeating unit. These four sub-pixels are the sub-pixel located in the i-th row and j-th column, the sub-pixel located in the i-th row and j+1-th column, the sub-pixel located in the i+1-th row and j+1-th column, and the sub-pixel located in the i+1-th row and j+1-th column, where i and j are positive integers greater than or equal to 1. As shown in Figure 5, the sub-pixel located at the i-th row and j+1-th column and the sub-pixel located at the i+1-th row and j-th column are located in different rows and the two sub-pixels are obliquely opposite to each other. The pixel electrodes 102 of the two sub-pixels are respectively electrically connected to the drain 111B of the corresponding thin film transistor 111 through the second connecting line 109, and the orthographic projection of the second connecting line 109 on the base substrate 101 does not overlap with the orthographic projection of the touch signal line TX1 on the base substrate 101; the sub-pixel located at the i-th row and j-th column and the sub-pixel located at the i+1-th row and j+1-th column are located in different rows and the two sub-pixels are obliquely opposite to each other. The touch electrodes 104 of the two sub-pixels are electrically connected to each other through the first connecting line 107, and the orthographic projection of the first connecting line 107 on the base substrate 101 partially overlaps with the orthographic projection of the touch signal line TX1 on the base substrate 101.

[0061] In the array substrate 100, the touch electrodes 104 of two adjacent rows of sub-pixels within each touch sensing block 103 are connected via a first connecting line 107. At least a portion of the pixel electrodes 102 are connected to the drain electrode 111B of the thin-film transistor 111 via a second connecting line 109. Since the second connecting line 109 does not cross the touch signal line TX, the connection via the second connecting line 109 can be referred to as a "short connection." Since the orthographic projection of the first connecting line 107 on the base substrate 101 partially overlaps with the orthographic projection of the touch signal line TX on the base substrate 101, i.e., the first connecting line 107 needs to cross the touch signal line TX, while the orthographic projection of the second connecting line 109 on the base substrate 101 does not overlap with the orthographic projection of the touch signal line TX on the base substrate 101, i.e., the second connecting line 109 does not need to cross the touch signal line TX. Therefore, the first connecting line 107 can be arranged in the position of the second connecting line 109, thereby effectively utilizing wiring space and avoiding undesirable coupling caused by wiring clutter.

[0062] It should be noted that, in this document, the terms "source 111C of the thin film transistor 111" and "drain 111B of the thin film transistor 111" can be used interchangeably, that is, the source 111C of the thin film transistor 111 can also be referred to as the drain 111B of the thin film transistor 111, and the drain 111B of the thin film transistor 111 can also be referred to as the source 111C of the thin film transistor 111. It should be pointed out that a sub-pixel is usually an area surrounded by a gate line Gate and a data line Data. The phrase "each sub-pixel includes at least one thin film transistor 111" means that each sub-pixel is configured with at least one thin film transistor 111 (for example, the pixel electrode 102 of each sub-pixel is electrically connected to the drain 111B of the thin film transistor 111), but this does not limit the thin film transistor 111 to be located within the area of ​​the sub-pixel. For example, due to different connection methods of the thin film transistor 111, the thin film transistor 111 of some sub-pixels may not be completely located within the area of ​​the sub-pixel. In addition, in this document, terms such as "A and B are located in the same layer" mean that A and B are made of the same material and through the same process, but do not necessarily require that A and B have exactly the same thickness or height. The phrase "each row of sub-pixels is associated with two gate lines Gate among the multiple gate lines Gate" means that the gates 111A of the thin-film transistors 111 of the same row of sub-pixels are connected to two different gate lines Gate.

[0063] In some embodiments, the gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the first sub-pixel SP1 in the same row of pixels is electrically connected to the first gate line of the two gate lines Gate, the gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the second sub-pixel SP2 in the same row of pixels is electrically connected to the second gate line of the two gate lines Gate, and the gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the third sub-pixel SP3 of two adjacent pixels in the same row of pixels is electrically connected to the first gate line and the second gate line respectively. Exemplarily, Figure 1 shows three rows of pixels, the first row of pixels is associated with the first gate line Gate1 and the second gate line Gate2, the first row of pixels includes adjacent pixels P1 and pixel P2, the gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the first sub-pixel SP1 of pixels P1 and P2 is electrically connected to the first gate line Gate1, the gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the second sub-pixel SP2 of pixels P1 and P2 is electrically connected to the second gate line Gate2, the gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the third sub-pixel SP3 of pixel P1 is electrically connected to the second gate line Gate2, and the gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the third sub-pixel SP3 of pixel P2 is electrically connected to the first gate line Gate1. The second row of pixels is associated with the first gate line Gate3 and the second gate line Gate4. The second row of pixels includes adjacent pixels P3 and P4. The gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the first sub-pixel SP1 of pixels P3 and P4 is electrically connected to the first gate line Gate3, the gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the second sub-pixel SP2 of pixels P3 and P4 is electrically connected to the second gate line Gate4, the gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the third sub-pixel SP3 of pixel P3 is electrically connected to the second gate line Gate4, and the gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the third sub-pixel SP3 of pixel P4 is electrically connected to the first gate line Gate3.The third row of pixels is associated with the first gate line Gate5 and the second gate line Gate6. The third row of pixels includes adjacent pixels P5 and P6. The gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the first sub-pixel SP1 of pixels P5 and P6 is electrically connected to the first gate line Gate5, the gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the second sub-pixel SP2 of pixels P5 and P6 is electrically connected to the second gate line Gate6, the gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the third sub-pixel SP3 of pixel P5 is electrically connected to the second gate line Gate6, and the gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the third sub-pixel SP3 of pixel P6 is electrically connected to the first gate line Gate5.

[0064] Among the multiple pixels of the array substrate 100, every four adjacent pixels form a repeating unit. The four adjacent pixels are arranged in two rows and two columns and include a first pixel, a second pixel, a third pixel, and a fourth pixel. For example, in FIG1 , the four adjacent pixels P1, P2, P3, and P4 form a repeating unit. The four pixels P1, P2, P3, and P4 are arranged in two rows and two columns. Pixel P1 can be denoted as the first pixel P1, pixel P2 can be denoted as the second pixel P2, pixel P3 can be denoted as the third pixel P3, and pixel P4 can be denoted as the fourth pixel P4. The first pixel P1 and the second pixel P2 are located in the same row, and the first pixel P1 and the third pixel P3 are located in the same column. The third pixel P3 and the fourth pixel P4 are located in the same row, and the second pixel P2 and the fourth pixel P4 are located in the same column. The source 111C of the thin film transistor 111 electrically connected to the pixel electrodes 102 of the first sub-pixel SP1 and the second sub-pixel SP2 of the first pixel P1 is electrically connected to the first data line Data1 among the plurality of data lines Data, the source 111C of the thin film transistor 111 electrically connected to the pixel electrodes 102 of the third sub-pixel SP3 of the first pixel P1 and the first sub-pixel SP1 of the second pixel P2 is electrically connected to the second data line Data2 among the plurality of data lines Data, and the source 111C of the thin film transistor 111 electrically connected to the pixel electrodes 102 of the second sub-pixel SP2 and the third sub-pixel SP3 of the second pixel P2 is electrically connected to the third data line Data among the plurality of data lines Data. The thin film transistor 111 is electrically connected to the pixel electrode 102 of the first sub-pixel SP1 and the second sub-pixel SP2 of the third pixel P3, and the source 111C of the thin film transistor 111 is electrically connected to the second data line Data3. The source 111C of the thin film transistor 111 is electrically connected to the pixel electrode 102 of the third sub-pixel SP3 of the third pixel P3 and the first sub-pixel SP1 of the fourth pixel P4 is electrically connected to the third data line Data3, and the source 111C of the thin film transistor 111 is electrically connected to the pixel electrode 102 of the second sub-pixel SP2 and the third sub-pixel SP3 of the fourth pixel P4 is electrically connected to the fourth data line Data4 among the multiple data lines Data.

[0065] It should be noted that FIG1 illustrates, as an example, a Z-architecture pixel arrangement of the array substrate 100. However, this does not limit the array substrate 100 to adopting only this pixel arrangement. The array substrate 100 can also adopt other Z-architecture pixel arrangements. With Z-architecture pixels, even if adjacent data lines have different charging conditions, adjacent pixel columns will not produce display differences, thereby avoiding undesirable phenomena such as vertical stripes and head-shaking lines.

[0066] The array substrate 100 can be an array substrate for a touch display device, and the touch principle of the touch display device can be roughly described in conjunction with Figure 2. The touch display device can be an embedded touch display device using self-capacitive touch technology. As shown in Figure 2, the array substrate 100 includes a plurality of touch sensing blocks 103 (as self-capacitive electrodes) arranged in an array and touch signal lines TX electrically connected to the touch sensing blocks 103 respectively. The touch signal lines TX electrically connect the touch sensing blocks 103 to the touch control circuit 105. When a touch is performed, a touching object (for example, a human finger) touches the touch display device, and the capacitance of the touch sensing block 103 at the touch point changes. The touch control circuit 105 determines the touch position by detecting the change in the self-capacitance of the touch sensing block 103.

[0067] In some embodiments, each pixel electrode 102 of the array substrate 100 is electrically connected to the drain electrode 111B of a corresponding thin film transistor 111 via a second connection line 109, that is, each pixel electrode 102 is electrically connected to the drain electrode 111B of the thin film transistor 111 in a short connection manner. In some alternative embodiments, some pixel electrodes 102 of the array substrate 100 are electrically connected to the drain electrode 111B of a corresponding thin film transistor 111 via a second connection line 109, and other pixel electrodes 102 of the array substrate 102 are electrically connected to the drain electrode 111B of a corresponding thin film transistor 111 via another connection line.

[0068] Figure 6 is a partial enlarged view of the area III circled by the dotted rectangular frame in Figure 4. Referring to Figures 4 and 6, the array substrate 100 may further include a third connecting line 110, wherein some pixel electrodes 102 are electrically connected to the drain 111B of a corresponding thin film transistor 111 through the second connecting line 109, and the remaining pixel electrodes 102 are electrically connected to the drain 111B of a corresponding thin film transistor 111 through the third connecting line 110. The orthographic projection of the third connecting line 110 on the base substrate 101 partially overlaps with the orthographic projection of the touch signal line TX (shown as the touch signal line TX3 in Figure 6) on the base substrate 101. Since the third connecting line 110 needs to cross the touch signal line TX, the way in which the pixel electrode 102 is connected to the drain 111B of the thin film transistor 111 through the third connecting line 110 can be called a "long connection". In other words, in this alternative embodiment, a portion of the pixel electrode 102 is electrically connected to the drain electrode 111B of the thin-film transistor 111 via a short connection, and a portion of the pixel electrode 102 is electrically connected to the drain electrode 111B of the thin-film transistor 111 via a long connection. The length of the third connecting line 110 is greater than the length of the second connecting line 109. The specific values ​​of the lengths of the third connecting line 110 and the second connecting line 109 can be determined based on the specific design of the array substrate 100. In some embodiments, the first connecting line 107, the second connecting line 109, the third connecting line 110, and the pixel electrode 102 can be located on the same layer. During the manufacturing process, the four can be formed using the same material and the same mask. As shown in Figures 4 and 6, the orthographic projection of the third connecting line 110 on the base substrate 101 does not overlap with the orthographic projection of the first connecting line 107 on the base substrate 101. A first connection line 107 is provided between two adjacent rows of sub-pixels in each repeating unit. Since the first connection line 107 crosses the touch signal line TX, and the third connection line 110 located on the same layer as the first connection line 107 also crosses the touch signal line TX, the first connection line 107 is not provided where the third connection line 110 is arranged. This prevents the first and third connection lines 107, 110, from overlapping, which would lead to crowded and chaotic wiring space and the generation of undesirable parasitic capacitance. Since the second connection line 109 does not need to cross the touch signal line TX, the first connection line 107 can be provided where the second connection line 109 is arranged, while the first connection line 107 is not provided where the third connection line 110 is arranged.

[0069] In some embodiments, as shown in FIG6 , the overlapping portion of the orthographic projection of each third connection line 110 on the base substrate 101 and the orthographic projection of the touch signal line TX3 on the base substrate 101 constitutes a first overlapping region R1, and the areas of all first overlapping regions R1 are equal. This ensures that the overlapping areas of all third connection lines 110 and the touch signal lines TX are equal.

[0070] In some embodiments, a data line Data is arranged between every two columns of sub-pixels, and at least some of the multiple data lines Data are arranged between two adjacent columns of sub-pixels. A touch signal line TX is arranged between every two columns of sub-pixels, and each touch signal line TX is arranged between two adjacent columns of sub-pixels and located between two adjacent data lines Data. As shown in FIG1 , in addition to data lines Data1 and Data4, data lines Data2 and Data3 are arranged between two adjacent columns of sub-pixels, touch signal line TX1 is arranged between two adjacent columns of sub-pixels and located between data lines Data1 and Data2, touch signal line TX2 is arranged between two adjacent columns of sub-pixels and located between data lines Data2 and Data3, and touch signal line TX3 is arranged between two adjacent columns of sub-pixels and located between data lines Data3 and Data4. In this embodiment, the number of data lines Data and touch signal lines TX in the array substrate 100 is equal, i.e., the two are arranged in a 1:1 ratio. In the array substrate 100, a data line Data is arranged every two columns of sub-pixels. Compared with the conventional technology in which a data line Data is arranged in each column of sub-pixels, the wiring method of the array substrate 100 reduces the number of data lines by half. The remaining space can be used to arrange the touch signal line TX, thereby not increasing the total number of signal lines and not reducing the aperture ratio.

[0071] In alternative embodiments, the ratio of the number of data lines Data to the number of touch signal lines TX on the array substrate 100 may not be 1:1. Instead, the ratio may be 1:2, i.e., one data line Data is arranged for every two columns of sub-pixels, and two touch signal lines TX are arranged for every two columns of sub-pixels. The two touch signal lines TX are adjacent to each other and arranged between two adjacent columns of sub-pixels. Since large-scale touch display panels generally require more touch electrodes 104, this wiring method is particularly suitable for large-scale touch display panels, such as large-scale touch monitors or televisions larger than 55 inches.

[0072] The array substrate 100 can be used in an In-Cell touch display panel. On-Cell touch display panels place touch electrodes outside the display panel, while In-Cell touch display panels place touch electrodes inside the display panel. Compared to On-Cell touch display panels, In-Cell touch display panels offer higher integration and are thinner and lighter, offering greater advantages in terms of cost and stability.

[0073] In some embodiments, the array substrate 100 may further include a liquid crystal layer (not shown in the figure), the touch electrode 104 and the pixel electrode 102 are located on the same side of the liquid crystal layer, the pixel electrode 102 may be an electrode with a slit, and the materials of the touch electrode 104 and the pixel electrode 102 are both indium tin oxide (ITO). In other words, the array substrate 100 is a FIC (Full In Cell) touch process based on advanced super-dimensional field switching (Advanced Super Dimension Switch, ADS) technology. ADS technology can overcome the low light transmittance problem of conventional in-plane switching (IPS) technology, and has advantages such as higher light transmittance efficiency, hard screen, ultra-wide viewing angle, ultra-high color expression, and ultra-high-speed motion picture processing. Therefore, it is more suitable for application in larger-sized In Cell touch display products.

[0074] Figure 7 is a partial enlarged view of area IV, outlined by the dashed rectangle in Figure 4 . As shown in Figure 7 , in some embodiments, the orthographic projection of the first connection line 107 on the base substrate 101 partially overlaps with the orthographic projection of the touch signal line TX3 on the base substrate 101, and the direction of extension of the first connection line 107 at the overlap is perpendicular to the direction of extension of the touch signal line TX3 at the overlap. For example, the first connection line 107 extends along a first direction D1 at the overlap, and the touch signal line TX3 extends along a second direction D2 at the overlap, with the first direction D1 and the second direction D2 being perpendicular to each other. The first connection line 107 and the touch signal line TX3 are routed perpendicularly to each other, reducing the overlap capacitance between the first connection line 107 and the touch signal line TX3.

[0075] Referring to Figure 3, the array substrate 100 may further include a plurality of common connection lines 106 extending along the first direction D1, each common connection line 106 being arranged between two adjacent rows of sub-pixels and located on one side of any one of two adjacent gate lines Gate. In some embodiments, the common connection line 106 and the gate line Gate are located on the same layer. The touch electrodes 104 located in the same row within each touch sensing block 103 are electrically connected to each other via the common connection line 106, and each common connection line 106 is disconnected at the spacing area S between two adjacent touch sensing blocks 103. Each common connection line 106 is electrically connected to the touch electrodes 104 of a row, but since the touch electrodes 104 of the array substrate 100 are time-division multiplexed, the touch sensing blocks 103 need to be independent of each other during the touch phase to achieve position detection. Therefore, each common connection line 106 is not continuous within the array substrate 100 and needs to be disconnected at the spacing area S between adjacent touch sensing blocks 103. The common connection line 106 electrically connects the touch electrodes 104 of a row of sub-pixels within each touch sensing block 103, and the touch electrodes 104 of two adjacent rows of sub-pixels within each touch sensing block 103 are electrically connected via the first connection line 107. In this way, the touch electrodes 104 within each touch sensing block 103 can form an electrode network, which is beneficial to improving the uniformity of the common voltage within the touch sensing block 103.

[0076] In this array substrate 100, the touch electrodes 104 are time-multiplexed. During the display phase, the touch electrodes 104 serve as common electrodes; during the touch scanning phase, the touch electrodes 104 serve as touch sensing electrodes. Therefore, in the array substrate 100, the touch sensing blocks 103 need to be designed as multiple, separate and electrically insulated blocks to meet the requirements of touch position detection. Each touch sensing block 103 is connected to the touch control circuit 105 via at least one touch signal line TX, so that the touch control circuit 105 can locate the coordinates where the touch occurs. In some embodiments, the shape of each touch sensing block 103 can be approximately square, and the side length of each touch sensing block 103 can be between 5 mm and 15 mm, depending on the panel size and application scenario. The better the touch performance, the smaller the area of ​​each touch sensing block 103. The smaller the area of ​​the touch sensing block 103, the more touch sensing blocks 103 are required. Based on this principle, and taking into account both performance and cost, for medium and large-sized touch display products (such as TVs), one touch signal line TX can be designed for every two sub-pixels in display products of 55 inches 4K and below, and two touch signal lines TX can be designed for each sub-pixel in display products of 55 inches 4K and above.

[0077] 8 shows a disconnection method for any four adjacent touch sensing blocks 103. The four touch sensing blocks 103 are arranged in two rows and two columns, and the four touch sensing blocks 103 are independent and insulated from each other.

[0078] The disconnection between two adjacent touch sensing blocks 103 in the first direction D1 is achieved by disconnecting the common connection line 106. Specifically, a data line Data is provided in a space S between two adjacent touch sensing blocks 103 in the first direction D1. A disconnected portion 106A of the common connection line 106 in the space S is located on a first side of the data line Data, which is, for example, the right side of the data line Data in FIG8 . The continuous portion of the common connection line 106 includes a first sub-portion 1061, a second sub-portion 1062, and a third sub-portion 1063, which are sequentially connected. The first sub-portion 1061 is located on a second side of the data line Data, which is, for example, the left side of the data line Data in FIG8 . The third sub-portion 1063 is located on the first side of the data line Data. The second sub-portion 1062 is located between the first sub-portion 1061 and the third sub-portion 1063. The orthographic projection of the second sub-portion 1062 on the base substrate 101 falls within the orthographic projection of the data line Data on the base substrate 101. As shown in Figure 8, the two boundaries of the second sub-portion 1062 along the first direction D1 overlap with the two boundaries of the data line Data along the first direction D1. In some embodiments, the length L1 of the third sub-portion 1063 along the first direction D1 is greater than or equal to a first threshold value. The first threshold value is, for example, the alignment deviation between the metal layer where the common connection line 106 and the metal layer where the data line Data are located during the manufacturing stage. By ensuring that the third sub-portion 1063 of the common connection line 106 exceeds the first threshold value of the data line Data, even if the common connection line 106 and the data line Data are misaligned during the manufacturing process, the common connection line 106 and the data line Data can be ensured to overlap. The spacing between the disconnected portions 106A of the common connection line 106 in the first direction D1 is generally required to be greater than or equal to d, where d is the minimum resolution of the exposure machine.

[0079] The disconnection between two adjacent touch sensing blocks 103 in the second direction D2 is achieved by disconnecting the fourth connecting line 114. Specifically, as shown in FIG8 , the array substrate 100 further includes a fourth connecting line 114. A first end 1141 of the fourth connecting line 114 is electrically connected to the touch electrode 104 of one of the two touch sensing blocks 103 adjacent to each other in the second direction D2, and a second end 1142 of the fourth connecting line 114 is disconnected from the touch electrode 104 of the other of the two touch sensing blocks 103 adjacent to each other in the second direction D2. This electrically insulates the two touch sensing blocks 103 adjacent to each other in the second direction D2, facilitating accurate detection of touch positions.

[0080] As shown in FIG8 , the orthographic projection of the fourth connecting line 114 on the base substrate 101 spans the orthographic projections on the base substrate 101 of two gate lines Gate located between two adjacent touch sensing blocks 103 along the second direction D2, and the second end 1142 of the fourth connecting line 114 extends beyond the gate line closest to the second end 1142 of the two gate lines Gate by a distance L2 that is greater than or equal to a second threshold value, where the second threshold value represents the alignment deviation between the metal layer where the fourth connecting line 114 is located and the metal layer where the gate line Gate is located during the manufacturing stage. The fourth connecting line 114 can be located on the same layer as the first connecting line 107, the second connecting line 109, the third connecting line 110, and the pixel electrode 102. By ensuring that the distance L2 between the second end 1142 of the fourth connecting line 114 and the adjacent gate lines is greater than or equal to the second threshold value, it can be ensured that even if the fourth connecting line 114 and the gate line Gate are misaligned, the fourth connecting line 114 can still span the two adjacent gate lines Gate. Since the first connection line 107 also spans two adjacent gate lines Gate, the load of the gate line Gate at the location of the fourth connection line 114 is substantially the same as the load of the gate line Gate at the location of the first connection line 107. Therefore, the parasitic capacitance between the fourth connection line 114 and the gate line Gate is substantially equal to the parasitic capacitance between the first connection line 107 and the gate line Gate.

[0081] As shown in Figure 8, in some embodiments, the touch signal line TX includes a first portion with a narrower width and a second portion with a wider width. The first portion has a line width S1 along the first direction D1, and the second portion has a line width S2 along the first direction D1, where S1 is smaller than S2. The data line Data has a line width S3 along the first direction D1. In some embodiments, the line width S2 of the touch signal line TX along the first direction D1 is greater than the line width S3 of the data line Data along the first direction D1. In alternative embodiments, the line width S1 of the touch signal line TX along the first direction D1 is greater than the line width S3 of the data line Data along the first direction D1.

[0082] Figure 9 illustrates the arrangement of vias 112. In the array substrate 100, each touch sensing block 103 is electrically connected to at least one of the multiple touch signal lines TX via a via 112. The orthographic projection of the via 112 on the base substrate 101 does not overlap with the orthographic projection of the first connecting line 107 on the base substrate 101. The touch signal lines TX and the touch sensing blocks 103 are connected via the vias 112. Because the vias 112 occupy a certain position, to ensure optimal pixel transmittance, the first connecting line 107 is not provided at the location where the vias 112 are located.

[0083] Figure 10 is a partial enlarged view of the area V enclosed by the dashed rectangular frame in Figure 4 . In addition to the first connecting line 107, each repeating unit of the array substrate 100 may also be provided with a compensation line 108. The orthographic projection of the compensation line 108 on the base substrate 101 partially overlaps with the orthographic projection of the touch signal line TX on the base substrate 101. Furthermore, within each repeating unit, the touch signal line TX overlapping with the compensation line 108 and the touch signal line TX overlapping with the first connecting line 107 are two different touch signal lines. For example, as previously described, every four adjacent pixels in the array substrate 100 constitute a repeating unit, and these four adjacent pixels are arranged in two rows and two columns. Figure 4 shows the pixel structure of one repeating unit. As shown in FIG4 , the repeating unit includes a complete first connection line 107 and a portion of the first connection line 107. The complete first connection line 107 crosses over the touch signal line TX3, thereby generating parasitic capacitance with the touch signal line TX3. The portion of the first connection line 107 crosses over the touch signal line TX1, thereby generating parasitic capacitance with the touch signal line TX1. Without the compensation line 108, the touch signal line TX2 within the repeating unit has no overlapping signal lines. Therefore, the parasitic capacitance of the touch signal line TX2 differs from the parasitic capacitance of the touch signal lines TX1 and TX3, thereby affecting the accuracy of touch position detection on the array substrate. To ensure that the parasitic capacitance of each touch signal line TX is equal, in the embodiments provided herein, a compensation line 108 is provided at the touch signal line TX2 of each repeating unit. The orthographic projection of the compensation line 108 on the base substrate 101 partially overlaps with the orthographic projection of the touch signal line TX2 on the base substrate 101, thereby generating parasitic capacitance. With this design, the parasitic capacitance of the touch signal line TX2 in the repeating unit is substantially equal to the parasitic capacitance of the touch signal lines TX1 and TX3 , thereby helping to improve the accuracy of touch position detection of the array substrate 100 .

[0084] It should be noted that the so-called "complete first connection line 107 within the repeating unit" is used to connect the touch electrodes 104 in two adjacent rows of sub-pixels. Therefore, half of the first connection line 107 is located in the upper sub-pixel, and the other half of the first connection line 107 is located in the lower sub-pixel. The first connection line 107 overlapping with the touch signal line TX3 can be called a complete first connection line 107 within the repeating unit, while the first connection line 107 overlapping with the touch signal line TX1 cannot be called a complete first connection line 107 within the repeating unit because only a part of the first connection line 107 overlapping with the touch signal line TX1 is located within the repeating unit.

[0085] As shown in FIG10 , in some embodiments, the overlapping portion of the orthographic projection of each compensation line 108 on the base substrate 101 and the orthographic projection of the touch signal line TX2 on the base substrate 101 constitutes a second overlapping region R2, and the areas of all second overlapping regions R2 are equal. This further ensures that the parasitic capacitance between the compensation line 108 and the touch signal line TX2 within each repeating unit is equal.

[0086] In some embodiments, the line width of compensation line 108 is equal to the line width of first connection line 107. Equal line widths further ensure that the parasitic capacitance generated between first connection line 107 and touch signal line TX1 or TX3 is equal to the parasitic capacitance generated between compensation line 108 and touch signal line TX2. In some embodiments, compensation line 108 is located on the same layer as pixel electrode 102.

[0087] As shown in Figure 10, the compensation line 108 includes a sub-portion 1081 extending along a first direction D1. The orthographic projection of the sub-portion 1081 on the base substrate 101 partially overlaps the orthographic projection of the touch signal line TX2 on the base substrate 101. Two opposing ends 1081A and 1081B of the sub-portion 1081 in the first direction D1 both extend beyond the touch signal line TX2. The sub-portion 1081 of the compensation line 108 transversely spans the touch signal line TX2, and the end 1081A of the transversely extending sub-portion 1081 of the compensation line 108 extends beyond the touch signal line TX2 by a distance, for example, 2 to 5 μm. This ensures that even if the compensation line 108 and the touch signal line TX2 are misaligned, the compensation line 108 still overlaps with the touch signal line TX2, thereby generating parasitic capacitance.

[0088] Referring to Figure 10 , the orthographic projection of compensation line 108 on base substrate 101 does not overlap with the orthographic projections of gate lines Gate4 and Gate5, or common connection line 106, on base substrate 101. In other words, compensation line 108 is disconnected after overlapping with touch signal line TX2, no longer crossing gate lines Gate4 and Gate5, or common connection line 106. Thus, a first connection line 107 within this repeating unit crosses gate lines Gate4 and Gate5, as well as common connection line 106, while another first connection line 107 crosses gate lines Gate2 and Gate3, as well as another common connection line 106. This ensures that gate lines Gate2, Gate3, Gate4, and Gate5 have equal parasitic capacitance.

[0089] As previously mentioned, the sub-pixels of pixels P1, P2, P3, and P4, a total of 12 sub-pixels, can constitute the minimum repeating period of the Z-structure, i.e., a repeating unit. Of course, the embodiments of the present disclosure do not limit the repeating unit to only this division method, and other reasonable division methods of the repeating unit should also fall within the scope of protection of this disclosure.

[0090] Figure 11 is a partially enlarged schematic diagram of a touch sensing block 103 in Figure 3 . Each dashed rectangular box in Figure 11 represents a repeating unit. As shown in Figure 11 , each repeating unit includes a complete first connection line 107 and a compensation line 108. Each touch sensing block 103 typically includes hundreds to thousands of sub-pixels. Assuming that each touch sensing block 103 includes M sub-pixels (M is generally an even number, for example, on the order of 10 to 103), and a touch signal line TX is provided for every two sub-pixels, there are M / 2 touch signal lines TX passing through the touch sensing block 103. In some embodiments, only one of the M / 2 touch signal lines TX is the touch signal line driving the touch sensing block 103. The touch signal line TX driving the touch sensing block 103 is connected to the touch sensing block 103 via a via 112. The other touch signal lines TX of the M / 2 touch signal lines TX merely pass through the touch sensing block 103 but are not connected to it. These other touch signal lines TX can pass through the touch sensing block 103 and be connected to other touch sensing blocks 103, or even if they are not connected to other touch sensing blocks 103, in order to ensure the consistency of pixel design, the touch signal lines TX in each touch sensing block 103 also need to be evenly arranged.

[0091] Figure 12 is a cross-sectional view taken along line AA' in Figure 4 , and Figure 13 is a cross-sectional view taken along line BB' in Figure 4 . As shown in Figures 12 and 13 , the array substrate 100 may further include a light-shielding layer 203 located on the side of the touch signal lines TX and the data lines Data away from the base substrate 101. The light-shielding layer 203 includes a first light-shielding portion 2031 and a second light-shielding portion 2032 . The orthographic projection of the data lines Data on the base substrate 101 falls within the orthographic projection of the first light-shielding portion 2031 on the base substrate 101, and the orthographic projection of the touch signal lines TX on the base substrate 101 falls within the orthographic projection of the second light-shielding portion 2032 on the base substrate 101. The width of the first light shielding portion 2031 along the first direction D1 is a first width W1, the width of the second light shielding portion 2032 along the first direction D1 is a second width W2, and the width of each sub-pixel along the first direction D1 is a third width W3 (see Figure 1). The first width W1, the second width W2, and the third width W3 satisfy the following conditions: the ratio of the absolute value of the difference between the first width W1 and the second width W2 to twice the third width W3 is less than or equal to 5%, that is, |W1-W2| / (2*W3)≤5%, which can ensure the uniformity of the display image.

[0092] As shown in Figures 12 and 13 , the orthographic projection of the data line Data on the substrate 101 does not overlap with the orthographic projection of the touch electrode 104 on the substrate 101, and the orthographic projection of the touch signal line TX on the substrate 101 does not overlap with the orthographic projection of the touch electrode 104 on the substrate 101. As previously mentioned, each touch sensing block 103 is not only passed through by the touch signal line TX connected to it, but also by multiple touch signal lines TX not connected to it. Since a smaller parasitic capacitance between a touch signal line TX and other touch sensing blocks 103 not electrically connected to it is more beneficial to touch performance, in an embodiment of the present disclosure, the touch electrode 104 below the touch signal line TX is removed so that the orthographic projection of the touch signal line TX on the substrate 101 does not overlap with the orthographic projection of the touch electrode 104 on the substrate 101, thereby reducing the parasitic capacitance between the touch signal line TX and the touch electrode 104 (and therefore the touch sensing block 103).

[0093] As shown in FIG12 , in array substrate 100, the orthographic projection of the touch electrode 104 in each subpixel on substrate 101 at least partially overlaps with the orthographic projection of the pixel electrode 102 in the subpixel on substrate 101. For each data line Data and the two columns of subpixels on either side of the data line Data, the distance between the orthographic projection of the touch electrode 104 in each of the two columns of subpixels on substrate 101 and the orthographic projection of the data line Data on substrate 101 is a first distance a, and the distance between the orthographic projection of the pixel electrode 102 in each of the two columns of subpixels on substrate 101 and the orthographic projection of the data line Data on substrate 101 is a second distance b. The second distance b is greater than the first distance a, and the difference between the second distance b and the first distance a is greater than or equal to a third threshold c, i.e., ba ≥ c. The third threshold c represents the alignment deviation between the mask used to form the touch electrode 104 and the mask used to form the pixel electrode 102 during the exposure process. In some embodiments, the values ​​of a, b, and c are less than or equal to 10 μm. By ensuring ba≥c, even if the touch electrode 104 and the pixel electrode 102 have an alignment deviation, the overlapping area of ​​the touch electrode 104 and the pixel electrode 102 will not change, thereby ensuring that the storage capacitance of the pixel remains unchanged and improving the yield of the array substrate 100.

[0094] As shown in FIG13 , in the array substrate 100, for each touch signal line TX and the two columns of sub-pixels located on either side of the touch signal line TX, the distance between the orthographic projection of the touch electrode 104 in each of the two columns of sub-pixels on the substrate 101 and the orthographic projection of the touch signal line TX on the substrate 101 is a third distance a′, and the distance between the orthographic projection of the pixel electrode 102 in each of the two columns of sub-pixels on the substrate 101 and the orthographic projection of the touch signal line TX on the substrate 101 is a fourth distance b′. The fourth distance b′ is greater than the third distance a′, and the difference between the fourth distance b′ and the third distance a′ is greater than or equal to a third threshold value c, i.e., b′-a′=ba≥c. a′ is not necessarily equal to a, and b′ is not necessarily equal to b. Generally speaking, the larger the values ​​of a′ and b′ are (i.e., the farther the touch signal line TX is from the touch electrode 104 and the pixel electrode 102), the smaller the parasitic capacitance between the touch signal line TX and the touch electrode 104 and the pixel electrode 102, which is more beneficial to the touch performance; however, the greater the distance, the smaller the effective light-transmitting area of ​​the pixel, so the values ​​of a′ and b′ can be set according to the specific specifications of the array substrate 100.

[0095] In some embodiments, the touch electrode 104 is located on the base substrate 101; the gate line Gate and the common connection line 106 are located on the same layer and both are located on the side of the touch electrode 104 away from the base substrate 101; the data line Data and the touch signal line TX are located on the same layer and both are located on the side of the gate line Gate away from the base substrate 101; the pixel electrode 102, the first connection line 107, the second connection line 109, the third connection line 110, the fourth connection line 114, and the compensation line 108 are located on the same layer and they are located on the side of the data line Data away from the base substrate 101. During the manufacturing process, the touch electrode 104 can be formed by patterning the first metal layer using a first mask, and the material of the first metal layer can be, for example, ITO; the gate line Gate and the common connection line 106 can be formed by patterning the second metal layer using a second mask; the data line Data and the touch signal line TX can be formed by patterning the third metal layer using a third mask; the pixel electrode 102, the first connection line 107, the second connection line 109, the third connection line 110, the fourth connection line 114, and the compensation line 108 can be formed by patterning the fourth metal layer using a fourth mask, and the material of the fourth metal layer can be, for example, ITO. In this way, the number of masks can be greatly reduced, and the process flow and cost can be saved. Other required film layers, such as a gate insulating layer, an active layer, etc., can also be set between the gate line Gate and the data line Data. Other required film layers, such as a passivation layer, etc., can also be set between the data line Data and the pixel electrode 102.

[0096] FIG14 is a schematic plan view showing a partial structure of the array substrate 200 . Except for the relative positions of certain film layers, the array substrate 200 shown in FIG14 has a structure substantially identical to that of the array substrate 100 shown in FIG4 . For example, the pixel structure of the array substrate 200 is also arranged as Z-structure pixels. The array substrate 200 includes the first connecting line 107 as described above, which is used to connect the touch electrodes of two adjacent rows of sub-pixels in each touch sensing block 103 . The first connecting line 107 is provided at the position of the second connecting line 109 of the array substrate 200 , but is not provided at the position of the third connecting line 110 . Each repeating unit includes a compensation line 108 so that all touch signal lines TX have substantially the same parasitic capacitance. Electrical isolation between two adjacent touch sensing blocks 103 in the first direction D1 is achieved by disconnecting a common connecting line, and electrical isolation between two adjacent touch sensing blocks 103 in the second direction D2 is achieved by disconnecting a fourth connecting line 114 . The detailed structures and functions of these components can be referred to in the description of FIG4 and will not be repeated here. For the sake of brevity, the similarities between the array substrate 200 in FIG. 14 and the array substrate 100 in FIG. 4 will not be described again, and only the differences will be described below.

[0097] Unlike array substrate 100, in array substrate 200, pixel electrodes 202 are located on base substrate 101, and touch electrodes 204 are located on the side of pixel electrodes 202 away from base substrate 101. Specifically, pixel electrodes 202 are located on base substrate 101; gate lines Gate are located on the side of pixel electrodes 202 away from base substrate 101; data lines Data and touch signal lines TX are located on the same layer and both are located on the side of gate lines Gate away from base substrate 101; and touch electrodes 204 are located on the side of data lines Data away from base substrate 101. The first connecting lines 107, second connecting lines 109, third connecting lines 110, fourth connecting lines 114, compensation lines 108, and common connecting lines 205 (see FIG. 15 ) can be located on the same layer as the touch electrodes 204. The pixel electrodes 202 and touch electrodes 204 can be made of ITO.

[0098] Figure 15 is a partial enlarged view of area VI enclosed by a dotted rectangle in Figure 14 . In the array substrate 200, each touch sensing block 103 is electrically connected to at least one of the multiple touch signal lines TX via a via 212. The orthographic projection of the via 212 on the base substrate 101 is located between the orthographic projections of two gate lines Gate between two adjacent rows of sub-pixels. For example, in Figure 15 , the orthographic projection of the via 212 on the base substrate 101 is located between the orthographic projections of two gate lines Gate2 and Gate3 between two adjacent rows of sub-pixels. This allows for efficient use of wiring space.

[0099] Figure 16 is a partial enlarged view of area VII, outlined by the dashed rectangle in Figure 14 . As shown in Figure 16 , two adjacent touch electrodes 204 in a first direction D1 can be electrically connected via a common connection line 205 . The touch electrodes 204 of two adjacent rows of sub-pixels within each touch sensing block 103 are electrically connected via a first connection line 107 . The extension direction of the first connection line 107 is substantially the same as that of the touch signal line TX, and the orthographic projection of the first connection line 107 on the base substrate 101 falls within the orthographic projection of the touch signal line TX on the base substrate 101. Because the first connection line 107 and the touch electrodes 204 are located on the same layer, the first connection line 107 can be directly connected to the touch electrodes 204 without requiring a via.

[0100] In some alternative embodiments, the extension direction of the first connection line 107 may be different from the extension direction of the touch signal line TX. For example, the extension direction of the first connection line 107 may be inclined at a certain angle relative to the extension direction of the touch signal line TX, and the orthographic projection of the first connection line 107 on the base substrate 101 may overlap with the orthographic projection of the touch signal line TX on the base substrate 101 at most. This arrangement can reduce the overlapping area between the first connection line 107 and the touch signal line TX, thereby reducing coupling between the two.

[0101] For other technical effects of the array substrate 200 , reference may be made to the description of the technical effects of the array substrate 100 , and for the sake of brevity, a repeated description will not be given here.

[0102] Figure 17 shows a block diagram of a touch display device provided according to an embodiment of the present disclosure. The touch display device may include the array substrate 100 or 200 described in any of the previous embodiments. In some embodiments, the touch display device may be an in-cell touch display device, comprising an array substrate, an opposing substrate, and a liquid crystal layer located between the array substrate and the opposing substrate. The array substrate is the array substrate 100 or 200 described in any of the previous embodiments. The touch display device includes, but is not limited to, any product or component with touch and display functions, such as a liquid crystal panel, electronic paper, an OLED (organic light-emitting diode) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or the like.

[0103] The touch display device can have substantially the same technical effects as the array substrate 100 or 200 described in the previous embodiments. For the sake of brevity, the technical effects of the touch display device will not be repeatedly described here.

[0104] It will be understood that although the terms first, second, third, etc. may be used to describe various elements, components, areas, layers and / or parts in this article, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer or part from another area, layer or part. Therefore, the first element, component, area, layer or part discussed above can be referred to as the second element, component, area, layer or part without departing from the teachings of the present disclosure.

[0105] Spatially relative terms such as "row," "column," "under," "above," "left," "right," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures for ease of description. It will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figure is flipped, the element described as "under other elements or features" will be oriented as "above other elements or features." Thus, the exemplary term "under" can encompass both orientations of "above" and "under." The device can be oriented otherwise (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein are interpreted accordingly. In addition, it will also be understood that when a layer is referred to as "between two layers," it can be the only layer between the two layers, or one or more intermediate layers may also be present.

[0106] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "one", "an" and "the" are intended to also include the plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "include" and / or "comprise" when used in this specification specify the presence of the features, wholes, steps, operations, elements and / or parts, but do not exclude the presence of one or more other features, wholes, steps, operations, elements, parts and / or their groups or add one or more other features, wholes, steps, operations, elements, parts and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In the description of this specification, the description of the reference terms "one embodiment", "another embodiment" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily need to be directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. Furthermore, those skilled in the art may combine and combine different embodiments or examples and features of different embodiments or examples described in this specification without mutual contradiction.

[0107] It will be understood that when an element or layer is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, directly connected to, directly coupled to, or directly adjacent to another element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “directly adjacent to” another element or layer, no intervening elements or layers are present. However, in no case should “on” or “directly on” be interpreted as requiring that one layer completely cover the underlying layer.

[0108] Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the present disclosure. Because of this, variations in the illustrated shapes, for example as a result of manufacturing techniques and / or tolerances, should be expected. Therefore, embodiments of the present disclosure should not be interpreted as being limited to the specific shapes of the regions illustrated herein, but should include shape deviations, for example, due to manufacturing. Therefore, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the regions of the device and are not intended to limit the scope of the present disclosure.

[0109] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0110] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate, comprising: A substrate, comprising a plurality of pixels arranged in an array, wherein the plurality of pixels comprises a plurality of sub-pixels arranged in an array, and each of the plurality of sub-pixels comprises a pixel electrode, a touch electrode, and a thin film transistor; A plurality of touch sensing blocks located on the substrate and electrically insulated from each other, each touch sensing block comprising a plurality of touch electrodes, the plurality of touch electrodes of each touch sensing block being electrically connected to each other and arranged in an array; A plurality of gate lines extending along a first direction, each row of sub-pixels being associated with two gate lines of the plurality of gate lines; A plurality of touch signal lines and a plurality of data lines extending along a second direction, wherein the touch signal lines and the data lines are located in the same layer, each touch sensing block is electrically connected to at least one of the plurality of touch signal lines, and the first direction is arranged to intersect with the second direction; A first connecting line, through which two adjacent rows of touch electrodes in each touch sensing block are electrically connected; as well as a second connecting line, each of at least a portion of the plurality of pixel electrodes is electrically connected to a drain of a corresponding thin film transistor through the second connecting line, and an orthographic projection of the second connecting line on the base substrate does not overlap with an orthographic projection of the touch signal line on the base substrate, The gate of the thin film transistor of each sub-pixel is electrically connected to the gate line, the drain of the thin film transistor of each sub-pixel is electrically connected to the pixel electrode of the sub-pixel, the source of the thin film transistor of each sub-pixel is electrically connected to the data line, every two adjacent sub-pixels in the same row of sub-pixels constitute a unit group, the source of the thin film transistor of each unit group is electrically connected to the same data line, the gate of the thin film transistor of each unit group is electrically connected to different gate lines, and the source of the thin film transistor of two adjacent sub-pixels in the same column of sub-pixels is electrically connected to different data lines, and Wherein, every four adjacent pixels in the plurality of pixels constitute a repeating unit, each repeating unit includes four adjacent sub-pixels, the adjacent four sub-pixels are arranged in two rows and two columns, the pixel electrodes of two sub-pixels in different rows and obliquely opposite to each other among the four adjacent sub-pixels are respectively electrically connected to the drain of a corresponding thin film transistor through the second connecting line, and the pixel electrodes of the other two sub-pixels in different rows and obliquely opposite to each other among the four adjacent sub-pixels are respectively electrically connected to the drain of the corresponding thin film transistor through the second connecting line. The touch electrodes of the pixels are electrically connected through the first connecting lines.

2. The array substrate according to claim 1, further comprising a third connecting line, wherein: Each of a portion of the multiple pixel electrodes is electrically connected to the drain of a corresponding thin film transistor through the second connecting line, and each of the remaining multiple pixel electrodes is electrically connected to the drain of a corresponding thin film transistor through the third connecting line, and the orthographic projection of the third connecting line on the base substrate partially overlaps with the orthographic projection of the touch signal line on the base substrate.

3. The array substrate according to claim 2, wherein: The orthographic projection of the third connecting line on the substrate does not overlap with the orthographic projection of the first connecting line on the substrate.

4. The array substrate according to claim 2, wherein: The overlapping portion of the orthographic projection of the third connection line on the substrate and the orthographic projection of the touch signal line on the substrate constitutes a first overlapping region, and areas of all first overlapping regions are equal to each other.

5. The array substrate according to claim 1, further comprising a plurality of common connection lines extending along the first direction, wherein: Each of the plurality of common connection lines is arranged between two adjacent rows of sub-pixels, the touch electrodes in the same row in each touch sensing block are electrically connected to each other via the common connection line, and each common connection line is disconnected at the interval area between two adjacent touch sensing blocks.

6. The array substrate according to claim 5, wherein: A data line is arranged at the interval area between any two adjacent touch sensing blocks along the first direction, the disconnected portion of the common connection line at the interval area is located on the first side of the data line, the continuous portion of the common connection line includes a first sub-portion, a second sub-portion and a third sub-portion connected in sequence, the first sub-portion is located on the second side of the data line, the third sub-portion is located on the first side of the data line, the second sub-portion is located between the first sub-portion and the third sub-portion, and the orthographic projection of the second sub-portion on the substrate falls within the orthographic projection of the data line on the substrate.

7. The array substrate according to claim 6, wherein: A length of the third subsection along the first direction is greater than or equal to a first threshold.

8. The array substrate according to claim 5, further comprising a fourth connecting line, wherein: The first end of the fourth connecting line is electrically connected to the touch electrode of one of the two touch sensing blocks arbitrarily adjacent to each other along the second direction, and the second end of the fourth connecting line is disconnected from the touch electrode of the other of the two touch sensing blocks arbitrarily adjacent to each other along the second direction, so that the two touch sensing blocks arbitrarily adjacent to each other along the second direction are electrically insulated from each other.

9. The array substrate according to claim 8, wherein: The orthographic projection of the fourth connecting line on the substrate crosses the orthographic projections of two gate lines located between any two adjacent touch sensing blocks along the second direction on the substrate, and the distance by which the second end of the fourth connecting line extends beyond the gate line closest to the second end of the two gate lines is greater than or equal to a second threshold.

10. The array substrate according to claim 1, wherein: The orthographic projection of the first connection line on the base substrate partially overlaps with the orthographic projection of the touch signal line on the base substrate, and an extension direction of the first connection line at the overlap is perpendicular to an extension direction of the touch signal line at the overlap.

11. The array substrate according to claim 1, wherein: Each touch sensing block is electrically connected to at least one of the plurality of touch signal lines via a via hole, and an orthographic projection of the via hole on the base substrate does not overlap with an orthographic projection of the first connection line on the base substrate.

12. The array substrate according to claim 5, wherein: The orthographic projection of the first connection line on the base substrate partially overlaps with the orthographic projection of the touch signal line on the base substrate, and one first connection line is arranged between two adjacent rows of sub-pixels in each repeating unit.

13. The array substrate according to claim 12, wherein: Each repeating unit is also provided with a compensation line, the orthographic projection of the compensation line on the substrate partially overlaps with the orthographic projection of the touch signal line on the substrate, and the touch signal line overlapping with the compensation line and the touch signal line overlapping with the first connecting line in each repeating unit are two different touch signal lines.

14. The array substrate according to claim 13, wherein: The compensation line includes a sub-portion extending along the first direction, an orthographic projection of the sub-portion on the base substrate partially overlaps with an orthographic projection of the touch signal line on the base substrate, and two opposite ends of the sub-portion in the first direction both extend beyond the touch signal line.

15. The array substrate according to claim 13, wherein: The orthographic projection of the compensation line on the base substrate does not overlap with the orthographic projection of the gate line and the common connection line on the base substrate.

16. The array substrate according to claim 13, wherein: The line width of the compensation line is equal to the line width of the first connection line.

17. The array substrate according to claim 13, wherein: The overlapping portion of the orthographic projection of the compensation line on the base substrate and the orthographic projection of the touch signal line on the base substrate constitutes a second overlapping region, and areas of all the second overlapping regions are equal to each other.

18. The array substrate according to claim 1, wherein: The line width of the touch signal line is greater than the line width of the data line.

19. The array substrate according to claim 18, wherein: The touch signal line includes a first portion and a second portion, and a line width of the first portion is smaller than a line width of the second portion.

20. The array substrate according to claim 1, further comprising a light shielding layer located on a side of the touch signal line and the data line away from the base substrate, wherein: The light shielding layer includes a first light shielding portion and a second light shielding portion, the orthographic projection of the data line on the base substrate falls within the orthographic projection of the first light shielding portion on the base substrate, the orthographic projection of the touch signal line on the base substrate falls within the orthographic projection of the second light shielding portion on the base substrate, the width of the first light shielding portion along the first direction is a first width, the width of the second light shielding portion along the first direction is a second width, the width of each sub-pixel along the first direction is a third width, and the first width, the second width, and the third width satisfy the following conditions: A ratio of an absolute value of a difference between the first width and the second width to twice the third width is less than or equal to 5%.

21. The array substrate according to claim 1, wherein: The orthographic projection of the data line on the base substrate does not overlap with the orthographic projection of the touch electrode on the base substrate, and the orthographic projection of the touch signal line on the base substrate does not overlap with the orthographic projection of the touch electrode on the base substrate.

22. The array substrate according to claim 21, wherein: A data line is arranged every two columns of sub-pixels, and each of at least part of the plurality of data lines is arranged between two adjacent columns of sub-pixels; and A touch signal line is arranged every two columns of sub-pixels, and each touch signal line is arranged between two adjacent columns of sub-pixels and between two adjacent data lines.

23. The array substrate according to claim 22, wherein: The orthographic projection of the touch electrode in each sub-pixel on the substrate at least partially overlaps with the orthographic projection of the pixel electrode in the sub-pixel on the substrate. For each data line and two columns of sub-pixels located on both sides of the data line, the distance between the orthographic projection of the touch control electrode in each column of the two columns of sub-pixels on the substrate and the orthographic projection of the data line on the substrate is a first distance, and the two columns of sub-pixels are The distance between the orthographic projection of the pixel electrode in each column of sub-pixels on the substrate and the orthographic projection of the data line on the substrate is a second distance, the second distance is greater than the first distance and the difference between the second distance and the first distance is greater than or equal to a third threshold.

24. The array substrate according to claim 23, wherein: For each touch signal line and the two columns of sub-pixels located on both sides of the touch signal line, the distance between the orthographic projection of the touch electrode in each column of the two columns of sub-pixels on the substrate substrate and the orthographic projection of the touch signal line on the substrate substrate is a third distance, and the distance between the orthographic projection of the pixel electrode in each column of the two columns of sub-pixels on the substrate substrate and the orthographic projection of the touch signal line on the substrate substrate is a fourth distance, and the fourth distance is greater than the third distance and the difference between the fourth distance and the third distance is greater than or equal to the third threshold.

25. The array substrate according to claim 1, wherein: The ratio of the number of the data lines to the number of the touch signal lines is 1:2, one data line is arranged for every two columns of sub-pixels, two touch signal lines are arranged for every two columns of sub-pixels, and the two touch signal lines are arranged between two adjacent columns of sub-pixels.

26. The array substrate according to any one of claims 1 to 25, wherein: The touch electrode is located on the base substrate, the gate line is located on a side of the touch electrode away from the base substrate, the data line and the touch signal line are located on a side of the gate line away from the base substrate, and the pixel electrode and the first connecting line are located in the same layer and both are located on a side of the data line away from the base substrate.

27. The array substrate according to any one of claims 1 to 9 and 12 to 25, wherein: The pixel electrode is located on the base substrate, the gate line is located on a side of the pixel electrode away from the base substrate, the data line and the touch signal line are located on a side of the gate line away from the base substrate, the touch electrode and the first connecting line are located in the same layer and both are located on a side of the data line away from the base substrate.

28. The array substrate according to claim 27, wherein: An extension direction of the first connection line is different from an extension direction of the touch signal line, and an orthographic projection of the first connection line on the base substrate overlaps at most a portion with an orthographic projection of the touch signal line on the base substrate.

29. The array substrate according to claim 27, wherein: Each touch sensing block is electrically connected to at least one of the plurality of touch signal lines via a via hole, and an orthographic projection of the via hole on the substrate is located between orthographic projections of two gate lines between two adjacent rows of sub-pixels on the substrate.

30. The array substrate according to claim 27, wherein: The first connection line and the touch signal line extend in the same direction, and an orthographic projection of the first connection line on the base substrate falls within an orthographic projection of the touch signal line on the base substrate.

31. The array substrate according to any one of claims 1 to 30, further comprising a liquid crystal layer, wherein: The touch electrode and the pixel electrode are located at a same side of the liquid crystal layer, and materials of the touch electrode and the pixel electrode include indium tin oxide.

32. The array substrate according to any one of claims 1 to 31, wherein: Each pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged in sequence along the first direction, the four adjacent pixels of each repeating unit are arranged in two rows and two columns and include a first pixel, a second pixel, a third pixel, and a fourth pixel, the first pixel and the second pixel are located in the same row and the first pixel and the third pixel are located in the same column, the third pixel and the fourth pixel are located in the same row and the second pixel and the fourth pixel are located in the same column, The sources of the thin film transistors of the first subpixel and the second subpixel of the first pixel are electrically connected to the first data line among the multiple data lines, the sources of the thin film transistors of the third subpixel of the first pixel and the first subpixel of the second pixel are electrically connected to the second data line among the multiple data lines, the sources of the thin film transistors of the second subpixel and the third subpixel of the second pixel are electrically connected to the third data line among the multiple data lines, the sources of the thin film transistors of the first subpixel and the second subpixel of the third pixel are electrically connected to the second data line, the sources of the thin film transistors of the third subpixel of the third pixel and the first subpixel of the fourth pixel are electrically connected to the third data line, and the sources of the thin film transistors of the second subpixel and the third subpixel of the fourth pixel are electrically connected to the fourth data line among the multiple data lines.

33. The array substrate according to claim 32, wherein: The gates of the thin film transistors of all first sub-pixels in the same row of pixels are electrically connected to the first gate line of the two gate lines, the gates of the thin film transistors of all second sub-pixels in the same row of pixels are electrically connected to the second gate line of the two gate lines, and the gates of the thin film transistors of the third sub-pixels of two adjacent pixels in the same row of pixels are electrically connected to the first gate line and the second gate line, respectively.

34. A touch display device, comprising the array substrate according to any one of claims 1-33.

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