Runtime mechanism for optimizing shader execution streams

Abstract

This disclosure provides systems, apparatus, apparatus, and methods, including computer programs encoded on a storage medium, for runtime optimization of shader execution streams. A graphics processor may obtain instruction execution data associated with a graphics workload, the instruction execution data including graphics data for a set of shader operations. The graphics processor may configure, at a first iteration, at least one predictor based on the instruction execution data including the graphics data for the set of shader operations. The graphics processor may adjust, at a second iteration, an execution stream of the graphics workload based on the configured at least one predicted value, the execution stream of the graphics workload including the set of shader operations. The graphics processor may perform or refrain from performing each shader operation of the set of shader operations based on the adjusted execution stream of the graphics workload at the second iteration.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. patent application serial number 17 / 817,815, filed on August 5, 2022, entitled "A RUNTIME MECHANISM TO OPTIMIZESHADER EXECUTION FLOW," which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to processing systems and, more particularly, to one or more techniques for graphics processing. Background Art

[0004] Computing devices typically perform graphics and / or display processing (e.g., using a graphics processing unit (GPU), a central processing unit (CPU), a display processor, etc.) to render and display visual content. Such computing devices may include, for example, computer workstations, mobile phones (such as smart phones), embedded systems, personal computers, tablet computers, and video game consoles. The GPU is configured to execute a graphics processing pipeline that includes one or more processing stages that operate together to execute graphics processing commands and output frames. The central processing unit (CPU) can control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern CPUs are typically capable of executing multiple applications concurrently, each of which may need to utilize a GPU during execution. A display processor may be configured to convert digital information received from the CPU into analog values, and may issue commands to a display panel to display visual content. A device that provides content for visual presentation on a display may utilize a CPU, a GPU, and / or a display processor.

[0005] Current techniques may not address unnecessary execution of redundant shader program operations in graphics applications. Improved shader program execution techniques are needed. Summary of the invention

[0006] The following presents a simplified summary of one or more aspects in order to provide a basic understanding of these aspects. This summary is not an extensive overview of all contemplated aspects, and is neither intended to identify key or important elements of all aspects, nor to describe the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to a more detailed description presented later.

[0007] In one aspect of the present disclosure, a method, a computer-readable medium, and a device are provided. The device may obtain instruction execution data associated with a graphics workload. The instruction execution data may include graphics data for a set of shader operations. The device may configure at least one prediction value based on the instruction execution data including the graphics data for the set of shader operations at a first iteration. The at least one prediction value may indicate the likelihood of occurrence of a condition of the graphics workload. The condition of the graphics workload may be associated with a stream processor of a graphics processing unit (GPU). The device may adjust the execution flow of the graphics workload based on the configured at least one prediction value at a second iteration after the first iteration and without changing the function or result of the graphics workload. The execution flow of the graphics workload may include the set of shader operations. The device may execute or refrain from executing each shader operation in the set of shader operations based on the adjusted execution flow of the graphics workload at a second iteration.

[0008] To achieve the aforementioned and other related purposes, the one or more aspects include the following features fully described below and particularly pointed out in the claims. The following description and the accompanying drawings set forth in detail some exemplary features of the one or more aspects. However, these features are merely indicative of some of the various ways in which the principles of the various aspects can be employed, and this specification is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating an example content generation system in accordance with one or more techniques of this disclosure.

[0010] Figure 2 An example GPU in accordance with one or more techniques of this disclosure is illustrated.

[0011] Figure 3 is a diagram illustrating example components for processing data according to one or more aspects of the present disclosure.

[0012] Figure 4 is a diagram illustrating an example GPU according to one or more aspects of the present disclosure.

[0013] Figure 5 is a diagram illustrating an example shader program according to one or more aspects of the present disclosure.

[0014] Fig. 6A is a diagram illustrating an example radius value graph according to one or more aspects of the present disclosure.

[0015] Figure 6B is a diagram illustrating an example tile radius value map according to one or more aspects.

[0016] Figure 7is a block diagram illustrating an example process for performing flow optimization of a shader program according to one or more aspects of the present disclosure.

[0017] Figure 8 is a diagram illustrating an example shader program according to one or more aspects.

[0018] Fig. 9 is a call-flow diagram illustrating example communications between a first GPU component, a second GPU component, and a memory, in accordance with one or more techniques of this disclosure.

[0019] Fig.10 is a flowchart of an example method of graphics processing in accordance with one or more techniques of this disclosure.

[0020] Fig.11 is a flowchart of an example method of graphics processing in accordance with one or more techniques of this disclosure. DETAILED DESCRIPTION

[0021] Various aspects of the system, device, computer program product and method will be described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be interpreted as being limited to any specific structure or function presented throughout the present disclosure. On the contrary, these aspects are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. Based on the teachings of this article, it should be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the system, device, computer program product and method disclosed herein, whether it is implemented independently of other aspects of the present disclosure or implemented in combination with other aspects of the present disclosure. For example, any number of aspects set forth herein may be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such devices or methods implemented using other structures, functionality, or structures and functionality other than the various aspects of the disclosure set forth herein or different from the various aspects of the disclosure set forth herein. Any aspect disclosed herein may be embodied by one or more elements of the claims.

[0022] Although various aspects are described herein, many variations and different combinations and arrangements of these aspects are within the scope of the disclosure. Although some potential benefits and advantages of various aspects of the disclosure are mentioned, the scope of the disclosure is not intended to be limited to specific benefits, uses or objectives. On the contrary, various aspects of the disclosure are intended to be widely applicable to different wireless technologies, system configurations, processing systems, networks and transmission protocols, some of which are illustrated by way of example in the drawings and the description below. The specific embodiments and drawings merely illustrate the disclosure and do not limit the disclosure. The scope of the disclosure is defined by the attached claims and their equivalent technical solutions.

[0023] Several aspects are presented with reference to various devices and methods. These devices and methods are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0024] For example, an element or any part of an element or any combination of elements may be implemented as a "processing system" including one or more processors (which may also be referred to as processing units). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems on chips (SOCs), baseband processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionalities described in this disclosure. One or more processors in a processing system may execute software. Whether referred to as software, firmware, middleware, microcode, hardware description language, or other names, software may be broadly understood to mean instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, processes, functions, etc.

[0025] The term "application" may refer to software. As described herein, one or more technologies may refer to an application (e.g., software) configured to perform one or more functions. In such examples, the application may be stored in a memory (e.g., an on-chip memory of a processor, a system memory, or any other memory). The hardware described herein (such as a processor) may be configured to execute an application. For example, an application may be described as including code that, when executed by hardware, causes the hardware to perform one or more technologies described herein. As an example, the hardware may access code from a memory and execute the code accessed from the memory to perform one or more technologies described herein. In some examples, components are identified in the present disclosure. In such examples, components may be hardware, software, or a combination thereof. Each component may be a separate component or a subcomponent of a single component.

[0026] In one or more examples described herein, the functions described can be implemented in hardware, software, or any combination thereof. If implemented in software, the functions can be stored or encoded on a computer-readable medium as one or more instructions or codes. Computer-readable media include computer storage media. Storage media can be any available media that can be accessed by a computer. By way of example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), optical disk storage, magnetic disk storage, other magnetic storage devices, a combination of computer-readable media of the above types, or any other medium that can be used to store computer executable code in the form of instructions or data structures that can be accessed by a computer.

[0027] As used herein, instances of the term "content" may refer to "graphic content," "image," and the like, regardless of whether the term is used as an adjective, noun, or other part of speech. In some examples, as used herein, the term "graphic content" may refer to content produced by one or more processes of a graphics processing pipeline. In other examples, as used herein, the term "graphic content" may refer to content produced by a processing unit configured to perform graphics processing. In yet other examples, as used herein, the term "graphic content" may refer to content produced by a graphics processing unit.

[0028] In some use cases associated with graphics applications, the final result or intermediate results of an operation (e.g., a "blending" operation) may depend on results from multiple possible previous operations. For example, for a result that can be calculated with result=a*b, each of operands a and b may be generated based on one or more of a sampling operation, a memory load operation, or a highly complex mathematical operation. In some cases, many operands for multiplication operations may be equal to 0.0. Other operations that perform texture fetches or other operands for multiplication operations where one of these operands is equal to 0.0 may represent wasted time, energy, and execution resources.

[0029] One or more aspects may relate to runtime optimization of shader execution flow. A graphics processor may obtain instruction execution data associated with a graphics workload, the instruction execution data including graphics data for a set of shader operations. The graphics processor may configure at least one prediction value based on the instruction execution data including the graphics data for the set of shader operations at a first iteration. The at least one prediction value may indicate the likelihood of occurrence of a condition of the graphics workload. The condition of the graphics workload may be associated with a stream processor of a GPU. The graphics processor may adjust the execution flow of the graphics workload based on the configured at least one prediction value at a second iteration after the first iteration and without changing the function or result of the graphics workload. The execution flow of the graphics workload may include the set of shader operations. The graphics processor may execute or refrain from executing each shader operation in the set of shader operations based on the adjusted execution flow of the graphics workload at a second iteration.

[0030] Figure 1 1 is a block diagram illustrating an example content generation system 100 configured to implement one or more techniques of the present disclosure. The content generation system 100 includes a device 104. The device 104 may include one or more components or circuits for performing various functions described herein. In some examples, one or more components of the device 104 may be components of a SOC. The device 104 may include one or more components configured to perform one or more techniques of the present disclosure. In the example shown, the device 104 may include a processing unit 120, a content encoder / decoder 122, and a system memory 124. In some aspects, the device 104 may include multiple components (e.g., a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131). The display 131 may refer to one or more displays 131. For example, the display 131 may include a single display or multiple displays, which may include a first display and a second display. The first display may be a left-eye display, and the second display may be a right-eye display. In some examples, the first display and the second display may receive different frames for presentation thereon. In other examples, the first display and the second display may receive the same frame for presentation thereon. In another example, the result of the graphics processing may not be displayed on the device, for example, the first display and the second display may not receive any frame for presentation thereon. Instead, the frame or graphics processing result may be passed to another device. In some aspects, this situation is referred to as split rendering.

[0031] The processing unit 120 may include an internal memory 121. The processing unit 120 may be configured to perform graphics processing using the graphics processing pipeline 107. The content encoder / decoder 122 may include an internal memory 123. In some examples, the device 104 may include a processor that may be configured to perform one or more display processing techniques on one or more frames generated by the processing unit 120 and then display the frames through one or more displays 131. Although the processor in the example content generation system 100 is configured as a display processor 127, it should be understood that the display processor 127 is an example of a processor and other types of processors, controllers, etc. may be used in place of the display processor 127. The display processor 127 may be configured to perform display processing. For example, the display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by the processing unit 120. The one or more displays 131 may be configured to display or otherwise present the frames processed by the display processor 127. In some examples, one or more displays 131 may include one or more of the following: a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head-mounted display, or any other type of display device.

[0032] Memory external to processing unit 120 and content encoder / decoder 122, such as system memory 124, may be accessible to processing unit 120 and content encoder / decoder 122. For example, processing unit 120 and content encoder / decoder 122 may be configured to read from and / or write to external memory, such as system memory 124. Processing unit 120 may be communicatively coupled to system memory 124 via a bus. In some examples, processing unit 120 and content encoder / decoder 122 may be communicatively coupled to internal memory 121 via the bus or via a different connection.

[0033] The content encoder / decoder 122 may be configured to receive graphics content from any source, such as the system memory 124 and / or the communication interface 126. The system memory 124 may be configured to store the received encoded or decoded graphics content. The content encoder / decoder 122 may be configured to receive the encoded or decoded graphics content in the form of encoded pixel data, for example, from the system memory 124 and / or the communication interface 126. The content encoder / decoder 122 may be configured to encode or decode any graphics content.

[0034] The internal memory 121 or the system memory 124 may include one or more volatile or non-volatile memories or storage devices. In some examples, the internal memory 121 or the system memory 124 may include RAM, static random access memory (SRAM), dynamic random access memory (DRAM), erasable programmable ROM (EPROM), EEPROM, flash memory, magnetic data medium or optical storage medium or any other type of memory. According to some examples, the internal memory 121 or the system memory 124 may be a non-transitory storage medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier or propagation signal. However, the term "non-transitory" should not be interpreted as meaning that the internal memory 121 or the system memory 124 is non-removable or that its contents are static. For example, the system memory 124 may be removed from the device 104 and moved to another device. As another example, the system memory 124 may not be removable from the device 104.

[0035] The processing unit 120 may be a CPU, a GPU, a GPGPU, or any other processing unit that may be configured to perform graphics processing. In some examples, the processing unit 120 may be integrated into the motherboard of the device 104. In another example, the processing unit 120 may be present on a graphics card installed in a port of the motherboard of the device 104, or may be otherwise incorporated into a peripheral device configured to interoperate with the device 104. The processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, ASICs, FPGAs, arithmetic logic units (ALUs), DSPs, discrete logic pieces, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the processing unit 120 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 121), and may use one or more processors to execute instructions in hardware to perform the technology of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) may be considered to be one or more processors.

[0036] The content encoder / decoder 122 may be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 may be integrated into the mainboard of the device 104. The content encoder / decoder 122 may include one or more processors, such as one or more microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the content encoder / decoder 122 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 123), and may use one or more processors to execute instructions in hardware to perform the technology of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) may be considered to be one or more processors.

[0037] In some aspects, the content generation system 100 may include a communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any receiving functions described herein with respect to the device 104. In addition, the receiver 128 may be configured to receive information from another device, such as eye or head position information, rendering commands, and / or position information. The transmitter 130 may be configured to perform any sending functions described herein with respect to the device 104. For example, the transmitter 130 may be configured to send information to another device, which may include a request for content. The receiver 128 and the transmitter 130 may be combined into a transceiver 132. In such examples, the transceiver 132 may be configured to perform any receiving functions and / or sending functions described herein with respect to the device 104.

[0038] Reference again Figure 1In some aspects, the processing unit 120 may include a flow controller 198 configured to obtain instruction execution data associated with a graphics workload. The instruction execution data may include graphics data for a set of shader operations. The flow controller 198 may be configured to configure at least one prediction value based on the instruction execution data including the graphics data for the set of shader operations at a first iteration. The at least one prediction value may indicate the likelihood of occurrence of a condition of the graphics workload. The condition of the graphics workload may be associated with a stream processor of the GPU. The flow controller 198 may be configured to adjust the execution flow of the graphics workload based on the configured at least one prediction value at a second iteration after the first iteration and without changing the function or result of the graphics workload. The execution flow of the graphics workload may include the set of shader operations. The flow controller 198 may be configured to execute or refrain from executing each shader operation in the set of shader operations based on the adjusted execution flow of the graphics workload at a second iteration. Although the following description focuses on graphics processing, the concepts described herein may be applicable to other similar processing technologies.

[0039] Devices such as device 104 may refer to any device, apparatus or system configured to perform one or more technologies described herein. For example, a device may be a server, a base station, a user equipment, a client device, a station, an access point, a computer (such as a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation or a mainframe computer), a final product, an apparatus, a phone, a smart phone, a server, a video game platform or console, a handheld device (such as a portable video game device or a personal digital assistant (PDA)), a wearable computing device (such as a smart watch, an augmented reality device or a virtual reality device), a non-wearable device, a display or display device, a television, a television set-top box, an intermediate network device, a digital media player, a video streaming device, a content streaming device, a vehicle-mounted computer, any mobile device, any device configured to generate graphics content, or any device configured to perform one or more technologies described herein. The process herein may be described as being performed by a specific component (e.g., a GPU), but in other embodiments, other components (e.g., a CPU) that conform to the disclosed embodiments may be used to perform.

[0040] The GPU can process multiple types of data or data packets in the GPU pipeline. For example, in some aspects, the GPU can process two types of data or data packets, such as context register packets and draw call data. The context register packet can be a set of global state information, such as information about global registers, shaders, or constant data, which can adjust how the graphics context will be processed. For example, the context register packet can include information about the color format. In some aspects of the context register packet, there can be a bit indicating which workload belongs to the context register. In addition, multiple functions or programs can be run simultaneously and / or in parallel. For example, a function or program can describe an operation, such as a color mode or color format. Therefore, the context register can define multiple states of the GPU.

[0041] The context state may be used to determine how a single processing unit (e.g., a vertex fetcher (VFD), a vertex shader (VS), a shader processor, or a geometry processor) operates and / or in which mode the processing unit operates. To do this, the GPU may use context registers and programming data. In some aspects, the GPU may generate workloads, such as vertex or pixel workloads, in a pipeline based on context register definitions of a mode or state. Certain processing units (e.g., VFDs) may use these states to determine certain functions, such as how to aggregate vertices. Since these modes or states may change, the GPU may need to change the corresponding context. In addition, the workload corresponding to the mode or state may follow the changed mode or state.

[0042] Figure 2 2 illustrates an exemplary GPU 200 in accordance with one or more techniques of this disclosure. Figure 2 As shown, GPU 200 includes a command processor (CP) 210, a draw call group 212, a VFD 220, a VS 222, a vertex cache (VPC) 224, a triangle setup engine (TSE) 226, a rasterizer (RAS) 228, a Z-pass engine (ZPE) 230, a pixel interpolator (PI) 232, a fragment shader (FS) 234, a rendering back end (RB) 236, an L2 cache (UCHE) 238, and a system memory 240. Although Figure 2 The GPU 200 is shown to include processing units 220 to 238, but the GPU 200 may include multiple additional processing units. In addition, the processing units 220 to 238 are only examples, and any combination or order of processing units may be used by the GPU according to the present disclosure. The GPU 200 also includes a command buffer 250, a context register group 260, and a context state 261.

[0043] like Figure 2As shown, the GPU may utilize a CP (e.g., CP 210) or a hardware accelerator to parse the command buffer into context register packets (e.g., context register packets 260) and / or draw call data packets (e.g., draw call packets 212). The CP 210 may then send the context register packets 260 or the draw call data packets 212 to a processing unit or block in the GPU via a separate path. Further, the command buffer 250 may alternate different states of context registers and draw calls. For example, the command buffer may be constructed in the following manner: context registers of context N, draw calls of context N, context registers of context N+1, and draw calls of context N+1.

[0044] Figure 3 300 is a diagram illustrating exemplary components (such as a processing unit 120 and a system memory 124) that may be identified in conjunction with a device 104 for processing data in accordance with one or more aspects of the present disclosure. In various aspects, the processing unit 120 may include a CPU 302 and a GPU 312. The GPU 312 and the CPU 302 may be formed as integrated circuits (e.g., a system on a chip (SOC)) and / or the GPU 312 may be incorporated into a motherboard having the CPU 302. Alternatively, the CPU 302 and the GPU 312 may be configured as different processing units that are communicatively coupled to each other. For example, the GPU 312 may be incorporated on a graphics card mounted in a port of a motherboard including the CPU 302.

[0045] The CPU 302 may be configured to execute a software application. The software application causes the display of graphical content (e.g., on the display 131 of the device 104) based on one or more operations of the GPU 312. The software application may issue instructions to a graphics application program interface (API) 304, which may be a runtime program that translates instructions received from the software application into a format that can be read by the GPU driver 310. After receiving instructions from the software application via the graphics API 304, the GPU driver 310 may control the operation of the GPU 312 based on the instructions. For example, the GPU driver 310 may generate one or more command streams placed in the system memory 124, in which the GPU 312 is instructed to execute the command stream (e.g., via one or more system calls). A command engine 314 included in the GPU 312 is configured to retrieve one or more commands stored in the command stream. The command engine 314 may provide commands from the command stream for execution by the GPU 312. The command engine 314 may be hardware of the GPU 312, software / firmware executed on the GPU 312, or a combination thereof. Although GPU driver 310 is configured to implement graphics API 304, GPU driver 310 is not limited to being configured according to any particular API. System memory 124 may store code for GPU driver 310, which CPU 302 may retrieve for execution. In an example, GPU driver 310 may be configured to allow communication between CPU 302 and GPU 312, such as when CPU 302 offloads graphics or non-graphics processing tasks to GPU 312 via GPU driver 310.

[0046] The system memory 124 may further store source code for one or more of the early preamble shader 324, the feedback shader 325, or the primary shader 326. In such a configuration, the shader compiler 308 executing on the CPU 302 may compile the source code of the shaders 324-326 to create an object code or intermediate code that can be executed by the shader core 316 of the GPU 312 during runtime (e.g., when the shaders 324-326 are to be executed on the shader core 316). In some examples, the shader compiler 308 may precompile the shaders 324-326 and store the object code or intermediate code of the shader program in the system memory 124. The shader compiler 308 executing on the CPU 302 (or in another example, the GPU driver 310) may create a shader program having multiple components, including the early preamble shader 324, the feedback shader 325, and the primary shader 326. The main shader 326 may correspond to a portion or all of a shader program that does not include the preamble shader 324 or the feedback shader 325. The shader compiler 308 may receive instructions to compile the shaders 324 to 326 from a program executed on the CPU 302. The shader compiler 308 may also identify constant load instructions and common operations in the shader program for including the common operations in the early preamble shader 324 (rather than the main shader 326). The shader compiler 308 may, for example, identify such common instructions based on a (currently undetermined) constant 306 to be included in the common instruction. The constant 306 may be defined in the graphics API 304 as a constant across the entire draw call. The shader compiler 308 may utilize instructions such as a preamble shader start to indicate the start of the early preamble shader 324 and a preamble shader end to indicate the end of the early preamble shader 324. Similar instructions may be used for the feedback shader 325 and the main shader 326. The feedback shader 325 will be described in further detail below.

[0047] The shader core 316 included in the GPU 312 may include a general purpose register (GPR) 318 and a constant memory 320. The GPR 318 may correspond to a single GPR, a GPR file, and / or a GPR library. Each of the GPRs 318 may store data accessible by a single thread. The software and / or firmware executed on the GPU 312 may be a shader program 324 to 326, which may be executed on the shader core 316 of the GPU 312. The shader core 316 may be configured to execute many instances of the same instructions of the same shader program in parallel. For example, the shader core 316 may execute a main shader 326 for each pixel defining a given shape. The shader core 316 may send and receive data from an application executed on the CPU 302. In an example, constants 306 for the execution of the shaders 324 to 326 may be stored in a constant memory 320 (e.g., read / write constant RAM) or in the GPR 318. The shader core 316 may load the constants 306 into a constant memory 320. In further examples, execution of the early preamble shader 324 or the feedback shader 325 may cause a constant value or set of constant values ​​to be stored in an on-chip memory such as the constant memory 320 (e.g., constant RAM), GPU memory 322, or system memory 124. The constant memory 320 may include memory accessible by all aspects of the shader core 316, rather than just specific portions (such as values ​​stored in the GPR 318) that are reserved for specific threads.

[0048] Figure 4 An example GPU 400 according to one or more aspects of the present disclosure is illustrated. Specifically, Figure 4 The stream processor (SP) system in GPU 400 is illustrated. Figure 4 As shown, GPU 400 includes a high level sequencer (HLSQ) 402, a texture processor (TP) 406, a secondary cache (UCHE) 408, a rendering backend (RB) 410, and a vertex cache (VPC) 412. GPU 400 also includes SP 420, a main engine 422, a sequencer 424, a local buffer 426, a wave scheduler 428, a texture sampling instruction decoder / controller (TEX) 430, an instruction cache 432, an arithmetic logic unit (ALU) 434, a GPR 436, a dispatcher 438, and a memory (MEM) load store (LDST) 440.

[0049] like Figure 4As shown, each unit or block in GPU 400 can transmit data or information to other blocks. For example, HLSQ 402 can transmit commands to main engine 422. In addition, HLSQ 402 can transmit vertex threads, vertex attributes, pixel threads, pixel attributes and / or calculation commands to sequencer 424. TP 406 can receive texture requests from TEX 430 and transmit texture elements (texture elements) back to TEX 430. In addition, TP 406 can transmit memory read requests to UCHE 408 and receive memory data from the UCHE. UCHE 408 can also receive memory read or write requests from MEM LDST 440 and transmit memory data back to MEM LDST 440, and receive memory read or write requests from RB 410 and transmit memory data back to RB 410. In addition, RB 410 can receive output in the form of color from GPR 436, for example, via dispatcher 438. VPC 412 may also receive output in the form of vertices from GPR 436, for example, via dispatcher 438. GPR 436 may transmit address data or receive write-back data from MEM LDST 440. GPR 436 may also transmit temporary data to and receive temporary data from ALU 434. In addition, ALU 434 may transmit address or predicate information to wave scheduler 428 and receive instructions from wave scheduler 428. Local buffer 426 may transmit constant data to ALU 434. TEX 430 may also receive texture attributes from or transmit texture data to GPR 436 and receive constant data from local buffer 426. In addition, TEX 430 may receive texture requests from wave scheduler 428 and receive constant data from local buffer 426. MEM LDST 440 may transmit constant data to / receive constant data from local buffer 426. The sequencer 424 may pass wave data to the wave scheduler 428, as well as pass data to the GPR 436. The sequencer 424 may allocate resources and local memory. In addition, the sequencer 424 may allocate wave slots and any associated GPR 436 space. For example, when the HLSQ 402 issues a pixel tile workload to the SP 420, the sequencer 424 may allocate a wave slot or GPR 436 space. The main engine 422 may pass program data to the instruction cache 432, as well as pass constant data to the local buffer 426 and receive instructions from the MEM LDST 440. The instruction cache 432 may pass instructions or decode information to the wave scheduler 428. The wave scheduler 428 may pass read requests to the local buffer 426, as well as pass memory requests to the MEM LDST 440.

[0050] like Figure 4As further shown, HLSQ 402 may prepare one or more context states for SP 420. For example, HLSQ 402 may prepare context states for different types of data, such as global register data, shader constant data, buffer descriptors, instructions, etc. In addition, HLSQ 402 may embed context states into command streams to SP 420. Main engine 422 may parse command streams from HLSQ 402 and set SP global states. In addition, main engine 422 may fill or add to instruction cache 432 and / or local buffer 426 or constant buffers. In some aspects, inside HLSQ 402, there may be an internal functional unit called state processor 402a. State processor 402a may be a single-fiber scalar processor that can execute special shader programs (e.g., preamble shaders). Preamble shaders may be generated by a GPU compiler to load constant data from different buffer objects. In addition, preamble shaders may bind buffer objects to a single constant buffer, such as a post-processing constant buffer. In addition, the HLSQ 402 may execute the preamble shader and thus skip utilizing the main shader. In some instances, the main shader may perform different shading tasks, such as normal vertex shading and / or fragment shading programs. In addition, the HLSQ 402 may include a data packer 402b.

[0051] In addition, if Figure 4 As shown, if HLSQ 402 decides to skip the preamble execution, SP 420 may not be limited to executing the preamble. For example, SP 420 may also process conventional graphics workloads, such as vertex shading and / or fragment shading. In some aspects, SP 420 may utilize its execution units and storage to process computing tasks as a general-purpose GPU (GPGPU). Inside SP 420, there may be multiple parallel instruction execution units, such as ALU, elementary function unit (EFU), branch unit, TEX, general memory read and write (also known as LDST), etc. SP 420 may also include on-chip storage memory, such as GPR 436 that can store per-fiber private data. In addition, SP 420 may include a local buffer 426 that stores per-shader or per-kernel constant data, per-wave uniform constants (also known as uGPRs), and per-compute workgroup (WG) local memory (LM). Processing the preamble shader may occupy one wave slot. Furthermore, most preamble shaders may use only uGPRs and no GPRs, and may execute ALU instructions on scalar ALUs. Thus, execution of preamble shaders may be associated with high performance and may be power efficient, since any available slot may be used to execute the preamble shader even without GPR space allocation.

[0052] In addition, if Figure 4As shown, the dispatcher 438 can extract data from the GPR 436. The dispatcher 438 can also perform format conversion and then dispatch the final color to multiple rendering targets (RTs). Each RT can have one or more components, such as red (r), green (G), blue (B), alpha (A) (RGBA) data, or only the alpha component of the RGBA data. In addition, each RT can generally be stored in a vector GPR, that is, R3.0 can store red data, R3.1 can store green data, R3.2 can store blue data, etc. In addition, the driver program in the SP context register can be used to define the GPR identifier (ID) in which the RT data is stored.

[0053] In some use cases associated with graphics applications, the final result or intermediate results of an operation (e.g., a "blending" operation, i.e., a two-factor multiplication, i.e., A*B) may depend on results from multiple possible previous operations. For example, for a result that can be calculated with result=a*b, each of operands a and b may be generated based on one or more of a sampling operation, a memory load operation, or a highly complex mathematical operation. In some cases, many operands for multiplication operations may be equal to 0.0. Other operations that perform texture fetches (for which the SP may issue a sampling instruction to the TP, and the TP may read the texture buffer, perform filtering, and return the result to the SP) or other operands for multiplication operations where one of these operands is equal to 0.0 may represent wasted time, energy, and execution resources.

[0054] Figure 5 is a diagram illustrating an example shader program 500 according to one or more aspects of the present disclosure. Figure 5 As shown in lines 17 and 18 of , the result of the variable output.xyz may depend on the values ​​of 4 products (the results of the multiplication operations), where each of the 4 products involves multiplying the illuminance value by the radius value. In addition, the illuminance value and the radius value may be the results from texture extraction and post-processing operations.

[0055] Fig. 6A 600 is a diagram illustrating an example radius value graph 600 according to one or more aspects of the present disclosure. The illustrated example radius values ​​may correspond to Figure 5 The shader program in the associated input. Fig. 6AIn the illustrated example, all radius (component) values ​​may be similar. In particular, the radius value may be 0.0, where the radius value graph 600 is dark (black in color). Therefore, in the light (non-black) area of ​​the radius value graph 600, the radius value may not be 0.0. Therefore, for light areas, it may be beneficial to extract both the illumination texture and the radius texture as a group in order to reduce the texture extraction latency. On the other hand, for dark areas, it may be beneficial to emit the radius texture first. Then, once the radius value is confirmed to be equal to 0.0, the corresponding illumination texture extraction and subsequent post-processing can be skipped, because regardless of the actual illumination value, the product is known to be 0.0. Therefore, by skipping texture extraction, subsequent post-processing associated with the illumination texture, the workload can be reduced and the performance at the GPU can be improved.

[0056] Figure 6B 6 is a diagram illustrating an example tile radius value map 650 according to one or more aspects. In the tile radius value map 650, each tile may include a large number (e.g., hundreds of thousands) of pixels that may be dispatched to one or more SPs. Each tile may be further divided into sub-tiles (also referred to as batches) (e.g., each batch may include 1000 pixels), so that for sub-tiles that are mostly light (e.g., >50% light, >60% light, etc.), the SP may collect a radius value profile at a batch (e.g., batch N) (the profile may indicate whether the radius value is equal to 0.0 and for most light sub-tiles, the indicated radius value may be negative), and may predict the next batch (e.g., batch N+1) based on the radius value profile, because the radius value profile may indicate that the pixels in the next batch are more likely to be light, so it may be beneficial to issue all sampling (texture fetch) instructions for both illumination and radius as a group so that memory fetch latency can be reduced or minimized. On the other hand, in most dark (e.g., >50% dark, >60% dark, etc.) sub-tiles, the SP may also collect a radius value profile at a batch (e.g., batch M) (the profile may indicate whether the radius value is equal to 0.0 and the indicated radius value may be positive for most dark sub-tiles), and may predict the next batch (e.g., batch M+1) based on the radius value profile, because the radius value profile may indicate that the pixels in the next batch are more likely to be dark, so it may be beneficial to first process the radius texture, generate a pixel execution disable mask based on the radius texture (the mask may disable further pixel illumination operations where the radius value associated with the pixel is equal to 0.0), and skip the corresponding pixel illumination operations based on the pixel execution disable mask.

[0057] Textures of pixels that are close to each other may have a correlation, which may be referred to as spatial coherence. In one or more aspects, hardware and software adaptations may be performed to exploit spatial coherence to predict optimized shader execution flows. Within GPU hardware, the SP may be configured to collect instruction execution feedback and generate feedback predictions. The power and / or chip area impact associated with feedback collection and prediction generation functionality may be minimized. In one or more configurations, zero value detection logic (i.e., multiplication of floating point numbers) within a floating multiplication (FMUL) unit in a SP single instruction multiple data (SIMD) ALU (in the case where any operand of the FMUL is equal to 0.0, the zero value detection logic may help skip the multiplication operation to save power) may be adjusted for use as a feedback strobe, so that the number of texture values ​​(e.g., illumination or radius values) equal to 0.0 may be counted (accumulated). More specifically, the feedback strobe may refer to feedback logic that may collect samples of texture values ​​of 0.0 from a multiplication unit (e.g., FMUL unit) input operand. A count of a batch of texture values ​​of 0.0 may be used to generate a texture value profile for the batch.

[0058] Furthermore, in one or more configurations, by leveraging an existing preamble shader scheme, the SP may generate a feedback prediction by executing a feedback shader (eg, feedback shader 325 ).

[0059] In one or more configurations, a prediction sampling interval may be defined. Thus, prediction generation may be based on sampling intervals, where each sampling interval may correspond to a batch (e.g., a batch of waves). In one or more configurations, sampling intervals or batches may be specified in multiple waves (e.g., 16 waves or equivalent sampling instances) (a wave may be a collection of threads such as pixels, vertices, or work items).

[0060] In one or more configurations, predictions generated based on feedback collected in a current batch may be used to optimize the flow of shader program execution for one or more batches in a subsequent batch. In one or more configurations, feedback collected from one previous batch or multiple previous batches (e.g., 2-4 previous batches) may be used to generate predictions for subsequent batches. In one configuration, the GPU may assign different weights to feedback collected in different previous batches, wherein earlier batches may be assigned lower weights so that feedback collected from earlier batches may have less impact on the flow of execution of subsequent batches. For example, if feedback collected from 4 previous batches is used, batch N-3 (i.e., 3 batches before the current batch) may be assigned a weight of 1 / 8, batch N-2 (i.e., 2 batches before the current batch) may be assigned a weight of 1 / 4, batch N-1 (i.e., the batch immediately before the current batch) may be assigned a weight of 5 / 8, and batch N (the current batch) may be assigned a weight of 1.

[0061] In one or more configurations, a compiler (e.g., shader compiler 308) may specify (specify) instruction operands to collect feedback. Thus, compiled shader programs may utilize hardware-generated feedback predictions to optimize shader program execution flow on a batch-by-batch basis. Herein, a shader program may refer to a user-defined program that may be run on one or more stages of a graphics processor.

[0062] Figure 7 7 is a block diagram illustrating an example process 700 for performing flow optimization of a shader program according to one or more aspects of the present disclosure. A feedback (FB) controller 702 may be provided in the SP. In particular, the FB controller 702 may include one or more groups of counters (FB_counter) (e.g., 8 counters per group, including FB_counter[0] to FB_counter[7], wherein each counter may include 32 bits (e.g., bits [31:0])) and one or more groups of context registers (FB_pred) for each shader slot (e.g., 4 bits per group) to accommodate parallel execution of multiple shader programs at the SP. The main engine 704 may instruct the FB controller 702 to enable feedback collection and prediction value calculation. At the beginning of a wave, each SP wave slot (Hwave) (i.e., hardware storage for waves and associated logic to store states from shader program execution) or execution slot (Eslot) (i.e., hardware logic for waves to execute shader programs) (when a shader program is to be executed, the SP may assign an execution slot to install shader program states and execute the shader program) may copy a prediction value. Herein, the prediction value may be a logical value generated from the shader program execution analysis result, and may typically be a single bit stored in a context register FB_pred, i.e., 0 or 1. In other words, the value of the context register FB_pred may be copied to ensure that the value remains consistent throughout the wave execution cycle.

[0063] In one example configuration, the SP (specifically, the FB controller 702) may use counter FB_counter[0] to collect counts of instances where the illumination value is equal to 0.0 (in this example, the illumination value may come from FMUL source operand 0 (src0) at SIMD ALU 706), and may use counter FB_counter[1] to collect counts of instances where the radius value is equal to 0.0 (in this example, the radius value may come from FMUL source operand 1 (src1) at SIMD ALU 706), and may use counter FB_counter[2] to collect counts of instances where a specified multiplication operation (i.e., output = illumination * radius) is performed. Furthermore, in this example, each batch may include 16 waves. In other words, the sampling interval (SAMPLE_INTERVAL) may be 16 waves. Thus, once a wave begins executing, the SP may detect instances where one or both of the operands of the specified FMUL instruction / operation (illuminance*radius) are equal to 0.0, and may update the counters FB_counter[0] and FB_counter[1] accordingly. Additionally, each time the specified FMUL instruction / operation (illuminance*radius) is executed, the SP may increment the counter FB_counter[2] by 1. Thus, the FB controller 702 may detect the end of a batch based on the value of the counter FB_counter[2] reaching 16. Upon detecting the end of a batch, the FB controller 702 may request the sequencer 708 of the SP to allocate an empty wave slot in which the feedback shader may be executed. In addition, the FB controller 702 may copy the values ​​of the counters FB_counter[n] (e.g., FB_counter[0] and FB_counter[1]) to the corresponding uGPR 710 (e.g., uGPR[n]), and may reset the counters FB_counter[n] (e.g., FB_counter[0] to FB_counter[2]) to 0, so that the counters FB_counter[n] may be ready for the next batch of profile data collection. Next, the wave scheduler 712 of the SP may execute the feedback shader, which may include issuing a scalar instruction to a scalar ALU (SALU) 714, where a prediction value FB_pred may be calculated. Once the context register FB_pred is updated at the FB controller 702, the wave scheduler 712 may abandon the wave slot associated with the feedback shader. Thereafter, at the start of a new wave, the wave slot may read (sample) the current value of the per-shader slot context register FB_pred from the FB controller 702 and may copy that value to the per-wave slot FB_pred context register to ensure that the value remains consistent throughout the wave execution cycle.

[0064] In one or more configurations, the compiler may append the feedback shader after the early preamble shader, and may use a feedback shader start (FBSS) and feedback shader end (FBSE) instruction pair to indicate the start and end of the feedback shader. Since the feedback shader is part of the shader code, the compiler may store the feedback shader offset in a context register to indicate to the GPU hardware the memory location where the feedback shader can be retrieved. Below is an example shader structure, where the double slashes ( / / ) may be followed by comments or explanations.

[0065] shs / / Early preamble (EP) shader starts

[0066] {EP} / / EP

[0067] she / / EP shader ends

[0068] FBSS / / FB shader (FBS) starts, FBS_offset pointer

[0069] {FBS} / / FBS

[0070] FBSE / / FBS End

[0071] {Main} / / Main shader

[0072] In addition, instructions for executing the feedback shader are summarized in Table 1 below. In addition, the SALU 714 may be configured such that the SALU 714 can write a feedback prediction value (ie, FB_pred value) to a context register FB_pred at the FB controller 702 .

[0073]

[0074] Table 1. Instructions for feedback shaders

[0075] Figure 8 800 according to one or more aspects. The execution flow of the shader program 800 can be adjusted based on the predicted value. In particular, the subroutine Label_PROG_A ( Figure 8 31-41 in the subroutine) may involve texture fetch and post-processing operations for the radius texture. The subroutine Label_PROG_B (lines 43-48) may involve texture fetch operations for the illumination texture. In addition, the subroutine label_PROG_C (lines 50-55) may involve the calculation of the final output, where the specified FMUL operation is performed at lines 52-53. The feedback may be collected at line 51 using the instruction collect_FB.

[0076] Based on the code at lines 6-13, if it is determined at line 7 that the prediction value (FB_pred[0]) associated with the illumination texture is 1 (which may indicate that the illumination value is equal to 0.0 in one or more previous batches in a large number of instances), and it is determined at line 9 that the illumination value of the current pixel is equal to 0.0, then the subroutine Label_PROG_B associated with the texture fetch operation for the illumination texture may be skipped.

[0077] In addition, if it is determined at line 7 that the prediction value (FB_pred[0]) associated with the illuminance texture is 0 (which may indicate that the illuminance value is equal to 0.0 in one or more previous batches in a case where there are few or no instances), the program can jump to subroutine Label_PASS1 (lines 15-23), where if it is determined at line 17 that the prediction value (FB_pred[1]) associated with the radius texture is 1 (which may indicate that the radius value is equal to 0.0 in one or more previous batches in a large number of instances), and it is determined at line 19 that the radius value of the current pixel is equal to 0.0, the subroutine Label_PROG_A associated with texture extraction and post-processing operations for the radius texture can be skipped.

[0078] Additionally, if it is determined at line 17 that the prediction value associated with the radius texture (FB_pred[1]) is 0 (which may indicate that in few or no instances, the radius value was equal to 0.0 in one or more previous batches), the program may jump to subroutine Label_PASS2 (lines 25-29). Under the control of subroutine Label_PASS2, all of subroutines Label_PROG_A, Label_PROG_B, and Label_PROG_C may be executed in the following order. Thus, the example shader program 800 illustrates that the prediction results from the previous batch may change the execution flow of the shader program for the next batch. The example shader program 800 may be functionally equivalent to Figure 5 However, based on the optimized execution flow, the example shader program 800 is comparable to the example shader program 500 in FIG. Figure 5 The example shader program 500 is executed in a more resource efficient manner.

[0079] In one or more configurations, the compiler may generate a store_FB instruction at the start of a feedback shader. The SP hardware may write feedback data from the uGPR to driver-allocated memory in an incremental manner. The driver (e.g., GPU driver 310) may analyze the feedback data to recompile the shader and update the shader with an optimized execution flow based on specific operand feedback data. Alternatively, in some configurations, the compiler may simply disable feedback shader execution if there is no optimization opportunity.

[0080] In one or more configurations, the compiler may utilize SIMD ALU FMUL operand 0.0 detection logic to detect any specified value (e.g., detect whether the value of register R0.0 is equal to 1.0) based on detecting whether the difference between the register value and the specified value is equal to 0.0. For example, to detect whether the value of register R0.0 is equal to 1.0, the compiler may generate the following instruction sequence

[0081] Fadd R1.0, R0.0, -1.0; / / store (the value of R0.0 + (-1.0)) into R1.0

[0082] Collect_FB;

[0083] Fmul R63.0,R1.0,R1.0; / / Write to dummy register (no write)

[0084] / / Call FMUL operand 0.0 detection logic

[0085] Thus, the above code can be used to collect a larger range of feedback from an initial profile. Then, some or all of the feedback collection code can be eliminated after the driver has collected feedback and recompiled the shader code.

[0086] Therefore, one or more aspects may relate to compiler execution sequence optimization based on hardware-enabled dynamic feedback results. Data patterns can be analyzed and utilized so that redundant or unnecessary shader operations can be skipped. In addition, different SPs or different batches of an SP can execute different shader sequences. This is more efficient than using a static execution flow across all SPs. The chip area and power overhead costs are negligible. For example, if the first batch of 1000 pixels is mostly light-colored, the feedback prediction value may be false ("0"). Then, for the second batch of 1000 pixels, the shader program may issue texture instructions together to calculate illumination and radius values. On the other hand, if the first batch is mostly dark, the feedback prediction value may be true ("1"). Therefore, for the second batch, the shader program may issue texture instructions to calculate the radius. If the radius value is not zero, the shader program may issue a texture sampling instruction to extract illumination data. If the radius value is zero, the texture sampling instruction may be skipped.

[0087] Fig. 99 is a call flow diagram 900 illustrating example communications between GPU component 902, GPU component 904, and memory 906 in accordance with one or more techniques of this disclosure. At 910, GPU component 902 may obtain instruction execution data 912 (results from shader instruction execution) (e.g., feedback data) associated with a graphics workload (a collection of pixels or vertices from a 3D draw call or a collection of work items from a compute kernel of a graphics processor) (e.g., vertex shading, fragment shading, etc.) from GPU component 904. The instruction execution data may include graphics data for a set of shader operations (shader program execution).

[0088] In one configuration, the graphics data for the set of shader operations may include at least one of: lighting data, illuminance data, depth data, shadow data, or radius data.

[0089] In one configuration, the instruction execution data may be obtained based on a FMUL unit of the GPU.The at least one prediction value configured at the first iteration may indicate a likelihood of occurrence of a condition of the graphics workload of the second iteration.

[0090] In one configuration, the set of shader operations may include a set of multiplication operations for a graphics workload.

[0091] At 920, GPU component 902 may configure at least one prediction value based on instruction execution data including graphics data for the set of shader operations at a first iteration (i.e., a first batch). The at least one prediction value may indicate a likelihood of occurrence of a condition of the graphics workload (e.g., a likelihood that a radius value for a batch is 0.0). The condition of the graphics workload may be associated with a stream processor of the GPU.

[0092] At 920a, to configure the at least one prediction value, the GPU component 902 can generate the at least one prediction value based on at least one of a shader preamble, a feedback shader, or a batch of data for a graphics workload.

[0093] In one configuration, the at least one prediction value may be a 1-bit value. For example, the 1-bit value may indicate whether the likelihood of the condition occurring is greater than a threshold likelihood.

[0094] At 930, GPU component 902 may adjust an execution flow of the graphics workload based on the configured at least one prediction value at a second iteration (i.e., a second batch) after the first iteration and without changing the functionality or results of the graphics workload. The execution flow of the graphics workload may include the set of shader operations.

[0095] At 930a, to adjust the execution flow of the graphics workload, the GPU component 902 can load the set of shader operations for the plurality of shader programs.

[0096] At 930b, the GPU component 902 can combine each shader program of the plurality of shader programs based on the loaded set of shader operations (eg, the compiler can append a feedback shader after an early preamble shader).

[0097] In one configuration, the execution flow of the graphics workload may correspond to a shader sequence of the plurality of shader programs.

[0098] At 940 , GPU component 902 may, at a second iteration, execute or refrain from executing each shader operation in the set of shader operations based on the adjusted execution flow of the graphics workload.

[0099] At 940a, to execute each shader operation in the set of shader operations, the GPU component 902 may execute one or more shader operations in the set of shader operations based on the adjusted execution flow of the graphics workload.

[0100] At 940b, to refrain from executing each shader operation in the set of shader operations, the GPU component 902 may skip at least one shader operation in the set of shader operations based on the adjusted execution flow of the graphics workload.

[0101] At 950 , the GPU component 902 can update or maintain a configuration of a shader processor or stream processor at the GPU based on executing or refraining from executing each shader operation in the set of shader operations.

[0102] At 960 , the GPU component 902 may store data 962 (eg, feedback data) associated with each shader operation in the set of shader operations to the memory 906 when executing or refraining from executing each shader operation in the set of shader operations.

[0103] In one configuration, data 962 may be stored in at least one of: system memory, double data rate (DDR) RAM, constant memory, or on-chip memory.

[0104] Fig.10 1000 is a flowchart of an example method of graphics processing according to one or more techniques of the present disclosure. The method may be performed by a device such as: a device for graphics processing, a GPU, a CPU, a wireless communication device, etc. (such as a combination of Figures 1 to 9 used in various aspects).

[0105] At 1002, the apparatus may obtain instruction execution data associated with a graphics workload. The instruction execution data may include graphics data for a set of shader operations. For example, referring to Fig. 9 At 910 , GPU component 902 may obtain instruction execution data 912 associated with a graphics workload from GPU component 904 . Additionally, 1002 may be performed by processing unit 120 .

[0106] At 1004, the apparatus may configure at least one prediction value based on instruction execution data including graphics data for the set of shader operations at a first iteration. The at least one prediction value may indicate a likelihood of occurrence of a graphics workload condition. The graphics workload condition may be associated with a stream processor of a GPU. For example, referring to Fig. 9 At 920 , GPU component 902 may configure at least one prediction value based on instruction execution data including graphics data for the set of shader operations at a first iteration. Additionally, step 1004 may be performed by processing unit 120 .

[0107] At 1006, the apparatus may adjust an execution flow of the graphics workload based on the configured at least one prediction value at a second iteration after the first iteration and without changing a function or result of the graphics workload. The execution flow of the graphics workload may include the set of shader operations. For example, referring to Fig. 9 At 930 , GPU component 902 may adjust the execution flow of the graphics workload based on the configured at least one prediction value at a second iteration after the first iteration and without changing the function or result of the graphics workload. Additionally, 1006 may be performed by processing unit 120 .

[0108] At 1008, the device may, at a second iteration, execute or refrain from executing each shader operation in the set of shader operations based on the adjusted execution flow of the graphics workload. Fig. 9 At 940 , GPU component 902 may execute or refrain from executing each shader operation in the set of shader operations based on the adjusted execution flow of the graphics workload at the second iteration. Additionally, 1008 may be performed by processing unit 120 .

[0109] Fig.11 1100 is a flowchart of an example method of graphics processing according to one or more techniques of the present disclosure. The method may be performed by a device such as: a device for graphics processing, a GPU, a CPU, a wireless communication device, etc. (such as a combination of Figures 1 to 9 used in various aspects).

[0110] At 1102, the apparatus may obtain instruction execution data associated with a graphics workload. The instruction execution data may include graphics data for a set of shader operations. For example, referring to Fig. 9 At 910 , GPU component 902 may obtain instruction execution data 912 associated with a graphics workload from GPU component 904 . Additionally, 1102 may be performed by processing unit 120 .

[0111] At 1104, the apparatus may configure at least one prediction value based on instruction execution data including graphics data for the set of shader operations at a first iteration. The at least one prediction value may indicate a likelihood of occurrence of a graphics workload condition. The graphics workload condition may be associated with a stream processor of a GPU. For example, referring to Fig. 9 At 920 , GPU component 902 may configure at least one prediction value based on instruction execution data including graphics data for the set of shader operations at a first iteration. Additionally, 1104 may be performed by processing unit 120 .

[0112] At 1106, the apparatus may adjust an execution flow of the graphics workload based on the configured at least one prediction value at a second iteration after the first iteration and without changing a function or result of the graphics workload. The execution flow of the graphics workload may include the set of shader operations. For example, referring to Fig. 9 At 930 , GPU component 902 may adjust the execution flow of the graphics workload based on the configured at least one prediction value at a second iteration after the first iteration and without changing the function or result of the graphics workload. Additionally, 1106 may be performed by processing unit 120 .

[0113] At 1108, the device may, at a second iteration, execute or refrain from executing each shader operation in the set of shader operations based on the adjusted execution flow of the graphics workload. Fig. 9 At 940 , GPU component 902 may execute or refrain from executing each shader operation in the set of shader operations based on the adjusted execution flow of the graphics workload at the second iteration. Additionally, 1108 may be performed by processing unit 120 .

[0114] In one configuration, the graphics data for the set of shader operations may include at least one of: lighting data, illuminance data, depth data, shadow data, or radius data.

[0115] In one configuration, the instruction execution data may be obtained based on a FMUL unit of the GPU.The at least one prediction value configured at the first iteration may indicate a likelihood of occurrence of a condition of the graphics workload of the second iteration.

[0116] In one configuration, the set of shader operations may include a set of multiplication operations for a graphics workload.

[0117] In one configuration, the at least one predicted value may be a 1-bit value.

[0118] In one configuration, to configure the at least one prediction value, at 1104a, the device may generate the at least one prediction value based on at least one of a shader preamble, a feedback shader, or a batch of data for a graphics workload. Fig. 9 At 920a, the GPU component 902 may generate the at least one prediction value based on at least one of a shader preamble, a feedback shader, or a batch of data for a graphics workload. In addition, 1104a may be performed by the processing unit 120.

[0119] In one configuration, to adjust the execution flow of the graphics workload, at 1106a, the device may load the set of shader operations for the plurality of shader programs. Fig. 9 At 930a, the GPU component 902 may load the set of shader operations for the plurality of shader programs. Additionally, 1106a may be performed by the processing unit 120.

[0120] At 1106b, the device may combine each of the plurality of shader programs based on the loaded set of shader operations. Fig. 9 At 930 b , the GPU component 902 may combine each of the plurality of shader programs based on the loaded set of shader operations. Additionally, 1104 b may be performed by the processing unit 120 .

[0121] In one configuration, the execution flow of the graphics workload may correspond to a shader sequence of the plurality of shader programs.

[0122] In one configuration, to execute each shader operation in the set of shader operations, at 1108a, the apparatus may execute one or more shader operations in the set of shader operations based on the adjusted execution flow of the graphics workload. Fig. 9 At 940a, GPU component 902 may perform one or more shader operations in the set of shader operations based on the adjusted execution flow of the graphics workload. In addition, 1108a may be performed by processing unit 120.

[0123] In one configuration, to refrain from executing each shader operation in the set of shader operations, at 1108b, the device may skip at least one shader operation in the set of shader operations based on the adjusted execution flow of the graphics workload. Fig. 9At 940b, GPU component 902 may skip at least one shader operation in the set of shader operations based on the adjusted execution flow of the graphics workload. In addition, 1108b may be performed by processing unit 120.

[0124] In one configuration, at 1110, the device may update or maintain a configuration of a shader processor or stream processor at the GPU based on executing or refraining from executing each shader operation in the set of shader operations. Fig. 9 At 950 , the GPU component 902 may update or maintain a configuration of a shader processor or stream processor at the GPU based on executing or refraining from executing each shader operation in the set of shader operations. Additionally, 1110 may be performed by the processing unit 120 .

[0125] In one configuration, at 1112, the device may store data associated with each shader operation in the set of shader operations when executing or refraining from executing each shader operation in the set of shader operations. Fig. 9 At 960, the GPU component 902 may store data 962 associated with each shader operation in the set of shader operations to the memory 906 when executing or refraining from executing each shader operation in the set of shader operations. In addition, 1112 may be performed by the processing unit 120.

[0126] In one configuration, data may be stored in at least one of: system memory, DDR RAM, constant memory, or on-chip memory.

[0127] In the configuration, a method or apparatus for graphics processing is provided. The apparatus may be a GPU, a CPU, or some other processor that can perform graphics processing. In various aspects, the apparatus may be a processing unit 120 within a device 104, or may be some other hardware within the device 104 or another device. The apparatus may include a component for the following operations: obtaining instruction execution data associated with a graphics workload, the instruction execution data including graphics data for a set of shader operations. The apparatus may also include a component for the following operations: at a first iteration, configuring at least one prediction value based on the instruction execution data including the graphics data for the set of shader operations. The at least one prediction value may indicate the likelihood of occurrence of a condition of the graphics workload. The condition of the graphics workload may be associated with a stream processor of a GPU. The apparatus may also include a component for the following operations: at a second iteration after the first iteration and without changing the function or result of the graphics workload, adjusting the execution flow of the graphics workload based on the configured at least one prediction value. The execution flow of the graphics workload may include the set of shader operations. The apparatus may also include means for, at a second iteration, executing or refraining from executing each shader operation in the set of shader operations based on the adjusted execution flow of the graphics workload.

[0128] In one configuration, the graphics data for the group of shader operations may include at least one of the following: lighting data, illumination data, depth data, shadow data, or radius data. In one configuration, the instruction execution data may be obtained based on the FMUL unit of the GPU. The at least one prediction value configured at the first iteration may indicate the likelihood of occurrence of a condition of the graphics workload of the second iteration. In one configuration, the group of shader operations may include a group of multiplication operations for the graphics workload. In one configuration, the at least one prediction value may be a 1-bit value. In one configuration, the component for configuring the at least one prediction value may be further configured to generate the at least one prediction value based on at least one of a shader preamble, a feedback shader, or a batch of data for the graphics workload. In one configuration, the component for adjusting the execution flow of the graphics workload may be further configured to load the group of shader operations for multiple shader programs; and combine each shader program in the multiple shader programs based on the loaded group of shader operations. In one configuration, the execution flow of the graphics workload may correspond to a shader sequence of the multiple shader programs. In one configuration, the components for executing each shader operation in the group of shader operations may be further configured to execute one or more shader operations in the group of shader operations based on the adjusted execution flow of the graphics workload. In one configuration, the components for preventing the execution of each shader operation in the group of shader operations may be further configured to skip at least one shader operation in the group of shader operations based on the adjusted execution flow of the graphics workload. In one configuration, the device may also include components for the following operations: updating or maintaining the configuration of the shader processor or stream processor at the GPU based on executing or preventing the execution of each shader operation in the group of shader operations. In one configuration, the device may also include components for the following operations: when executing or preventing the execution of each shader operation in the group of shader operations, storing data associated with each shader operation in the group of shader operations. In one configuration, the data may be stored in at least one of the following: system memory, DDR RAM, constant memory, or on-chip memory.

[0129] It should be understood that the specific order or hierarchy of the boxes / steps in the processes, flow charts and / or call flow charts disclosed herein is only an illustration of the exemplary method. It should be understood that the specific order or hierarchy of the boxes / steps in these processes, flow charts and / or call flow charts can be rearranged based on design preferences. In addition, some boxes / steps can be combined or omitted. Other boxes / steps can also be added. The attached method claims provide the elements of various boxes / steps in a sample order, but are not meant to be limited to the specific order or hierarchy provided.

[0130] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the various aspects shown herein, but should be given the full scope consistent with the language of the claims, wherein unless otherwise specified, reference to an element in the singular is not intended to mean "one and only one", but rather "one or more". The word "exemplary" is used herein to mean "used as an example, instance, or illustration". Any aspect described herein as "exemplary" is not necessarily to be interpreted as being preferred or having advantages over other aspects.

[0131] Unless specifically stated otherwise, the term “some” refers to one or more, and the term “or” may be interpreted as “and / or” if the context does not dictate otherwise. Combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” include any combination of A, B, and / or C, which may include multiple A, multiple B, or multiple C. Specifically, combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” may be only A, only B, only C, A and B, A and C, B and C, or A and B and C, where any such combination may include one or more members of A, B, or C. All structural and functional equivalents of the elements of the various aspects described throughout this disclosure that are known or will later become known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, nothing disclosed herein is intended to be dedicated to the public, regardless of whether such disclosure is explicitly stated in the claims. Words such as "module," "mechanism," "element," "device," etc. cannot replace the word "component." Therefore, no claim element will be understood to be a part plus function unless the element is explicitly stated using the phrase "component for..."

[0132] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module described herein may be stored or sent as one or more instructions or codes on a computer-readable medium.

[0133] Computer-readable media may include computer data storage media and communication media, including any media that facilitate the transfer of computer programs from one place to another. In this manner, computer-readable media may generally correspond to: (1) a non-transitory tangible computer-readable storage medium; or (2) a communication medium, such as a signal or carrier wave. Data storage media may be any available medium that can be accessed by one or more computers or one or more processors to extract instructions, codes, and / or data structures for implementing the techniques described in this disclosure. As an example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, compact disc read-only memory (CD-ROM) or other optical disc storage, magnetic disk storage, or other magnetic storage devices. As used herein, magnetic disks and optical disks include compact discs (CDs), laser discs, optical disks, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where magnetic disks typically reproduce data magnetically, while optical disks reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. A computer program product may include computer-readable media.

[0134] The technology of the present disclosure can be implemented in a variety of devices or apparatuses, including wireless mobile phones, integrated circuits (ICs) or IC groups (e.g., chipsets). Various components, modules, or units are described in the present disclosure to emphasize the functional aspects of devices configured to perform the disclosed technology, but they do not necessarily need to be implemented by different hardware units. On the contrary, as described above, the various units can be combined in any hardware unit, or provided by a collection of interoperable hardware units (including one or more processors as described above) in combination with appropriate software and / or firmware. Therefore, the term "processor" as used herein can refer to any of the above structures or any other structure suitable for implementing the technology described herein. Similarly, these technologies can be fully implemented in one or more circuits or logic elements.

[0135] The following aspects are merely illustrative and may be combined with other aspects or teachings described herein without limitation.

[0136] Aspect 1 is a method of graphics processing, the method comprising: obtaining instruction execution data associated with a graphics workload, the instruction execution data comprising graphics data for a set of shader operations; at a first iteration, configuring at least one prediction value based on the instruction execution data comprising the graphics data for the set of shader operations, the at least one prediction value indicating the likelihood of occurrence of a condition of the graphics workload, the condition of the graphics workload being associated with a stream processor of a GPU; at a second iteration after the first iteration and without changing a function or result of the graphics workload, adjusting an execution flow of the graphics workload based on the configured at least one prediction value, the execution flow of the graphics workload comprising the set of shader operations; and at the second iteration, executing or refraining from executing each shader operation in the set of shader operations based on the adjusted execution flow of the graphics workload.

[0137] Aspect 2 may be combined with Aspect 1 and include: the graphics data for the set of shader operations includes at least one of: lighting data, illuminance data, depth data, shadow data or radius data.

[0138] Aspect 3 can be combined with any one of Aspects 1 to 2, and includes: the instruction execution data is obtained based on the FMUL unit of the GPU, and the at least one prediction value configured at the first iteration indicates the possibility of the occurrence of the condition of the graphics workload of the second iteration.

[0139] Aspect 4 may be combined with any of aspects 1 to 3, and comprises: the set of shader operations comprising a set of multiplication operations for the graphics workload.

[0140] Aspect 5 may be combined with any one of aspects 1 to 4, and includes: the at least one prediction value is a 1-bit value.

[0141] Aspect 6 may be combined with any of Aspects 1 to 5 and include: configuring the at least one prediction value further includes generating the at least one prediction value based on at least one of a shader preamble, a feedback shader, or a batch of data for the graphics workload.

[0142] Aspect 7 can be combined with any one of Aspects 1 to 6, and includes: adjusting the execution flow of the graphics workload also includes: loading the set of shader operations for multiple shader programs; and combining each shader program in the multiple shader programs based on the loaded set of shader operations.

[0143] Aspect 8 may be combined with Aspect 7, and includes: said execution flow of said graphics workload corresponds to a shader sequence of said plurality of shader programs.

[0144] Aspect 9 may be combined with any of Aspects 1 to 8 and includes: executing each shader operation in the set of shader operations also includes executing one or more shader operations in the set of shader operations based on the adjusted execution flow of the graphics workload.

[0145] Aspect 10 may be combined with any of Aspects 1 to 9 and includes: refraining from executing each of the set of shader operations further includes skipping at least one of the set of shader operations based on the adjusted execution flow of the graphics workload.

[0146] Aspect 11 may be combined with any of aspects 1 to 10, and further comprises updating or maintaining a configuration of a shader processor or a stream processor at the GPU based on executing or refraining from executing each shader operation in the set of shader operations.

[0147] Aspect 12 may be combined with any of aspects 1 to 11, and further comprises storing data associated with each shader operation in the set of shader operations when each shader operation in the set of shader operations is executed or refrained from being executed.

[0148] Aspect 13 may be combined with aspect 12, and includes: the data being stored in at least one of: a system memory, a DDR RAM, a constant memory, or an on-chip memory.

[0149] Aspect 14 is an apparatus for graphics processing comprising at least one processor, the at least one processor being coupled to a memory and configured to implement the method as described in any one of aspects 1 to 13.

[0150] Aspect 15 may be combined with aspect 14, and includes: the apparatus being a wireless communication device.

[0151] Aspect 16 is a device for graphics processing, the device comprising means for implementing the method as described in any one of aspects 1 to 13.

[0152] Aspect 17 is a computer-readable medium (eg, a non-transitory computer-readable medium) storing computer-executable code, which, when executed by at least one processor, causes the at least one processor to implement the method as described in any one of aspects 1 to 13.

[0153] Various aspects have been described herein. These and other aspects are within the scope of the following claims.

Claims

1. A device for graphics processing, the device comprising: Memory; and at least one processor coupled to the memory and configured to: obtaining instruction execution data associated with a graphics workload, the instruction execution data comprising graphics data for a set of shader operations; At a first iteration, configuring at least one prediction value based on the instruction execution data including the graphics data for the set of shader operations, the at least one prediction value indicating a likelihood of occurrence of a condition of the graphics workload, The condition of the graphics workload is associated with a stream processor of a graphics processing unit (GPU); at a second iteration after the first iteration and without changing a function or result of the graphics workload, adjusting an execution flow of the graphics workload based on the configured at least one prediction value, the execution flow of the graphics workload including the set of shader operations; as well as At the second iteration, each shader operation in the set of shader operations is executed or refrained from execution based on the adjusted execution flow of the graphics workload. 2 . The device of claim 1 , wherein the graphics data for the set of shader operations comprises at least one of: lighting data, illuminance data, depth data, shadow data, or radius data.

3. The apparatus of claim 1 , wherein the instruction execution data is obtained based on a floating multiplication (FMUL) unit of the GPU, and the at least one prediction value configured at the first iteration indicates the likelihood of the occurrence of the condition of the graphics workload of the second iteration. 4 . The apparatus of claim 1 , wherein the set of shader operations comprises a set of multiplication operations for the graphics workload. The apparatus of claim 1 , wherein the at least one predicted value is a 1-bit value.

6. The apparatus of claim 1 , wherein to configure the at least one prediction value, the at least one processor is further configured to: The at least one prediction value is generated based on at least one of a shader preamble, a feedback shader, or a batch of data for the graphics workload.

7. The apparatus of claim 1 , wherein to adjust the execution flow of the graphics workload, the at least one processor is further configured to: loading the set of shader operations for a plurality of shader programs; and Each shader program of the plurality of shader programs is combined based on the loaded set of shader operations. 8 . The apparatus of claim 7 , wherein the execution flow of the graphics workload corresponds to a shader sequence of the plurality of shader programs.

9. The apparatus of claim 1 , wherein to perform each shader operation in the set of shader operations, the at least one processor is further configured to: One or more shader operations in the set of shader operations are executed based on the adjusted execution flow of the graphics workload.

10. The apparatus of claim 1, wherein to refrain from executing each shader operation in the set of shader operations, the at least one processor is further configured to: At least one shader operation in the set of shader operations is skipped based on the adjusted execution flow of the graphics workload.

11. The apparatus of claim 1 , wherein the at least one processor is further configured to: A configuration of a shader processor or the stream processor at the GPU is updated or maintained based on executing or refraining from executing each shader operation in the set of shader operations.

12. The apparatus of claim 1 , wherein the at least one processor is further configured to: Data associated with each shader operation in the set of shader operations is stored while each shader operation in the set of shader operations is executed or refrained from execution.

13. The apparatus of claim 12, wherein the data is stored in at least one of: system memory, double data rate (DDR) random access memory (RAM), constant memory, or on-chip memory.

14. The apparatus of claim 1, wherein the apparatus is a wireless communication device.

15. A graphics processing method, the graphics processing method comprising: obtaining instruction execution data associated with a graphics workload, the instruction execution data comprising graphics data for a set of shader operations; At a first iteration, configuring at least one prediction value based on the instruction execution data including the graphics data for the set of shader operations, the at least one prediction value indicating a likelihood of occurrence of a condition of the graphics workload, the condition of the graphics workload being associated with a stream processor of a graphics processing unit (GPU); at a second iteration after the first iteration and without changing a function or result of the graphics workload, adjusting an execution flow of the graphics workload based on the configured at least one prediction value, the execution flow of the graphics workload including the set of shader operations; as well as At the second iteration, each shader operation in the set of shader operations is executed or refrained from execution based on the adjusted execution flow of the graphics workload.

16. The method of claim 15, wherein the graphics data for the set of shader operations comprises at least one of: lighting data, illuminance data, depth data, shadow data, or radius data.

17. The method of claim 15, wherein the instruction execution data is obtained based on a floating multiplication (FMUL) unit of the GPU, and the at least one prediction value configured at the first iteration indicates the likelihood of the occurrence of the condition of the graphics workload of the second iteration.

18. The method of claim 15, wherein the set of shader operations comprises a set of multiplication operations for the graphics workload. The method of claim 15 , wherein the at least one predicted value is a 1-bit value.

20. The method of claim 15, wherein configuring the at least one prediction value further comprises generating the at least one prediction value based on at least one of a shader preamble, a feedback shader, or a batch of data for the graphics workload.

21. The method of claim 15, wherein adjusting the execution flow of the graphics workload further comprises: loading the set of shader operations for a plurality of shader programs; as well as Each shader program of the plurality of shader programs is combined based on the loaded set of shader operations.

22. The method of claim 21, wherein the execution flow of the graphics workload corresponds to a shader sequence of the plurality of shader programs.

23. The method of claim 15, wherein executing each shader operation in the set of shader operations further comprises executing one or more shader operations in the set of shader operations based on the adjusted execution flow of the graphics workload.

24. The method of claim 15, wherein refraining from executing each shader operation in the set of shader operations further comprises skipping at least one shader operation in the set of shader operations based on the adjusted execution flow of the graphics workload.

25. The method according to claim 15, further comprising: A configuration of a shader processor or the stream processor at the GPU is updated or maintained based on executing or refraining from executing each shader operation in the set of shader operations.

26. The method according to claim 15, further comprising: Data associated with each shader operation in the set of shader operations is stored while each shader operation in the set of shader operations is executed or refrained from execution.

27. The method of claim 26, wherein the data is stored in at least one of: system memory, double data rate (DDR) random access memory (RAM), constant memory, or on-chip memory.

28. A computer readable medium storing computer executable code which, when executed by at least one processor, causes the at least one processor to: obtaining instruction execution data associated with a graphics workload, the instruction execution data comprising graphics data for a set of shader operations; At a first iteration, configuring at least one prediction value based on the instruction execution data including the graphics data for the set of shader operations, the at least one prediction value indicating a likelihood of occurrence of a condition of the graphics workload, the condition of the graphics workload being associated with a stream processor of a graphics processing unit (GPU); at a second iteration after the first iteration and without changing a function or result of the graphics workload, adjusting an execution flow of the graphics workload based on the configured at least one prediction value, the execution flow of the graphics workload including the set of shader operations; as well as At the second iteration, each shader operation in the set of shader operations is executed or refrained from execution based on the adjusted execution flow of the graphics workload.

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