Driving circuit and display substrate

Abstract

According to the driving circuit and the display substrate, the purpose that one driving circuit drives multiple rows of grid lines is achieved, the number of transistors adopted by the driving circuit is effectively reduced, and a narrow frame can be achieved. The driving circuit comprises a driving control signal generating circuit (10) and a multi-path output circuit; the multi-path output circuit comprises N stages of output sub-circuits; n is an integer greater than 1; the driving control signal generation circuit (10) is used for generating a driving control signal; the nth output sub-circuit is electrically connected with a driving control signal output end (G01), an nth output clock signal line and an nth driving signal output end, and the nth output sub-circuit is used for controlling the nth output clock signal line to provide an nth output clock signal to the nth driving signal output end under the control of the driving control signal; n is a positive integer smaller than or equal to N.

Description

Driving circuit and display substrate Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driving circuit and a display substrate. Background Art

[0002] In related technologies, oxide thin-film transistors (TFTs) offer high electron mobility and low leakage current, enabling high-resolution, high-refresh-rate, low-power, and low-frequency drive designs for display panels. However, these driver circuits employing TFTs only drive one row of pixels. To ensure the proper operation of a display panel with multiple rows of pixels, a large number of transistors are required, hindering the reduction of bezel area.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a driving circuit, comprising a driving control signal generating circuit and a multi-channel output circuit; the multi-channel output circuit comprises N-stage output sub-circuits; N is an integer greater than 1;

[0005] The drive control signal generating circuit is used to generate a drive control signal, and the drive control signal is output through the drive control signal output terminal;

[0006] The nth output sub-circuit is electrically connected to the drive control signal output terminal, the nth output clock signal line and the nth drive signal output terminal respectively, and the nth output sub-circuit is used to control the nth output clock signal line to provide the nth output clock signal to the nth drive signal output terminal under the control of the drive control signal; n is a positive integer less than or equal to N.

[0007] Optionally, the nth output sub-circuit includes an nth output transistor;

[0008] The control electrode of the nth output transistor is electrically connected to the drive control signal output terminal, the first electrode of the nth output transistor is electrically connected to the nth output clock signal line, and the second electrode of the nth output transistor is electrically connected to the nth drive signal output terminal.

[0009] Optionally, the nth output sub-circuit further includes an nth on-off control transistor; the control electrode of the nth output transistor is electrically connected to the drive control signal output terminal through the nth on-off control transistor;

[0010] The control electrode of the nth on-off control transistor is electrically connected to the first voltage line, the first electrode of the nth on-off control transistor is electrically connected to the drive control signal output end, and the second electrode of the nth on-off control transistor is electrically connected to the control electrode of the nth output transistor.

[0011] Optionally, the nth output sub-circuit further includes an nth output capacitor;

[0012] The first plate of the nth output capacitor is electrically connected to the control electrode of the nth output transistor, and the second plate of the nth output capacitor is electrically connected to the second electrode of the nth output transistor.

[0013] Optionally, the nth output sub-circuit further includes an nth output pull-down unit;

[0014] The nth output pull-down unit is electrically connected to the pull-down node, the nth drive signal output terminal and the second voltage line respectively, and is used to control the connection between the nth drive signal output terminal and the second voltage line under the control of the potential of the pull-down node.

[0015] Optionally, the pull-down node includes a first pull-down node and a second pull-down node; the nth output pull-down unit includes an nth first output pull-down transistor and an nth second output pull-down transistor;

[0016] a control electrode of the nth first output pull-down transistor electrically connected to the first pull-down node, a first electrode of the nth first output pull-down transistor electrically connected to the nth drive signal output terminal, and a second electrode of the nth first output pull-down transistor electrically connected to a second voltage line;

[0017] The control electrode of the nth second output pull-down transistor is electrically connected to the second pull-down node, the first electrode of the nth second output pull-down transistor is electrically connected to the nth drive signal output terminal, and the second electrode of the nth second output pull-down transistor is electrically connected to the second voltage line.

[0018] Optionally, the driving control signal generating circuit includes a pull-up node control circuit, a first pull-down node control circuit, a second pull-down node control circuit and a driving control output circuit;

[0019] The pull-up node control circuit is used to control the potential of the pull-up node;

[0020] The first pull-down node control circuit is used to control the potential of the first pull-down node under the control of the potential of the pull-up node;

[0021] The second pull-down node control circuit is used to control the potential of the second pull-down node under the control of the potential of the pull-up node;

[0022] The drive control output circuit is electrically connected to the pull-up node, the first pull-down node, the second pull-down node, the drive control signal output end, the drive control clock signal line and the second voltage line, respectively, and is used to control the drive control clock signal line to be electrically connected to the drive control signal output end under the control of the potential of the pull-up node, control the drive control signal output end to be connected to the second voltage line under the control of the potential of the first pull-down node, and control the drive control signal output end to be connected to the second voltage line under the control of the potential of the second pull-down node.

[0023] Optionally, the drive control signal generating circuit further includes a carry output circuit;

[0024] The carry output circuit is electrically connected to the pull-up node, the first pull-down node, the second pull-down node, the carry output terminal, the drive control clock signal line and the third voltage line, respectively, and is used to control the drive control clock signal line to be electrically connected to the carry output terminal under the control of the potential of the pull-up node, control the carry output terminal to be connected to the third voltage line under the control of the potential of the first pull-down node, and control the carry output terminal to be connected to the third voltage line under the control of the potential of the second pull-down node.

[0025] Optionally, the pull-up node control circuit is electrically connected to the input terminal, the frame reset line, the first pull-down node, the second pull-down node, the first reset terminal, the pull-up node, and the third voltage line, respectively, and is configured to control the potential of the pull-up node under the control of an input signal provided by the input terminal, and control the connection between the pull-up node and the third voltage line under the control of a frame reset signal provided by the frame reset line, control the connection between the pull-up node and the third voltage line under the control of the potential of the first pull-down node, control the connection between the pull-up node and the third voltage line under the control of the potential of the second pull-down node, and control the connection between the pull-up node and the third voltage line under the control of a first reset signal provided by the first reset terminal;

[0026] The first pull-down node control circuit is electrically connected to the first control voltage line, the first pull-down node, the pull-up node and the third voltage line, respectively, and is configured to control the potential of the first pull-down node under the control of the first control voltage provided by the first control voltage line and the potential of the pull-up node;

[0027] The second pull-down node control circuit is electrically connected to the second control voltage line, the second pull-down node, the pull-up node and the third voltage line, respectively, and is configured to control the potential of the second pull-down node under the control of the second control voltage provided by the second control voltage line and the potential of the pull-up node;

[0028] The drive control output circuit is also electrically connected to the second reset terminal, and is used to control the connection between the drive control signal output terminal and the second voltage line under the control of a second reset signal provided by the second reset terminal.

[0029] Optionally, the pull-up node control circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor;

[0030] The control electrode of the first transistor and the first electrode of the first transistor are electrically connected to the input terminal, and the second electrode of the first transistor is electrically connected to the pull-up node;

[0031] The control electrode of the second transistor is electrically connected to the first reset terminal, the first electrode of the second transistor is electrically connected to the pull-up node, and the second electrode of the second transistor is electrically connected to the third voltage line;

[0032] The control electrode of the third transistor is electrically connected to the frame reset terminal, the first electrode of the third transistor is electrically connected to the pull-up node, and the second electrode of the third transistor is electrically connected to the third voltage line;

[0033] A control electrode of the fourth transistor is electrically connected to the first pull-down node, a first electrode of the fourth transistor is electrically connected to the pull-up node, and a second electrode of the fourth transistor is electrically connected to the third voltage line;

[0034] The control electrode of the fifth transistor is electrically connected to the second pull-down node, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the third voltage line;

[0035] The first pull-down node control circuit includes a sixth transistor and a seventh transistor;

[0036] The control electrode of the sixth transistor and the first electrode of the sixth transistor are electrically connected to the first control voltage line, and the second electrode of the sixth transistor is electrically connected to the first pull-down node;

[0037] A control electrode of the seventh transistor is electrically connected to the pull-up node, a first electrode of the seventh transistor is electrically connected to the first pull-down node, and a second electrode of the seventh transistor is electrically connected to the third voltage line;

[0038] The second pull-down node control circuit includes an eighth transistor and a ninth transistor;

[0039] The control electrode of the eighth transistor and the first electrode of the eighth transistor are electrically connected to the second control voltage line, and the second electrode of the eighth transistor is electrically connected to the second pull-down node;

[0040] The control electrode of the ninth transistor is electrically connected to the pull-up node, the first electrode of the ninth transistor is electrically connected to the second pull-down node, and the second electrode of the ninth transistor is electrically connected to the third voltage line.

[0041] Optionally, the ratio of the channel width-to-length ratio of the seventh transistor to the channel width-to-length ratio of the sixth transistor is greater than or equal to 6, and the ratio of the channel width-to-length ratio of the ninth transistor to the channel width-to-length ratio of the eighth transistor is greater than or equal to 6.

[0042] Optionally, the first pull-down node control circuit further includes a tenth transistor, and the second pull-down node control circuit further includes an eleventh transistor;

[0043] The control electrode of the tenth transistor is electrically connected to the input terminal, the first electrode of the tenth transistor is electrically connected to the first pull-down node, and the second electrode of the tenth transistor is electrically connected to the third voltage line;

[0044] The control electrode of the eleventh transistor is electrically connected to the input terminal, the first electrode of the eleventh transistor is electrically connected to the second pull-down node, and the second electrode of the eleventh transistor is electrically connected to the third voltage line.

[0045] Optionally, the carry output circuit includes a twelfth transistor, a thirteenth transistor and a fourteenth transistor;

[0046] The control electrode of the twelfth transistor is electrically connected to the pull-up node, the first electrode of the twelfth transistor is electrically connected to the drive control clock signal line, and the second electrode of the twelfth transistor is electrically connected to the carry output terminal;

[0047] The control electrode of the thirteenth transistor is electrically connected to the first pull-down node, the first electrode of the thirteenth transistor is electrically connected to the carry output terminal, and the second electrode of the thirteenth transistor is electrically connected to the third voltage line;

[0048] The control electrode of the fourteenth transistor is electrically connected to the second pull-down node, the first electrode of the fourteenth transistor is electrically connected to the carry output terminal, and the second electrode of the fourteenth transistor is electrically connected to the third voltage line;

[0049] The drive control output circuit includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor and a first capacitor;

[0050] The control electrode of the fifteenth transistor is electrically connected to the pull-up node, the first electrode of the fifteenth transistor is electrically connected to the drive control clock signal line, and the second electrode of the fifteenth transistor is electrically connected to the drive control signal output terminal;

[0051] The control electrode of the sixteenth transistor is electrically connected to the first pull-down node, the first electrode of the sixteenth transistor is electrically connected to the drive control signal output terminal, and the second electrode of the sixteenth transistor is electrically connected to the second voltage line;

[0052] The control electrode of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the drive control signal output terminal, and the second electrode of the seventeenth transistor is electrically connected to the second voltage line;

[0053] The control electrode of the eighteenth transistor is electrically connected to the second reset terminal, the first electrode of the eighteenth transistor is electrically connected to the drive control signal output terminal, and the second electrode of the eighteenth transistor is electrically connected to the second voltage line;

[0054] The first plate of the first capacitor is electrically connected to the pull-up node, and the second plate of the first capacitor is electrically connected to the drive control signal output terminal.

[0055] In a second aspect, an embodiment of the present disclosure further provides a display substrate, comprising a base substrate and a plurality of stages of the above-mentioned driving circuits disposed on the base substrate.

[0056] Optionally, the display substrate includes a peripheral area and a display area; the driving circuit includes a driving control signal generating circuit and a multi-channel output circuit;

[0057] The multi-channel output circuit and the drive control signal generating circuit are arranged in the peripheral area;

[0058] The multi-channel output circuit is arranged on a side of the driving control signal generating circuit close to the display area.

[0059] Optionally, the multi-channel output circuit includes N output sub-circuits and N output clock signal lines; N is an integer greater than 1;

[0060] The output clock signal line is arranged on a side of the output sub-circuit close to the display area, and the output clock signal line extends along a first direction.

[0061] Optionally, the nth output sub-circuit includes an nth output transistor, and the nth output transistor is arranged between the drive control signal generating circuit and the display area; n is a positive integer less than or equal to N.

[0062] Optionally, the nth output subcircuit includes an nth output transistor; n is a positive integer less than or equal to N;

[0063] The active layer pattern of the nth output transistor includes at least one active portion independent of each other; the active portion extends along a first direction.

[0064] Optionally, active layer patterns of output transistors respectively included in the N output sub-circuits are arranged along the first direction.

[0065] Optionally, the nth output sub-circuit further includes an nth output pull-down unit, and the nth output pull-down unit includes an nth first output pull-down transistor and an nth second output pull-down transistor;

[0066] The active layer pattern of the nth first output pull-down transistor and the active layer pattern of the nth second output pull-down transistor are arranged along a first direction;

[0067] The active layer pattern of the nth first output pull-down transistor and the active layer pattern of the nth second output pull-down transistor both extend along the first direction.

[0068] Optionally, the output pull-down units respectively included in the N output sub-circuits are arranged along the first direction.

[0069] Optionally, the display substrate includes a peripheral area and a display area; the driving circuit includes a driving control signal generating circuit and a multi-channel output circuit;

[0070] The driving control signal generating circuit is arranged in the peripheral area;

[0071] The multi-channel output circuit includes N output sub-circuits, and the nth output sub-circuit includes the nth output transistor; N is an integer greater than 1, and n is a positive integer less than or equal to N;

[0072] The nth output transistor is disposed in the display area.

[0073] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a plurality of rows of gate lines and a plurality of rows of common electrode lines arranged in the display area;

[0074] The gate lines and the common electrode lines both extend along a second direction;

[0075] The nth output transistor is disposed between the gate line and the common electrode line.

[0076] Optionally, the multi-channel output circuit further includes N output clock signal lines;

[0077] The output clock signal line is arranged in the display area.

[0078] Optionally, the driving circuit includes a driving control signal generating circuit; the driving control signal generating circuit includes a first transistor, a fourth transistor, a fifth transistor, a tenth transistor, a twelfth transistor and a fifteenth transistor;

[0079] The aspect ratio of the active layer pattern of the first transistor is greater than or equal to 80 and less than or equal to 130;

[0080] The aspect ratio of the active layer pattern of the fourth transistor and the aspect ratio of the active layer pattern of the fifth transistor are greater than or equal to 18 and less than or equal to 32;

[0081] The aspect ratio of the active layer pattern of the tenth transistor is greater than or equal to 5 and less than or equal to 10;

[0082] The aspect ratio of the active layer pattern of the twelfth transistor is greater than or equal to 25 and less than or equal to 50;

[0083] The aspect ratio of the active layer pattern of the fifteenth transistor is greater than or equal to 16 and less than or equal to 40;

[0084] The aspect ratio is a ratio between a length of the active layer pattern along a first direction and a width of the active layer pattern along a second direction.

[0085] Optionally, the driving circuit includes a driving control signal generating circuit; the driving control signal generating circuit includes a first capacitor;

[0086] The electrode plate of the first capacitor includes a first electrode plate portion and a second electrode plate portion that are interconnected; the first electrode plate portion is in a block shape;

[0087] The second electrode portion extends along a first direction;

[0088] A ratio of a length of the second electrode portion along the first direction to a width of the second electrode portion along the second direction is greater than or equal to 6 and less than or equal to 25.

[0089] Optionally, the driving circuit includes a driving control signal generating circuit and a multi-channel output circuit; the driving control signal generating circuit includes a first capacitor and a fifteenth transistor; the multi-channel output circuit includes an output sub-circuit; and the output sub-circuit includes an on-off control transistor;

[0090] The first capacitor is arranged between the fifteenth transistor and the on-off control transistor.

[0091] Optionally, the nth output sub-circuit further includes an nth on-off control transistor and an nth output capacitor; the nth on-off control transistor and the nth output capacitor are both arranged in the peripheral area;

[0092] The active layer pattern of the nth on-off control transistor extends along a first direction;

[0093] The active layer patterns of the on-off control transistors respectively included in the N output sub-circuits are arranged along a first direction;

[0094] The output capacitors respectively included in the N output sub-circuits are arranged along a first direction.

[0095] Optionally, the display substrate includes a plurality of signal lines, the signal lines are electrically connected to a drive control signal generating circuit included in the drive circuit, and the signal lines extend along a first direction;

[0096] The shortest distance along the second direction between the gate of the transistor included in the drive control signal generating circuit and the signal line closest to the transistor in the drive control signal generating circuit is greater than the first predetermined distance;

[0097] The first direction intersects the second direction;

[0098] The gate of the transistor and the signal line are located in the same layer.

[0099] Optionally, active layer patterns of transistors in the driving control signal generating circuit included in the driving circuit all extend along the first direction.

[0100] Optionally, the active layer pattern of at least one transistor included in the driving circuit includes at least two active pattern portions extending along the first direction;

[0101] A distance in the second direction between two adjacent active pattern portions in the first direction is greater than a second predetermined distance. BRIEF DESCRIPTION OF THE DRAWINGS

[0102] FIG1 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0103] FIG2 is a circuit diagram of at least one embodiment of the first output sub-circuit;

[0104] FIG3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0105] FIG4 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0106] FIG5 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG4 ;

[0107] 6 is a timing diagram of the drive control signal provided by G01, the potential of PM1, and the first drive signal output by GO1 during operation of at least one embodiment of the drive circuit shown in FIG. 4 ;

[0108] 7 is a timing diagram of the drive control signal provided by G01, the potential of PM1, and the first drive signal output by GO1 when at least one embodiment of the drive circuit shown in FIG4 is not provided with each on-off control transistor;

[0109] FIG8 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0110] FIG9 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG8 ;

[0111] FIG10 is a plan view of at least one embodiment of the driving circuit shown in FIG8 of the present disclosure;

[0112] FIG11A is a plan view of the gate metal layer in FIG10 ;

[0113] FIG11B is a plan view of the gate metal layer in FIG10 ;

[0114] FIG11C is a plan view of the gate metal layer in FIG10 ;

[0115] FIG12A is a top plan view of the semiconductor layer in FIG10;

[0116] FIG12B is a top plan view of the semiconductor layer in FIG10;

[0117] FIG13 is a plan view of the source / drain metal layer in FIG10 ;

[0118] FIG14 is a plan view of the second ITO (indium tin oxide) layer in FIG10;

[0119] FIG15 is a circuit diagram of at least one embodiment of each output sub-circuit;

[0120] FIG16 is a waveform of each driving signal output by the driving circuit in the initial state when each output pull-down transistor is removed;

[0121] FIG17 shows the waveforms of the drive signals output by the drive circuit after being at 60 degrees Celsius for 1000 hours when the output pull-down transistors are removed;

[0122] FIG18 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0123] 19 is a plan view of a portion other than MO1, MO2, MO3, and MO4 in at least one embodiment of the driving circuit shown in FIG. 18 ;

[0124] FIG20A is a plan view of the gate metal layer in FIG19;

[0125] FIG20B is a plan view of the gate metal layer in FIG19;

[0126] FIG21 is a plan view of the semiconductor layer in FIG19;

[0127] FIG22 is a plan view of the source / drain metal layer in FIG19 ;

[0128] FIG23 is a plan view of the second ITO (indium tin oxide) layer in FIG19;

[0129] FIG24 is a plan view of a first output transistor provided in a display region;

[0130] FIG25 is a plan view of the gate metal layer in FIG24;

[0131] FIG26 is a top plan view of the semiconductor layer in FIG24;

[0132] FIG27 is a plan view of the source / drain metal layer in FIG24 ;

[0133] FIG28 is a plan view of the first ITO layer in FIG24;

[0134] FIG29 is a plan view of the second ITO layer in FIG24;

[0135] FIG30 is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0136] FIG31 is a schematic diagram of an active layer pattern of at least one transistor in the driving circuit;

[0137] FIG32 is a schematic diagram of an active layer pattern of at least one transistor in the driving circuit;

[0138] FIG33 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0139] FIG34 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG33 of the present disclosure in an initial state before undergoing a reliability test.

[0140] FIG35 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG33 of the present disclosure after undergoing a reliability test (reliability test at 60 degrees Celsius for less than 1000 hours).

[0141] FIG36 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0142] FIG37 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0143] FIG38 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0144] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0145] The transistors used in all embodiments of the present disclosure may be triodes, thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor other than the control electrode, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0146] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0147] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.

[0148] The driving circuit of the embodiment of the present disclosure includes a driving control signal generating circuit and a multi-channel output circuit; the multi-channel output circuit includes N-level output sub-circuits; N is an integer greater than 1;

[0149] The drive control signal generating circuit is used to generate a drive control signal, and the drive control signal is output through the drive control signal output terminal;

[0150] The nth output sub-circuit is electrically connected to the drive control signal output terminal, the nth output clock signal line and the nth drive signal output terminal respectively, and the nth output sub-circuit is used to control the nth output clock signal line to provide the nth output clock signal to the nth drive signal output terminal under the control of the drive control signal; n is a positive integer less than or equal to N.

[0151] In the relevant driving circuit, it is usually a driving circuit that drives a row of gate lines. In order to ensure that a driving circuit works normally, many transistors are required, and transistors need to occupy the frame area. With the development of display products, the market requirement for the frame is getting narrower and narrower. In the related art, most of the data voltage output terminals of the IC (integrated circuit) are multiplexed by a multiplexing circuit, so as to provide data voltages for multiple data lines respectively, so as to reduce the data voltage output terminals of the IC used. Since the drive control is currently mainly carried out by the GOA (Gate On Array, array substrate row drive) circuit, the driving architecture is already complex, and the design difficulty of the multiplexed gate drive architecture is relatively high. In order to further achieve a narrow frame and reduce costs, the driving circuit described in the embodiment of the present disclosure is at work, the drive control signal generating circuit outputs the drive control signal, and the N-level output sub-circuit outputs N-level drive signals under the control of the drive control signal respectively, so that the purpose of driving multiple rows of gate lines can be achieved by a driving circuit, effectively reducing the number of transistors used in the driving circuit, which is conducive to achieving a narrow frame.

[0152] In at least one embodiment of the present disclosure, N is taken as 4 as an example for description.

[0153] As shown in FIG1 , the driving circuit according to at least one embodiment of the present disclosure includes a driving control signal generating circuit 10 , a first output sub-circuit 11 , a second output sub-circuit 12 , a third output sub-circuit 13 , and a fourth output sub-circuit 14 ;

[0154] The driving control signal generating circuit 10 includes a driving control signal output terminal G01;

[0155] The driving control signal generating circuit 10 is used to generate and output a driving control signal through the driving control signal output terminal G01;

[0156] The first output sub-circuit 11 is electrically connected to the drive control signal output terminal G01, the first output clock signal line HC1 and the first drive signal output terminal GO1, respectively, and is used to control the first output clock signal line HC1 to provide a first output clock signal to the first drive signal output terminal GO1 under the control of the drive control signal;

[0157] The second output sub-circuit 12 is electrically connected to the drive control signal output terminal G01, the second output clock signal line HC2 and the second drive signal output terminal GO2, respectively, and is used to control the second output clock signal line HC2 to provide a second output clock signal to the second drive signal output terminal GO2 under the control of the drive control signal;

[0158] The third output sub-circuit 13 is electrically connected to the drive control signal output terminal G01, the third output clock signal line HC3 and the third drive signal output terminal GO3, respectively, and is used to control the third output clock signal line HC3 to provide a third output clock signal to the third drive signal output terminal GO3 under the control of the drive control signal;

[0159] The fourth output sub-circuit 14 is electrically connected to the drive control signal output terminal G01, the fourth output clock signal line HC4 and the fourth drive signal output terminal GO4, respectively, and is used to control the fourth output clock signal line HC4 to provide a fourth output clock signal to the fourth drive signal output terminal GO4 under the control of the drive control signal.

[0160] Optionally, the nth output sub-circuit includes an nth output transistor;

[0161] The control electrode of the nth output transistor is electrically connected to the drive control signal output terminal, the first electrode of the nth output transistor is electrically connected to the nth output clock signal line, and the second electrode of the nth output transistor is electrically connected to the nth drive signal output terminal.

[0162] Optionally, the nth output sub-circuit further includes an nth on-off control transistor; the control electrode of the nth output transistor is electrically connected to the drive control signal output terminal through the nth on-off control transistor;

[0163] The control electrode of the nth on-off control transistor is electrically connected to the first voltage line, the first electrode of the nth on-off control transistor is electrically connected to the drive control signal output end, and the second electrode of the nth on-off control transistor is electrically connected to the control electrode of the nth output transistor.

[0164] Optionally, the nth output sub-circuit further includes an nth output capacitor;

[0165] The first plate of the nth output capacitor is electrically connected to the control electrode of the nth output transistor, and the second plate of the nth output capacitor is electrically connected to the second electrode of the nth output transistor.

[0166] In at least one embodiment of the present disclosure, the nth output sub-circuit further includes an nth output pull-down unit;

[0167] The nth output pull-down unit is electrically connected to the pull-down node, the nth drive signal output terminal and the second voltage line respectively, and is used to control the connection between the nth drive signal output terminal and the second voltage line under the control of the potential of the pull-down node.

[0168] In a specific implementation, the nth output sub-circuit may further include an nth output pull-down unit. The nth output pull-down unit controls the connection between the nth driving signal output terminal and the second signal line under the control of the pull-down node.

[0169] Optionally, the pull-down node may include a first pull-down node and a second pull-down node; the nth output pull-down unit includes an nth first output pull-down transistor and an nth second output pull-down transistor;

[0170] a control electrode of the nth first output pull-down transistor electrically connected to the first pull-down node, a first electrode of the nth first output pull-down transistor electrically connected to the nth drive signal output terminal, and a second electrode of the nth first output pull-down transistor electrically connected to a second voltage line;

[0171] The control electrode of the nth second output pull-down transistor is electrically connected to the second pull-down node, the first electrode of the nth second output pull-down transistor is electrically connected to the nth drive signal output terminal, and the second electrode of the nth second output pull-down transistor is electrically connected to the second voltage line.

[0172] In at least one embodiment of the present disclosure, the first voltage line may be a high voltage line, and the second voltage line may be a first low voltage line, but the present invention is not limited thereto.

[0173] As shown in FIG2 , at least one embodiment of the first output sub-circuit may include a first output transistor MO1, a first on-off control transistor MV1, a first output capacitor CO1, and a first output pull-down unit 21; the pull-down node may include a first pull-down node PD1 and a second pull-down node PD2; the first output pull-down unit 21 includes a first first output pull-down transistor MD11 and a first second output pull-down transistor MD12;

[0174] The drain of the first output transistor MO1 is electrically connected to the first output clock signal line HC1, and the source of the first output transistor MO1 is electrically connected to the first drive signal output terminal GO1;

[0175] The gate of the first output transistor MO1 is electrically connected to the drive control signal output terminal G01 through the first on-off control transistor MV1;

[0176] The gate of the first on-off control transistor MV1 is electrically connected to the high voltage line VGH, the drain of the first on-off control transistor MV1 is electrically connected to the drive control signal output terminal G01, and the source of the first on-off control transistor MV1 is electrically connected to the gate of the first output transistor MO1;

[0177] The first plate of the first output capacitor CO1 is electrically connected to the gate of the first output transistor MO1, and the second plate of the first output capacitor CO1 is electrically connected to the source of the first output transistor MO1;

[0178] The gate of the first first output pull-down transistor MD11 is electrically connected to the first pull-down node PD1, the drain of the first first output pull-down transistor MD11 is electrically connected to the first drive signal output terminal GO1, and the source of the first first output pull-down transistor MD11 is electrically connected to the first low voltage line VGL;

[0179] The gate of the first second output pull-down transistor MD12 is electrically connected to the second pull-down node PD2, the drain of the first second output pull-down transistor MD12 is electrically connected to the first drive signal output terminal GO1, and the source of the first second output pull-down transistor MD12 is electrically connected to the first low voltage line VGL.

[0180] In at least one embodiment shown in FIG. 2 , all transistors are n-type transistors, and all transistors are oxide thin film transistors, but the present invention is not limited thereto.

[0181] In at least one embodiment of the present disclosure, the driving control signal generating circuit includes a pull-up node control circuit, a first pull-down node control circuit, a second pull-down node control circuit, and a driving control output circuit;

[0182] The pull-up node control circuit is used to control the potential of the pull-up node;

[0183] The first pull-down node control circuit is used to control the potential of the first pull-down node under the control of the potential of the pull-up node;

[0184] The second pull-down node control circuit is used to control the potential of the second pull-down node under the control of the potential of the pull-up node;

[0185] The drive control output circuit is electrically connected to the pull-up node, the first pull-down node, the second pull-down node, the drive control signal output end, the drive control clock signal line and the second voltage line, respectively, and is used to control the drive control clock signal line to be electrically connected to the drive control signal output end under the control of the potential of the pull-up node, control the drive control signal output end to be connected to the second voltage line under the control of the potential of the first pull-down node, and control the drive control signal output end to be connected to the second voltage line under the control of the potential of the second pull-down node.

[0186] In a specific implementation, the driving control clock signal line is used to provide a driving control clock signal.

[0187] In a specific implementation, the drive control signal generating circuit may include a pull-up node control circuit, a first pull-down node control circuit, a second pull-down node control circuit and a drive control output circuit. The pull-up node control circuit controls the potential of the pull-up node, the first pull-down node control circuit controls the potential of the first pull-down node, and the second pull-down node control circuit controls the potential of the second pull-down node. The drive control output circuit controls the drive control signal output end to provide a corresponding drive control signal under the control of the potential of the pull-up node, the potential of the first pull-down node and the potential of the second pull-down node.

[0188] In at least one embodiment of the present disclosure, the drive control signal generating circuit further includes a carry output circuit;

[0189] The carry output circuit is electrically connected to the pull-up node, the first pull-down node, the second pull-down node, the carry output terminal, the drive control clock signal line and the third voltage line, respectively, and is used to control the drive control clock signal line to be electrically connected to the carry output terminal under the control of the potential of the pull-up node, control the carry output terminal to be connected to the third voltage line under the control of the potential of the first pull-down node, and control the carry output terminal to be connected to the third voltage line under the control of the potential of the second pull-down node.

[0190] In a specific implementation, the drive control signal generating circuit may further include a carry output circuit, which controls the carry output terminal to provide a corresponding carry signal under the control of the potential of the pull-up node, the potential of the first pull-down node and the potential of the second pull-down node. The carry signal can be used for cascading.

[0191] Optionally, the pull-up node control circuit is electrically connected to the input terminal, the frame reset line, the first pull-down node, the second pull-down node, the first reset terminal, the pull-up node, and the third voltage line, respectively, and is configured to control the potential of the pull-up node under the control of an input signal provided by the input terminal, and control the connection between the pull-up node and the third voltage line under the control of a frame reset signal provided by the frame reset line, control the connection between the pull-up node and the third voltage line under the control of the potential of the first pull-down node, control the connection between the pull-up node and the third voltage line under the control of the potential of the second pull-down node, and control the connection between the pull-up node and the third voltage line under the control of a first reset signal provided by the first reset terminal;

[0192] The first pull-down node control circuit is electrically connected to the first control voltage line, the first pull-down node, the pull-up node and the third voltage line, respectively, and is configured to control the potential of the first pull-down node under the control of the first control voltage provided by the first control voltage line and the potential of the pull-up node;

[0193] The second pull-down node control circuit is electrically connected to the second control voltage line, the second pull-down node, the pull-up node and the third voltage line, respectively, and is configured to control the potential of the second pull-down node under the control of the second control voltage provided by the second control voltage line and the potential of the pull-up node;

[0194] The drive control output circuit is also electrically connected to the second reset terminal, and is used to control the connection between the drive control signal output terminal and the second voltage line under the control of a second reset signal provided by the second reset terminal.

[0195] In at least one embodiment of the present disclosure, the third voltage line may be a second low voltage line, but is not limited thereto.

[0196] As shown in FIG3 , based on at least one embodiment of the driving circuit shown in FIG1 , the driving control signal generating circuit may include a pull-up node control circuit 31, a first pull-down node control circuit 32, a second pull-down node control circuit 33, a driving control output circuit 34, and a carry output circuit 35;

[0197] The pull-up node control circuit 31 is electrically connected to the input terminal I1, the frame reset line TRST, the first pull-down node PD1, the second pull-down node PD2, the first reset terminal RST1, the pull-up node PU, and the second low-voltage line LVGL, respectively, and is configured to control the potential of the pull-up node PU under the control of the input signal provided by the input terminal I1, and control the connection between the pull-up node PU and the second low-voltage line LVGL under the control of the frame reset signal provided by the frame reset line TRST, control the connection between the pull-up node PU and the second low-voltage line LVGL under the control of the potential of the first pull-down node PD1, control the connection between the pull-up node PU and the second low-voltage line LVGL under the control of the potential of the second pull-down node PD2, and control the connection between the pull-up node PU and the second low-voltage line LVGL under the control of the first reset signal provided by the first reset terminal RST1;

[0198] The first pull-down node control circuit 32 is electrically connected to the first control voltage line VDDo, the first pull-down node PD1, the pull-up node PU, and the second low voltage line LVGL, respectively, and is configured to control the potential of the first pull-down node PD1 under the control of the first control voltage provided by the first control voltage line VDDo and the potential of the pull-up node PU;

[0199] The second pull-down node control circuit 33 is electrically connected to the second control voltage line VDDe, the second pull-down node PD2, the pull-up node PU, and the second low voltage line LVGL, respectively, and is used to control the potential of the second pull-down node PD2 under the control of the second control voltage provided by the second control voltage line VDDe and the potential of the pull-up node PU;

[0200] The drive control output circuit 34 is electrically connected to the pull-up node PU, the first pull-down node PD1, the second pull-down node PD2, the drive control signal output terminal G01, the drive control clock signal line CLK, and the first low-voltage line VGL, respectively, and is configured to control the drive control clock signal line CLK to be electrically connected to the drive control signal output terminal G01 under the control of the potential of the pull-up node PU, control the drive control signal output terminal G01 to be connected to the first low-voltage line VGL under the control of the potential of the first pull-down node PD1, and control the drive control signal output terminal G01 to be connected to the first low-voltage line VGL under the control of the potential of the second pull-down node PD2;

[0201] The drive control output circuit 34 is also electrically connected to the second reset terminal RST2, and is used to control the connection between the drive control signal output terminal G01 and the first low voltage line VGL under the control of the second reset signal provided by the second reset terminal RST2;

[0202] The carry output circuit 35 is electrically connected to the pull-up node PU, the first pull-down node PD1, the second pull-down node PD2, the carry output terminal CR, the drive control clock signal line CLK and the second low voltage line LVGL, respectively, and is used to control the drive control clock signal line CLK to be electrically connected to the carry output terminal CR under the control of the potential of the pull-up node PU, control the carry output terminal CR to be connected to the second low voltage line under the control of the potential of the first pull-down node PD1, and control the carry output terminal CR to be connected to the second low voltage line LVGL under the control of the potential of the second pull-down node PD3.

[0203] As shown in FIG4 , based on at least one embodiment of the driving circuit shown in FIG3 , the first output sub-circuit 11 may include a first output transistor MO1 , a first on / off control transistor MV1 , a first output capacitor CO1 , a first first output pull-down transistor MD11 , and a first second output pull-down transistor MD12 ;

[0204] The gate of the first output transistor MO1 is electrically connected to the first pull-up control node PM1, the drain of the first output transistor MO1 is electrically connected to the first output clock signal line HC1, and the source of the first output transistor MO1 is electrically connected to the first drive signal output terminal GO1;

[0205] The gate of the first output transistor MO1 is electrically connected to the drive control signal output terminal G01 through the first on-off control transistor MV1;

[0206] The gate of the first on-off control transistor MV1 is electrically connected to the high voltage line VGH, the drain of the first on-off control transistor MV1 is electrically connected to the drive control signal output terminal G01, and the source of the first on-off control transistor MV1 is electrically connected to the gate of the first output transistor MO1;

[0207] The first plate of the first output capacitor CO1 is electrically connected to the gate of the first output transistor MO1, and the second plate of the first output capacitor CO1 is electrically connected to the source of the first output transistor MO1;

[0208] The gate of the first first output pull-down transistor MD11 is electrically connected to the first pull-down node PD1, the drain of the first first output pull-down transistor MD11 is electrically connected to the first drive signal output terminal GO1, and the source of the first first output pull-down transistor MD11 is electrically connected to the first low voltage line VGL;

[0209] The gate of the first second output pull-down transistor MD12 is electrically connected to the second pull-down node PD2, the drain of the first second output pull-down transistor MD12 is electrically connected to the first drive signal output terminal GO1, and the source of the first second output pull-down transistor MD12 is electrically connected to the first low voltage line VGL;

[0210] The second output sub-circuit 12 may include a second output transistor MO2, a second on-off control transistor MV2, a second output capacitor CO2, a second first output pull-down transistor MD21 and a second second output pull-down transistor MD22;

[0211] The gate of the second output transistor MO2 is electrically connected to the second pull-up control node PM2, the drain of the second output transistor MO2 is electrically connected to the second output clock signal line HC2, and the source of the second output transistor MO2 is electrically connected to the second drive signal output terminal GO2;

[0212] The gate of the second output transistor MO2 is electrically connected to the drive control signal output terminal G01 through the second on-off control transistor MV2;

[0213] The gate of the second on-off control transistor MV2 is electrically connected to the high voltage line VGH, the drain of the second on-off control transistor MV2 is electrically connected to the drive control signal output terminal G01, and the source of the second on-off control transistor MV2 is electrically connected to the gate of the second output transistor MO2;

[0214] The first plate of the second output capacitor CO2 is electrically connected to the gate of the second output transistor MO2, and the second plate of the second output capacitor CO2 is electrically connected to the source of the second output transistor MO2;

[0215] The gate of the second first output pull-down transistor MD21 is electrically connected to the first pull-down node PD1, the drain of the second first output pull-down transistor MD21 is electrically connected to the second drive signal output terminal GO2, and the source of the second first output pull-down transistor MD21 is electrically connected to the first low voltage line VGL;

[0216] The gate of the second second output pull-down transistor MD22 is electrically connected to the second pull-down node PD2, the drain of the second second output pull-down transistor MD22 is electrically connected to the second drive signal output terminal GO2, and the source of the second second output pull-down transistor MD22 is electrically connected to the first low voltage line VGL;

[0217] The third output sub-circuit 13 may include a third output transistor MO3, a third on-off control transistor MV3, a third output capacitor CO3, a third first output pull-down transistor MD31 and a third second output pull-down transistor MD32;

[0218] The gate of the third output transistor MO3 is electrically connected to the third pull-up control node PM3, the drain of the third output transistor MO3 is electrically connected to the third output clock signal line HC3, and the source of the third output transistor MO3 is electrically connected to the third drive signal output terminal GO3;

[0219] The gate of the third output transistor MO3 is electrically connected to the drive control signal output terminal G01 through the third on-off control transistor MV3;

[0220] The gate of the third on-off control transistor MV3 is electrically connected to the high voltage line VGH, the drain of the third on-off control transistor MV3 is electrically connected to the drive control signal output terminal G01, and the source of the third on-off control transistor MV3 is electrically connected to the gate of the third output transistor MO3;

[0221] The first plate of the third output capacitor CO3 is electrically connected to the gate of the third output transistor MO3, and the second plate of the third output capacitor CO3 is electrically connected to the source of the third output transistor MO3;

[0222] The gate of the third first output pull-down transistor MD31 is electrically connected to the first pull-down node PD1, the drain of the third first output pull-down transistor MD31 is electrically connected to the third drive signal output terminal GO3, and the source of the third first output pull-down transistor MD31 is electrically connected to the first low voltage line VGL;

[0223] The gate of the third second output pull-down transistor MD32 is electrically connected to the second pull-down node PD2, the drain of the third second output pull-down transistor MD32 is electrically connected to the third drive signal output terminal GO3, and the source of the third second output pull-down transistor MD32 is electrically connected to the first low voltage line VGL;

[0224] The fourth output sub-circuit 14 may include a fourth output transistor MO4, a fourth on-off control transistor MV4, a fourth output capacitor CO4, a fourth first output pull-down transistor MD41 and a fourth second output pull-down transistor MD42;

[0225] The gate of the fourth output transistor MO4 is electrically connected to the fourth pull-up control node PM4, the drain of the fourth output transistor MO4 is electrically connected to the fourth output clock signal line HC4, and the source of the fourth output transistor MO4 is electrically connected to the fourth drive signal output terminal GO4;

[0226] The gate of the fourth output transistor MO4 is electrically connected to the drive control signal output terminal G01 through the fourth on-off control transistor MV4;

[0227] The gate of the fourth on-off control transistor MV4 is electrically connected to the high voltage line VGH, the drain of the fourth on-off control transistor MV4 is electrically connected to the drive control signal output terminal G01, and the source of the fourth on-off control transistor MV4 is electrically connected to the gate of the fourth output transistor MO4;

[0228] The first plate of the fourth output capacitor CO4 is electrically connected to the gate of the fourth output transistor MO4, and the second plate of the fourth output capacitor CO4 is electrically connected to the source of the fourth output transistor MO4;

[0229] The gate of the fourth first output pull-down transistor MD41 is electrically connected to the first pull-down node PD1, the drain of the fourth first output pull-down transistor MD41 is electrically connected to the fourth drive signal output terminal GO4, and the source of the fourth first output pull-down transistor MD41 is electrically connected to the first low voltage line VGL;

[0230] The gate of the fourth second output pull-down transistor MD42 is electrically connected to the second pull-down node PD2, the drain of the fourth second output pull-down transistor MD42 is electrically connected to the fourth drive signal output terminal GO4, and the source of the fourth second output pull-down transistor MD42 is electrically connected to the first low voltage line VGL.

[0231] In at least one embodiment of the driving circuit shown in FIG. 4 , all transistors are n-type transistors, and all transistors are oxide thin film transistors, but the present invention is not limited thereto.

[0232] As shown in FIG5 , at least one embodiment of the driving circuit shown in FIG4 of the present disclosure is in operation.

[0233] In the first stage t1, G01 outputs a high voltage signal, MV1 is turned on, and PM1 is charged;

[0234] In the second phase t2, G01 outputs a high voltage signal, MO1 turns on, HC1 provides a high voltage signal to charge GO1, and at the same time, the potential of PM1 is further increased by the bootstrap effect of CO1, and GO1 outputs a high voltage signal. It should be noted that MV1 is in the off state at this time to prevent the potential of PM1 from being unable to bootstrap and increase.

[0235] In the third stage t3, G01 outputs a high voltage signal, MO1 is still in the open state, HC1 provides a low voltage signal, and GO1 outputs a low voltage signal;

[0236] In the period after the third stage t3, the potential of PD1 or the potential of PD2 is high, MD11 and MD12 are turned on, and GO1 is continuously discharged;

[0237] At least one embodiment of the driving circuit shown in FIG4 of the present disclosure is in operation.

[0238] When G01 outputs a high voltage signal and HC2 outputs a high voltage signal, GO2 outputs a high voltage signal;

[0239] When G01 outputs a high voltage signal and HC3 outputs a low voltage signal, GO2 outputs a low voltage signal;

[0240] When G01 outputs a high voltage signal and HC3 outputs a high voltage signal, GO3 outputs a high voltage signal;

[0241] When G01 outputs a high voltage signal and HC3 outputs a low voltage signal, GO3 outputs a low voltage signal;

[0242] When G01 outputs a high voltage signal and HC4 outputs a high voltage signal, GO4 outputs a high voltage signal;

[0243] When G01 outputs a high voltage signal and HC4 outputs a low voltage signal, GO4 outputs a low voltage signal.

[0244] In at least one embodiment of the driving circuit shown in FIG4 , the function of the on-off control transistor is described as follows (taking MV1 as an example):

[0245] At the beginning of the first stage t1, the potential of PM1 is low. For MV1, its gate-source voltage is greater than the threshold voltage of MV1, and the drive control signal output by G01 charges PM1. When the potential of PM1 is bootstrapped, the potential of PM1 is greater than the voltage value of the high voltage signal provided by VGH, and MV1 is in the off state.

[0246] If MV1 is not set, the potential of PM1 cannot be self-booted. The reason is that the transistor whose gate is electrically connected to the pull-up node PU included in the drive control output circuit on the left is in the open state, and the drive control clock signal line outputs a high voltage signal, which is an active signal. The bootstrapped charge will flow through the transistor to the drive control clock signal line, thereby failing to complete the bootstrap of PM2.

[0247] FIG6 is a timing diagram of the driving control signal provided by G01, the potential of PM1, and the first driving signal output by GO1 during operation of at least one embodiment of the driving circuit shown in FIG4.

[0248] Figure 7 is a timing diagram of the drive control signal provided by G01, the potential of PM1, and the first drive signal output by GO1, when at least one embodiment of the drive circuit shown in Figure 4 is not provided with the on / off control transistors. As shown in Figure 7, when MV1 is not provided, the potential of PM1 cannot be bootstrapped.

[0249] Optionally, the pull-up node control circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor;

[0250] The control electrode of the first transistor and the first electrode of the first transistor are electrically connected to the input terminal, and the second electrode of the first transistor is electrically connected to the pull-up node;

[0251] The control electrode of the second transistor is electrically connected to the first reset terminal, the first electrode of the second transistor is electrically connected to the pull-up node, and the second electrode of the second transistor is electrically connected to the third voltage line;

[0252] The control electrode of the third transistor is electrically connected to the frame reset terminal, the first electrode of the third transistor is electrically connected to the pull-up node, and the second electrode of the third transistor is electrically connected to the third voltage line;

[0253] A control electrode of the fourth transistor is electrically connected to the first pull-down node, a first electrode of the fourth transistor is electrically connected to the pull-up node, and a second electrode of the fourth transistor is electrically connected to the third voltage line;

[0254] The control electrode of the fifth transistor is electrically connected to the second pull-down node, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the third voltage line;

[0255] The first pull-down node control circuit includes a sixth transistor and a seventh transistor;

[0256] The control electrode of the sixth transistor and the first electrode of the sixth transistor are electrically connected to the first control voltage line, and the second electrode of the sixth transistor is electrically connected to the first pull-down node;

[0257] A control electrode of the seventh transistor is electrically connected to the pull-up node, a first electrode of the seventh transistor is electrically connected to the first pull-down node, and a second electrode of the seventh transistor is electrically connected to the third voltage line;

[0258] The second pull-down node control circuit includes an eighth transistor and a ninth transistor;

[0259] The control electrode of the eighth transistor and the first electrode of the eighth transistor are electrically connected to the second control voltage line, and the second electrode of the eighth transistor is electrically connected to the second pull-down node;

[0260] The control electrode of the ninth transistor is electrically connected to the pull-up node, the first electrode of the ninth transistor is electrically connected to the second pull-down node, and the second electrode of the ninth transistor is electrically connected to the third voltage line.

[0261] In at least one embodiment of the present disclosure, the ratio of the channel width-to-length ratio of the seventh transistor to the channel width-to-length ratio of the sixth transistor is greater than or equal to 6, and the ratio of the channel width-to-length ratio of the ninth transistor to the channel width-to-length ratio of the eighth transistor is greater than or equal to 6.

[0262] Optionally, the first pull-down node control circuit further includes a tenth transistor, and the second pull-down node control circuit further includes an eleventh transistor;

[0263] The control electrode of the tenth transistor is electrically connected to the input terminal, the first electrode of the tenth transistor is electrically connected to the first pull-down node, and the second electrode of the tenth transistor is electrically connected to the third voltage line;

[0264] The control electrode of the eleventh transistor is electrically connected to the input terminal, the first electrode of the eleventh transistor is electrically connected to the second pull-down node, and the second electrode of the eleventh transistor is electrically connected to the third voltage line.

[0265] Optionally, the carry output circuit includes a twelfth transistor, a thirteenth transistor and a fourteenth transistor;

[0266] The control electrode of the twelfth transistor is electrically connected to the pull-up node, the first electrode of the twelfth transistor is electrically connected to the drive control clock signal line, and the second electrode of the twelfth transistor is electrically connected to the carry output terminal;

[0267] The control electrode of the thirteenth transistor is electrically connected to the first pull-down node, the first electrode of the thirteenth transistor is electrically connected to the carry output terminal, and the second electrode of the thirteenth transistor is electrically connected to the third voltage line;

[0268] The control electrode of the fourteenth transistor is electrically connected to the second pull-down node, the first electrode of the fourteenth transistor is electrically connected to the carry output terminal, and the second electrode of the fourteenth transistor is electrically connected to the third voltage line;

[0269] The drive control output circuit includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor and a first capacitor;

[0270] The control electrode of the fifteenth transistor is electrically connected to the pull-up node, the first electrode of the fifteenth transistor is electrically connected to the drive control clock signal line, and the second electrode of the fifteenth transistor is electrically connected to the drive control signal output terminal;

[0271] The control electrode of the sixteenth transistor is electrically connected to the first pull-down node, the first electrode of the sixteenth transistor is electrically connected to the drive control signal output terminal, and the second electrode of the sixteenth transistor is electrically connected to the second voltage line;

[0272] The control electrode of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the drive control signal output terminal, and the second electrode of the seventeenth transistor is electrically connected to the second voltage line;

[0273] The control electrode of the eighteenth transistor is electrically connected to the second reset terminal, the first electrode of the eighteenth transistor is electrically connected to the drive control signal output terminal, and the second electrode of the eighteenth transistor is electrically connected to the second voltage line;

[0274] The first plate of the first capacitor is electrically connected to the pull-up node, and the second plate of the first capacitor is electrically connected to the drive control signal output terminal.

[0275] As shown in FIG8 , based on at least one embodiment of the driving circuit shown in FIG4 , the pull-up node control circuit includes a first transistor M1 , a second transistor M2 , a third transistor M3 , a fourth transistor M4 and a fifth transistor M5 ;

[0276] The gate of the first transistor M1 and the drain of the first transistor M1 are electrically connected to the input terminal I1, and the source of the first transistor M1 is electrically connected to the pull-up node PU;

[0277] The source of the second transistor M2 is electrically connected to the first reset terminal RST1, the drain of the second transistor M2 is electrically connected to the pull-up node PU, and the source of the second transistor M2 is electrically connected to the second low voltage line LVGL;

[0278] The gate of the third transistor M3 is electrically connected to the frame reset terminal TRST, the drain of the third transistor M3 is electrically connected to the pull-up node PU, and the source of the third transistor M3 is electrically connected to the second low voltage line LVGL;

[0279] The gate of the fourth transistor M4 is electrically connected to the first pull-down node PD1, the drain of the fourth transistor M4 is electrically connected to the pull-up node PU, and the source of the fourth transistor M4 is electrically connected to the second low voltage line LVGL;

[0280] The gate of the fifth transistor M5 is electrically connected to the second pull-down node PD2, the drain of the fifth transistor M5 is electrically connected to the pull-up node PU, and the source of the fifth transistor M5 is electrically connected to the second low voltage line LVGL;

[0281] The first pull-down node control circuit includes a sixth transistor M6 and a seventh transistor M7;

[0282] The gate of the sixth transistor M6 and the drain of the sixth transistor M6 are electrically connected to the first control voltage line VDDo, and the source of the sixth transistor M6 is electrically connected to the first pull-down node PD1;

[0283] The gate of the seventh transistor M7 is electrically connected to the pull-up node PU, the drain of the seventh transistor M7 is electrically connected to the first pull-down node PD1, and the source of the seventh transistor M7 is electrically connected to the second low voltage line LVGL;

[0284] The second pull-down node control circuit includes an eighth transistor M8 and a ninth transistor M9;

[0285] The gate of the eighth transistor M8 and the drain of the eighth transistor M8 are electrically connected to the second control voltage line VDDe, and the source of the eighth transistor M8 is electrically connected to the second pull-down node PD2;

[0286] The gate of the ninth transistor M9 is electrically connected to the pull-up node PU, the drain of the ninth transistor M9 is electrically connected to the second pull-down node PD2, and the source of the ninth transistor M9 is electrically connected to the second low voltage line LVGL;

[0287] The first pull-down node control circuit further includes a tenth transistor M10, and the second pull-down node control circuit 33 further includes an eleventh transistor M11;

[0288] The gate of the tenth transistor M10 is electrically connected to the input terminal I1, the drain of the tenth transistor M10 is electrically connected to the first pull-down node PD1, and the source of the tenth transistor M10 is electrically connected to the second low voltage line LVGL;

[0289] The gate of the eleventh transistor M11 is electrically connected to the input terminal I1, the drain of the eleventh transistor M11 is electrically connected to the second pull-down node PD2, and the source of the eleventh transistor M11 is electrically connected to the second voltage line LVGL;

[0290] The carry output circuit 35 includes a twelfth transistor M12, a thirteenth transistor M13 and a fourteenth transistor M14;

[0291] The gate of the twelfth transistor M12 is electrically connected to the pull-up node PU, the drain of the twelfth transistor M12 is electrically connected to the drive control clock signal line CLK, and the source of the twelfth transistor M12 is electrically connected to the carry output terminal CR;

[0292] The gate of the thirteenth transistor M13 is electrically connected to the first pull-down node PD1, the drain of the thirteenth transistor M13 is electrically connected to the carry output terminal CR, and the source of the thirteenth transistor M13 is electrically connected to the second low voltage line LVGL;

[0293] The gate of the fourteenth transistor M14 is electrically connected to the second pull-down node PD2, the drain of the fourteenth transistor M14 is electrically connected to the carry output terminal CR, and the source of the fourteenth transistor M14 is electrically connected to the second low voltage line LVGL;

[0294] The driving control output circuit includes a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18 and a first capacitor C1;

[0295] The gate of the fifteenth transistor M15 is electrically connected to the pull-up node PU, the drain of the fifteenth transistor M15 is electrically connected to the drive control clock signal line CLK, and the source of the fifteenth transistor M15 is electrically connected to the drive control signal output terminal G01;

[0296] The gate of the sixteenth transistor M16 is electrically connected to the first pull-down node PD1, the drain of the sixteenth transistor M16 is electrically connected to the driving control signal output terminal G01, and the source of the sixteenth transistor M16 is electrically connected to the first low voltage line VGL;

[0297] The gate of the seventeenth transistor M17 is electrically connected to the second pull-down node PD2, the drain of the seventeenth transistor M17 is electrically connected to the driving control signal output terminal G01, and the source of the seventeenth transistor M17 is electrically connected to the first low voltage line VGL;

[0298] The gate of the eighteenth transistor M18 is electrically connected to the second reset terminal RST2, the drain of the eighteenth transistor M18 is electrically connected to the driving control signal output terminal G01, and the source of the eighteenth transistor M18 is electrically connected to the first low voltage line VGL;

[0299] The first plate of the first capacitor C1 is electrically connected to the pull-up node PU, and the second plate of the first capacitor C1 is electrically connected to the driving control signal output terminal G01.

[0300] In at least one embodiment of the driving circuit shown in FIG8 , the ratio of the channel width-to-length ratio of the seventh transistor M7 to the channel width-to-length ratio of the sixth transistor M6 is greater than or equal to 6, so that when the potential of the pull-up node PU is a high voltage, the potential of the first pull-down node PD1 can be a low voltage; and the ratio of the channel width-to-length ratio of the ninth transistor M9 to the channel width-to-length ratio of the eighth transistor M8 is greater than or equal to 6, so that when the potential of the pull-up node PU is a high voltage, the potential of the second pull-down node PD2 can be a low voltage. For example, the ratio of the channel width-to-length ratio of the seventh transistor M7 to the channel width-to-length ratio of the sixth transistor M6 can be equal to 10, and the ratio of the channel width-to-length ratio of the ninth transistor M9 to the channel width-to-length ratio of the eighth transistor M8 can be equal to 10.

[0301] In at least one embodiment of the driving circuit shown in FIG. 8 , all transistors are n-type transistors, and all transistors are oxide thin film transistors, but the present invention is not limited thereto.

[0302] In at least one embodiment of the driving circuit shown in FIG8 , the width-to-length ratio of M1 may be greater than or equal to 12 and less than or equal to 15, the width-to-length ratio of M2 may be greater than or equal to 2 and less than or equal to 5, the width-to-length ratio of M15 may be greater than or equal to 100 and less than or equal to 200, the width-to-length ratio of M18 may be greater than or equal to 4 and less than or equal to 6, the width-to-length ratio of M6 and the width-to-length ratio of M8 may be greater than or equal to 0.8 and less than or equal to 1.2, the width-to-length ratio of M7 and the width-to-length ratio of M9 may be greater than or equal to 4 and less than or equal to 4.8, the width-to-length ratio of M10 and the width-to-length ratio of M11 may be greater than or equal to 3 and less than or equal to 5, the width-to-length ratio of M4 and the width-to-length ratio of M5 may be greater than or equal to 13 and less than or equal to 15, and the width-to-length ratio of M12 may be greater than or equal to 1. The aspect ratio of M13 and M14 can be greater than or equal to 1 and less than or equal to 3, the aspect ratio of M16 and M17 can be greater than or equal to 7 and less than or equal to 9, the aspect ratio of M3 can be greater than or equal to 0.8 and less than or equal to 1.2, the aspect ratio of each on-off control transistor can be greater than or equal to 40 and less than or equal to 80, the aspect ratio of each output transistor can be greater than or equal to 100 and less than or equal to 200, the aspect ratio of each output pull-down transistor can be greater than or equal to 7 and less than or equal to 9, the capacitance value of the first capacitor can be greater than or equal to 1pF and less than or equal to 3pF, and the capacitance value of each output capacitor can be greater than or equal to 1pF and less than or equal to 3pF.

[0303] As shown in FIG9 , when at least one embodiment of the driving circuit shown in FIG8 of the present disclosure is in operation, a display cycle may include a first display stage S1 , a second display stage S2 , a third display stage S3 , a fourth display stage S4 and a fifth display stage S5 ;

[0304] In the first display phase S1, TRST provides a high voltage signal, M3 is turned on, and other transistors are turned off. A low voltage signal is written to the pull-up nodes in all row driver circuits. TRST connects all row driver circuits and reduces noise for all rows before the frame. The frame reset signal provided by TRST prevents abnormal signals at the front end of the gate driver architecture (such as the timing control chip) from causing noise to be transferred to the next frame.

[0305] In the second display stage S2, STV1 is a high voltage signal (the input terminal I1 in FIG8 is connected to the first start signal STV1), M1 is turned on, M10 and M11 are turned on, and other transistors are turned off. M1 writes a high voltage signal to the PU, M10 writes a low voltage signal to PD1, and M11 writes a low voltage signal to PD2. This design can reduce the discharge current through M10 and M11 when charging the PU. When the PU is charged to a certain level (usually when the potential of the PU rises to above 2V), M15 is turned on, G01 outputs a low voltage signal, and M7 and M9 are turned on to write low voltage signals to PD1 and PD2.

[0306] In the third display stage S3, M15 is turned on, CLK outputs a high voltage signal, M15 is turned on, M7 and M9 remain on, G01 outputs a high voltage signal, and the potential of PU is further increased under the bootstrap effect of C1;

[0307] In the fourth display stage S4, RST1 provides a high voltage signal, M2 is turned on, a low voltage signal is written to PU, M7 and M9 are turned off, VDDo writes a high voltage to PD1 through M6, VDDe writes a high voltage to PD2 through M8, M4, M5, M13, M14, M16 and M17 are all turned on to continuously reduce noise for PU, CR and G01, the potential of PU is low voltage, and CR and G01 both output low voltage signals;

[0308] In the period after the fourth display stage S4, the potentials of PD1 and PD2 are both high voltages, and M4, M5, M13, M14, M16 and M17 are continuously controlled to be turned on, and noise reduction is continuously performed for PU, CR and G01 until the end of this frame.

[0309] In FIG9 , the second drive control clock signal is labeled CK2 , the third drive control clock signal is labeled CK3 , and the fourth drive control clock signal is labeled CK4 ;

[0310] In a specific implementation, when the first-stage driving circuit is electrically connected to CLK in FIG. 9 , the second-stage driving circuit can be connected to CK2 , the third-stage driving circuit can be connected to CK3 , and the fourth-stage driving circuit can be connected to CK4 ; A is a positive integer;

[0311] The input terminal of the first stage driving circuit is connected to the first starting signal STV1, and the input terminal of the second stage driving circuit is connected to the second starting signal STV2 (STV2 is shown in FIG9 );

[0312] The input terminal of the third-stage driving circuit can be electrically connected to the driving control signal output terminal of the first-stage driving circuit, and the input terminal of the fourth-stage driving circuit can be electrically connected to the driving control signal output terminal of the second-stage driving circuit;

[0313] The first reset terminal of the first stage driving circuit can be electrically connected to the driving control signal output terminal of the third stage driving circuit, and the first reset terminal of the second stage driving circuit can be electrically connected to the driving control signal output terminal of the fourth stage driving circuit.

[0314] In at least one embodiment of the present disclosure, the driving circuit includes an input terminal and a driving control signal output terminal;

[0315] The input terminal of the B-th level driving circuit is electrically connected to the driving control signal output terminal of the B-2-th level driving circuit, and the reset terminal of the A-th level driving circuit is electrically connected to the driving control signal output terminal of the A+2-th level driving circuit.

[0316] A is a positive integer, B is an integer greater than 2;

[0317] The input end of the first-stage driving circuit is connected to the first starting signal, and the input end of the second-stage driving circuit is connected to the second starting signal.

[0318] The display substrate described in the embodiment of the present disclosure includes a base substrate and the above-mentioned multi-stage driving circuit arranged on the base substrate.

[0319] In at least one embodiment of the present disclosure, the display substrate includes a peripheral area and a display area; the driving circuit includes a driving control signal generating circuit and a multi-channel output circuit;

[0320] The multi-channel output circuit and the drive control signal generating circuit are arranged in the peripheral area;

[0321] The multi-channel output circuit is arranged on a side of the driving control signal generating circuit close to the display area.

[0322] In a specific implementation, the driving circuit can be arranged in the peripheral area, and the multi-channel output circuit is arranged on the side of the driving control signal generating circuit close to the display area, so that the driving signal output ends respectively included in the multi-channel output circuit are electrically connected to each row gate line in the display area.

[0323] In at least one embodiment of the present disclosure, the multi-channel output circuit includes N output sub-circuits and N output clock signal lines; N is an integer greater than 1;

[0324] The output clock signal line is arranged on a side of the output sub-circuit close to the display area, and the output clock signal line extends along a first direction.

[0325] In a specific implementation, each of the output clock signal lines is arranged on a side of the output sub-circuit close to the display area, which is beneficial to reducing the crossover distance between the output sub-circuit and the output clock signal line, thereby saving space.

[0326] In at least one embodiment of the present disclosure, the nth output sub-circuit may include an nth output transistor, and the nth output transistor may be disposed between the drive control signal generating circuit and the display area;

[0327] n is a positive integer less than or equal to N.

[0328] Optionally, the nth output subcircuit includes an nth output transistor; n is a positive integer less than or equal to N;

[0329] The active layer pattern of the nth output transistor includes at least one active portion independent of each other; the active portion extends along a first direction.

[0330] In at least one embodiment of the present disclosure, the extension direction of the active portion and the extension direction of the output clock signal line may both be a first direction. For example, the first direction may be vertical, but is not limited thereto.

[0331] In at least one embodiment of the present disclosure, active layer patterns of output transistors respectively included in the N output sub-circuits are arranged along a first direction.

[0332] Optionally, the nth output sub-circuit further includes an nth output pull-down unit, and the nth output pull-down unit includes an nth first output pull-down transistor and an nth second output pull-down transistor;

[0333] The active layer pattern of the nth first output pull-down transistor and the active layer pattern of the nth second output pull-down transistor are arranged along a first direction;

[0334] The active layer pattern of the nth first output pull-down transistor and the active layer pattern of the nth second output pull-down transistor both extend along the first direction.

[0335] In a specific implementation, the output pull-down units respectively included in the N output sub-circuits are arranged along the first direction.

[0336] In at least one embodiment of the present disclosure, the active layer pattern of each transistor extends along a first direction, the active layer patterns of the output transistors respectively included in the N output sub-circuits are arranged along the first direction, the active layer pattern of the nth first output pull-down transistor and the active layer pattern of the nth second output pull-down transistor are arranged along the first direction, and the output pull-down units respectively included in the N output sub-circuits are arranged along the first direction. The active layer patterns of each transistor are very dispersed, which is beneficial to heat dissipation of the active layer.

[0337] In a specific implementation, the display substrate includes a plurality of signal lines, the signal lines are electrically connected to the drive control signal generating circuit included in the drive circuit, and the signal lines extend along a first direction;

[0338] The shortest distance along the second direction between the gate of the transistor included in the drive control signal generating circuit and the signal line closest to the transistor in the drive control signal generating circuit is greater than the first predetermined distance;

[0339] The first direction intersects the second direction;

[0340] The gate of the transistor and the signal line are located in the same layer.

[0341] In at least one embodiment of the present disclosure, the shortest distance along the second direction between the gate of the transistor included in the drive control signal generating circuit and the signal line closest to the transistor in the drive control signal generating circuit is greater than the first predetermined distance, which is beneficial to prevent ESD (electrostatic discharge) of the wiring from damaging the transistor.

[0342] For example, the first predetermined distance may be 40 μm, and the second direction may be a horizontal direction, but is not limited thereto.

[0343] As shown in FIG. 11B and FIG. 20B , G6 is closest to VDDE, and the shortest distance between G6 and VDDE along the horizontal direction is a first shortest distance L01 , which is greater than 40 μm.

[0344] In at least one embodiment of the present disclosure, active layer patterns of transistors in the driving control signal generating circuit included in the driving circuit may all extend along the first direction, but the present invention is not limited thereto.

[0345] FIG. 10 is a top plan view of at least one embodiment of the driving circuit shown in FIG. 8 according to the present disclosure.

[0346] In Figures 10 and 11A, GND is a ground line, DR is a first peripheral test line, DG is a second peripheral test line, STV is a start signal line, CLK1 is a first drive control clock signal line, TRST is a frame reset line, VGL1 is a first first low voltage line, LVGL is a second low voltage line, VGH is a high voltage line, VDDo is a first control voltage line, and VDDe is a second control voltage line; VGL2 is a second first low voltage line, HC1 is a first output clock signal line, HC2 is a second output clock signal line, HC3 is a third output clock signal line, and HC4 is a fourth output clock signal line;

[0347] In FIG10 , CO1 is a first output capacitor, CO2 is a second output capacitor, CO3 is a third output capacitor, and CO4 is a fourth output capacitor;

[0348] The capacitor labeled C1 is the first capacitor.

[0349] 11A , 11B and 11C are plan views of the gate metal layer in FIG. 10 .

[0350] In FIG11A , GO1 is the gate of the first output transistor MO1 , GO2 is the gate of the second output transistor MO2 , GO3 is the gate of the third output transistor MO3 , and GO4 is the gate of the fourth output transistor MO4 ;

[0351] The gate of the first first output pull-down transistor MD11 is labeled GD11, the gate of the first second output pull-down transistor MD12 is labeled GD12, the gate of the second first output pull-down transistor MD21 is labeled GD21, the gate of the second second output pull-down transistor MD22 is labeled GD22, the gate of the third first output pull-down transistor MD31 is labeled GD32, the gate of the third second output pull-down transistor MD32 is labeled GD41, the gate of the fourth first output pull-down transistor MD41, and the gate of the fourth second output pull-down transistor MD42 is labeled GD42;

[0352] The gate of the first on-off control transistor MV1 is labeled GV1, the gate of the second on-off control transistor MV2 is labeled GV2, the gate of the third on-off control transistor MV3 is labeled GV3, and the gate of the fourth on-off control transistor MV4 is labeled GV4;

[0353] The gate of the first transistor M1 is labeled G1, the gate of the second transistor M2 is labeled G2, the gate of the third transistor M3 is labeled G3, the gate of the fourth transistor M4 is labeled G4, the gate of the fifth transistor M5 is labeled G5, the gate of the sixth transistor M6 is labeled G6, the gate of the seventh transistor M7 is labeled G7, the gate of the eighth transistor M8 is labeled G8, the gate of the ninth transistor M9 is labeled G9, and the gate of the tenth transistor M10 is labeled G11. The gate of the 11th transistor M10 is labeled G11, the gate of the 11th transistor M11 is labeled G12, the gate of the 12th transistor M12 is labeled G13, the gate of the 13th transistor M13 is labeled G14, the gate of the 14th transistor M14 is labeled G15, the gate of the 15th transistor M15 is labeled G16, the gate of the 16th transistor M16, the gate of the 17th transistor M17, and the gate of the 18th transistor M18 is labeled G18.

[0354] In FIG11A , CO1a is the first electrode plate of CO1 , CO2a is the first electrode plate of CO2 , CO3a is the first electrode plate of CO3 , CO4a is the first electrode plate of CO4 , and C1a is the first electrode plate of C1 .

[0355] 12A and 12B are plan views of the semiconductor layer in FIG. 10 .

[0356] FIG13 is a top plan view of the source / drain metal layer in FIG10 .

[0357] In FIG12A , the active layer pattern of the first output transistor MO1, labeled PO11, includes a first active portion, and the active layer pattern of the first output transistor MO1, labeled PO12, includes a second active portion; the active layer pattern of the second output transistor MO2, labeled PO21, includes a first active portion, and the active layer pattern of the second output transistor MO2, labeled PO22, includes a second active portion; the active layer pattern of the third output transistor MO3, labeled PO31, includes a first active portion, and the active layer pattern of the third output transistor MO3, labeled PO32, includes a second active portion; the active layer pattern of the fourth output transistor MO4, labeled PO41, includes a first active portion, and the active layer pattern of the fourth output transistor MO4, labeled PO42, includes a second active portion;

[0358] The active layer pattern labeled PD11 is the first first output pull-down transistor MD11, the active layer pattern labeled PD12 is the first second output pull-down transistor MD12, the active layer pattern labeled PD21 is the second first output pull-down transistor MD21, the active layer pattern labeled PD22 is the second second output pull-down transistor MD22, the active layer pattern labeled PD31 is the third first output pull-down transistor MD31, the active layer pattern labeled PD32 is the third second output pull-down transistor MD32, the active layer pattern labeled PD41 is the fourth first output pull-down transistor MD41, and the active layer pattern labeled PD42 is the fourth second output pull-down transistor MD42;

[0359] The active layer pattern labeled PV1 is for the first on-off control transistor MV1, the active layer pattern labeled PV2 is for the second on-off control transistor MV2, the active layer pattern labeled PV3 is for the third on-off control transistor MV3, and the active layer pattern labeled PV4 is for the fourth on-off control transistor MV4;

[0360] The active layer pattern labeled P1 is the active layer pattern of the first transistor M1, the active layer pattern labeled P2 is the active layer pattern of the second transistor M2, the active layer pattern labeled P3 is the active layer pattern of the third transistor M3, the active layer pattern labeled P4 is the active layer pattern of the fourth transistor M4, the active layer pattern labeled P5 is the active layer pattern of the fifth transistor M5, the active layer pattern labeled P6 is the active layer pattern of the sixth transistor M6, the active layer pattern labeled P7 is the active layer pattern of the seventh transistor M7, the active layer pattern labeled P8 is the active layer pattern of the eighth transistor M8, the active layer pattern labeled P9 is the active layer pattern of the ninth transistor M9, and the active layer pattern labeled P10 is the active layer pattern of the tenth transistor The active layer pattern labeled P11 is the active layer pattern of the eleventh transistor M11, the active layer pattern labeled P12 is the active layer pattern of the twelfth transistor M12, the active layer pattern labeled P13 is the active layer pattern of the thirteenth transistor M13, the active layer pattern labeled P14 is the active layer pattern of the fourteenth transistor M14, the active layer pattern labeled P15 is the active layer pattern of the fifteenth transistor M15, the active layer pattern labeled P16 is the active layer pattern of the sixteenth transistor M16, the active layer pattern labeled P17 is the active layer pattern of the seventeenth transistor M17, and the active layer pattern labeled P18 is the active layer pattern of the eighteenth transistor M18.

[0361] In FIG13 , CO1b is the second electrode plate of CO1, CO2b is the first electrode plate of CO2, CO3b is the second electrode plate of CO3, CO4b is the second electrode plate of CO4, and C1b is the second electrode plate of C1.

[0362] As shown in Figures 10 to 13, GND, DR, DG, STV, CLK1, CLK3, TRST, VGL1, LVGL, VGH, VDDo, VDDe, VGL2, HC1, HC2, HC3, and HC4 all extend vertically;

[0363] GND, DR, DG, STV, CLK1, CLK3, TRST, VGL1, LVGL, VGH, VDDo and VDDe are all arranged on the side of the transistor included in the driving circuit away from the display area, and VGL2, HC1, HC2, HC3 and HC4 are all arranged on the side of the transistor included in the driving circuit close to the display area.

[0364] As shown in Figures 10 to 13, PO11, PO12, PO21, PO22, PO31, PO32, PO41 and PO42 all extend in the vertical direction;

[0365] PO11, PO21, PO31, and PO41 are arranged in sequence along the vertical direction;

[0366] PO21, PO22, PO32 and PO42 are arranged in sequence along the vertical direction;

[0367] PD11, PD12, PD21, PD22, PD31, PD32, PD41 and PD42 all extend in the vertical direction;

[0368] PD11, PD12, PD21, PD22, PD31, PD32, PD41 and PD42 are arranged in sequence along the vertical direction;

[0369] CO1a, CO2a, CO3a and CO4a are arranged in sequence along the vertical direction;

[0370] PV1, PV2, PV3 and PV4 extend in the vertical direction, and PV1, PV2, PV3 and PV4 are arranged in sequence in the vertical direction;

[0371] P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16, P17 and P18 all extend in the vertical direction.

[0372] When the layout shown in Figures 10 to 13 is applied to a TPC (tablet computer) product, the width of the frame occupied by the driving circuit can be reduced by 0.1mm-0.5mm compared to the width of the frame occupied by the related driving circuit;

[0373] When the layout shown in Figures 10 to 13 is applied to NB (notebook computer) products, the width of the frame occupied by the driving circuit can be reduced by 0.1mm-0.5mm compared to the width of the frame occupied by the related driving circuit;

[0374] When the layout shown in Figures 10 to 13 is applied to a TV product, the width of the frame occupied by the driving circuit can be reduced by 0.2mm-0.8mm compared to the width of the frame occupied by the related driving circuit;

[0375] To facilitate the realization of narrow borders.

[0376] In at least one embodiment shown in FIG. 10 to FIG. 13 , the active layer of the transistor extends vertically, and the transistors are arranged vertically. The active layer is highly dispersed, which is beneficial to heat dissipation of the active layer.

[0377] Furthermore, in at least one embodiment of the present disclosure, different unit active layer layouts are selected, and each transistor selects a suitable unit according to its own size, and the unit of the active layer of each transistor varies from 5um to 25um;

[0378] The unit of the active layer of the transistor is 5 μm, which means that the width of each channel portion of the active layer of the transistor is 5 μm.

[0379] The unit of the active layer of the transistor is 10 μm, which means that the width of each channel portion of the active layer of the transistor is 10 μm.

[0380] The fact that the unit of the active layer of the transistor is 25 μm means that the width of each channel portion of the active layer of the transistor is 25 μm.

[0381] It should be noted that the ratio of the channel width-to-length ratio of M6 to that of M7, as well as the ratio of the channel width-to-length ratio of M8 to that of M9 will affect the waveform of the PU potential. M6 and M7 are preferably designed to maintain the same unit, and M8 and M9 are preferably designed to maintain the same unit, for example, the unit is equal to 5um; if M6 and M7 use different units, and M8 and M9 use different units, the ratio of the channel width-to-length ratio of M7 to that of M6 is greater than or equal to 6, and the ratio of the channel width-to-length ratio of M9 to that of M8 is greater than or equal to 6.

[0382] As shown in FIG12B , the width of P1 in the horizontal direction is W1, which is equal to 5 μm;

[0383] The width of P4 in the horizontal direction is W4, which is equal to 10 μm;

[0384] The width of PO11 in the horizontal direction is WO11, which is equal to 25 μm;

[0385] The width of P15 in the horizontal direction is W15, which is equal to 20 μm;

[0386] The width of PV1 in the horizontal direction is WV1, which is equal to 7 μm;

[0387] a width of P10 along the horizontal direction, a width of P6 along the horizontal direction, a width of P7 along the horizontal direction, a width of P11 along the horizontal direction, a width of P8 along the horizontal direction, a width of P9 along the horizontal direction, a width of P3 along the horizontal direction, a width of P13 along the horizontal direction, a width of P14 along the horizontal direction, a width of P16 along the horizontal direction, a width of P17 along the horizontal direction, a width of P2 along the horizontal direction, and a width of P18 along the horizontal direction may all be 5 μm;

[0388] The width of PV2 along the horizontal direction, the width of PV3 along the horizontal direction, and the width of PV4 along the horizontal direction may all be 7 μm;

[0389] The horizontal width of P5 can be 10 μm.

[0390] The width of PO12 along the horizontal direction, the width of PO21 along the horizontal direction, the width of PO22 along the horizontal direction, the width of PO31 along the horizontal direction, the width of PO32 along the horizontal direction, the width of PO41 along the horizontal direction, and the width of PO42 along the horizontal direction may all be 25 μm;

[0391] The horizontal width of PD11, the horizontal width of PD12, the horizontal width of PD21, the horizontal width of PD22, the horizontal width of PD31, the horizontal width of PD32, the horizontal width of PD41, and the horizontal width of PD42 may all be 5 μm.

[0392] In at least one embodiment shown in FIG. 12A and FIG. 12B , the length of P6 in the vertical direction is 10 μm, and the width of P6 in the horizontal direction is 5 μm;

[0393] The length of P10 in the vertical direction is 35 μm, and the width of P10 in the horizontal direction is 5 μm;

[0394] The length of P4 in the vertical direction is 250 μm, and the width of P4 in the horizontal direction is 10 μm;

[0395] The length of P1 in the vertical direction is 540 μm, and the width of P1 in the horizontal direction is 5 μm;

[0396] The length of PD11 in the vertical direction is 72 μm, and the width of PD11 in the horizontal direction is 5 μm;

[0397] The vertical length of PV1 is 180 μm, and the horizontal width of PD11 is 7 μm.

[0398] The length of P12 in the vertical direction is 360 μm, and the width of P12 in the horizontal direction is 10 μm;

[0399] The length of P15 in the vertical direction is 450 μm, and the width of P15 in the horizontal direction is 20 μm;

[0400] The length of P3 in the vertical direction is 35 μm, and the width of P1 in the horizontal direction is 5 μm;

[0401] The length of P13 in the vertical direction is 20 μm, and the width of P13 in the horizontal direction is 5 μm;

[0402] The length of P16 in the vertical direction is 75 μm, and the width of P16 in the horizontal direction is 5 μm;

[0403] The length of P2 in the vertical direction is 90 μm, and the width of P1 in the horizontal direction is 5 μm;

[0404] The length of P18 in the vertical direction is 40 μm, and the width of P18 in the horizontal direction is 5 μm;

[0405] The length of P8 in the vertical direction is the same as that of P6 in the vertical direction, and the width of P8 in the horizontal direction is the same as that of P6 in the horizontal direction;

[0406] The length of P7, the length of P9, and the length of P17 in the vertical direction are equal to the length of P16 in the vertical direction;

[0407] The horizontal width of P7, the horizontal width of P9, the horizontal width of P17, and the horizontal width of P16 are equal;

[0408] The length of P5 in the vertical direction is the same as that of P4 in the vertical direction, and the width of P5 in the horizontal direction is the same as that of P4 in the horizontal direction;

[0409] The length of PV2, the length of PV3, and the length of PV4 in the vertical direction are equal to the length of PV1 in the vertical direction;

[0410] The width of PV2, the width of PV3, and the width of PV4 along the horizontal direction are equal to the width of PV1 along the horizontal direction;

[0411] The length of PO12 along the vertical direction, the length of PO21 along the vertical direction, the length of PO22 along the vertical direction, the length of PO31 along the vertical direction, the length of PO32 along the vertical direction, the length of PO41 along the vertical direction, and the length of PO42 along the vertical direction are equal to the length of PO11 along the vertical direction;

[0412] The width of PO12 along the horizontal direction, the width of PO21 along the horizontal direction, the width of PO22 along the horizontal direction, the width of PO31 along the horizontal direction, the width of PO32 along the horizontal direction, the width of PO41 along the horizontal direction, and the width of PO42 along the horizontal direction are equal to the width of PO11 along the horizontal direction;

[0413] The length of PD12 along the vertical direction, the length of PD21 along the vertical direction, the length of PD22 along the vertical direction, the length of PD31 along the vertical direction, the length of PD32 along the vertical direction, the length of PD41 along the vertical direction, and the length of PD42 along the vertical direction are equal to the length of PD11 along the vertical direction;

[0414] The width of PD12 along the horizontal direction, the width of PD21 along the horizontal direction, the width of PD22 along the horizontal direction, the width of PD31 along the horizontal direction, the width of PD32 along the horizontal direction, the width of PD41 along the horizontal direction, and the width of PD42 along the horizontal direction are equal to the width of PO11 along the horizontal direction.

[0415] In at least one embodiment of the present disclosure, a ratio of the length of P6 in the vertical direction to the width of P6 in the horizontal direction may be greater than or equal to 1 and less than or equal to 3;

[0416] A ratio of the length of P10 in the vertical direction to the width of P6 in the horizontal direction may be greater than or equal to 5 and less than or equal to 10;

[0417] A ratio of the length of P4 in the vertical direction to the width of P5 in the horizontal direction may be greater than or equal to 18 and less than or equal to 32;

[0418] The ratio of the length of P1 in the vertical direction to the width of P6 in the horizontal direction may be greater than or equal to 80 and less than or equal to 130;

[0419] The ratio of the length of PO11 in the vertical direction to the width of P6 in the horizontal direction may be greater than or equal to 3 and less than or equal to 10;

[0420] The ratio of the length of PD11 in the vertical direction to the width of PD11 in the horizontal direction may be greater than or equal to 8 and less than or equal to 25;

[0421] A ratio of a length of PV1 in a vertical direction to a width of PV1 in a horizontal direction may be greater than or equal to 15 and less than or equal to 35;

[0422] The ratio of the length of P12 in the vertical direction to the width of P12 in the horizontal direction may be greater than or equal to 25 and less than or equal to 50;

[0423] The ratio of the length of P15 in the vertical direction to the width of P6 in the horizontal direction may be greater than or equal to 16 and less than or equal to 40;

[0424] The ratio of the length of P3 in the vertical direction to the width of P6 in the horizontal direction may be greater than or equal to 4 and less than or equal to 12;

[0425] The ratio of the length of P13 in the vertical direction to the width of P6 in the horizontal direction may be greater than or equal to 2 and less than or equal to 8;

[0426] The ratio of the length of P16 in the vertical direction to the width of P6 in the horizontal direction may be greater than or equal to 8 and less than or equal to 25;

[0427] The ratio of the length of P2 in the vertical direction to the width of P6 in the horizontal direction may be greater than or equal to 10 and less than or equal to 25;

[0428] A ratio of the length of P18 in the vertical direction to the width of P18 in the horizontal direction may be greater than or equal to 4 and less than or equal to 16;

[0429] But it is not limited to this.

[0430] In at least one embodiment of the present disclosure, in order to achieve a narrow frame, the active layer pattern of each transistor is designed to be a vertically long narrow strip type, which is convenient for layout.

[0431] In at least one embodiment of the present disclosure, the aspect ratio of the active layer pattern of the tenth transistor is greater than or equal to 5 and less than or equal to 10;

[0432] The aspect ratio of the active layer pattern of the fourth transistor and the aspect ratio of the active layer pattern of the fifth transistor are greater than or equal to 18 and less than or equal to 32;

[0433] The aspect ratio of the active layer pattern of the fifteenth transistor is greater than or equal to 16 and less than or equal to 40;

[0434] The aspect ratio of the active layer pattern of the twelfth transistor is greater than or equal to 25 and less than or equal to 50;

[0435] The aspect ratio of the active layer pattern of the first transistor is greater than or equal to 80 and less than or equal to 130;

[0436] The aspect ratio is a ratio between a length of the active layer pattern along a first direction and a width of the active layer pattern along a second direction.

[0437] Optionally, the first direction may be a vertical direction, and the second direction may be a horizontal direction.

[0438] In FIG. 10 , FIG. 11A, FIG. 11B, FIG. 12A, FIG. 12B, FIG. 13 , FIG. 19 , FIG. 20A, FIG. 20B, FIG. 21 , and FIG. 22 , Y indicates a first direction, and X indicates a second direction.

[0439] In at least one embodiment of the present disclosure, the width of the active layer pattern of each transistor along the horizontal direction is greater than or equal to 3 μm, so as to avoid the risk of breakage when the process fluctuates;

[0440] The active layer pattern of each transistor is greater than or equal to 10 μm, and the length in the vertical direction and the width in the horizontal direction of the active layer pattern of different transistors can be adjusted.

[0441] In at least one embodiment of the present disclosure, the driving circuit may include a driving control signal generating circuit; the driving control signal generating circuit includes a first capacitor;

[0442] The electrode plate of the first capacitor includes a first electrode plate portion and a second electrode plate portion that are interconnected; the first electrode plate portion is in a block shape;

[0443] The second electrode portion extends along a first direction;

[0444] A ratio of a length of the second electrode portion along the first direction to a width of the second electrode portion along the second direction is greater than or equal to 6 and less than or equal to 25.

[0445] In a specific implementation, the electrode plate of the first capacitor may be a first electrode plate and / or a second electrode plate. The following description takes the electrode plate as the first electrode plate as an example.

[0446] As shown in FIG11C , the first plate of the first capacitor includes a first plate portion C1a1 and a second plate portion C1a2 that are interconnected;

[0447] C1a1 is blocky, and C1a2 extends in the vertical direction;

[0448] The length of C1a2 along the vertical direction may be 467 μm, and the width of C1a2 along the horizontal direction may be 35 μm;

[0449] The length of C1a1 in the vertical direction may be 123 μm, and the width of C1a1 in the horizontal direction may be 85 μm;

[0450] But it is not limited to this.

[0451] In a specific implementation, a ratio of a length of the second electrode plate portion C1a2 in a vertical direction to a width of the second electrode plate portion C1a2 in a horizontal direction may be greater than or equal to 6 and less than or equal to 25.

[0452] In actual operation, since the active layer patterns of the transistors around the first capacitor are all long strips extending in the vertical direction, for layout convenience, the first plate of the first capacitor may include a second plate portion extending in the vertical direction.

[0453] Optionally, the driving circuit includes a driving control signal generating circuit and a multi-channel output circuit; the driving control signal generating circuit includes a first capacitor and a fifteenth transistor; the multi-channel output circuit includes an output sub-circuit; and the output sub-circuit includes an on-off control transistor;

[0454] The first capacitor is arranged between the fifteenth transistor and the on-off control transistor.

[0455] In at least one embodiment shown in FIG. 10 to FIG. 14 , the first capacitor C1 may be disposed between the fifteenth transistor M15 , the first on-off control transistor MV1 , the second on-off control transistor MV2 , and the third on-off control transistor MV3 .

[0456] In at least one embodiment shown in FIG. 10 to FIG. 14 , HC1, HC2, HC3, and HC4 are disposed on a side of each transistor included in the driving circuit close to the display area, which helps to reduce the crossover distance and save space.

[0457] The horizontal distance between the orthographic projection of VDDe on the substrate and the orthographic projection of P7 on the substrate is 60 μm, which helps to prevent ESD of the wiring from damaging the transistor.

[0458] FIG14 is a plan view of the second ITO (indium tin oxide) layer in FIG10 , and various components in the driving circuit can be coupled to each other through various conductive patterns provided on the second ITO layer.

[0459] In at least one embodiment shown in FIG10 , a gate metal layer, a semiconductor layer, a source / drain metal layer, and a second ITO layer are sequentially provided in a direction away from the base substrate;

[0460] An organic film layer and a passivation layer are provided between the source / drain metal layer and the second ITO layer. Vias are provided on the organic film layer and the passivation layer. Components in the driving circuit can be coupled to conductive patterns provided on the second ITO layer through the vias.

[0461] In at least one embodiment of the present disclosure, the channel width-to-length ratio of M1 may be greater than or equal to 12 and less than or equal to 15, and the channel width-to-length ratio of M2 may be greater than or equal to 2 and less than or equal to 5.

[0462] The channel width-to-length ratio of M15 can be greater than or equal to 100 and less than or equal to 200, and the channel width-to-length ratio of M18 can be greater than or equal to 4 and less than or equal to 6.

[0463] The channel width-to-length ratio of M6 may be greater than or equal to 0.8 and less than or equal to 1.2, and the channel width-to-length ratio of M7 may be greater than or equal to 4 and less than or equal to 4.8.

[0464] The channel width-to-length ratio of M11 may be greater than or equal to 3 and less than or equal to 5, and the channel width-to-length ratio of M5 may be greater than or equal to 13 and less than or equal to 15.

[0465] The channel width-to-length ratio of M12 may be greater than or equal to 70 and less than or equal to 90, the channel width-to-length ratio of M13 and the channel width-to-length ratio of M14 may be greater than or equal to 1 and less than or equal to 3, and the channel width-to-length ratio of M16 and the channel width-to-length ratio of M17 may be greater than or equal to 7 and less than or equal to 9.

[0466] The channel width-to-length ratio of MV1, the channel width-to-length ratio of MV2, the channel width-to-length ratio of MV3, and the channel width-to-length ratio of MV4 may be greater than or equal to 40 and less than or equal to 80;

[0467] The channel width-to-length ratio of MO1, the channel width-to-length ratio of MO2, the channel width-to-length ratio of MO3, and the channel width-to-length ratio of MO4 may be greater than or equal to 100 and less than or equal to 200;

[0468] The channel width-to-length ratio of MD11, the channel width-to-length ratio of MD12, the channel width-to-length ratio of MD21, the channel width-to-length ratio of MD22, the channel width-to-length ratio of MD31, the channel width-to-length ratio of MD32, the channel width-to-length ratio of MD41, and the channel width-to-length ratio of MD42 may be greater than or equal to 7 and less than or equal to 9;

[0469] The capacitance value of C1 can be greater than or equal to 1pF and less than or equal to 3pF;

[0470] The capacitance value of CO1, the capacitance value of CO2, the capacitance value of CO3, and the capacitance value of CO2 may be greater than or equal to 1 pF and less than or equal to 3 pF;

[0471] But it is not limited to this.

[0472] In at least one embodiment of the present disclosure, the display substrate includes a peripheral area and a display area; the driving circuit includes a driving control signal generating circuit and a multi-channel output circuit;

[0473] The driving control signal generating circuit is arranged in the peripheral area;

[0474] The multi-channel output circuit includes N output sub-circuits, and the nth output sub-circuit includes the nth output transistor; N is an integer greater than 1, and n is a positive integer less than or equal to N;

[0475] The nth output transistor is disposed in the display area.

[0476] In a specific implementation, the drive control signal generating circuit can be set in the peripheral area, and the multi-channel output circuit can be set in the display area; the nth output transistor included in the multi-channel output circuit can be set next to the thin film transistor included in the pixel circuit, the gate of the nth output transistor is electrically connected to the drive control signal output end, the drain of the nth output transistor is electrically connected to the output clock signal line, and the source of the nth output transistor is electrically connected to the drive signal output end.

[0477] As shown in FIG15 , the first first output transistor is labeled MO11, the first second output transistor is labeled MO12, the second first output transistor is labeled MO21, the second second output transistor is labeled MO22, the third first output transistor is labeled MO31, the third second output transistor is labeled MO32, the fourth first output transistor is labeled MO41, and the fourth second output transistor is labeled MO42.

[0478] The gate of MO11 is electrically connected to the first drive control signal output terminal G011, the drain of MO11 is electrically connected to the first first output clock signal line HC11, and the source of MO11 is electrically connected to the first drive signal output terminal GO1;

[0479] The gate of MO12 is electrically connected to the second drive control signal output terminal G012, the drain of MO12 is electrically connected to the first second output clock signal line HC12, and the source of MO12 is electrically connected to the second drive signal output terminal GO2;

[0480] The gate of MO21 is electrically connected to the first drive control signal output terminal G011, the drain of MO21 is electrically connected to the second first output clock signal line HC21, and the source of MO21 is electrically connected to the first drive signal output terminal GO1;

[0481] The gate of MO22 is electrically connected to the second drive control signal output terminal G012, the drain of MO22 is electrically connected to the second second output clock signal line HC22, and the source of MO22 is electrically connected to the second drive signal output terminal GO2;

[0482] The gate of MO31 is electrically connected to the first drive control signal output terminal G011, the drain of MO31 is electrically connected to the third first output clock signal line HC31, and the source of MO31 is electrically connected to the first drive signal output terminal GO1;

[0483] The gate of MO32 is electrically connected to the second drive control signal output terminal G012, the drain of MO32 is electrically connected to the third second output clock signal line HC32, and the source of MO32 is electrically connected to the second drive signal output terminal GO2;

[0484] The gate of MO41 is electrically connected to the first drive control signal output terminal G011, the drain of MO41 is electrically connected to the fourth first output clock signal line HC41, and the source of MO41 is electrically connected to the first drive signal output terminal GO1;

[0485] The gate of MO42 is electrically connected to the second driving control signal output terminal G012, the drain of MO42 is electrically connected to the fourth second output clock signal line HC42, and the source of MO42 is electrically connected to the second driving signal output terminal GO2.

[0486] In at least one embodiment shown in FIG. 15 , each output transistor is an n-type transistor, but the present invention is not limited thereto.

[0487] For example, when the display device is a display screen with a resolution of 1600×2560, there are 1600 pixel circuits in the horizontal direction.

[0488] In one case, each pixel circuit has an output clock signal line, and an output transistor is placed next to each pixel circuit. A drive control signal output terminal can be connected to 1600 output transistors. According to simulation, the channel width-to-length ratio of each output transistor is about 1000 / 5.

[0489] In another case, one output transistor may be provided for every eight pixel circuits, and one drive control signal output terminal may be connected to 200 output transistors.

[0490] But it is not limited to this.

[0491] It should be noted that the design of setting output transistors in the display area will affect the aperture ratio, which will reduce the aperture ratio by about 10%. This design is suitable for displays that require extremely narrow bezels but do not require extremely high brightness.

[0492] In addition, simulations have shown that M16 and M17 continuously reduce the noise of the drive control signal output terminal, and the output transistor is small in size. The output clock signal has little effect on the coupling of the drive control signal output terminal through the parasitic capacitance of the output transistor. The noise of the drive control signal is very small, and the noise of the drive signal provided by the corresponding drive signal output terminal is also very small. Therefore, in pursuit of an extremely narrow bezel design, MD11, MD12, MD21, MD22, MD31, MD32, MD41, and MD42 can be removed.

[0493] Simulations show that when the output pull-down transistors are removed, the driver circuit can normally output the corresponding drive signals. Figure 16 shows the waveforms of the drive signals output by the driver circuit in the initial state when the output pull-down transistors are removed. Figure 17 shows the waveforms of the drive signals output by the driver circuit after 1000 hours at 60 degrees Celsius when the output pull-down transistors are removed.

[0494] In a specific implementation, the multi-channel output circuit further includes N output clock signal lines;

[0495] The output clock signal line is arranged in the display area, thereby further achieving a narrow frame.

[0496] Optionally, the nth output sub-circuit further includes an nth on-off control transistor and an nth output capacitor; the nth on-off control transistor and the nth output capacitor are both arranged in the peripheral area;

[0497] The active layer pattern of the nth on-off control transistor extends along a first direction;

[0498] The active layer patterns of the on-off control transistors respectively included in the N output sub-circuits are arranged along a first direction;

[0499] The output capacitors respectively included in the N output sub-circuits are arranged along a first direction.

[0500] In a specific implementation, the active layer patterns of each on-off control transistor extend along the first direction, and the active layer patterns of the on-off control transistors respectively included in the N output sub-circuits are arranged along the first direction. The active layer patterns of each transistor are very dispersed, which is conducive to the heat dissipation of the active layer.

[0501] In at least one embodiment of the present disclosure, the active layer pattern of the nth on-off control transistor extends along a first direction;

[0502] The active layer patterns of the on-off control transistors respectively included in the N output sub-circuits are arranged along a first direction;

[0503] The output capacitors respectively included in the N output sub-circuits are arranged along a first direction.

[0504] FIG18 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.

[0505] As shown in FIG18 , based on at least one embodiment of the driving circuit shown in FIG3 , the first output sub-circuit 11 may include a first output transistor MO1 , a first on / off control transistor MV1 , and a first output capacitor CO1 ;

[0506] The gate of the first output transistor MO1 is electrically connected to the first pull-up control node PM1, the drain of the first output transistor MO1 is electrically connected to the first output clock signal line HC1, and the source of the first output transistor MO1 is electrically connected to the first drive signal output terminal GO1;

[0507] The gate of the first output transistor MO1 is electrically connected to the drive control signal output terminal G01 through the first on-off control transistor MV1;

[0508] The gate of the first on-off control transistor MV1 is electrically connected to the high voltage line VGH, the drain of the first on-off control transistor MV1 is electrically connected to the drive control signal output terminal G01, and the source of the first on-off control transistor MV1 is electrically connected to the gate of the first output transistor MO1;

[0509] The first plate of the first output capacitor CO1 is electrically connected to the gate of the first output transistor MO1, and the second plate of the first output capacitor CO1 is electrically connected to the source of the first output transistor MO1;

[0510] The second output sub-circuit 12 may include a second output transistor MO2, a second on-off control transistor MV2 and a second output capacitor CO2;

[0511] The gate of the second output transistor MO2 is electrically connected to the second pull-up control node PM2, the drain of the second output transistor MO2 is electrically connected to the second output clock signal line HC2, and the source of the second output transistor MO2 is electrically connected to the second drive signal output terminal GO2;

[0512] The gate of the second output transistor MO2 is electrically connected to the drive control signal output terminal G01 through the second on-off control transistor MV2;

[0513] The gate of the second on-off control transistor MV2 is electrically connected to the high voltage line VGH, the drain of the second on-off control transistor MV2 is electrically connected to the drive control signal output terminal G01, and the source of the second on-off control transistor MV2 is electrically connected to the gate of the second output transistor MO2;

[0514] The first plate of the second output capacitor CO2 is electrically connected to the gate of the second output transistor MO2, and the second plate of the second output capacitor CO2 is electrically connected to the source of the second output transistor MO2;

[0515] The third output sub-circuit 13 may include a third output transistor MO3, a third on-off control transistor MV3 and a third output capacitor CO3;

[0516] The gate of the third output transistor MO3 is electrically connected to the third pull-up control node PM3, the drain of the third output transistor MO3 is electrically connected to the third output clock signal line HC3, and the source of the third output transistor MO3 is electrically connected to the third drive signal output terminal GO3;

[0517] The gate of the third output transistor MO3 is electrically connected to the drive control signal output terminal G01 through the third on-off control transistor MV3;

[0518] The gate of the third on-off control transistor MV3 is electrically connected to the high voltage line VGH, the drain of the third on-off control transistor MV3 is electrically connected to the drive control signal output terminal G01, and the source of the third on-off control transistor MV3 is electrically connected to the gate of the third output transistor MO3;

[0519] The first plate of the third output capacitor CO3 is electrically connected to the gate of the third output transistor MO3, and the second plate of the third output capacitor CO3 is electrically connected to the source of the third output transistor MO3;

[0520] The fourth output sub-circuit 14 may include a fourth output transistor MO4, a fourth on-off control transistor MV4 and a fourth output capacitor CO4;

[0521] The gate of the fourth output transistor MO4 is electrically connected to the fourth pull-up control node PM4, the drain of the fourth output transistor MO4 is electrically connected to the fourth output clock signal line HC4, and the source of the fourth output transistor MO4 is electrically connected to the fourth drive signal output terminal GO4;

[0522] The gate of the fourth output transistor MO4 is electrically connected to the drive control signal output terminal G01 through the fourth on-off control transistor MV4;

[0523] The gate of the fourth on-off control transistor MV4 is electrically connected to the high voltage line VGH, the drain of the fourth on-off control transistor MV4 is electrically connected to the drive control signal output terminal G01, and the source of the fourth on-off control transistor MV4 is electrically connected to the gate of the fourth output transistor MO4;

[0524] The first plate of the fourth output capacitor CO4 is electrically connected to the gate of the fourth output transistor MO4, and the second plate of the fourth output capacitor CO4 is electrically connected to the source of the fourth output transistor MO4;

[0525] The pull-up node control circuit 31 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4 and a fifth transistor M5;

[0526] The gate of the first transistor M1 and the drain of the first transistor M1 are electrically connected to the input terminal I1, and the source of the first transistor M1 is electrically connected to the pull-up node PU;

[0527] The source of the second transistor M2 is electrically connected to the first reset terminal RST1, the drain of the second transistor M2 is electrically connected to the pull-up node PU, and the source of the second transistor M2 is electrically connected to the second low voltage line LVGL;

[0528] The gate of the third transistor M3 is electrically connected to the frame reset terminal TRST, the drain of the third transistor M3 is electrically connected to the pull-up node PU, and the source of the third transistor M3 is electrically connected to the second low voltage line LVGL;

[0529] The gate of the fourth transistor M4 is electrically connected to the first pull-down node PD1, the drain of the fourth transistor M4 is electrically connected to the pull-up node PU, and the source of the fourth transistor M4 is electrically connected to the second low voltage line LVGL;

[0530] The gate of the fifth transistor M5 is electrically connected to the second pull-down node PD2, the drain of the fifth transistor M5 is electrically connected to the pull-up node PU, and the source of the fifth transistor M5 is electrically connected to the second low voltage line LVGL;

[0531] The first pull-down node control circuit 32 includes a sixth transistor M6 and a seventh transistor M7;

[0532] The gate of the sixth transistor M6 and the drain of the sixth transistor M6 are electrically connected to the first control voltage line VDDo, and the source of the sixth transistor M6 is electrically connected to the first pull-down node PD1;

[0533] The gate of the seventh transistor M7 is electrically connected to the pull-up node PU, the drain of the seventh transistor M7 is electrically connected to the first pull-down node PD1, and the source of the seventh transistor M7 is electrically connected to the second low voltage line LVGL;

[0534] The second pull-down node control circuit 33 includes an eighth transistor M8 and a ninth transistor M9;

[0535] The gate of the eighth transistor M8 and the drain of the eighth transistor M8 are electrically connected to the second control voltage line VDDe, and the source of the eighth transistor M8 is electrically connected to the second pull-down node PD2;

[0536] The gate of the ninth transistor M9 is electrically connected to the pull-up node PU, the drain of the ninth transistor M9 is electrically connected to the second pull-down node PD2, and the source of the ninth transistor M9 is electrically connected to the second low voltage line LVGL;

[0537] The first pull-down node control circuit 32 further includes a tenth transistor M10, and the second pull-down node control circuit 33 further includes an eleventh transistor M11;

[0538] The gate of the tenth transistor M10 is electrically connected to the input terminal I1, the drain of the tenth transistor M10 is electrically connected to the first pull-down node PD1, and the source of the tenth transistor M10 is electrically connected to the second low voltage line LVGL;

[0539] The gate of the eleventh transistor M11 is electrically connected to the input terminal I1, the drain of the eleventh transistor M11 is electrically connected to the second pull-down node PD2, and the source of the eleventh transistor M11 is electrically connected to the second voltage line LVGL;

[0540] The carry output circuit 35 includes a twelfth transistor M12, a thirteenth transistor M13 and a fourteenth transistor M14;

[0541] The gate of the twelfth transistor M12 is electrically connected to the pull-up node PU, the drain of the twelfth transistor M12 is electrically connected to the drive control clock signal line CLK, and the source of the twelfth transistor M12 is electrically connected to the carry output terminal CR;

[0542] The gate of the thirteenth transistor M13 is electrically connected to the first pull-down node PD1, the drain of the thirteenth transistor M13 is electrically connected to the carry output terminal CR, and the source of the thirteenth transistor M13 is electrically connected to the second low voltage line LVGL;

[0543] The gate of the fourteenth transistor M14 is electrically connected to the second pull-down node PD2, the drain of the fourteenth transistor M14 is electrically connected to the carry output terminal CR, and the source of the fourteenth transistor M14 is electrically connected to the second low voltage line LVGL;

[0544] The driving control output circuit 34 includes a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18 and a first capacitor C1;

[0545] The gate of the fifteenth transistor M15 is electrically connected to the pull-up node PU, the drain of the fifteenth transistor M15 is electrically connected to the drive control clock signal line CLK, and the source of the fifteenth transistor M15 is electrically connected to the drive control signal output terminal G01;

[0546] The gate of the sixteenth transistor M16 is electrically connected to the first pull-down node PD1, the drain of the sixteenth transistor M16 is electrically connected to the driving control signal output terminal G01, and the source of the sixteenth transistor M16 is electrically connected to the first low voltage line VGL;

[0547] The gate of the seventeenth transistor M17 is electrically connected to the second pull-down node PD2, the drain of the seventeenth transistor M17 is electrically connected to the driving control signal output terminal G01, and the source of the seventeenth transistor M17 is electrically connected to the first low voltage line VGL;

[0548] The gate of the eighteenth transistor M18 is electrically connected to the second reset terminal RST2, the drain of the eighteenth transistor M18 is electrically connected to the driving control signal output terminal G01, and the source of the eighteenth transistor M18 is electrically connected to the first low voltage line VGL;

[0549] The first plate of the first capacitor C1 is electrically connected to the pull-up node PU, and the second plate of the first capacitor C1 is electrically connected to the driving control signal output terminal G01.

[0550] In at least one embodiment of the driving circuit shown in FIG. 18 , MO1 , MO2 , MO3 , and MO4 are disposed in the display area A0 , and other transistors and capacitors are disposed in the peripheral area B0 .

[0551] FIG. 19 is a top plan view of a portion excluding MO1 , MO2 , MO3 , and MO4 in at least one embodiment of the driving circuit shown in FIG. 18 .

[0552] In Figures 19 and 20A, GND is a ground line, DR is a first peripheral test line, DG is a second peripheral test line, STV is a start signal line, CLK1 is a first drive control clock signal line, TRST is a frame reset line, VGL1 is a first low voltage line, LVGL is a second low voltage line, VGH is a high voltage line, VDDo is a first control voltage line, and VDDe is a second control voltage line.

[0553] In FIG19 , CO1 is the first output capacitor, CO2 is the second output capacitor, CO3 is the third output capacitor, and CO4 is the fourth output capacitor;

[0554] The capacitor labeled C1 is the first capacitor.

[0555] 20A and 20B are plan views of the gate metal layer in FIG. 19 .

[0556] In FIG20A , GV1 is the gate of the first on-off control transistor MV1 , GV2 is the gate of the second on-off control transistor MV2 , GV3 is the gate of the third on-off control transistor MV3 , and GV4 is the gate of the fourth on-off control transistor MV4 ;

[0557] The gate of the first transistor M1 is labeled G1, the gate of the second transistor M2 is labeled G2, the gate of the third transistor M3 is labeled G3, the gate of the fourth transistor M4 is labeled G4, the gate of the fifth transistor M5 is labeled G5, the gate of the sixth transistor M6 is labeled G6, the gate of the seventh transistor M7 is labeled G7, the gate of the eighth transistor M8 is labeled G8, the gate of the ninth transistor M9 is labeled G9, and the gate of the tenth transistor M10 is labeled G11. The gate of the 11th transistor M10 is labeled G11, the gate of the 11th transistor M11 is labeled G12, the gate of the 12th transistor M12 is labeled G13, the gate of the 13th transistor M13 is labeled G14, the gate of the 14th transistor M14 is labeled G15, the gate of the 15th transistor M15 is labeled G16, the gate of the 16th transistor M16, the gate of the 17th transistor M17, and the gate of the 18th transistor M18 is labeled G18.

[0558] In FIG20A , CO1a is the first electrode plate of CO1, CO2a is the first electrode plate of CO2, CO3a is the first electrode plate of CO3, CO4a is the first electrode plate of CO4, and C1a is the first electrode plate of C1.

[0559] FIG. 21 is a top plan view of the semiconductor layer in FIG. 20A .

[0560] FIG. 22 is a top plan view of the source / drain metal layer in FIG. 20A .

[0561] In FIG21 , reference numeral PV1 is an active layer pattern of the first on-off control transistor MV1, reference numeral PV2 is an active layer pattern of the second on-off control transistor MV2, reference numeral PV3 is an active layer pattern of the third on-off control transistor MV3, and reference numeral PV4 is an active layer pattern of the fourth on-off control transistor MV4;

[0562] The active layer pattern labeled P1 is the active layer pattern of the first transistor M1, the active layer pattern labeled P2 is the active layer pattern of the second transistor M2, the active layer pattern labeled P3 is the active layer pattern of the third transistor M3, the active layer pattern labeled P4 is the active layer pattern of the fourth transistor M4, the active layer pattern labeled P5 is the active layer pattern of the fifth transistor M5, the active layer pattern labeled P6 is the active layer pattern of the sixth transistor M6, the active layer pattern labeled P7 is the active layer pattern of the seventh transistor M7, the active layer pattern labeled P8 is the active layer pattern of the eighth transistor M8, the active layer pattern labeled P9 is the active layer pattern of the ninth transistor M9, and the active layer pattern labeled P10 is the active layer pattern of the tenth transistor The active layer pattern labeled P11 is the active layer pattern of the eleventh transistor M11, the active layer pattern labeled P12 is the active layer pattern of the twelfth transistor M12, the active layer pattern labeled P13 is the active layer pattern of the thirteenth transistor M13, the active layer pattern labeled P14 is the active layer pattern of the fourteenth transistor M14, the active layer pattern labeled P15 is the active layer pattern of the fifteenth transistor M15, the active layer pattern labeled P16 is the active layer pattern of the sixteenth transistor M16, the active layer pattern labeled P17 is the active layer pattern of the seventeenth transistor M17, and the active layer pattern labeled P18 is the active layer pattern of the eighteenth transistor M18.

[0563] In FIG22 , CO1b is the second electrode plate of CO1, CO2b is the first electrode plate of CO2, CO3b is the second electrode plate of CO3, CO4b is the second electrode plate of CO4, and C1b is the second electrode plate of C1.

[0564] As shown in Figures 19 to 22, GND, DR, DG, STV, CLK1, CLK3, TRST, VGL1, LVGL, VGH, VDDo, and VDDe all extend vertically;

[0565] GND, DR, DG, STV, CLK1, CLK3, TRST, VGL1, LVGL, VGH, VDDo, and VDDe are all arranged on a side of the transistor included in the driving circuit away from the display area.

[0566] As shown in Figures 19 to 22, CO1a, CO2a, CO3a, and CO4a are arranged in sequence along the vertical direction;

[0567] PV1, PV2, PV3 and PV4 extend in the vertical direction, and PV1, PV2, PV3 and PV4 are arranged in sequence in the vertical direction;

[0568] P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16, P17 and P18 all extend in the vertical direction.

[0569] By adopting the layout of FIG. 19 to FIG. 22 , the width of the frame occupied by the driving circuit can be reduced by 0.4 mm compared with the width of the frame occupied by the existing driving circuit, which is conducive to achieving a narrow frame.

[0570] In at least one embodiment shown in FIG. 19 to FIG. 22 , the active layer of the transistor extends vertically, and the transistors are arranged vertically, and the active layer is dispersed, which is beneficial to heat dissipation of the active layer.

[0571] In at least one embodiment shown in FIG. 19 to FIG. 22 , the horizontal distance between the orthographic projection of VDDe on the substrate and the orthographic projection of P7 on the substrate is 60 μm, which helps prevent ESD from the wiring from damaging the transistor.

[0572] FIG23 is a plan view of the second ITO (indium tin oxide) layer in FIG19 , and various components in the driving circuit can be coupled to each other through various conductive patterns provided on the second ITO layer.

[0573] In at least one embodiment shown in FIG19 , a gate metal layer, a semiconductor layer, a source / drain metal layer, and a second ITO layer are sequentially provided in a direction away from the substrate.

[0574] An organic film layer and a passivation layer are provided between the source / drain metal layer and the second ITO layer. Vias are provided on the organic film layer and the passivation layer. Components in the driving circuit can be coupled to conductive patterns provided on the second ITO layer through the vias.

[0575] FIG24 is a plan view of a first output transistor provided in the display region.

[0576] Figure 25 is a top plan view of the gate metal layer in Figure 24, Figure 26 is a top plan view of the semiconductor layer in Figure 24, Figure 27 is a top plan view of the source and drain metal layer in Figure 24, Figure 28 is a top plan view of the first ITO layer in Figure 24, and Figure 29 is a top plan view of the second ITO layer in Figure 24.

[0577] In FIG25 , the gate of the first output transistor MO1 is labeled GT1 , the drive control signal output terminal is labeled G01 , and the first drive signal output terminal is labeled GO1 .

[0578] In FIG. 26 , the active layer pattern PO1 of MO1 is labeled. The active layer pattern PO1 of MO1 includes a source of MO1, a channel portion of MO1, and a drain of MO1, which are sequentially arranged from left to right.

[0579] In FIG27 , L1 is a first conductive connection portion, HC1 is a first output clock signal line, and the first conductive connection portion L1 is used to electrically connect the source of MO1 and the first drive signal output terminal GO1.

[0580] In FIG28 , the pixel electrode is denoted by PX.

[0581] In FIG29 , the common electrode is labeled CM.

[0582] In at least one embodiment shown in FIG. 24 , a gate metal layer, a semiconductor layer, a source / drain metal layer, a first ITO layer, and a second ITO layer are sequentially provided along a side away from the base substrate, but the present invention is not limited thereto.

[0583] In at least one embodiment of the present disclosure, the nth output transistor may be disposed in a display area; the display substrate may further include a plurality of rows of gate lines and a plurality of rows of common electrode lines disposed in the display area;

[0584] The gate lines and the common electrode lines both extend along a second direction;

[0585] The nth output transistor is disposed between the gate line and the common electrode line.

[0586] As shown in FIG30 , at least one embodiment of the display substrate may include a first output clock signal line HC1, a first data line DL1, a second output clock signal line HC2, a second data line DL2, a third output clock signal line HC3, a third data line DL3, a fourth output clock signal line HC4, a fourth data line DL4, a fifth output clock signal line HC5, a fifth data line DL5, a sixth output clock signal line HC6, and a sixth data line DL6, as well as gate lines GL extending in a horizontal direction, drive scan lines GS extending in a horizontal direction, and common electrode lines CML extending in a horizontal direction, which are disposed on a base substrate.

[0587] The display substrate further includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5 and a sixth thin film transistor T6;

[0588] The gate of T1 is electrically connected to the gate line GL, the source of T1 is electrically connected to the first data line DL1, and the drain of T1 is electrically connected to the corresponding pixel electrode;

[0589] The gate of T2 is electrically connected to the gate line GL, the source of T2 is electrically connected to the second data line DL2, and the drain of T2 is electrically connected to the corresponding pixel electrode;

[0590] The gate electrode of T3 is electrically connected to the gate line GL, the source electrode of T3 is electrically connected to the third data line DL3, and the drain electrode of T3 is electrically connected to the corresponding pixel electrode;

[0591] The gate electrode of T4 is electrically connected to the gate line GL, the source electrode of T4 is electrically connected to the fourth data line DL4, and the drain electrode of T4 is electrically connected to the corresponding pixel electrode;

[0592] The gate electrode of T5 is electrically connected to the gate line GL, the source electrode of T5 is electrically connected to the fifth data line DL5, and the drain electrode of T5 is electrically connected to the corresponding pixel electrode;

[0593] The gate electrode of T6 is electrically connected to the gate line GL, the source electrode of T6 is electrically connected to the sixth data line DL6, and the drain electrode of T6 is electrically connected to the corresponding pixel electrode;

[0594] The display substrate further includes a first output transistor MO1, a second output transistor MO2, a third output transistor MO3, a fourth output transistor MO4, a fifth output transistor MO5 and a sixth output transistor MO6;

[0595] MO1, MO2, MO3, MO4, MO5 and MO6 are all arranged between the gate line GL and the common electrode line CML;

[0596] The gate of MO1 is electrically connected to the driving scan line GS, the source of MO1 is electrically connected to HC1, and the drain of MO1 is electrically connected to the gate line GL;

[0597] The gate of MO2 is electrically connected to the driving scan line GS, the source of MO2 is electrically connected to HC2, and the drain of MO2 is electrically connected to the gate line GL;

[0598] The gate of MO3 is electrically connected to the driving scan line GS, the source of MO3 is electrically connected to HC3, and the drain of MO3 is electrically connected to the gate line GL;

[0599] The gate of MO4 is electrically connected to the driving scan line GS, the source of MO4 is electrically connected to HC4, and the drain of MO4 is electrically connected to the gate line GL;

[0600] The gate of MO5 is electrically connected to the driving scan line GS, the source of MO5 is electrically connected to HC5, and the drain of MO5 is electrically connected to the gate line GL;

[0601] The gate electrode of MO6 is electrically connected to the driving scan line GS, the source electrode of MO6 is electrically connected to HC6, and the drain electrode of MO6 is electrically connected to the gate line GL.

[0602] In at least one embodiment of the display substrate shown in FIG. 30 , MO1 , MO2 , MO3 , MO4 , MO5 , and MO6 are all disposed between the gate line GL and the common electrode line CML.

[0603] In at least one embodiment shown in FIG. 30 , each data line and each output clock signal line may be formed in a source / drain metal layer, and the gate line GL, the drive scan line GS, and the common electrode line CML may be formed in a gate metal layer.

[0604] Optionally, the active layer pattern of at least one transistor included in the driving circuit may include at least two active pattern portions extending along the first direction;

[0605] A distance in the second direction between two adjacent active pattern portions in the first direction is greater than a second predetermined distance.

[0606] For example, the second predetermined distance may be 3 μm, but is not limited thereto.

[0607] In at least one embodiment of the present disclosure, the active layer pattern of the transistor in the driver circuit can be a long, vertically extending strip, facilitating a narrow bezel. If a narrow bezel is not required, the transistor active layer pattern can include at least two vertically extending active pattern portions, with the horizontal distance between each two adjacent active pattern portions being greater than or equal to 3 μm, to facilitate heat dissipation and improve transistor performance.

[0608] As shown in FIG31 , the active layer pattern of at least one transistor in the driving circuit may include a first active pattern portion A11, a second active pattern portion A12, a third active pattern portion A13, a fourth active pattern portion A14, a fifth active pattern portion A15, a sixth active pattern portion A16, a seventh active pattern portion A17, and an eighth active pattern portion A18, which are independent of each other.

[0609] A11, A12, A13, A14, A15, A16, A17 and A18 extend in the vertical direction;

[0610] The width W011 of A11 along the horizontal direction is 5 μm;

[0611] A11 is adjacent to A12, and the distance L311 between A11 and A12 in the horizontal direction is 7 μm;

[0612] the width of A12 along the horizontal direction, the width of A13 along the horizontal direction, the width of A14 along the horizontal direction, the width of A15 along the horizontal direction, the width of A16 along the horizontal direction, the width of A17 along the horizontal direction, and the width of A18 along the horizontal direction are all 5 μm;

[0613] The horizontal distance between two adjacent active pattern portions is 7 μm.

[0614] But it is not limited to this.

[0615] In at least one embodiment shown in FIG31 , the lengths of the active pattern portions along the vertical direction are consistent, but the present invention is not limited thereto. In actual operation, the lengths of the active pattern portions along the vertical direction may be inconsistent or not completely consistent.

[0616] As shown in FIG32 , the active layer pattern of at least one transistor in the driving circuit may include a first active pattern portion A11, a second active pattern portion A12, a third active pattern portion A13, a fourth active pattern portion A14, a fifth active pattern portion A15, a sixth active pattern portion A16, a seventh active pattern portion A17, an eighth active pattern portion A18, a ninth active pattern portion A19, and a tenth active pattern portion A110, which are independent of each other.

[0617] A11, A12, A13, A14, A15, A16, A17, A18, A19 and A110 extend in the vertical direction;

[0618] the width of A11 along the horizontal direction, the width of A12 along the horizontal direction, the width of A13 along the horizontal direction, the width of A14 along the horizontal direction, the width of A15 along the horizontal direction, the width of A16 along the horizontal direction, the width of A17 along the horizontal direction, the width of A18 along the horizontal direction, the width of A19 along the horizontal direction, and the width of A110 along the horizontal direction are all 5 μm;

[0619] The horizontal distance between two adjacent active pattern portions is 7 μm.

[0620] The vertical lengths of A11, A12, A13, A14, A15, A16, A17, and A18 are all equal; the vertical length of A19 is less than the vertical length of A11, and the vertical length of A110 is less than the vertical length of A11. In a specific implementation, after the driver circuit and pixel circuit are fabricated on the substrate, a sealant is applied. The sealant may cover transistors in the driver circuit except for M15, M18, the output transistors, the output pull-down transistors, and the on / off control transistors.

[0621] The difference between at least one embodiment of the driving circuit shown in FIG33 of the present disclosure and at least one embodiment of the driving circuit shown in FIG8 of the present disclosure is that at least one embodiment of the driving signal generating circuit shown in FIG33 of the present disclosure removes MV1, MV2, MV3, MV4, CO1, CO2, CO3 and CO4;

[0622] After removing the on-off transistors and the output capacitors, the gate voltage of each output transistor no longer has a bootstrap effect. In order to ensure that each drive signal output end has a normal waveform output, the high voltage value of the output clock signal provided by each output clock signal line can be set to 17V, and the high voltage value of each drive control clock signal can be set to 30V. By increasing the gate-source voltage of each output transistor, the charging of each drive signal output end is guaranteed.

[0623] As shown in FIG. 34 and FIG. 35 , at least one embodiment of the driving circuit shown in FIG. 33 of the present disclosure can operate normally after the reliability test.

[0624] FIG34 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG33 of the present disclosure in an initial state before undergoing a reliability test.

[0625] FIG35 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG33 of the present disclosure after undergoing a reliability test (reliability test at 60 degrees Celsius for less than 1000 hours).

[0626] When using at least one embodiment of the driving circuit shown in FIG33 of the present disclosure and arranging the driving circuit in the peripheral area, the width of the frame occupied by the driving circuit can be reduced by 0.3 mm compared with the width of the frame occupied by the existing driving circuit, which is conducive to achieving a narrow frame.

[0627] When using at least one embodiment of the driving circuit shown in Figure 33 of the present disclosure, and setting the driving control signal generating circuit in the peripheral area, and setting each output transistor and each output clock signal generating circuit in the display area, the width of the border occupied by the driving circuit can be reduced by 0.5mm compared with the width of the border occupied by the existing driving circuit, which is conducive to achieving a narrow border.

[0628] The difference between at least one embodiment of the driving circuit shown in FIG36 of the present disclosure and at least one embodiment of the driving circuit shown in FIG8 of the present disclosure is that: the driving control signal generating circuit does not include M10, M11 and M18;

[0629] The driving control signal generating circuit further includes a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21 and a twentieth transistor M22;

[0630] The gate of M7 is electrically connected to the pull-up node PU, the drain of M7 is electrically connected to the source of M6, and the source of M7 is electrically connected to the second low voltage line LVGL;

[0631] The gate of M19 is electrically connected to the drain of M7, the drain of M19 is electrically connected to the first control voltage line VDDo, and the source of M19 is electrically connected to the first pull-down node PD1;

[0632] The gate of M20 is electrically connected to the pull-up node PU, the drain of M20 is electrically connected to the first pull-down node PD1, and the source of M20 is electrically connected to the second low voltage line LVGL;

[0633] The gate of M9 is electrically connected to the pull-up node PU, the drain of M9 is electrically connected to the source of M8, and the source of M9 is connected to the second low voltage line LVGL;

[0634] The gate of M21 is electrically connected to the drain of M9, the drain of M21 is electrically connected to the second control voltage line VDDe, and the source of M21 is electrically connected to the second pull-down node PD2;

[0635] A gate of M22 is electrically connected to the pull-up node PU, a drain of M22 is electrically connected to the second pull-down node PD2, and a source of M22 is electrically connected to the second low voltage line LVGL.

[0636] The difference between at least one embodiment of the driving circuit shown in FIG37 of the present disclosure and at least one embodiment of the driving circuit shown in FIG36 of the present disclosure is that the twelfth transistor M12, the thirteenth transistor M13 and the fourteenth transistor M14 are not provided.

[0637] The difference between at least one embodiment of the driving circuit shown in FIG. 38 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 8 of the present disclosure is that the fourth output sub-circuit 14 is not provided.

[0638] In at least one embodiment of the driving circuit shown in Figure 38 of the present disclosure, the three-level output sub-circuit outputs three-level driving signals under the control of the driving control signal, respectively, which can achieve the purpose of one driving circuit driving multiple rows of gate lines, effectively reducing the number of transistors used in the driving circuit, and facilitating the realization of a narrow frame.

[0639] In at least one embodiment of the present disclosure, the process conditions used are an oxide process with a mobility of 10, but the present invention is not limited thereto. In actual operation, an oxidation process with a mobility of 20 or 30 may also be used, but the present invention is not limited thereto.

[0640] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A driving circuit, comprising a driving control signal generating circuit and a multi-channel output circuit; the multi-channel output circuit comprises N-level output sub-circuits; N is an integer greater than 1; The drive control signal generating circuit is used to generate a drive control signal, and the drive control signal is output through the drive control signal output terminal; The nth output sub-circuit is electrically connected to the drive control signal output terminal, the nth output clock signal line and the nth drive signal output terminal respectively, and the nth output sub-circuit is used to control the nth output clock signal line to provide the nth output clock signal to the nth drive signal output terminal under the control of the drive control signal; n is a positive integer less than or equal to N.

2. The driving circuit according to claim 1, wherein: The nth output subcircuit comprises an nth output transistor; The control electrode of the nth output transistor is electrically connected to the drive control signal output terminal, the first electrode of the nth output transistor is electrically connected to the nth output clock signal line, and the second electrode of the nth output transistor is electrically connected to the nth drive signal output terminal.

3. The driving circuit according to claim 2, wherein: The nth output subcircuit further comprises an nth on-off control transistor; the control electrode of the nth output transistor is electrically connected to the drive control signal output terminal through the nth on-off control transistor; The control electrode of the nth on-off control transistor is electrically connected to the first voltage line, the first electrode of the nth on-off control transistor is electrically connected to the drive control signal output terminal, and the second electrode of the nth on-off control transistor is electrically connected to the control electrode of the nth output transistor.

4. The driving circuit according to claim 3, wherein: The nth output subcircuit further includes an nth output capacitor; The first plate of the nth output capacitor is electrically connected to the control electrode of the nth output transistor, and the second plate of the nth output capacitor is electrically connected to the second electrode of the nth output transistor.

5. The driving circuit according to claim 2, wherein: The nth output subcircuit further includes an nth output pull-down unit; The nth output pull-down unit is electrically connected to the pull-down node, the nth drive signal output terminal and the second voltage line respectively, and is used to control the nth drive signal output terminal under the control of the potential of the pull-down node. The signal output terminal is connected to the second voltage line.

6. The driving circuit according to claim 5, wherein: The pull-down node includes a first pull-down node and a second pull-down node; the nth output pull-down unit includes an nth first output pull-down transistor and an nth second output pull-down transistor; The control electrode of the nth first output pull-down transistor is electrically connected to the first pull-down node, the first electrode of the nth first output pull-down transistor is electrically connected to the nth drive signal output terminal, and the second electrode of the nth first output pull-down transistor is electrically connected to the second voltage line; The control electrode of the nth second output pull-down transistor is electrically connected to the second pull-down node, the first electrode of the nth second output pull-down transistor is electrically connected to the nth drive signal output terminal, and the second electrode of the nth second output pull-down transistor is electrically connected to the second voltage line.

7. The driving circuit according to any one of claims 1 to 6, wherein: The driving control signal generating circuit includes a pull-up node control circuit, a first pull-down node control circuit, a second pull-down node control circuit and a driving control output circuit; The pull-up node control circuit is used to control the potential of the pull-up node; The first pull-down node control circuit is used to control the potential of the first pull-down node under the control of the potential of the pull-up node; The second pull-down node control circuit is used to control the potential of the second pull-down node under the control of the potential of the pull-up node; The drive control output circuit is electrically connected to the pull-up node, the first pull-down node, the second pull-down node, the drive control signal output terminal, the drive control clock signal line and the second voltage line, respectively, and is used to control the drive control clock signal line to be electrically connected to the drive control signal output terminal under the control of the potential of the pull-up node, control the drive control signal output terminal to be connected to the second voltage line under the control of the potential of the first pull-down node, and control the drive control signal output terminal to be connected to the second voltage line under the control of the potential of the second pull-down node.

8. The driving circuit according to claim 7, wherein: The drive control signal generating circuit further includes a carry output circuit; The carry output circuit is electrically connected to the pull-up node, the first pull-down node, the second pull-down node, the carry output terminal, the drive control clock signal line and the third voltage line respectively, and is used for Under the control of the potential of the pull-up node, the drive control clock signal line is controlled to be electrically connected to the carry output terminal; under the control of the potential of the first pull-down node, the carry output terminal is controlled to be connected to the third voltage line; under the control of the potential of the second pull-down node, the carry output terminal is controlled to be connected to the third voltage line.

9. The driving circuit according to claim 8, wherein: The pull-up node control circuit is electrically connected to the input terminal, the frame reset line, the first pull-down node, the second pull-down node, the first reset terminal, the pull-up node and the third voltage line, respectively, and is used to control the potential of the pull-up node under the control of the input signal provided by the input terminal, and control the connection between the pull-up node and the third voltage line under the control of the frame reset signal provided by the frame reset line, control the connection between the pull-up node and the third voltage line under the control of the potential of the first pull-down node, control the connection between the pull-up node and the third voltage line under the control of the potential of the second pull-down node, and control the connection between the pull-up node and the third voltage line under the control of the first reset signal provided by the first reset terminal; The first pull-down node control circuit is electrically connected to the first control voltage line, the first pull-down node, the pull-up node and the third voltage line respectively, and is used to control the potential of the first pull-down node under the control of the first control voltage provided by the first control voltage line and the potential of the pull-up node; The second pull-down node control circuit is electrically connected to the second control voltage line, the second pull-down node, the pull-up node and the third voltage line respectively, and is used to control the potential of the second pull-down node under the control of the second control voltage provided by the second control voltage line and the potential of the pull-up node; The drive control output circuit is also electrically connected to the second reset terminal, and is used to control the connection between the drive control signal output terminal and the second voltage line under the control of a second reset signal provided by the second reset terminal.

10. The driving circuit according to claim 9, wherein: The pull-up node control circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor; The control electrode of the first transistor and the first electrode of the first transistor are electrically connected to the input terminal, and the second electrode of the first transistor is electrically connected to the pull-up node; The control electrode of the second transistor is electrically connected to the first reset terminal, the first electrode of the second transistor is electrically connected to the pull-up node, and the second electrode of the second transistor is electrically connected to the third voltage line; The control electrode of the third transistor is electrically connected to the frame reset terminal, the first electrode of the third transistor is electrically connected to the pull-up node, and the second electrode of the third transistor is electrically connected to the third voltage line; The control electrode of the fourth transistor is electrically connected to the first pull-down node, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the third voltage line; The control electrode of the fifth transistor is electrically connected to the second pull-down node, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the third voltage line; The first pull-down node control circuit includes a sixth transistor and a seventh transistor; The control electrode of the sixth transistor and the first electrode of the sixth transistor are electrically connected to the first control voltage line, and the second electrode of the sixth transistor is electrically connected to the first pull-down node; The control electrode of the seventh transistor is electrically connected to the pull-up node, the first electrode of the seventh transistor is electrically connected to the first pull-down node, and the second electrode of the seventh transistor is electrically connected to the third voltage line; The second pull-down node control circuit includes an eighth transistor and a ninth transistor; The control electrode of the eighth transistor and the first electrode of the eighth transistor are electrically connected to the second control voltage line, and the second electrode of the eighth transistor is electrically connected to the second pull-down node; The control electrode of the ninth transistor is electrically connected to the pull-up node, the first electrode of the ninth transistor is electrically connected to the second pull-down node, and the second electrode of the ninth transistor is electrically connected to the third voltage line.

11. The driving circuit according to claim 10, wherein: A ratio of a channel width-to-length ratio of the seventh transistor to a channel width-to-length ratio of the sixth transistor is greater than or equal to 6, and a ratio of a channel width-to-length ratio of the ninth transistor to a channel width-to-length ratio of the eighth transistor is greater than or equal to 6.

12. The driving circuit according to claim 10, wherein: The first pull-down node control circuit further includes a tenth transistor, and the second pull-down node control circuit further includes an eleventh transistor; The control electrode of the tenth transistor is electrically connected to the input terminal, the first electrode of the tenth transistor is electrically connected to the first pull-down node, and the second electrode of the tenth transistor is electrically connected to the third voltage line; The control electrode of the eleventh transistor is electrically connected to the input terminal, the first electrode of the eleventh transistor is electrically connected to the second pull-down node, and the second electrode of the eleventh transistor is electrically connected to the third voltage line.

13. The driving circuit according to claim 10, wherein: The carry output circuit includes a twelfth transistor, a thirteenth transistor and a fourteenth transistor; The control electrode of the twelfth transistor is electrically connected to the pull-up node, the first electrode of the twelfth transistor is electrically connected to the drive control clock signal line, and the second electrode of the twelfth transistor is electrically connected to the carry output terminal; The control electrode of the thirteenth transistor is electrically connected to the first pull-down node, the first electrode of the thirteenth transistor is electrically connected to the carry output terminal, and the second electrode of the thirteenth transistor is electrically connected to the third voltage line; The control electrode of the fourteenth transistor is electrically connected to the second pull-down node, the first electrode of the fourteenth transistor is electrically connected to the carry output terminal, and the second electrode of the fourteenth transistor is electrically connected to the third voltage line; The drive control output circuit includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor and a first capacitor; The control electrode of the fifteenth transistor is electrically connected to the pull-up node, the first electrode of the fifteenth transistor is electrically connected to the drive control clock signal line, and the second electrode of the fifteenth transistor is electrically connected to the drive control signal output terminal; The control electrode of the sixteenth transistor is electrically connected to the first pull-down node, the first electrode of the sixteenth transistor is electrically connected to the drive control signal output terminal, and the second electrode of the sixteenth transistor is electrically connected to the second voltage line; The control electrode of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the drive control signal output terminal, and the second electrode of the seventeenth transistor is electrically connected to the second voltage line; The control electrode of the eighteenth transistor is electrically connected to the second reset terminal, the first electrode of the eighteenth transistor is electrically connected to the drive control signal output terminal, and the second electrode of the eighteenth transistor is electrically connected to the second voltage line; The first plate of the first capacitor is electrically connected to the pull-up node, and the second plate of the first capacitor is electrically connected to the pull-up node. The electrode plate is electrically connected to the drive control signal output terminal.

14. A display substrate, comprising a base substrate and a plurality of driving circuits as claimed in any one of claims 1 to 13 arranged on the base substrate.

15. The display substrate according to claim 14, wherein: The display substrate includes a peripheral area and a display area; the driving circuit includes a driving control signal generating circuit and a multi-channel output circuit; The multi-channel output circuit and the drive control signal generating circuit are arranged in the peripheral area; The multi-channel output circuit is arranged on a side of the driving control signal generating circuit close to the display area.

16. The display substrate according to claim 15, wherein: The multi-channel output circuit includes N output sub-circuits and N output clock signal lines; N is an integer greater than 1; The output clock signal line is arranged on a side of the output sub-circuit close to the display area, and the output clock signal line extends along a first direction.

17. The display substrate according to claim 16, wherein: The nth output subcircuit includes an nth output transistor, and the nth output transistor is arranged between the driving control signal generating circuit and the display area; n is a positive integer less than or equal to N.

18. The display substrate according to claim 16, wherein: The nth output subcircuit includes an nth output transistor; n is a positive integer less than or equal to N; The active layer pattern of the nth output transistor includes at least one active portion independent of each other; the active portion extends along a first direction.

19. The display substrate according to claim 18, wherein: The active layer patterns of the output transistors respectively included in the N output sub-circuits are arranged along a first direction.

20. The display substrate according to claim 18, wherein: The nth output subcircuit further includes an nth output pull-down unit, wherein the nth output pull-down unit includes an nth first output pull-down transistor and an nth second output pull-down transistor; The active layer pattern of the nth first output pull-down transistor and the active layer pattern of the nth second output pull-down transistor are arranged along a first direction; The active layer pattern of the nth first output pull-down transistor and the active layer pattern of the nth second output pull-down transistor both extend along the first direction.

21. The display substrate according to claim 20, wherein: The output pull-down units respectively included in the N output sub-circuits are arranged along a first direction.

22. The display substrate according to claim 14, wherein: The display substrate includes a peripheral area and a display area; the driving circuit includes a driving control signal generating circuit and a multi-channel output circuit; The driving control signal generating circuit is arranged in the peripheral area; The multi-channel output circuit includes N output sub-circuits, and the nth output sub-circuit includes the nth output transistor; N is an integer greater than 1, and n is a positive integer less than or equal to N; The nth output transistor is disposed in the display area.

23. The display substrate according to claim 22, wherein: It also includes a plurality of rows of gate lines and a plurality of rows of common electrode lines arranged in the display area; The gate lines and the common electrode lines both extend along a second direction; The nth output transistor is disposed between the gate line and the common electrode line.

24. The display substrate according to claim 22, wherein: The multi-channel output circuit also includes N output clock signal lines; The output clock signal line is arranged in the display area.

25. The display substrate according to claim 14, wherein: The driving circuit includes a driving control signal generating circuit; the driving control signal generating circuit includes a first transistor, a fourth transistor, a fifth transistor, a tenth transistor, a twelfth transistor and a fifteenth transistor; The aspect ratio of the active layer pattern of the first transistor is greater than or equal to 80 and less than or equal to 130; The aspect ratio of the active layer pattern of the fourth transistor and the aspect ratio of the active layer pattern of the fifth transistor are greater than or equal to 18 and less than or equal to 32; The aspect ratio of the active layer pattern of the tenth transistor is greater than or equal to 5 and less than or equal to 10; The aspect ratio of the active layer pattern of the twelfth transistor is greater than or equal to 25 and less than or equal to 50; The aspect ratio of the active layer pattern of the fifteenth transistor is greater than or equal to 16 and less than or equal to 40; The aspect ratio is a ratio between a length of the active layer pattern along a first direction and a width of the active layer pattern along a second direction.

26. The display substrate according to claim 14, wherein: The driving circuit includes a driving control signal generating circuit; the driving control signal generating circuit includes a first capacitor; The electrode plate of the first capacitor includes a first electrode plate portion and a second electrode plate portion that are interconnected; the first electrode plate portion is in a block shape; The second electrode portion extends along a first direction; A ratio of a length of the second electrode portion along the first direction to a width of the second electrode portion along the second direction is greater than or equal to 6 and less than or equal to 25.

27. The display substrate according to claim 14, wherein: The driving circuit includes a driving control signal generating circuit and a multi-channel output circuit; the driving control signal generating circuit includes a first capacitor and a fifteenth transistor; the multi-channel output circuit includes an output sub-circuit; the output sub-circuit includes an on-off control transistor; The first capacitor is arranged between the fifteenth transistor and the on-off control transistor.

28. The display substrate according to claim 18 or 22, wherein: The nth output subcircuit further includes an nth on-off control transistor and an nth output capacitor; the nth on-off control transistor and the nth output capacitor are both arranged in the peripheral area; The active layer pattern of the nth on-off control transistor extends along the first direction; The active layer patterns of the on-off control transistors respectively included in the N output sub-circuits are arranged along a first direction; The output capacitors respectively included in the N output sub-circuits are arranged along a first direction.

29. The display substrate according to any one of claims 14 to 27, wherein: The display substrate includes a plurality of signal lines, the signal lines are electrically connected to a drive control signal generating circuit included in the drive circuit, and the signal lines extend along a first direction; The shortest distance along the second direction between the gate of the transistor included in the drive control signal generating circuit and the signal line closest to the transistor in the drive control signal generating circuit is greater than the first predetermined distance; The first direction intersects the second direction; The gate of the transistor is located at the same layer as the signal line.

30. The display substrate according to any one of claims 14 to 27, wherein: The active layer patterns of transistors in the driving control signal generating circuit included in the driving circuit all extend along the first direction.

31. The display substrate according to any one of claims 14 to 24, wherein: The active layer pattern of at least one transistor included in the driving circuit includes at least two active pattern parts extending along the first direction; A distance in the second direction between two active pattern portions adjacent to each other in the first direction is greater than a second predetermined distance.

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