Driving circuit, driving method, driving module and display device

Abstract

The present disclosure provides a driving circuit, a driving method, a driving module and a display device. The driving circuit comprises a driving signal generation circuit, a gating circuit, an output control circuit and an output circuit; the driving signal generation circuit is configured to perform a shift operation on an N-1th driving signal to obtain an Nth driving signal; the gating circuit is configured to control a gating input signal to be written into a first node under the control of a gating control signal; the output control circuit is configured to perform an AND NOT operation on the Nth driving signal and a potential at a second end of the output control circuit to obtain a first output signal; the output circuit is configured to invert the first output signal to obtain an output driving signal and provide the output driving signal through an output driving end; N is a positive integer. The present disclosure can update a local picture of a display screen by controlling a gating input signal provided by the gating input end, thereby reducing power consumption.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a driving circuit, driving method, driving module and display device. Background Technology

[0002] In related technologies, when updating the screen of an OLED (Organic Light Emitting Diode) display, the pixel voltage of all row pixel circuits needs to be initialized and written within one frame. However, in certain special screen conditions (such as Always-On Display (AOD) screens, where only a portion of the screen is illuminated without lighting up the entire phone screen), static screens, or screens with infrequent updates), most pixel circuits on the screen do not need to update their pixel voltages. That is, most pixel circuits can maintain their original display brightness through low-leakage LTPO (Low Temperature Polycrystalline Oxide) TFTs (Thin Film Transistors). Repeatedly writing and updating these pixel circuits results in wasted power consumption. Summary of the Invention

[0003] In one aspect, embodiments of this disclosure provide a driving circuit, including a driving signal generation circuit, a gating circuit, an output control circuit, and an output circuit;

[0004] The drive signal generation circuit is electrically connected to the N-1th stage drive signal output terminal and the Nth stage drive signal output terminal, respectively, and is used to perform a shift operation on the N-1th stage drive signal provided by the N-1th stage drive signal output terminal to obtain and output the Nth stage drive signal through the Nth stage drive signal output terminal.

[0005] The gating circuit is electrically connected to the first node, the gating input terminal, and the gating control terminal, respectively, and is used to control the gating input signal provided by the gating input terminal to be written into the first node under the control of the gating control signal provided by the gating control terminal;

[0006] The first terminal of the output control circuit is electrically connected to the output terminal of the Nth stage drive signal, and the second terminal of the output control circuit is electrically connected to the first node. It is used to perform a AND-NOT operation on the potential of the Nth stage drive signal and the second terminal of the output control circuit to obtain the first output signal.

[0007] The output circuit is used to invert the first output signal to obtain an output drive signal that is provided through the output drive terminal.

[0008] N is a positive integer.

[0009] Optionally, the gating circuit is used to control the writing of the gating input signal provided by the gating input terminal into the first node when the potential of the N-1th stage driving signal is a first voltage and the potential of the Nth stage driving signal is a second voltage.

[0010] Optionally, the gating circuit includes a first transistor; the gate of the first transistor is electrically connected to the gating control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the gating input terminal.

[0011] Optionally, the gating control terminal includes a first gating control terminal and a second gating control terminal; the gating circuit includes a first transistor and a second transistor;

[0012] The gate of the first transistor is electrically connected to the first gating control terminal, the first terminal of the first transistor is electrically connected to the first node, and the second terminal of the first transistor is electrically connected to the first terminal of the second transistor.

[0013] The gate of the second transistor is electrically connected to the second gating control terminal, and the second terminal of the second transistor is electrically connected to the gating input terminal;

[0014] The first gating control terminal is the output terminal of the (N-1)th stage drive signal, the second gating control terminal is the output terminal of the Nth stage drive signal, the first transistor is an n-type transistor, and the second transistor is a p-type transistor; or...

[0015] The first gating control terminal is the output terminal of the Nth stage drive signal, the second gating control terminal is the output terminal of the (N-1)th stage drive signal, the first transistor is a p-type transistor, and the second transistor is an n-type transistor; or...

[0016] The first gating control terminal is connected to the inverted signal of the (N-1)th stage drive signal, and the second gating control terminal is the output terminal of the Nth stage drive signal. Both the first transistor and the second transistor are p-type transistors; or...

[0017] The first gating control terminal is the output terminal of the Nth stage drive signal, and the second gating control terminal is connected to the inverted signal of the (N-1)th stage drive signal; both the first transistor and the second transistor are p-type transistors; or,

[0018] The first gating control terminal is the (N-1)th stage drive signal terminal, and the second gating control terminal is connected to the inverted signal of the Nth stage drive signal. Both the first transistor and the second transistor are n-type transistors; or,

[0019] The first gating control terminal is connected to the inverted signal of the Nth stage drive signal, and the second gating control terminal is the N-1th stage drive signal terminal. Both the first transistor and the second transistor are n-type transistors.

[0020] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a first initialization circuit;

[0021] The first initialization circuit is electrically connected to the initial control terminal, the first voltage terminal, and the first node, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.

[0022] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a first voltage sustaining circuit;

[0023] The first terminal of the first voltage maintenance circuit is electrically connected to the first node, and the second terminal of the first voltage maintenance circuit is electrically connected to a DC voltage terminal or the second node. The first voltage maintenance circuit is used to maintain the potential of the first node.

[0024] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a second voltage sustaining circuit, wherein the first node is electrically connected to the second terminal of the output control circuit through the second voltage sustaining circuit;

[0025] The second voltage sustaining circuit includes a first inverter, a second inverter, and a sustaining control circuit;

[0026] The input terminal of the first inverter is electrically connected to the first node, the output terminal of the first inverter is electrically connected to the second node, the input terminal of the second inverter is electrically connected to the second node, and the output terminal of the second inverter is electrically connected to the third node and the second terminal of the output control circuit.

[0027] The first inverter is used to invert the potential of the first node and output the inverted potential of the first node through the output terminal of the first inverter. The second inverter is used to invert the potential of its input terminal and output the inverted potential through the output terminal of the second inverter.

[0028] The maintenance control circuit is electrically connected to the maintenance control terminal, the third node, and the first node, respectively, and is used to control the connection or disconnection between the third node and the first node under the control of the maintenance control signal provided by the maintenance control terminal.

[0029] Optionally, the maintenance control terminal includes a first maintenance control terminal and a second maintenance control terminal;

[0030] The sustaining control circuit includes a third transistor and a fourth transistor;

[0031] The gate of the third transistor is electrically connected to the first sustaining control terminal, the first terminal of the third transistor is electrically connected to the first node, and the second terminal of the third transistor is electrically connected to the third node.

[0032] The gate of the fourth transistor is electrically connected to the second sustain control terminal, the first terminal of the fourth transistor is electrically connected to the third node, and the second terminal of the fourth transistor is electrically connected to the first node.

[0033] The third transistor is a p-type transistor, and the fourth transistor is an n-type transistor;

[0034] The first sustain control terminal is the (N-1)th stage drive signal terminal, and the second sustain control terminal is the first clock signal terminal; or,

[0035] The first sustain control terminal is the second clock signal terminal, and the second sustain control terminal is the first clock signal terminal.

[0036] Optionally, the first inverter includes a fifth transistor and a sixth transistor, and the second inverter includes a seventh transistor and an eighth transistor;

[0037] The gate of the fifth transistor is electrically connected to the first node, the first terminal of the fifth transistor is electrically connected to the first voltage terminal, and the second terminal of the fifth transistor is electrically connected to the second node.

[0038] The gate of the sixth transistor is electrically connected to the first node, the first terminal of the sixth transistor is electrically connected to the second node, and the second terminal of the sixth transistor is electrically connected to the second voltage terminal.

[0039] The fifth transistor is a p-type transistor, and the sixth transistor is an n-type transistor;

[0040] The gate of the seventh transistor is electrically connected to the second node, the first terminal of the seventh transistor is electrically connected to the first voltage terminal, and the second terminal of the seventh transistor is electrically connected to the third node;

[0041] The gate of the eighth transistor is electrically connected to the second node, the first terminal of the eighth transistor is electrically connected to the third node, and the second terminal of the eighth transistor is electrically connected to the second voltage terminal.

[0042] The seventh transistor is a p-type transistor, and the eighth transistor is an n-type transistor.

[0043] Optionally, the first initialization circuit includes a ninth transistor, and the first voltage sustaining circuit includes a first capacitor;

[0044] The gate of the ninth transistor is electrically connected to the initial control terminal, the first terminal of the ninth transistor is electrically connected to the first voltage terminal, and the second terminal of the ninth transistor is electrically connected to the first node.

[0045] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the DC voltage terminal or the second node.

[0046] Optionally, the output control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

[0047] The gate of the tenth transistor is electrically connected to the output terminal of the Nth stage drive signal, the first terminal of the tenth transistor is electrically connected to the first voltage terminal, and the second terminal of the tenth transistor is electrically connected to the fourth node.

[0048] The gate of the eleventh transistor is electrically connected to the first node, the first terminal of the eleventh transistor is electrically connected to the first voltage terminal, and the second terminal of the eleventh transistor is electrically connected to the fourth node.

[0049] The gate of the twelfth transistor is electrically connected to the output terminal of the Nth stage drive signal, the first terminal of the twelfth transistor is electrically connected to the fourth node, and the second terminal of the twelfth transistor is electrically connected to the fifth node.

[0050] The gate of the thirteenth transistor is electrically connected to the first node, the first terminal of the thirteenth transistor is electrically connected to the fifth node, and the second terminal of the thirteenth transistor is electrically connected to the second voltage terminal.

[0051] The tenth and eleventh transistors are p-type transistors, and the twelfth and thirteenth transistors are n-type transistors.

[0052] Optionally, the output control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

[0053] The gate of the tenth transistor is electrically connected to the output terminal of the Nth stage drive signal, the first terminal of the tenth transistor is electrically connected to the first voltage terminal, and the second terminal of the tenth transistor is electrically connected to the fourth node.

[0054] The gate of the eleventh transistor is electrically connected to the third node, the first terminal of the eleventh transistor is electrically connected to the first voltage terminal, and the second terminal of the eleventh transistor is electrically connected to the fourth node.

[0055] The gate of the twelfth transistor is electrically connected to the output terminal of the Nth stage drive signal, the first terminal of the twelfth transistor is electrically connected to the fourth node, and the second terminal of the twelfth transistor is electrically connected to the fifth node.

[0056] The gate of the thirteenth transistor is electrically connected to the third node, the first terminal of the thirteenth transistor is electrically connected to the fifth node, and the second terminal of the thirteenth transistor is electrically connected to the second voltage terminal.

[0057] The tenth and eleventh transistors are p-type transistors, and the twelfth and thirteenth transistors are n-type transistors.

[0058] Optionally, the output circuit includes a fourteenth transistor and a fifteenth transistor;

[0059] The gate of the fourteenth transistor is electrically connected to the fourth node, the first terminal of the fourteenth transistor is electrically connected to the first voltage terminal, and the second terminal of the fourteenth transistor is electrically connected to the output drive terminal.

[0060] The gate of the fifteenth transistor is electrically connected to the fourth node, the first terminal of the fifteenth transistor is electrically connected to the output drive terminal, and the second terminal of the fifteenth transistor is electrically connected to the second voltage terminal.

[0061] Optionally, the drive signal generation circuit includes a first control circuit, a second control circuit, a third inverter, and a second initialization circuit;

[0062] The first control circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the N-1th stage drive signal output terminal and the sixth node, respectively. Under the control of the first clock signal provided by the first clock signal terminal and the second clock signal provided by the second clock signal terminal, the N-1th stage drive signal output terminal is shifted and inverted to obtain the inverted signal output through the sixth node.

[0063] The second control circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the Nth stage drive signal output terminal, and the sixth node, respectively. It is used to invert the Nth stage drive signal provided by the Nth stage drive signal output terminal under the control of the first clock signal and the second clock signal, so as to obtain the inverted signal and output it through the sixth node.

[0064] The third inverter is electrically connected to the sixth node and the Nth stage drive signal output terminal, respectively, and is used to invert the potential of the sixth node and output the inverted signal through the Nth stage drive signal output terminal;

[0065] The second initialization circuit is electrically connected to the initial control terminal, the first voltage terminal, and the Nth stage drive signal output terminal, respectively, and is used to control the connection between the Nth stage drive signal output terminal and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.

[0066] Optionally, the first control circuit includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor;

[0067] The gate of the sixteenth transistor is electrically connected to the second clock signal terminal, the first terminal of the sixteenth transistor is electrically connected to the first voltage terminal, and the second terminal of the sixteenth transistor is electrically connected to the first terminal of the seventeenth transistor.

[0068] The gate of the seventeenth transistor is electrically connected to the output terminal of the (N-1)th stage drive signal, and the second terminal of the seventeenth transistor is electrically connected to the sixth node;

[0069] The gate of the eighteenth transistor is electrically connected to the output terminal of the (N-1)th stage drive signal, the first terminal of the eighteenth transistor is electrically connected to the sixth node, and the second terminal of the eighteenth transistor is electrically connected to the first terminal of the nineteenth transistor.

[0070] The gate of the nineteenth transistor is electrically connected to the first clock signal terminal, and the second terminal of the nineteenth transistor is electrically connected to the second voltage terminal.

[0071] The sixteenth and seventeenth transistors are p-type transistors, and the eighteenth and nineteenth transistors are n-type transistors.

[0072] Optionally, the second control circuit includes a twentieth transistor, a twenty-first transistor, a twenty-second transistor, and a twenty-third transistor;

[0073] The gate of the twentieth transistor is electrically connected to the first clock signal terminal, the first terminal of the twentieth transistor is electrically connected to the first voltage terminal, and the second terminal of the twentieth transistor is electrically connected to the first terminal of the twentieth transistor.

[0074] The gate of the 21st transistor is electrically connected to the output terminal of the Nth stage drive signal, and the second terminal of the 21st transistor is electrically connected to the sixth node;

[0075] The gate of the 22nd transistor is electrically connected to the output terminal of the Nth stage drive signal, the first terminal of the 22nd transistor is electrically connected to the sixth node, and the second terminal of the 22nd transistor is electrically connected to the first terminal of the 23rd transistor.

[0076] The gate of the 23rd transistor is electrically connected to the second clock signal terminal, and the second terminal of the 23rd transistor is electrically connected to the second voltage terminal;

[0077] The twentieth and twentieth transistors are p-type transistors, and the twentieth and twentieth transistors are n-type transistors.

[0078] Optionally, the third inverter includes a twenty-fourth transistor and a twenty-fifth transistor; the second initialization circuit includes a twenty-sixth transistor;

[0079] The gate of the 24th transistor is electrically connected to the sixth node, the first terminal of the 24th transistor is electrically connected to the first voltage terminal, and the second terminal of the 24th transistor is electrically connected to the first terminal of the 25th transistor.

[0080] The gate of the 25th transistor is electrically connected to the sixth node, and the second terminal of the 25th transistor is electrically connected to the second voltage terminal;

[0081] The twenty-fourth transistor is a p-type transistor, and the twenty-fifth transistor is an n-type transistor;

[0082] The gate of the 26th transistor is electrically connected to the initial control terminal, the first terminal of the 26th transistor is electrically connected to the first voltage terminal, and the second terminal of the 26th transistor is electrically connected to the Nth stage drive signal output terminal.

[0083] In a second aspect, embodiments of this disclosure provide a driving method applied to the aforementioned driving circuit, the driving method comprising:

[0084] The drive signal generation circuit performs a shift operation on the (N-1)th stage drive signal to obtain and output the Nth stage drive signal through the Nth stage drive signal output terminal.

[0085] Under the control of the gating control signal, the gating circuit controls the writing of the gating input signal provided by the gating input terminal into the first node;

[0086] The output control circuit performs a AND-NOT operation on the Nth stage drive signal and the potential of the second terminal of the output control circuit to obtain the first output signal;

[0087] The output circuit is used to invert the first output signal to obtain an output drive signal that is provided through the output drive terminal.

[0088] In a third aspect, embodiments of this disclosure provide a driving module including multiple levels of the driving circuits described above;

[0089] The Nth stage drive circuit is electrically connected to the drive signal output terminals of the (N-1)th stage drive circuit; N is a positive integer.

[0090] In a third aspect, an embodiment of the present disclosure provides a display device including the aforementioned driving module. Attached Figure Description

[0091] Figure 1 This is a structural diagram of the driving circuit described in the embodiments of this disclosure;

[0092] Figure 2 It is the circuit diagram of the relevant pixel circuit;

[0093] Figure 3 yes Figure 2 The timing diagram of the relevant pixel circuit is shown below;

[0094] Figure 4 It is the circuit diagram of the relevant pixel circuit;

[0095] Figure 5 This is a circuit diagram of at least one embodiment of the gating circuit in the driving circuit described in the embodiments of this disclosure;

[0096] Figure 6 This is a circuit diagram of at least one embodiment of the gating circuit in the driving circuit described in the embodiments of this disclosure;

[0097] Figure 7 This is a circuit diagram of at least one embodiment of the gating circuit in the driving circuit described in the embodiments of this disclosure;

[0098] Figure 8 This is a circuit diagram of at least one embodiment of the gating circuit in the driving circuit described in the embodiments of this disclosure;

[0099] Figure 9 This is a circuit diagram of at least one embodiment of the gating circuit in the driving circuit described in the embodiments of this disclosure;

[0100] Figure 10 This is a circuit diagram of at least one embodiment of the gating circuit in the driving circuit described in the embodiments of this disclosure;

[0101] Figure 11 This is a circuit diagram of at least one embodiment of the gating circuit in the driving circuit described in the embodiments of this disclosure;

[0102] Figure 12 This is a circuit diagram of at least one embodiment of the gating circuit in the driving circuit described in the embodiments of this disclosure;

[0103] Figure 13 This is a circuit diagram of at least one embodiment of an inverter;

[0104] Figure 14 This is a circuit diagram of at least one embodiment of an inverter;

[0105] Figure 15 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0106] Figure 16 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0107] Figure 17 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0108] Figure 18 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0109] Figure 19 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0110] Figure 20 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0111] Figure 21 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0112] Figure 22 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0113] Figure 23 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0114] Figure 24 yes Figure 23 The timing diagram of at least one embodiment of the driving circuit shown;

[0115] Figure 25 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0116] Figure 26 This is a structural diagram of the drive module described in at least one embodiment of the present disclosure;

[0117] Figure 27 yes Figure 26 The timing diagram shows the operation of at least one embodiment of the driving module. Detailed Implementation

[0118] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0119] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0120] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0121] like Figure 1 As shown, the driving circuit described in this embodiment includes a driving signal generation circuit 10, a gating circuit 11, an output control circuit 12, and an output circuit 13.

[0122] The drive signal generation circuit 10 is electrically connected to the N-1th drive signal output terminal NS(N-1) and the Nth drive signal output terminal NS(N) respectively, and is used to perform a shift operation on the N-1th drive signal provided by the N-1th drive signal output terminal NS(N-1) to obtain and output the Nth drive signal through the Nth drive signal output terminal NS(N).

[0123] The gating circuit 11 is electrically connected to the first node N1, the gating input terminal VCT, and the gating control terminal CX, respectively, and is used to control the gating input signal provided by the gating input terminal VCT to be written into the first node N1 under the control of the gating control signal provided by the gating control terminal CX.

[0124] The first terminal of the output control circuit 12 is electrically connected to the Nth stage drive signal output terminal NS(N), and the second terminal of the output control circuit 12 is electrically connected to the first node N1. It is used to perform a AND-NOT operation on the potential of the Nth stage drive signal and the second terminal of the output control circuit to obtain the first output signal.

[0125] The output circuit 13 is electrically connected to the output control circuit 12 and the output drive terminal NO(N) respectively, and is used to invert the first output signal to obtain an output drive signal provided through the output drive terminal NO(N);

[0126] N is a positive integer.

[0127] This disclosure Figure 1In the embodiment of the driving circuit shown, during operation, the driving signal generation circuit 10 shifts the N-1 level driving signal provided by the N-1 level driving signal output terminal NS(N-1) to obtain the N-th level driving signal output through the N-th level driving signal output terminal NS(N). Under the control of the gating control signal, the gating circuit 11 writes the gating input signal into the first node N1. The output control circuit 12 performs a AND-NOT operation on the potential of the N-th level driving signal and the second terminal of the output control circuit 12 to obtain the first output signal. The output circuit 13 inverts the first output signal to obtain the output driving signal provided through the output driving terminal NO(N).

[0128] This disclosure Figure 1 The embodiment of the driving circuit shown can be the Nth stage driving circuit.

[0129] This disclosure Figure 1 The illustrated driving circuit embodiment, when in operation, within one frame time,

[0130] Before the Nth stage of driving signal provision, the gating circuit 11, under the control of the gating control signal, writes the gating input signal provided by the gating input terminal VCT into the first node N1;

[0131] When the strobe input signal is a high voltage signal, during the Nth level drive signal provision stage, the Nth level drive signal output terminal NS(N) outputs a high voltage signal. Then, the first output signal output by the output control circuit 12 is a low voltage signal. The output circuit 13 provides a high voltage signal through the output drive terminal NO(N), which can control the corresponding row pixel circuit to update the pixel voltage.

[0132] When the strobe input signal is a low voltage signal, during the Nth level drive signal provision stage, the Nth level drive signal output terminal NS(N) outputs a high voltage signal. Then, the first output signal output by the output control circuit 12 is a high voltage signal. The output circuit 13 provides a low voltage signal through the output drive terminal NO(N), which can control the corresponding row pixel circuit not to update the pixel voltage.

[0133] This disclosure embodiment can update a portion of the display screen by controlling the gating input signal provided by the gating input terminal VCT, thereby reducing power consumption, or achieve ultra-low power consumption of OLED display products such as wearable products, mobile terminals, and notebook computers by updating the display screen partially.

[0134] like Figure 2As shown, the related pixel circuit may include a first display control transistor M1, a second display control transistor M2, a driving transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, a storage capacitor Cst, and an organic light-emitting diode O1.

[0135] The gate of M1 is electrically connected to the first reset terminal NR(N), the source of M1 is electrically connected to the initial voltage terminal I1, and the drain of M1 is electrically connected to the gate of M3.

[0136] The gate of M2 is electrically connected to the first scan terminal NG(N), the source of M2 is electrically connected to the gate of M3, and the drain of M2 is electrically connected to the drain of M3.

[0137] The gate of M4 is electrically connected to the second scan terminal PG(N), the source of M4 is electrically connected to the data line D1, and the drain of M4 is electrically connected to the source of M3.

[0138] The gate of M5 is electrically connected to the light-emitting control terminal E(N), the source of M5 is electrically connected to the power supply voltage terminal ELVDD, and the drain of M5 is electrically connected to the source of M3.

[0139] The gate of M6 is electrically connected to the light-emitting control terminal E(N), the source of M6 is electrically connected to the drain of M3, the drain of M6 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low-level terminal ELVSS.

[0140] The gate of M7 is electrically connected to the second scan terminal PG(N), the source of M7 is electrically connected to the initial voltage terminal I1, and the drain of M7 is electrically connected to the anode of O1.

[0141] In specific implementation, the first reset terminal NR(N) can be the first scan terminal NG(N) of the N-1th stage, but is not limited thereto.

[0142] exist Figure 2 In the related pixel circuit shown, M1 and M2 are n-type transistors, M3, M4, M5, M6 and M7 are all p-type transistors, M1 and M2 are IGZO TFTs with low leakage current, and M3, M4, M5, M6 and M7 are all LTPS TFTs.

[0143] exist Figure 2 In the related pixel circuit shown, M1 and M2 are IGZO TFTs. When using low-frequency displays, IGZO TFTs can ensure that Cst can maintain the gate voltage of M3 for a longer period of time.

[0144] exist Figure 2In the related pixel circuit shown, the second scan terminal PG(N) is responsible for resetting the voltage of the anode of O1 and writing the data voltage on the data line to the source of the driving transistor. The first scan terminal NG(N) is responsible for resetting Cst, extracting Vth (Vth is the threshold voltage of the driving transistor), and writing the data voltage to the gate of the driving transistor.

[0145] In specific implementation, the first scan signal provided by the first scanning terminal NG(N) and the second scan signal provided by the second scanning terminal PG(N) can be inversely related, but are not limited thereto.

[0146] The driving circuit described in at least one embodiment of this disclosure can provide a first scanning signal to the first scanning terminal NG(N) through the output driving terminal NO(N), but is not limited thereto.

[0147] like Figure 3 As shown, Figure 2 When the related pixel circuit shown is working, the display cycle may include a first display control stage t1, a second display control stage t2, and a third display control stage t3 set sequentially.

[0148] In the first display control phase t1, E(N) outputs a high voltage signal, NR(N) provides a high voltage signal, PG(N) provides a high voltage signal, NG(N) provides a low voltage signal, M5 and M6 are turned off, M1 is turned on, and the potential of the gate of M3 is pulled low to the initial voltage Vinit; the initial voltage terminal I1 is used to provide the initial voltage Vinit.

[0149] In the second display control phase t2, E(N) outputs a high voltage signal, NR(N) provides a low voltage signal, PG(N) provides a low voltage signal, and NG(N) provides a high voltage signal. M5 and M6 are turned off, M1 is turned off, M2 is turned on, and M4 is turned on. M2 and M3 form a diode structure, charging Cst through the data voltage Vdata provided by data line D1 until M3 is turned off. At this time, the gate voltage of M3 is Vdata + Vth, where Vth is the threshold voltage of M3. M7 is turned on to reset the anode voltage of O1.

[0150] In the third display control stage t3, E(N) outputs a low voltage signal, NR(N) provides a low voltage signal, PG(N) provides a high voltage signal, NG(N) provides a low voltage signal, M5 and M6 are turned on, and M3 drives O1 to emit light; O1 emits light according to the voltage setting of Vdata.

[0151] As can be seen from the above-mentioned pixel circuit operation process, NG(N) can control whether the data voltage Vdata (which can be the pixel voltage) is written into the gate of M3 during the second display control stage.

[0152] Figure 4 This is the circuit diagram of the relevant pixel circuit.

[0153] like Figure 4 As shown, the related pixel circuit may include a first display control transistor M1, a second display control transistor M2, a driving transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, a storage capacitor Cst, and an organic light-emitting diode O1.

[0154] The gate of M1 is electrically connected to the third reset terminal RST1, the source of M1 is electrically connected to the initial voltage terminal I1, and the drain of M1 is electrically connected to the drain of M3.

[0155] The gate of M2 is electrically connected to the first scan terminal NG(N), the source of M2 is electrically connected to the gate of M3, and the drain of M2 is electrically connected to the drain of M3.

[0156] The gate of M4 is electrically connected to the second scan terminal PG(N), the source of M4 is electrically connected to the data line D1, and the drain of M4 is electrically connected to the source of M3.

[0157] The gate of M5 is electrically connected to the light-emitting control terminal E(N), the source of M5 is electrically connected to the power supply voltage terminal ELVDD, and the drain of M5 is electrically connected to the source of M3.

[0158] The gate of M6 is electrically connected to the light-emitting control terminal E(N), the source of M6 is electrically connected to the drain of M3, the drain of M6 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low-level terminal ELVSS.

[0159] The gate of M7 is electrically connected to the fourth reset terminal RST2, the source of M7 is electrically connected to the initial voltage terminal I1, and the drain of M7 is electrically connected to the anode of O1.

[0160] Figure 4 When the related pixel circuit shown is working, NG(N) can control whether the data voltage Vdata on the data line D1 is written to the gate of the driving transistor M3.

[0161] In practical implementation, the first scan signal provided by NG(N) can be used to control the opening or closing of the second transistor, thereby controlling whether the data voltage on the data line is written to the gate of the driving transistor, and thus controlling whether the brightness of the current row of pixel circuits is updated. When NG(N) outputs a high voltage signal, the second transistor is turned on, allowing the brightness of the current row of pixel circuits to be updated. When NG(N) outputs a low voltage signal, the second transistor is always turned off, and changes in the data voltage on the data line are not written to the gate of the driving transistor, so the brightness of the organic light-emitting diode does not change, meaning the display brightness of the current row of pixel circuits remains unchanged in the current frame. In summary, pixel brightness can be refreshed by controlling the opening or closing of the N-type transistor. Therefore, to prevent some pixels from being refreshed, simply ensure that the N-type transistor is turned off.

[0162] In at least one embodiment of this disclosure, the gating circuit is used to control the writing of the gating input signal provided by the gating input terminal into the first node when the potential of the N-1th stage driving signal is a first voltage and the potential of the Nth stage driving signal is a second voltage.

[0163] In a specific implementation, the gating circuit can write the gating input signal into the first node when the potential of the (N-1)th stage driving signal is the first voltage and the potential of the Nth stage driving signal is the second voltage.

[0164] Optionally, the first voltage can be a high voltage and the second voltage can be a low voltage, but this is not a limitation. In at least one embodiment of this disclosure, the first voltage can also be a low voltage and the second voltage can be a high voltage.

[0165] Optionally, the gating circuit includes a first transistor; the gate of the first transistor is electrically connected to the gating control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the gating input terminal.

[0166] like Figure 5 As shown, the gating circuit may include a first transistor T1;

[0167] The gate of the first transistor T1 is electrically connected to the gating control terminal S0, the drain of the first transistor T1 is electrically connected to the first node N1, and the source of the first transistor T1 is electrically connected to the gating input terminal VCT.

[0168] T1 is a p-type transistor.

[0169] like Figure 6 As shown, the gating circuit may include a first transistor T1;

[0170] The gate of the first transistor T1 is electrically connected to the gating control terminal S0, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the gating input terminal VCT.

[0171] T1 is an n-type transistor.

[0172] In at least one embodiment of this disclosure, the gating control terminal includes a first gating control terminal and a second gating control terminal; the gating circuit includes a first transistor and a second transistor;

[0173] The gate of the first transistor is electrically connected to the first gating control terminal, the first terminal of the first transistor is electrically connected to the first node, and the second terminal of the first transistor is electrically connected to the first terminal of the second transistor.

[0174] The gate of the second transistor is electrically connected to the second gating control terminal, and the second terminal of the second transistor is electrically connected to the gating input terminal;

[0175] The first gating control terminal is the output terminal of the (N-1)th stage drive signal, the second gating control terminal is the output terminal of the Nth stage drive signal, the first transistor is an n-type transistor, and the second transistor is a p-type transistor; or...

[0176] The first gating control terminal is the output terminal of the Nth stage drive signal, the second gating control terminal is the output terminal of the (N-1)th stage drive signal, the first transistor is a p-type transistor, and the second transistor is an n-type transistor; or...

[0177] The first gating control terminal is connected to the inverted signal of the (N-1)th stage drive signal, and the second gating control terminal is the output terminal of the Nth stage drive signal. Both the first transistor and the second transistor are p-type transistors; or...

[0178] The first gating control terminal is the output terminal of the Nth stage drive signal, and the second gating control terminal is connected to the inverted signal of the (N-1)th stage drive signal; both the first transistor and the second transistor are p-type transistors; or,

[0179] The first gating control terminal is the (N-1)th stage drive signal terminal, and the second gating control terminal is connected to the inverted signal of the Nth stage drive signal. Both the first transistor and the second transistor are n-type transistors; or,

[0180] The first gating control terminal is connected to the inverted signal of the Nth stage drive signal, and the second gating control terminal is the N-1th stage drive signal terminal. Both the first transistor and the second transistor are n-type transistors.

[0181] like Figure 7As shown, the gating circuit may include a first transistor T1 and a second transistor T2;

[0182] The gate of the first transistor T1 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the drain of the second transistor T2.

[0183] The gate of the second transistor T2 is electrically connected to the Nth stage drive signal output terminal NS(N), and the source of the second transistor T2 is electrically connected to the gating input terminal VCT.

[0184] T1 is an n-type transistor, and T2 is a p-type transistor.

[0185] like Figure 8 As shown, the gating circuit may include a first transistor T1 and a second transistor T2;

[0186] The gate of the first transistor T1 is electrically connected to the Nth stage drive signal output terminal NS(N), the drain of the first transistor T1 is electrically connected to the first node N1, and the source of the first transistor T1 is electrically connected to the source of the second transistor T2.

[0187] The gate of the second transistor T2 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), and the drain of the second transistor T2 is electrically connected to the gating input terminal VCT.

[0188] T1 is a p-type transistor, and T2 is an n-type transistor.

[0189] like Figure 9 As shown, the gating circuit may include a first transistor T1 and a second transistor T2;

[0190] The gate of the first transistor T1 is electrically connected to the first inverting drive signal terminal NGI1, the drain of the first transistor T1 is electrically connected to the first node N1, and the source of the first transistor T1 is electrically connected to the drain of the second transistor T2; the first inverting drive signal provided by the first inverting drive signal terminal NGI1 is inverted with the N-1th stage drive signal provided by the N-1th stage drive signal output terminal NS(N-1);

[0191] The gate of the second transistor T2 is electrically connected to the Nth stage drive signal output terminal NS(N), and the source of the second transistor T2 is electrically connected to the gating input terminal VCT.

[0192] T1 is a p-type transistor, and T2 is a p-type transistor.

[0193] like Figure 10As shown, the gating circuit may include a first transistor T1 and a second transistor T2;

[0194] The gate of the first transistor T1 is electrically connected to the Nth stage drive signal output terminal NS(N), the drain of the first transistor T1 is electrically connected to the first node N1, and the source of the first transistor T1 is electrically connected to the drain of the second transistor T2.

[0195] The gate of the second transistor T2 is electrically connected to the first inverting drive signal terminal NGI1, and the source of the second transistor T2 is electrically connected to the gating input terminal VCT; the first inverting drive signal provided by the first inverting drive signal terminal NGI1 is inverted with the N-1th stage drive signal provided by the N-1th stage drive signal output terminal NS(N-1);

[0196] T1 is a p-type transistor, and T2 is a p-type transistor.

[0197] like Figure 11 As shown, the gating circuit may include a first transistor T1 and a second transistor T2;

[0198] The gate of the first transistor T1 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the source of the second transistor T2.

[0199] The gate of the second transistor T2 is electrically connected to the second inverting drive signal terminal NGI2, and the drain of the second transistor T2 is electrically connected to the gating input terminal VCT; the second inverting drive signal provided by the second inverting drive signal terminal NGI2 is inverted with the Nth stage drive signal provided by the Nth stage drive signal output terminal NS(N);

[0200] T1 is an n-type transistor, and T2 is an n-type transistor.

[0201] like Figure 12 As shown, the gating circuit may include a first transistor T1 and a second transistor T2;

[0202] The gate of the first transistor T1 is electrically connected to the second inverting drive signal terminal NGI2, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the source of the second transistor T2; the second inverting drive signal provided by the second inverting drive signal terminal NGI2 is inverted with the Nth stage drive signal provided by the Nth stage drive signal output terminal NS(N);

[0203] The gate of the second transistor T2 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), and the drain of the second transistor T2 is electrically connected to the gating input terminal VCT.

[0204] T1 is an n-type transistor, and T2 is an n-type transistor.

[0205] like Figure 13 As shown, the N-1th stage drive signal provided by the N-1th stage drive signal output terminal NS(N-1) can be inverted by the first inverting circuit to obtain the first inverted drive signal provided by the first inverted drive signal terminal NGI1.

[0206] The first inverting circuit includes a first inverting control transistor T01 and a second inverting control transistor T02;

[0207] T01 is a p-type transistor, and T02 is an n-type transistor.

[0208] like Figure 14 As shown, the Nth stage drive signal provided by the Nth stage drive signal output terminal NS(N) can be inverted by the second inverting circuit to obtain the second inverted drive signal provided by the second inverted drive signal terminal NGI2;

[0209] The second inverting circuit includes a third inverting control transistor T03 and a fourth inverting control transistor T04;

[0210] T03 is a p-type transistor, and T04 is an n-type transistor.

[0211] The driving circuit described in at least one embodiment of this disclosure further includes a first initialization circuit;

[0212] The first initialization circuit is electrically connected to the initial control terminal, the first voltage terminal, and the first node, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.

[0213] In a specific implementation, the driving circuit may further include a first initialization circuit, which controls the connection between the first node and the first voltage terminal under the control of the initial control signal.

[0214] Optionally, the first voltage terminal can be a high voltage terminal.

[0215] The driving circuit described in at least one embodiment of this disclosure further includes a first voltage sustaining circuit;

[0216] The first terminal of the first voltage sustaining circuit is electrically connected to the first node, and the second terminal of the first voltage sustaining circuit is electrically connected to the second DC voltage terminal. The first voltage sustaining circuit is used to maintain the potential of the first node.

[0217] In a specific implementation, the driving circuit may further include a first voltage sustaining circuit, which sustains the potential of the first node.

[0218] like Figure 15 As shown, in Figure 1 Based on at least one embodiment of the driving circuit shown, the driving circuit described in at least one embodiment of this disclosure may further include a first initialization circuit 21;

[0219] The first initialization circuit 21 is electrically connected to the initial control terminal NCX, the first voltage terminal V1 and the first node N1 respectively, and is used to control the connection between the first node N1 and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.

[0220] Figure 15 In at least one embodiment of the driving circuit shown, when in operation, at the start of a frame time, NCX provides an effective voltage signal, and the first initialization circuit 21 controls the connection between the first node N1 and the first voltage terminal V1.

[0221] like Figure 16 As shown, in Figure 15 Based on at least one embodiment of the driving circuit shown, the driving circuit described in at least one embodiment of this disclosure may further include a first voltage sustaining circuit 22;

[0222] The first terminal of the first voltage sustaining circuit 22 is electrically connected to the first node N1, and the second terminal of the first voltage sustaining circuit 22 is electrically connected to the first voltage terminal V1. The first voltage sustaining circuit 22 is used to maintain the potential of the first node N1.

[0223] In at least one embodiment of this disclosure, the driving circuit further includes a second voltage sustaining circuit, and the first node is electrically connected to the second terminal of the output control circuit through the second voltage sustaining circuit;

[0224] The second voltage sustaining circuit includes a first inverter, a second inverter, and a sustaining control circuit;

[0225] The input terminal of the first inverter is electrically connected to the first node, the output terminal of the first inverter is electrically connected to the second node, the input terminal of the second inverter is electrically connected to the second node, and the output terminal of the second inverter is electrically connected to the third node and the second terminal of the output control circuit.

[0226] The first inverter is used to invert the potential of the first node and output the inverted potential of the first node through the output terminal of the first inverter. The second inverter is used to invert the potential of its input terminal and output the inverted potential through the output terminal of the second inverter.

[0227] The maintenance control circuit is electrically connected to the maintenance control terminal, the third node, and the first node, respectively, and is used to control the connection or disconnection between the third node and the first node under the control of the maintenance control signal provided by the maintenance control terminal.

[0228] In a specific implementation, the driving circuit may further include a second voltage sustaining circuit. The first node can be electrically connected to the second terminal of the output control circuit through the second voltage sustaining circuit. The second voltage sustaining circuit may include a first inverter, a second inverter, and a sustaining control circuit. The first inverter inverts the potential of the first node, and the second inverter inverts the potential of its input terminal. Under the control of the sustaining control signal provided by the sustaining control terminal, the sustaining control circuit controls the connection or disconnection between the third node and the first node.

[0229] The sustaining control circuit can disconnect the third node from the first node when the gating circuit controls the gating input signal to be written to the first node.

[0230] In at least one embodiment of the driving circuit described in this disclosure, when in operation, a second voltage sustaining circuit is added. The second voltage sustaining circuit includes a first inverter and a second inverter. When the potential of the first node is high, the second inverter controls the connection between the third node and the high voltage terminal, so that the potential of the third node is higher than that of the first node. When the potential of the first node is low, the third inverter controls the connection between the third node and the low voltage terminal, so that the potential of the third node is lower than that of the first node. This allows the third node to better control the transistor whose gate is electrically connected to the third node in the output control circuit.

[0231] like Figure 17 As shown, in Figure 15 Based on at least one embodiment of the driving circuit shown,

[0232] The driving circuit may further include a second voltage sustaining circuit; the sustaining control terminal includes the (N-1)th stage driving signal output terminal NS(N-1) and the first clock signal terminal GCK;

[0233] The first node N1 is electrically connected to the second terminal of the output control circuit 12 through the second voltage sustaining circuit;

[0234] The second voltage sustaining circuit includes a first inverter F1, a second inverter F2, and a sustaining control circuit W1;

[0235] The input terminal of the first inverter F1 is electrically connected to the first node N1, and the output terminal of the first inverter F1 is electrically connected to the second node N2.

[0236] The input terminal of the second inverter F2 is electrically connected to the second node N2, and the output terminal of the second inverter F2 is electrically connected to the third node N3 and the second terminal of the output control circuit 12.

[0237] The first inverter F1 is used to invert the potential of the first node N1, and outputs the inverted potential of the first node through the output terminal of the first inverter F1.

[0238] The second inverter F2 is used to invert the potential at its input terminal and output the inverted potential through the output terminal of the second inverter F2;

[0239] The sustaining control circuit W1 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the first clock signal terminal GCK, the third node N3, and the first node N1, respectively. It is used to control the connection or disconnection between the third node N3 and the first node N1 under the control of the N-1th stage drive signal provided by the N-1th stage drive signal output terminal NS(N-1), and to control the connection or disconnection between the third node N3 and the first node N1 under the control of the first clock signal provided by the first clock signal terminal GCK.

[0240] exist Figure 17 In at least one of the embodiments shown, the N-1th stage drive signal output terminal can be replaced with a second clock signal terminal, but is not limited thereto.

[0241] Optionally, the maintenance control terminal includes a first maintenance control terminal and a second maintenance control terminal;

[0242] The sustaining control circuit includes a third transistor and a fourth transistor;

[0243] The gate of the third transistor is electrically connected to the first sustaining control terminal, the first terminal of the third transistor is electrically connected to the first node, and the second terminal of the third transistor is electrically connected to the third node.

[0244] The gate of the fourth transistor is electrically connected to the second sustain control terminal, the first terminal of the fourth transistor is electrically connected to the third node, and the second terminal of the fourth transistor is electrically connected to the first node.

[0245] The third transistor is a p-type transistor, and the fourth transistor is an n-type transistor;

[0246] The first sustain control terminal is the (N-1)th stage drive signal terminal, and the second sustain control terminal is the first clock signal terminal; or,

[0247] The first sustain control terminal is the second clock signal terminal, and the second sustain control terminal is the first clock signal terminal.

[0248] Optionally, the first inverter includes a fifth transistor and a sixth transistor, and the second inverter includes a seventh transistor and an eighth transistor;

[0249] The gate of the fifth transistor is electrically connected to the first node, the first terminal of the fifth transistor is electrically connected to the first voltage terminal, and the second terminal of the fifth transistor is electrically connected to the second node.

[0250] The gate of the sixth transistor is electrically connected to the first node, the first terminal of the sixth transistor is electrically connected to the second node, and the second terminal of the sixth transistor is electrically connected to the second voltage terminal.

[0251] The fifth transistor is a p-type transistor, and the sixth transistor is an n-type transistor;

[0252] The gate of the seventh transistor is electrically connected to the second node, the first terminal of the seventh transistor is electrically connected to the first voltage terminal, and the second terminal of the seventh transistor is electrically connected to the third node;

[0253] The gate of the eighth transistor is electrically connected to the second node, the first terminal of the eighth transistor is electrically connected to the third node, and the second terminal of the eighth transistor is electrically connected to the second voltage terminal.

[0254] The seventh transistor is a p-type transistor, and the eighth transistor is an n-type transistor.

[0255] Optionally, the first initialization circuit includes a ninth transistor, and the first voltage sustaining circuit includes a first capacitor;

[0256] The gate of the ninth transistor is electrically connected to the initial control terminal, the first terminal of the ninth transistor is electrically connected to the first voltage terminal, and the second terminal of the ninth transistor is electrically connected to the first node.

[0257] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the DC voltage terminal or the second node.

[0258] Optionally, the output control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

[0259] The gate of the tenth transistor is electrically connected to the output terminal of the Nth stage drive signal, the first terminal of the tenth transistor is electrically connected to the first voltage terminal, and the second terminal of the tenth transistor is electrically connected to the fourth node.

[0260] The gate of the eleventh transistor is electrically connected to the first node, the first terminal of the eleventh transistor is electrically connected to the first voltage terminal, and the second terminal of the eleventh transistor is electrically connected to the fourth node.

[0261] The gate of the twelfth transistor is electrically connected to the output terminal of the Nth stage drive signal, the first terminal of the twelfth transistor is electrically connected to the fourth node, and the second terminal of the twelfth transistor is electrically connected to the fifth node.

[0262] The gate of the thirteenth transistor is electrically connected to the first node, the first terminal of the thirteenth transistor is electrically connected to the fifth node, and the second terminal of the thirteenth transistor is electrically connected to the second voltage terminal.

[0263] The tenth and eleventh transistors are p-type transistors, and the twelfth and thirteenth transistors are n-type transistors.

[0264] Optionally, the output control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

[0265] The gate of the tenth transistor is electrically connected to the output terminal of the Nth stage drive signal, the first terminal of the tenth transistor is electrically connected to the first voltage terminal, and the second terminal of the tenth transistor is electrically connected to the fourth node.

[0266] The gate of the eleventh transistor is electrically connected to the third node, the first terminal of the eleventh transistor is electrically connected to the first voltage terminal, and the second terminal of the eleventh transistor is electrically connected to the fourth node.

[0267] The gate of the twelfth transistor is electrically connected to the output terminal of the Nth stage drive signal, the first terminal of the twelfth transistor is electrically connected to the fourth node, and the second terminal of the twelfth transistor is electrically connected to the fifth node.

[0268] The gate of the thirteenth transistor is electrically connected to the third node, the first terminal of the thirteenth transistor is electrically connected to the fifth node, and the second terminal of the thirteenth transistor is electrically connected to the second voltage terminal.

[0269] The tenth and eleventh transistors are p-type transistors, and the twelfth and thirteenth transistors are n-type transistors.

[0270] Optionally, the output circuit includes a fourteenth transistor and a fifteenth transistor;

[0271] The gate of the fourteenth transistor is electrically connected to the fourth node, the first terminal of the fourteenth transistor is electrically connected to the first voltage terminal, and the second terminal of the fourteenth transistor is electrically connected to the output drive terminal.

[0272] The gate of the fifteenth transistor is electrically connected to the fourth node, the first terminal of the fifteenth transistor is electrically connected to the output drive terminal, and the second terminal of the fifteenth transistor is electrically connected to the second voltage terminal.

[0273] In at least one embodiment of this disclosure, the drive signal generation circuit may include a first control circuit, a second control circuit, a third inverter, and a second initialization circuit;

[0274] The first control circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the N-1th stage drive signal output terminal and the sixth node, respectively. Under the control of the first clock signal provided by the first clock signal terminal and the second clock signal provided by the second clock signal terminal, the N-1th stage drive signal output terminal is shifted and inverted to obtain the inverted signal output through the sixth node.

[0275] The second control circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the Nth stage drive signal output terminal, and the sixth node, respectively. It is used to invert the Nth stage drive signal provided by the Nth stage drive signal output terminal under the control of the first clock signal and the second clock signal, so as to obtain the inverted signal and output it through the sixth node.

[0276] The third inverter is electrically connected to the sixth node and the Nth stage drive signal output terminal, respectively, and is used to invert the potential of the sixth node and output the inverted signal through the Nth stage drive signal output terminal;

[0277] The second initialization circuit is electrically connected to the initial control terminal, the first voltage terminal, and the Nth stage drive signal output terminal, respectively, and is used to control the connection between the Nth stage drive signal output terminal and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.

[0278] In a specific implementation, the drive signal generation circuit may include a first control circuit, a second control circuit, a third inverter, and a second initialization circuit. Under the control of a first clock signal and a second clock signal, the first control circuit shifts and inverts the (N-1)th drive signal, and outputs the inverted signal through the sixth node. Under the control of the first clock signal and the second clock signal, the second control circuit inverts the Nth stage drive signal, and outputs the inverted signal through the sixth node. The third inverter inverts the potential of the sixth node, and outputs the inverted signal through the Nth stage drive signal output terminal. Under the control of the initial control signal, the second initialization circuit controls the connection between the Nth stage drive signal output terminal and the first voltage terminal.

[0279] like Figure 18 As shown, in Figure 16 Based on at least one embodiment of the driving circuit shown, the driving signal generation circuit may include a first control circuit 31, a second control circuit 32, a third inverter F3, and a second initialization circuit 30.

[0280] The first control circuit 31 is electrically connected to the first clock signal terminal GCK, the second clock signal terminal GCB, the N-1th stage drive signal output terminal NS(N-1), and the sixth node N6, respectively. Under the control of the first clock signal provided by the first clock signal terminal GCK and the second clock signal provided by the second clock signal terminal GCB, it shifts and inverts the N-1th stage drive signal provided by the N-1th stage drive signal output terminal NS(N-1) to obtain the inverted signal output through the sixth node N6.

[0281] The second control circuit 32 is electrically connected to the first clock signal terminal GCK, the second clock signal terminal GCB, the Nth stage drive signal output terminal NS(N), and the sixth node N6, respectively. It is used to invert the Nth stage drive signal provided by the Nth stage drive signal output terminal NS(N) under the control of the first clock signal and the second clock signal, so as to obtain the inverted signal and output it through the sixth node N6.

[0282] The third inverter F3 is electrically connected to the sixth node N6 and the Nth stage drive signal output terminal NS(N) respectively, and is used to invert the potential of the sixth node N6 and output the inverted signal through the Nth stage drive signal output terminal NS(N);

[0283] The second initialization circuit 30 is electrically connected to the initial control terminal NCX, the first voltage terminal V1 and the Nth stage drive signal output terminal NS(N), respectively, and is used to control the connection between the Nth stage drive signal output terminal NS(N) and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.

[0284] like Figure 19 As shown, in Figure 17 Based on at least one embodiment of the driving circuit shown, the driving signal generation circuit may include a first control circuit 31, a second control circuit 32, a third inverter F3, and a second initialization circuit 30.

[0285] The first control circuit 31 is electrically connected to the first clock signal terminal GCK, the second clock signal terminal GCB, the N-1th stage drive signal output terminal NS(N-1), and the sixth node N6, respectively. Under the control of the first clock signal provided by the first clock signal terminal GCK and the second clock signal provided by the second clock signal terminal GCB, it shifts and inverts the N-1th stage drive signal provided by the N-1th stage drive signal output terminal NS(N-1) to obtain the inverted signal output through the sixth node N6.

[0286] The second control circuit 32 is electrically connected to the first clock signal terminal GCK, the second clock signal terminal GCB, the Nth stage drive signal output terminal NS(N), and the sixth node N6, respectively. It is used to invert the Nth stage drive signal provided by the Nth stage drive signal output terminal NS(N) under the control of the first clock signal and the second clock signal, so as to obtain the inverted signal and output it through the sixth node N6.

[0287] The third inverter F3 is electrically connected to the sixth node N6 and the Nth stage drive signal output terminal NS(N) respectively, and is used to invert the potential of the sixth node N6 and output the inverted signal through the Nth stage drive signal output terminal NS(N);

[0288] The second initialization circuit 30 is electrically connected to the initial control terminal NCX, the first voltage terminal V1 and the Nth stage drive signal output terminal NS(N), respectively, and is used to control the connection between the Nth stage drive signal output terminal NS(N) and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.

[0289] Optionally, the first control circuit includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor;

[0290] The gate of the sixteenth transistor is electrically connected to the second clock signal terminal, the first terminal of the sixteenth transistor is electrically connected to the first voltage terminal, and the second terminal of the sixteenth transistor is electrically connected to the first terminal of the seventeenth transistor.

[0291] The gate of the seventeenth transistor is electrically connected to the output terminal of the (N-1)th stage drive signal, and the second terminal of the seventeenth transistor is electrically connected to the sixth node;

[0292] The gate of the eighteenth transistor is electrically connected to the output terminal of the (N-1)th stage drive signal, the first terminal of the eighteenth transistor is electrically connected to the sixth node, and the second terminal of the eighteenth transistor is electrically connected to the first terminal of the nineteenth transistor.

[0293] The gate of the nineteenth transistor is electrically connected to the first clock signal terminal, and the second terminal of the nineteenth transistor is electrically connected to the second voltage terminal.

[0294] The sixteenth and seventeenth transistors are p-type transistors, and the eighteenth and nineteenth transistors are n-type transistors.

[0295] Optionally, the second control circuit includes a twentieth transistor, a twenty-first transistor, a twenty-second transistor, and a twenty-third transistor;

[0296] The gate of the twentieth transistor is electrically connected to the first clock signal terminal, the first terminal of the twentieth transistor is electrically connected to the first voltage terminal, and the second terminal of the twentieth transistor is electrically connected to the first terminal of the twentieth transistor.

[0297] The gate of the 21st transistor is electrically connected to the output terminal of the Nth stage drive signal, and the second terminal of the 21st transistor is electrically connected to the sixth node;

[0298] The gate of the 22nd transistor is electrically connected to the output terminal of the Nth stage drive signal, the first terminal of the 22nd transistor is electrically connected to the sixth node, and the second terminal of the 22nd transistor is electrically connected to the first terminal of the 23rd transistor.

[0299] The gate of the 23rd transistor is electrically connected to the second clock signal terminal, and the second terminal of the 23rd transistor is electrically connected to the second voltage terminal;

[0300] The twentieth and twentieth transistors are p-type transistors, and the twentieth and twentieth transistors are n-type transistors.

[0301] Optionally, the third inverter includes a twenty-fourth transistor and a twenty-fifth transistor; the second initialization circuit includes a twenty-sixth transistor;

[0302] The gate of the 24th transistor is electrically connected to the sixth node, the first terminal of the 24th transistor is electrically connected to the first voltage terminal, and the second terminal of the 24th transistor is electrically connected to the first terminal of the 25th transistor.

[0303] The gate of the 25th transistor is electrically connected to the sixth node, and the second terminal of the 25th transistor is electrically connected to the second voltage terminal;

[0304] The twenty-fourth transistor is a p-type transistor, and the twenty-fifth transistor is an n-type transistor;

[0305] The gate of the 26th transistor is electrically connected to the initial control terminal, the first terminal of the 26th transistor is electrically connected to the first voltage terminal, and the second terminal of the 26th transistor is electrically connected to the Nth stage drive signal output terminal.

[0306] Optionally, the first voltage terminal can be a high voltage terminal and the second voltage terminal can be a low voltage terminal, but this is not a limitation.

[0307] Figure 20 At least one embodiment of the driving circuit shown is Figure 18 The difference in at least one embodiment of the driving circuit shown is that: Figure 20 At least one embodiment of the driving circuit shown does not include a first voltage sustaining circuit.

[0308] Figure 21 At least one embodiment of the driving circuit shown is Figure 19 The difference in at least one embodiment of the driving circuit shown is that: Figure 21 At least one embodiment of the driving circuit shown further includes a first voltage sustaining circuit 22;

[0309] The first terminal of the first voltage sustaining circuit 22 is electrically connected to the first node N1, and the second terminal of the first voltage sustaining circuit 22 is electrically connected to the first voltage terminal V1. The first voltage sustaining circuit 22 is used to maintain the potential of the first node N1.

[0310] like Figure 22 As shown, in Figure 20 Based on at least one embodiment of the driving circuit shown,

[0311] The gating circuit may include a first transistor T1 and a second transistor T2;

[0312] The gate of the first transistor T1 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the drain of the second transistor T2.

[0313] The gate of the second transistor T2 is electrically connected to the Nth stage drive signal output terminal NS(N), and the source of the second transistor T2 is electrically connected to the gating input terminal VCT.

[0314] T1 is an n-type transistor, and T2 is a p-type transistor;

[0315] The first initialization circuit includes a ninth transistor T9;

[0316] The gate of the ninth transistor T9 is electrically connected to the initial control terminal NCX, the source of the ninth transistor T9 is electrically connected to the high voltage terminal VGH, and the drain of the ninth transistor T9 is electrically connected to the first node N1.

[0317] The output control circuit includes a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13;

[0318] The gate of the tenth transistor T10 is electrically connected to the Nth stage drive signal output terminal NS(N), the source of the tenth transistor T10 is electrically connected to the high voltage terminal VGH, and the source of the tenth transistor T10 is electrically connected to the fourth node N4.

[0319] The gate of the eleventh transistor T11 is electrically connected to the first node N1, the source of the eleventh transistor T11 is electrically connected to the high voltage terminal VGH, and the drain of the eleventh transistor T11 is electrically connected to the fourth node N4.

[0320] The gate of the twelfth transistor T12 is electrically connected to the Nth stage drive signal output terminal NS(N), the source of the twelfth transistor T12 is electrically connected to the fourth node N4, and the drain of the twelfth transistor T12 is electrically connected to the fifth node N5.

[0321] The gate of the thirteenth transistor T13 is electrically connected to the first node N1, the source of the thirteenth transistor T13 is electrically connected to the fifth node N5, and the drain of the thirteenth transistor T13 is electrically connected to the low voltage terminal VGL.

[0322] The tenth transistor T10 and the eleventh transistor T11 are p-type transistors, and the twelfth transistor T12 and the thirteenth transistor T13 are n-type transistors;

[0323] The output circuit includes a fourteenth transistor T14 and a fifteenth transistor T15;

[0324] The gate of the fourteenth transistor T14 is electrically connected to the fourth node N4, the source of the fourteenth transistor T14 is electrically connected to the high voltage terminal VGH, and the drain of the fourteenth transistor T14 is electrically connected to the output drive terminal NO(N).

[0325] The gate of the fifteenth transistor T15 is electrically connected to the fourth node N4, the source of the fifteenth transistor T15 is electrically connected to the output drive terminal NO(N), and the drain of the fifteenth transistor T15 is electrically connected to the low voltage terminal VGL.

[0326] The first control circuit includes a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, and a nineteenth transistor T19;

[0327] The gate of the sixteenth transistor T16 is electrically connected to the second clock signal terminal GCB, the source of the sixteenth transistor T16 is electrically connected to the high voltage terminal VGH, and the drain of the sixteenth transistor T16 is electrically connected to the source of the seventeenth transistor T17.

[0328] The gate of the seventeenth transistor T17 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), and the drain of the seventeenth transistor T17 is electrically connected to the sixth node N6.

[0329] The gate of the eighteenth transistor T18 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the source of the eighteenth transistor T18 is electrically connected to the sixth node N6, and the drain of the eighteenth transistor T18 is electrically connected to the source of the nineteenth transistor T19.

[0330] The gate of the nineteenth transistor T19 is electrically connected to the first clock signal terminal GCK, and the source of the nineteenth transistor T19 is electrically connected to the low voltage terminal VGL.

[0331] The sixteenth transistor T16 and the seventeenth transistor T17 are p-type transistors, and the eighteenth transistor T18 and the nineteenth transistor T19 are n-type transistors;

[0332] The second control circuit includes the twentieth transistor T20, the twenty-first transistor T21, the twenty-second transistor T22, and the twenty-third transistor T23;

[0333] The gate of the twentieth transistor T20 is electrically connected to the first clock signal terminal GCK, the source of the twentieth transistor T20 is electrically connected to the high voltage terminal VGH, and the drain of the twentieth transistor T20 is electrically connected to the source of the twentieth transistor T21.

[0334] The gate of the 21st transistor T21 is electrically connected to the Nth stage drive signal output terminal NS(N), and the drain of the 21st transistor T21 is electrically connected to the sixth node N6.

[0335] The gate of the twelfth transistor T22 is electrically connected to the Nth stage drive signal output terminal NS(N), the source of the twelfth transistor T22 is electrically connected to the sixth node N6, and the source of the twelfth transistor T22 is electrically connected to the drain of the twelfth transistor T23.

[0336] The gate of the 23rd transistor T23 is electrically connected to the second clock signal terminal GCB, and the drain of the 23rd transistor T23 is electrically connected to the low voltage terminal VGL.

[0337] The twentieth transistor T20 and the twenty-first transistor T21 are p-type transistors, and the twenty-second transistor T22 and the twenty-third transistor T23 are n-type transistors;

[0338] The third inverter includes a twenty-fourth transistor T24 and a twenty-fifth transistor T25; the second initialization circuit includes a twenty-sixth transistor T26.

[0339] The gate of the 24th transistor T24 is electrically connected to the sixth node N6, the source of the 24th transistor T24 is electrically connected to the high voltage terminal VGH, and the drain of the 24th transistor T24 is electrically connected to the source of the 25th transistor T25.

[0340] The gate of the 25th transistor T25 is electrically connected to the sixth node N6, and the drain of the 25th transistor T25 is electrically connected to the low voltage terminal VGL.

[0341] The 24th transistor T24 is a p-type transistor, and the 25th transistor T25 is an n-type transistor;

[0342] The gate of the 26th transistor T26 is electrically connected to the initial control terminal NCX, the source of the 26th transistor T26 is electrically connected to the high voltage terminal VGH, and the second terminal of the 26th transistor is electrically connected to the Nth stage drive signal output terminal NS(N).

[0343] The 26th transistor, T26, is a p-type transistor.

[0344] In at least one embodiment of this disclosure, the structure of the drive signal generation circuit is not limited to that shown below. Figure 22 As shown, the drive signal generation circuit can be, for example, a 16T3C circuit, a 13T3C circuit, a 12T3C circuit, a 10T3C circuit, etc., but is not limited thereto.

[0345] This disclosure Figure 22 At least one embodiment of the driving circuit, when in operation,

[0346] 1. When GCK provides a high voltage signal, T19 is turned on and T20 is turned off. When GCB provides a low voltage signal, T16 is turned on and T23 is turned off. At this time, the drive signal generation circuit is in the transmission state.

[0347] When NS(N) provides a low voltage signal, T17 is turned on and T18 is turned off. The potential of N6 is high voltage. When T25 is turned on and T24 is turned off, NS(N) provides a low voltage signal and NS(N-1) provides a low voltage signal.

[0348] When NS(N) provides a high voltage signal, T17 is turned off and T18 is turned on, the potential of N6 is low voltage, T25 is turned off and T24 is turned on, and both NS(N) and NS(N-1) provide high voltage signals.

[0349] 2. When GCK provides a low voltage signal, T19 is turned off and T20 is turned on. When GCB provides a high voltage signal, T16 is turned off and T23 is turned on. At this time, the circuit is in a register state. T21, T22, T23 and T11 form a latch circuit. The potential of N6 and the signal provided by NS(N) remain unchanged from the previous state.

[0350] 3. When the signal provided by NS(N-1) switches from a low voltage signal to a high voltage signal, GCK provides a low voltage signal, turns off T19 and turns on T20, and GCB provides a high voltage signal, turns off T16 and turns on T23. At this time, the circuit is in the register state. T21, T22, T23 and T11 form a latch circuit. The potential of N6 remains unchanged from the previous low voltage state of the signal provided by NS(N), completing the shift. At the next moment, GCK provides a high voltage signal, turns on T19 and turns off T20, and GCB provides a low voltage signal, turns on T16 and turns off T23. At this time, the circuit is in the transmission state. NS(N-1) provides a high voltage signal, turns off T17 and turns on T18. The potential of N6 is low voltage, turns off T25 and turns on T24. Both NS(N) and NS(N-1) provide high voltage signals, realizing the shift register from NS(N-1) to NS(N).

[0351] 4. When NS(N-1) switches from providing a high voltage signal to providing a low voltage signal, GCK provides a low voltage signal, turns off T19 and turns on T20, and GCB provides a high voltage signal, turns off T16 and turns on T23. At this time, the circuit is in the register state. T21, T22, T23 and T11 form a latch circuit. The potential of N6 and the signal provided by NS(N) remain unchanged at the previous high voltage state, completing the shift. At the next moment, GCK provides a high voltage signal, turns on T19 and turns off T20, and GCB provides a low voltage signal, turns on T16 and turns off T23. At this time, the circuit is in the transmission state. NS(N-1) provides a low voltage signal, turns on T17 and turns off T18. The potential of N6 is high voltage, turns on T25 and turns off T24. Both NS(N) and NS(N-1) provide low voltage signals, realizing the shift register from NS(N-1) to NS(N).

[0352] This disclosure Figure 22 At least one embodiment of the driving circuit, when in operation,

[0353] When NS(N-1) provides a high voltage signal, T1 is turned on; when NS(N) provides a low voltage signal, T2 is turned on. By simultaneously selecting the two signals, the state of the gating input signal provided by VCT within a high-low frequency switching cycle H can be obtained and written to the first node N1. Then, T1 and T2 will not be turned on simultaneously at other times to prevent the potential of N1 from being affected by the potential change of the gating input signal provided by VCT. T10, T11, T12, and T13 form a NAND gate. The input signals of this NAND gate are the signal provided by NS(N) and the potential of N1, respectively. The output of this NAND gate is electrically connected to the fourth node N4. T24 and T25 form a third inverter. The input of the third inverter is electrically connected to N4, and the output of the third inverter is electrically connected to NO(N).

[0354] If VCT provides a high voltage signal when T1 and T2 are open, N1 will be written with a high voltage, and the gating state of the NAND gate can ensure that NS(N) is normally passed to NO(N);

[0355] If VCT provides a low voltage signal when T1 and T2 are open, N1 will be written with a low voltage, the NAND gate will be in the off state, ensuring that NO(N) provides a low voltage signal, thereby maintaining the low level of NO(N).

[0356] Optionally, at the start of display (i.e., when the display device is powered on), during the power-on phase before the first stage, NCX outputs a low voltage signal, T9 turns on to control the potential of N1 to be high voltage, and T26 turns on to enable NS(N) to provide a high voltage signal; at this time, both T12 and T13 are turned on, the potential of N4 is low voltage, T14 is turned on, T15 is turned off, and NO(N) outputs a high voltage signal, which can turn on all pixel circuits in the effective display area, including the second display control transistor M2, clear the residual charge in the storage capacitor Cst, and improve the poor screen flicker at startup;

[0357] Then, when NS(N-1) outputs a high voltage signal and NS(N) outputs a low voltage signal, T1 and T2 are turned on.

[0358] When VCT provides a low voltage signal, the potential of N1 is a low voltage signal, and C1 maintains the potential of N1; T11 is turned on, T10 is turned on, the potential of N4 is a high voltage, T15 is turned on, and NO(N) outputs a low voltage signal.

[0359] When VCT provides a high voltage signal, the potential of N1 is a high voltage signal, C1 maintains the potential of N1, T11 is turned off, T10 is turned on, the potential of N4 is high voltage, T15 is turned on, and NO(N) outputs a low voltage signal.

[0360] Subsequently, during the Nth stage of drive signal provision, NS(N) outputs a high-voltage signal.

[0361] When the potential of N1 is low, T10 is off and T11 is on; when the potential of N4 is high, T15 is on, and NO(N) outputs a low voltage signal.

[0362] When the potential of N1 is high, T10 is off, T11 is off, and T12 and T13 are on. When the potential of N4 is low, T14 is on, and NO(N) outputs a high voltage signal.

[0363] After the Nth stage drive signal is provided, NS(N) outputs a low voltage signal.

[0364] When the potential of N1 is a low voltage signal, T10 is turned on, T11 is turned on, the potential of N4 is a high voltage, and NO(N) outputs a low voltage signal.

[0365] When the potential of N1 is a high voltage signal, T10 is turned on and T11 is turned off, the potential of N4 is a high voltage, and NO(N) outputs a low voltage signal.

[0366] This disclosure Figure 22In at least one embodiment of the driving circuit shown, when NS(N-1) outputs a high voltage signal and NS(N) outputs a low voltage signal, T1 and T2 are turned on. By simultaneously selecting the two signals, the state of the selected input signal within a high-low frequency switching cycle can be obtained.

[0367] exist Figure 22 In the diagram, node N7 is the seventh node, and node N7 is electrically connected to the drain of T1.

[0368] like Figure 23 As shown in this disclosure Figure 22 Based on at least one embodiment of the driving circuit shown, the driving circuit of at least one embodiment of this disclosure further includes a second voltage sustaining circuit; the first node N1 is electrically connected to the gate of T11 through the second voltage sustaining circuit;

[0369] The second voltage sustaining circuit includes a first inverter, a second inverter, and a sustaining control circuit;

[0370] The sustaining control circuit includes a third transistor T3 and a fourth transistor T4;

[0371] The gate of the third transistor T3 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the source of the third transistor T3 is electrically connected to the first node N1, and the drain of the third transistor T3 is electrically connected to the third node N3.

[0372] The gate of the fourth transistor T4 is electrically connected to the first clock signal terminal GCK, the source of the fourth transistor T4 is electrically connected to the third node N3, and the drain of the fourth transistor T4 is electrically connected to the first node N1.

[0373] The first inverter includes a fifth transistor T5 and a sixth transistor T6, and the second inverter includes a seventh transistor T7 and an eighth transistor T8;

[0374] The gate of the fifth transistor T5 is electrically connected to the first node N1, the source of the fifth transistor T5 is electrically connected to the high voltage terminal VGH, and the drain of the fifth transistor T5 is electrically connected to the second node N2.

[0375] The gate of the sixth transistor T6 is electrically connected to the first node N1, the source of the sixth transistor T6 is electrically connected to the second node N2, and the drain of the sixth transistor T6 is electrically connected to the low voltage terminal VGL.

[0376] The gate of the seventh transistor T7 is electrically connected to the second node N2, the source of the seventh transistor T7 is electrically connected to the high voltage terminal VGH, and the drain of the seventh transistor T7 is electrically connected to the third node N3.

[0377] The gate of the eighth transistor T8 is electrically connected to the second node N2, the source of the eighth transistor T8 is electrically connected to the third node N3, and the drain of the eighth transistor T8 is electrically connected to the low voltage terminal VGL.

[0378] The third node N3 is electrically connected to the gate of T11 and the gate of T13, respectively.

[0379] exist Figure 23 In at least one embodiment of the driving circuit shown, the third transistor T3 is a p-type transistor, the fourth transistor T4 is an n-type transistor, the fifth transistor T5 is a p-type transistor, the sixth transistor T6 is an n-type transistor, the seventh transistor T7 is a p-type transistor, and the eighth transistor T8 is an n-type transistor.

[0380] This disclosure Figure 23 In at least one embodiment of the driving circuit shown, since the p-type transistor has a threshold voltage loss when transmitting low voltage and the n-type transistor has a threshold voltage loss when transmitting high voltage, the absolute value of the potential of N1 will be lower. The absolute value of the potential of N1 can be increased by controlling the first inverter and the second inverter, thereby better controlling the corresponding transistor in the output circuit to turn on or off. When the control circuit is turned on by T1 and T2, it controls the disconnection between N1 and N3 so as not to affect the writing of the potential of N1.

[0381] Figure 24 This is a public announcement Figure 23 The timing diagram shows the operation of at least one embodiment of the driving circuit.

[0382] Figure 25 At least one embodiment of the driving circuit shown is Figure 22 The difference in at least one embodiment of the driving circuit shown is that: Figure 25 At least one embodiment of the driving circuit shown further includes a first capacitor C1;

[0383] The first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the low voltage terminal VGL.

[0384] C1 is used to stabilize the potential of N1.

[0385] The driving method described in this embodiment is applied to the above-mentioned driving circuit, and the driving method includes:

[0386] The drive signal generation circuit performs a shift operation on the (N-1)th stage drive signal to obtain and output the Nth stage drive signal through the Nth stage drive signal output terminal.

[0387] Under the control of the gating control signal, the gating circuit controls the writing of the gating input signal provided by the gating input terminal into the first node;

[0388] The output control circuit performs a AND-NOT operation on the Nth stage drive signal and the potential of the second terminal of the output control circuit to obtain the first output signal;

[0389] The output circuit is used to invert the first output signal to obtain an output drive signal that is provided through the output drive terminal.

[0390] The driving module described in this embodiment includes multiple stages of the above-described driving circuits;

[0391] The Nth stage drive circuit is electrically connected to the drive signal output terminals of the (N-1)th stage drive circuit; N is a positive integer.

[0392] like Figure 26 As shown, S1 is the first-stage driving circuit, S2 is the second-stage driving circuit, S3 is the third-stage driving circuit, S4 is the fourth-stage driving circuit, S5 is the fifth-stage driving circuit, S6 is the sixth-stage driving circuit, S7 is the seventh-stage driving circuit, S8 is the eighth-stage driving circuit, S9 is the ninth-stage driving circuit, S10 is the tenth-stage driving circuit, S11 is the eleventh-stage driving circuit, and S12 is the twelfth-stage driving circuit.

[0393] The terminal labeled NS(1) is the drive signal output terminal of S1, and the terminal labeled NO(1) is the output drive terminal of S1.

[0394] The terminal labeled NS(2) is the drive signal output terminal of S2, and the terminal labeled NO(2) is the output drive terminal of S2; S2 is electrically connected to NS(1);

[0395] The terminal labeled NS(3) is the drive signal output terminal of S3, and the terminal labeled NO(3) is the output drive terminal of S3; S3 is electrically connected to NS(2);

[0396] The terminal labeled NS(4) is the drive signal output terminal of S4, and the terminal labeled NO(4) is the output drive terminal of S4; S4 is electrically connected to NS(3);

[0397] The terminal labeled NS(5) is the drive signal output terminal of S5, and the terminal labeled NO(5) is the output drive terminal of S5; S5 is electrically connected to NS(4);

[0398] The terminal labeled NS(6) is the drive signal output terminal of S6, and the terminal labeled NO(6) is the output drive terminal of S6; S6 is electrically connected to NS(5).

[0399] The terminal labeled NS(7) is the drive signal output terminal of S7, and the terminal labeled NO(7) is the output drive terminal of S7; S7 is electrically connected to NS(6);

[0400] The terminal labeled NS(8) is the drive signal output terminal of S8, and the terminal labeled NO(8) is the output drive terminal of S8; S8 is electrically connected to NS(7);

[0401] The terminal labeled NS(9) is the drive signal output terminal of S9, and the terminal labeled NO(9) is the output drive terminal of S9; S9 is electrically connected to NS(8);

[0402] The terminal labeled NS(10) is the drive signal output terminal of S10, and the terminal labeled NO(10) is the output drive terminal of S10; S10 is electrically connected to NS(9);

[0403] The terminal labeled NS(11) is the drive signal output terminal of S11, and the terminal labeled NO(11) is the output drive terminal of S11; S11 is electrically connected to NS(10);

[0404] The terminal labeled NS(12) is the drive signal output terminal of S12, and the terminal labeled NO(12) is the output drive terminal of S12; S12 is electrically connected to NS(11);

[0405] S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11 and S12 are all electrically connected to the gating input terminal VCT;

[0406] S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11 and S12 are all electrically connected to the first clock signal terminal GCK;

[0407] S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11 and S12 are all electrically connected to the second clock signal terminal GCB.

[0408] exist Figure 26 In the diagram, the terminal labeled STV is the starting voltage terminal, and S1 is electrically connected to STV.

[0409] Figure 27 yes Figure 26 The timing diagram shows the operation of at least one embodiment of the driving module.

[0410] This disclosure Figure 26In at least one embodiment of the drive module shown, when NS(N-1) outputs a high voltage signal and NS(N) outputs a low voltage signal, if VCT outputs a low voltage signal, then when NS(N) outputs a high voltage signal, NO(N) outputs a low voltage signal.

[0411] When NS(N-1) outputs a high voltage signal and NS(N) outputs a low voltage signal, if VCT outputs a high voltage signal, then when NS(N) outputs a high voltage signal, NO(N) will also output a high voltage signal.

[0412] The display device described in this disclosure includes the driving module described above.

[0413] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A driving circuit, comprising a driving signal generation circuit, a gating circuit, an output control circuit, and an output circuit; The drive signal generation circuit is electrically connected to the N-1th stage drive signal output terminal and the Nth stage drive signal output terminal, respectively, and is used to perform a shift operation on the N-1th stage drive signal provided by the N-1th stage drive signal output terminal to obtain and output the Nth stage drive signal through the Nth stage drive signal output terminal. The gating circuit is electrically connected to the first node, the gating input terminal, and the gating control terminal, respectively, and is used to control the gating input signal provided by the gating input terminal to be written into the first node under the control of the gating control signal provided by the gating control terminal; The first terminal of the output control circuit is electrically connected to the output terminal of the Nth stage drive signal, and the second terminal of the output control circuit is electrically connected to the first node. It is used to perform a AND-NOT operation on the potential of the Nth stage drive signal and the second terminal of the output control circuit to obtain the first output signal. The output circuit is used to invert the first output signal to obtain an output drive signal that is provided through the output drive terminal. N is a positive integer.

2. The driving circuit as described in claim 1, wherein, The gating circuit is used to control the writing of the gating input signal provided by the gating input terminal into the first node when the potential of the N-1 level driving signal is a first voltage and the potential of the N level driving signal is a second voltage.

3. The driving circuit as described in claim 1, wherein, The gating circuit includes a first transistor; the gate of the first transistor is electrically connected to the gating control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the gating input terminal.

4. The driving circuit as described in claim 1, wherein, The gating control terminal includes a first gating control terminal and a second gating control terminal; the gating circuit includes a first transistor and a second transistor; The gate of the first transistor is electrically connected to the first gating control terminal, the first terminal of the first transistor is electrically connected to the first node, and the second terminal of the first transistor is electrically connected to the first terminal of the second transistor. The gate of the second transistor is electrically connected to the second gating control terminal, and the second terminal of the second transistor is electrically connected to the gating input terminal; The first gating control terminal is the output terminal of the (N-1)th stage drive signal, the second gating control terminal is the output terminal of the Nth stage drive signal, the first transistor is an n-type transistor, and the second transistor is a p-type transistor; or... The first gating control terminal is the Nth stage drive signal output terminal, the second gating control terminal is the N-1th stage drive signal output terminal, the first transistor is a p-type transistor, and the second transistor is an n-type transistor; or, The first gating control terminal is connected to the inverted signal of the (N-1)th stage drive signal, and the second gating control terminal is the output terminal of the Nth stage drive signal. Both the first transistor and the second transistor are p-type transistors; or... The first gating control terminal is the output terminal of the Nth stage drive signal, and the second gating control terminal is connected to the inverted signal of the (N-1)th stage drive signal; both the first transistor and the second transistor are p-type transistors; or, The first gating control terminal is the N-1th stage drive signal terminal, and the second gating control terminal is connected to the inverted signal of the Nth stage drive signal. Both the first transistor and the second transistor are n-type transistors. or, The first gating control terminal is connected to the inverted signal of the Nth stage drive signal, and the second gating control terminal is the N-1th stage drive signal terminal. Both the first transistor and the second transistor are n-type transistors.

5. The driving circuit as described in claim 1, wherein, It also includes a first initialization circuit; The first initialization circuit is electrically connected to the initial control terminal, the first voltage terminal, and the first node, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.

6. The driving circuit as described in claim 5, wherein, It also includes a first voltage sustaining circuit; The first terminal of the first voltage maintenance circuit is electrically connected to the first node, and the second terminal of the first voltage maintenance circuit is electrically connected to a DC voltage terminal or the second node. The first voltage maintenance circuit is used to maintain the potential of the first node.

7. The driving circuit according to any one of claims 1 to 6, wherein, It also includes a second voltage sustaining circuit, through which the first node is electrically connected to the second terminal of the output control circuit; The second voltage sustaining circuit includes a first inverter, a second inverter, and a sustaining control circuit; The input terminal of the first inverter is electrically connected to the first node, the output terminal of the first inverter is electrically connected to the second node, the input terminal of the second inverter is electrically connected to the second node, and the output terminal of the second inverter is electrically connected to the third node and the second terminal of the output control circuit. The first inverter is used to invert the potential of the first node and output the inverted potential of the first node through the output terminal of the first inverter. The second inverter is used to invert the potential of its input terminal and output the inverted potential through the output terminal of the second inverter. The maintenance control circuit is electrically connected to the maintenance control terminal, the third node, and the first node, respectively, and is used to control the connection or disconnection between the third node and the first node under the control of the maintenance control signal provided by the maintenance control terminal.

8. The driving circuit as described in claim 7, wherein, The maintenance control terminal includes a first maintenance control terminal and a second maintenance control terminal; The sustaining control circuit includes a third transistor and a fourth transistor; The gate of the third transistor is electrically connected to the first sustaining control terminal, the first terminal of the third transistor is electrically connected to the first node, and the second terminal of the third transistor is electrically connected to the third node. The gate of the fourth transistor is electrically connected to the second sustain control terminal, the first terminal of the fourth transistor is electrically connected to the third node, and the second terminal of the fourth transistor is electrically connected to the first node. The third transistor is a p-type transistor, and the fourth transistor is an n-type transistor; The first sustain control terminal is the (N-1)th stage drive signal terminal, and the second sustain control terminal is the first clock signal terminal; or, The first sustain control terminal is the second clock signal terminal, and the second sustain control terminal is the first clock signal terminal.

9. The driving circuit as described in claim 7, wherein, The first inverter includes a fifth transistor and a sixth transistor, and the second inverter includes a seventh transistor and an eighth transistor; The gate of the fifth transistor is electrically connected to the first node, the first terminal of the fifth transistor is electrically connected to the first voltage terminal, and the second terminal of the fifth transistor is electrically connected to the second node. The gate of the sixth transistor is electrically connected to the first node, the first terminal of the sixth transistor is electrically connected to the second node, and the second terminal of the sixth transistor is electrically connected to the second voltage terminal. The fifth transistor is a p-type transistor, and the sixth transistor is an n-type transistor; The gate of the seventh transistor is electrically connected to the second node, the first terminal of the seventh transistor is electrically connected to the first voltage terminal, and the second terminal of the seventh transistor is electrically connected to the third node; The gate of the eighth transistor is electrically connected to the second node, the first terminal of the eighth transistor is electrically connected to the third node, and the second terminal of the eighth transistor is electrically connected to the second voltage terminal. The seventh transistor is a p-type transistor, and the eighth transistor is an n-type transistor.

10. The driving circuit as described in claim 6, wherein, The first initialization circuit includes a ninth transistor, and the first voltage sustaining circuit includes a first capacitor; The gate of the ninth transistor is electrically connected to the initial control terminal, the first terminal of the ninth transistor is electrically connected to the first voltage terminal, and the second terminal of the ninth transistor is electrically connected to the first node. The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the DC voltage terminal or the second node.

11. The driving circuit according to any one of claims 1 to 6, wherein, The output control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor; The gate of the tenth transistor is electrically connected to the output terminal of the Nth stage drive signal, the first terminal of the tenth transistor is electrically connected to the first voltage terminal, and the second terminal of the tenth transistor is electrically connected to the fourth node. The gate of the eleventh transistor is electrically connected to the first node, the first terminal of the eleventh transistor is electrically connected to the first voltage terminal, and the second terminal of the eleventh transistor is electrically connected to the fourth node. The gate of the twelfth transistor is electrically connected to the output terminal of the Nth stage drive signal, the first terminal of the twelfth transistor is electrically connected to the fourth node, and the second terminal of the twelfth transistor is electrically connected to the fifth node. The gate of the thirteenth transistor is electrically connected to the first node, the first terminal of the thirteenth transistor is electrically connected to the fifth node, and the second terminal of the thirteenth transistor is electrically connected to the second voltage terminal. The tenth and eleventh transistors are p-type transistors, and the twelfth and thirteenth transistors are n-type transistors.

12. The driving circuit as claimed in claim 7, wherein, The output control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor; The gate of the tenth transistor is electrically connected to the output terminal of the Nth stage drive signal, the first terminal of the tenth transistor is electrically connected to the first voltage terminal, and the second terminal of the tenth transistor is electrically connected to the fourth node. The gate of the eleventh transistor is electrically connected to the third node, the first terminal of the eleventh transistor is electrically connected to the first voltage terminal, and the second terminal of the eleventh transistor is electrically connected to the fourth node. The gate of the twelfth transistor is electrically connected to the output terminal of the Nth stage drive signal, the first terminal of the twelfth transistor is electrically connected to the fourth node, and the second terminal of the twelfth transistor is electrically connected to the fifth node. The gate of the thirteenth transistor is electrically connected to the third node, the first terminal of the thirteenth transistor is electrically connected to the fifth node, and the second terminal of the thirteenth transistor is electrically connected to the second voltage terminal. The tenth and eleventh transistors are p-type transistors, and the twelfth and thirteenth transistors are n-type transistors.

13. The driving circuit according to any one of claims 1 to 6, wherein, The output circuit includes a fourteenth transistor and a fifteenth transistor; The gate of the fourteenth transistor is electrically connected to the fourth node, the first terminal of the fourteenth transistor is electrically connected to the first voltage terminal, and the second terminal of the fourteenth transistor is electrically connected to the output drive terminal. The gate of the fifteenth transistor is electrically connected to the fourth node, the first terminal of the fifteenth transistor is electrically connected to the output drive terminal, and the second terminal of the fifteenth transistor is electrically connected to the second voltage terminal.

14. The driving circuit according to any one of claims 1 to 6, wherein, The drive signal generation circuit includes a first control circuit, a second control circuit, a third inverter, and a second initialization circuit. The first control circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the N-1th stage drive signal output terminal and the sixth node, respectively. Under the control of the first clock signal provided by the first clock signal terminal and the second clock signal provided by the second clock signal terminal, the N-1th stage drive signal output terminal is shifted and inverted to obtain the inverted signal output through the sixth node. The second control circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the Nth stage drive signal output terminal, and the sixth node, respectively. It is used to invert the Nth stage drive signal provided by the Nth stage drive signal output terminal under the control of the first clock signal and the second clock signal, so as to obtain the inverted signal and output it through the sixth node. The third inverter is electrically connected to the sixth node and the Nth stage drive signal output terminal, respectively, and is used to invert the potential of the sixth node and output the inverted signal through the Nth stage drive signal output terminal; The second initialization circuit is electrically connected to the initial control terminal, the first voltage terminal, and the Nth stage drive signal output terminal, respectively, and is used to control the connection between the Nth stage drive signal output terminal and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.

15. The driving circuit as described in claim 14, wherein, The first control circuit includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor; The gate of the sixteenth transistor is electrically connected to the second clock signal terminal, the first terminal of the sixteenth transistor is electrically connected to the first voltage terminal, and the second terminal of the sixteenth transistor is electrically connected to the first terminal of the seventeenth transistor. The gate of the seventeenth transistor is electrically connected to the output terminal of the (N-1)th stage drive signal, and the second terminal of the seventeenth transistor is electrically connected to the sixth node; The gate of the eighteenth transistor is electrically connected to the output terminal of the (N-1)th stage drive signal, the first terminal of the eighteenth transistor is electrically connected to the sixth node, and the second terminal of the eighteenth transistor is electrically connected to the first terminal of the nineteenth transistor. The gate of the nineteenth transistor is electrically connected to the first clock signal terminal, and the second terminal of the nineteenth transistor is electrically connected to the second voltage terminal. The sixteenth and seventeenth transistors are p-type transistors, and the eighteenth and nineteenth transistors are n-type transistors.

16. The driving circuit as claimed in claim 14, wherein, The second control circuit includes the twentieth transistor, the twenty-first transistor, the twenty-second transistor, and the twenty-third transistor; The gate of the twentieth transistor is electrically connected to the first clock signal terminal, the first terminal of the twentieth transistor is electrically connected to the first voltage terminal, and the second terminal of the twentieth transistor is electrically connected to the first terminal of the twentieth transistor. The gate of the 21st transistor is electrically connected to the output terminal of the Nth stage drive signal, and the second terminal of the 21st transistor is electrically connected to the sixth node; The gate of the 22nd transistor is electrically connected to the output terminal of the Nth stage drive signal, the first terminal of the 22nd transistor is electrically connected to the sixth node, and the second terminal of the 22nd transistor is electrically connected to the first terminal of the 23rd transistor. The gate of the 23rd transistor is electrically connected to the second clock signal terminal, and the second terminal of the 23rd transistor is electrically connected to the second voltage terminal; The twentieth and twentieth transistors are p-type transistors, and the twentieth and twentieth transistors are n-type transistors.

17. The driving circuit as claimed in claim 14, wherein, The third inverter includes a twenty-fourth transistor and a twenty-fifth transistor; the second initialization circuit includes a twenty-sixth transistor. The gate of the 24th transistor is electrically connected to the sixth node, the first terminal of the 24th transistor is electrically connected to the first voltage terminal, and the second terminal of the 24th transistor is electrically connected to the first terminal of the 25th transistor. The gate of the 25th transistor is electrically connected to the sixth node, and the second terminal of the 25th transistor is electrically connected to the second voltage terminal; The twenty-fourth transistor is a p-type transistor, and the twenty-fifth transistor is an n-type transistor; The gate of the 26th transistor is electrically connected to the initial control terminal, the first terminal of the 26th transistor is electrically connected to the first voltage terminal, and the second terminal of the 26th transistor is electrically connected to the Nth stage drive signal output terminal.

18. A driving method applied to a driving circuit as described in any one of claims 1 to 17, the driving method comprising: The drive signal generation circuit performs a shift operation on the (N-1)th stage drive signal to obtain and output the Nth stage drive signal through the Nth stage drive signal output terminal. Under the control of the gating control signal, the gating circuit controls the writing of the gating input signal provided by the gating input terminal into the first node; The output control circuit performs a AND-NOT operation on the Nth stage drive signal and the potential of the second terminal of the output control circuit to obtain the first output signal; The output circuit is used to invert the first output signal to obtain an output drive signal that is provided through the output drive terminal.

19. A driving module comprising multiple stages of driving circuits as described in any one of claims 1 to 17; The Nth stage drive circuit is electrically connected to the drive signal output terminals of the (N-1)th stage drive circuit; N is a positive integer.

20. A display device comprising the driving module as described in claim 19.

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