Display substrate, preparation method thereof and display device

Abstract

The invention discloses a display substrate, a preparation method thereof and a display device. The display substrate comprises a substrate, a plurality of sub-pixels and a plurality of transparent conducting layers (300), the sub-pixels and the transparent conducting layers (300) are arranged on the substrate, each sub-pixel comprises at least one transparent conducting layer (300), and at least one part of the sub-pixels at least comprise a second transistor and a third transistor. The second electrode of the second transistor and the second electrode of the third transistor in the same sub-pixel are electrically connected through at least one transparent conductive layer (300).

Description

Display substrate and manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) are active light-emitting display devices with advantages such as luminescence, ultra-thinness, wide viewing angles, high brightness, high contrast, low power consumption, and extremely fast response times. With the continuous advancement of display technology, OLED technology is increasingly being used in flexible display devices and has gradually become a highly promising next-generation display technology. Depending on the driving method, OLEDs can be divided into two types: passive matrix (PM) and active matrix (AM). AMOLEDs are current-driven devices that use independent thin-film transistors (TFTs) to control each sub-pixel, allowing each sub-pixel to emit light continuously and independently.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, the present disclosure provides a display substrate, including a base and a plurality of sub-pixels and a plurality of transparent conductive layers arranged on the base, each sub-pixel includes at least one transparent conductive layer, at least a portion of the sub-pixels include at least a second transistor and a third transistor, and the second electrode of the second transistor and the second electrode of the third transistor located in the same sub-pixel are electrically connected through at least one transparent conductive layer.

[0006] In an exemplary embodiment, at least a portion of the transparent conductive layer includes an anode, a first connection electrode, and a second connection electrode, and in the same transparent conductive layer, the anode is electrically connected to the first connection electrode and the second connection electrode;

[0007] In the same sub-pixel, the second electrode of the second transistor is electrically connected to the corresponding anode through the first connecting electrode, the second electrode of the third transistor is electrically connected to the corresponding anode through the second connecting electrode, and the second electrode of the second transistor and the second electrode of the third transistor are electrically connected through the corresponding first connecting electrode, second connecting electrode, and anode.

[0008] In an exemplary embodiment, the first connecting electrode and the second connecting electrode are integrally formed with the corresponding anode.

[0009] In an exemplary embodiment, the display substrate further includes a pixel definition layer, which is located on a side of the transparent conductive layer away from the substrate, the pixel definition layer being formed with a plurality of pixel openings, each sub-pixel including at least one pixel opening, an orthographic projection of the pixel opening on the substrate and an orthographic projection of the corresponding anode on the substrate having an overlapping area, and the transparent conductive layer being located in the light-emitting area of ​​the corresponding sub-pixel.

[0010] In an exemplary embodiment, the second electrode of the second transistor is electrically connected to the corresponding first connecting electrode through a first transfer via, and the orthographic projection of the first transfer via on the substrate is located within the range of the orthographic projection of the first connecting electrode on the substrate; the second electrode of the third transistor is electrically connected to the corresponding second connecting electrode through a second transfer via, and the orthographic projection of the second transfer via on the substrate is located within the range of the orthographic projection of the second connecting electrode on the substrate; the closest distance from the first transfer via to the edge of the corresponding pixel opening is smaller than the closest distance from the second transfer via to the edge of the corresponding pixel opening, and the first transfer via and the second transfer via are located on both sides of the corresponding pixel opening.

[0011] In an exemplary embodiment, the multiple sub-pixels are arranged along row and column directions. In the row direction, the distance between the first transfer vias in two adjacent sub-pixels includes a first distance and a second distance, the first distance is greater than the second distance, and the first distance and the second distance are alternately arranged along the row direction.

[0012] In an exemplary embodiment, in the row direction, the distance between the second transfer vias in two adjacent sub-pixels includes a third distance and a fourth distance, the third distance is greater than the fourth distance, and the third distance and the fourth distance are alternately arranged along the row direction.

[0013] In an exemplary embodiment, in the same sub-pixel, in the column direction, the second transistor and the third transistor are located on both sides of the corresponding anode, and the distance between the second transistor and the third transistor is greater than 0.5 times the size of the sub-pixel in the column direction.

[0014] In an exemplary embodiment, the display substrate further includes a plurality of data signal lines and a plurality of auxiliary data lines, the plurality of data signal lines being electrically connected to the plurality of auxiliary data lines, respectively. The data signal lines and the auxiliary data lines are located in different conductive layers. In a direction perpendicular to a plane of the display substrate, the conductive layer where the data signal lines and the auxiliary data lines are located is located between the substrate and the transparent conductive layer, and the orthographic projections of the plurality of data signal lines on the substrate at least partially overlap with the orthographic projections of the plurality of auxiliary data lines on the substrate, respectively.

[0015] In an exemplary embodiment, the display substrate includes a gate metal layer disposed on the base, and at least a portion of the auxiliary data line is located in the gate metal layer.

[0016] In an exemplary embodiment, the display substrate further includes a blocking metal layer. In a direction perpendicular to the plane of the display substrate, the gate metal layer is located on a side of the blocking metal layer away from the base. The multiple data signal lines are located in the blocking metal layer.

[0017] In an exemplary embodiment, the shielding metal layer is further provided with a plurality of first power lines, and the gate metal layer is further provided with a plurality of first power auxiliary lines, and the plurality of first power lines are electrically connected to the plurality of first power auxiliary lines respectively, and the orthographic projections of the plurality of first power lines on the substrate respectively at least partially overlap with the orthographic projections of the plurality of first power auxiliary lines on the substrate.

[0018] In an exemplary embodiment, the multiple sub-pixels form a plurality of pixel units arranged in an array, each pixel unit includes at least three sub-pixels, the gate metal layer is further provided with a plurality of first power connection lines, the same pixel unit includes two first power auxiliary lines, the two ends of the first power connection line located in the same pixel unit are respectively connected to the two first power auxiliary lines, on a plane parallel to the display substrate, the main portion of the first power auxiliary line extends along the second direction, the main portion of the first power connection line extends along the first direction, and the first direction intersects with the second direction.

[0019] In an exemplary embodiment, the display substrate further includes a semiconductor layer, which is located on a side of the shielding metal layer away from the base in a direction perpendicular to the plane of the display substrate, and the semiconductor layer is provided with a plurality of compensation connection lines. The shielding metal layer is also provided with a plurality of compensation signal lines. In a plane parallel to the display substrate, the compensation connection lines are strip structures extending along a first direction, and the compensation signal lines are strip structures extending along a second direction, the first direction intersects with the second direction, and the compensation connection lines are electrically connected to at least one compensation signal line.

[0020] In an exemplary embodiment, the display substrate further includes a source-drain metal layer, which is located on a side of the gate metal layer away from the base in a direction perpendicular to the plane of the display substrate, and the multiple data signal lines are located in the source-drain metal layer.

[0021] In an exemplary embodiment, the display substrate further includes a second blocking metal layer, and in a direction perpendicular to the plane of the display substrate, the second blocking metal layer is located between the base and the gate metal layer, the multiple auxiliary data lines include a plurality of first auxiliary data lines and a plurality of second auxiliary data lines, the plurality of first auxiliary data lines are located in the second blocking metal layer, and the plurality of second auxiliary data lines are located in the gate metal layer, the orthographic projections of the plurality of first auxiliary data lines and the plurality of second auxiliary data lines on the base have an overlapping area with the orthographic projections of the corresponding plurality of data signal lines on the base, and the plurality of first auxiliary data lines and the plurality of second auxiliary data lines are electrically connected to the corresponding plurality of data signal lines.

[0022] In an exemplary embodiment, the source / drain metal layer is further provided with a plurality of first power lines, and the gate metal layer is further provided with a plurality of first power auxiliary lines, and the plurality of first power lines are electrically connected to the plurality of first power auxiliary lines, respectively, and the orthographic projections of the plurality of first power lines on the substrate are at least partially overlapped with the orthographic projections of the plurality of first power auxiliary lines on the substrate.

[0023] In an exemplary embodiment, the multiple sub-pixels form a plurality of pixel units arranged in an array, each pixel unit includes at least three sub-pixels, and the display substrate further includes a semiconductor layer. In a direction perpendicular to the plane of the display substrate, the semiconductor layer is located on a side of the second blocking metal layer away from the base, and the semiconductor layer is provided with a plurality of first power connection lines, two of which are included in the same pixel unit, and both ends of the first power connection line located in the same pixel unit are electrically connected to the two first power lines, respectively. In a plane parallel to the display substrate, the main portion of the first power connection line extends along the second direction, and the main portion of the first power connection line extends along the first direction, and the first direction intersects with the second direction.

[0024] In an exemplary embodiment, the second blocking metal layer is further provided with a plurality of compensation connection lines, and the source / drain metal layer is further provided with a plurality of compensation signal lines. On a plane parallel to the display substrate, the compensation connection lines are strip structures extending along a first direction, and the compensation signal lines are strip structures extending along a second direction. The first direction intersects with the second direction, and the compensation connection lines are electrically connected to at least one compensation signal line.

[0025] In an exemplary embodiment, the display substrate further includes a first blocking metal layer, which is located between the base and the second blocking metal layer in a direction perpendicular to the plane of the display substrate, the first blocking metal layer is provided with a plurality of first scanning signal lines, and the second blocking metal layer is provided with a plurality of first scanning signal auxiliary lines respectively electrically connected to the plurality of first scanning signal lines, and the orthographic projections of the plurality of first scanning signal lines on the base at least partially overlap with the orthographic projections of the plurality of first scanning signal auxiliary lines on the base.

[0026] In an exemplary embodiment, a thickness of the first blocking metal layer is greater than a thickness of the second blocking metal layer.

[0027] In an exemplary embodiment, the display substrate further includes a first conductive layer, which is located between the base and the transparent conductive layer. The sub-pixel further includes a capacitor, and the first conductive layer includes a first plate of the capacitor, the first plate is a transparent structure, and the anode is reused as the second plate of the capacitor. In the same sub-pixel, the orthographic projection of the first plate on the base and the orthographic projection of the second plate on the base have a first overlapping area, and the first overlapping area is located in the light-emitting area of ​​the sub-pixel.

[0028] In an exemplary embodiment, the display substrate further includes a first conductive layer, the first conductive layer is located between the base and the transparent conductive layer, the sub-pixel further includes a capacitor, the first conductive layer includes a first electrode plate of the capacitor, and the first electrode plate is a transparent structure;

[0029] The display substrate also includes a gate metal layer, the transparent conductive layer is located on the gate metal layer, the transparent conductive layer is reused as the second electrode plate of the capacitor, and the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the second electrode plate on the substrate have a first overlapping area, and the first overlapping area is located in the light-emitting area of ​​the sub-pixel.

[0030] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0031] On the other hand, the present disclosure also provides a method for preparing a display substrate, comprising: forming a plurality of sub-pixels and a plurality of transparent conductive layers on one side of a substrate, wherein at least a portion of the sub-pixels include at least a second transistor and a third transistor, and the second electrode of the second transistor and the second electrode of the third transistor located in the same sub-pixel are electrically connected through at least one transparent conductive layer.

[0032] Other aspects will become apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0034] FIG1 is a schematic structural diagram of a display device;

[0035] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0036] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0037] FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0038] FIG5a is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0039] FIG5 b is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0040] FIG5c is a schematic diagram of an equivalent circuit of the pixel driving circuit in the four sub-pixels shown in FIG5a and FIG5b;

[0041] FIG6 is a schematic diagram of an exemplary embodiment of the present disclosure after forming a first conductive layer pattern;

[0042] FIG7 a is a schematic diagram of an exemplary embodiment of the present disclosure after forming a second conductive layer pattern;

[0043] FIG7 b is a schematic plan view of the second conductive layer in FIG7 a ;

[0044] FIG8 a is a schematic diagram of an exemplary embodiment of the present disclosure after forming a semiconductor layer pattern;

[0045] FIG8b is a schematic plan view of the semiconductor layer in FIG8a;

[0046] FIG9 is a schematic diagram of an exemplary embodiment of the present disclosure after forming a second insulation layer pattern;

[0047] FIG10 a is a schematic diagram of an exemplary embodiment of the present disclosure after forming a third conductive layer pattern;

[0048] FIG10 b is a schematic plan view of the third conductive layer in FIG10 a ;

[0049] FIG10c is a schematic diagram of the cross-sectional structure at position A1-A1 in FIG10a;

[0050] FIG10d is a schematic diagram of the cross-sectional structure at position A2-A2 in FIG10a;

[0051] FIG11 is a schematic diagram of an exemplary embodiment of the present disclosure after a planar layer pattern is formed;

[0052] FIG12a is a schematic diagram of an exemplary embodiment of the present disclosure after forming a fourth conductive layer pattern;

[0053] FIG12b is a schematic plan view of the fourth conductive layer in FIG12a;

[0054] FIG13a is a schematic diagram of an exemplary embodiment of the present disclosure after forming a pixel definition layer pattern;

[0055] FIG13 b is a plan view schematically showing the pixel definition layer in FIG13 a ;

[0056] FIG14 is a schematic diagram of an exemplary embodiment of the present disclosure after forming a first conductive layer pattern;

[0057] FIG15 is a schematic diagram of an exemplary embodiment of the present disclosure after forming a second conductive layer pattern;

[0058] FIG16a is a schematic diagram of an exemplary embodiment of the present disclosure after forming a third conductive layer pattern;

[0059] FIG16 b is a schematic plan view of the third conductive layer in FIG16 a ;

[0060] FIG17a is a schematic diagram of an exemplary embodiment of the present disclosure after forming a semiconductor layer pattern;

[0061] FIG17 b is a schematic plan view of the semiconductor layer in FIG17 a ;

[0062] FIG18a is a schematic diagram of an exemplary embodiment of the present disclosure after forming a fourth conductive layer pattern;

[0063] FIG18b is a schematic plan view of the fourth conductive layer in FIG18a;

[0064] FIG19 is a schematic diagram of an exemplary embodiment of the present disclosure after forming a third insulation layer pattern;

[0065] FIG20 a is a schematic diagram of an exemplary embodiment of the present disclosure after forming a fifth conductive layer pattern;

[0066] FIG20 b is a schematic plan view of the fifth conductive layer in FIG20 a ;

[0067] FIG21 is a schematic diagram of an exemplary embodiment of the present disclosure after a planar layer pattern is formed;

[0068] FIG22 a is a schematic diagram of an exemplary embodiment of the present disclosure after forming a sixth conductive layer pattern;

[0069] FIG22 b is a schematic plan view of the sixth conductive layer in FIG20 a ;

[0070] FIG23a is a schematic diagram of an exemplary embodiment of the present disclosure after forming a pixel definition layer pattern;

[0071] FIG23 b is a plan view schematically showing the pixel definition layer in FIG23 a ;

[0072] FIG23c is a schematic diagram of the cross-sectional structure at position A3-A3 in FIG22a;

[0073] FIG24 a is a schematic plan view of a semiconductor layer according to an exemplary embodiment of the present disclosure;

[0074] FIG24 b is a schematic diagram of an exemplary embodiment of the present disclosure after forming a fourth conductive layer pattern;

[0075] FIG24c is a schematic plan view of the fourth conductive layer in FIG24b;

[0076] FIG24 d is a schematic diagram of an exemplary embodiment of the present disclosure after forming a third insulation layer pattern;

[0077] FIG24e is a schematic diagram of an exemplary embodiment of the present disclosure after forming a fifth conductive layer pattern;

[0078] FIG24f is a schematic plan view of the fifth conductive layer in FIG24e;

[0079] FIG25 a is a schematic diagram of an exemplary embodiment of the present disclosure after forming a fourth conductive layer pattern;

[0080] FIG25 b is a schematic diagram of an exemplary embodiment of the present disclosure after forming a fifth conductive layer pattern;

[0081] FIG. 25 c is a schematic diagram of an exemplary embodiment of the present disclosure after forming a sixth conductive layer pattern. DETAILED DESCRIPTION

[0082] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other in any way.

[0083] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0084] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0085] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0086] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0087] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0088] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0089] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0090] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0091] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0092] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0093] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0094] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, and a pixel array. The timing controller is respectively connected to the data driver and the scan driver. The data driver is respectively connected to multiple data signal lines (D1 to D), and the scan driver is respectively connected to multiple scan signal lines (S1 to Sm). The pixel array may include multiple sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include at least one scan signal line, at least one data signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, and may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the scan driver. The data driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., and D. For example, the data driver can sample the grayscale value using a clock signal and apply a data voltage corresponding to the grayscale value to the data signal lines D1 to D in units of pixel rows, where n can be a natural number. The scan driver can generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan driver can sequentially provide a scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan driver can be constructed in the form of a shift register and can generate a scan signal in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to the next level circuit under the control of a clock signal, where m can be a natural number.

[0095] FIG2 is a schematic diagram of a planar structure of a display substrate. As shown in FIG2 , the display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, a third subpixel P3 that emits a third color light, and a fourth subpixel P4 that emits a fourth color light. Each of the four subpixels may include a circuit unit and a light-emitting device. The circuit unit may include scan signal lines, data signal lines, and a pixel driver circuit. The pixel driver circuit is connected to the scan signal lines and the data signal lines, respectively. The pixel driver circuit is configured to receive a data voltage transmitted by the data signal lines under the control of the scan signal lines and output a corresponding current to the light-emitting device. The light-emitting device in each subpixel is connected to the pixel driver circuit of the subpixel in which it is located. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driver circuit of the subpixel in which it is located.

[0096] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a white subpixel (W) that emits white light, the third subpixel P3 may be a blue subpixel (B) that emits blue light, and the fourth subpixel P4 may be a green subpixel (G) that emits green light.

[0097] In an exemplary embodiment, the shape of the sub-pixels may be rectangular, diamond, pentagonal, or hexagonal. In one exemplary embodiment, four sub-pixels may be arranged horizontally in parallel to form a RWBG pixel arrangement. In another exemplary embodiment, the four sub-pixels may be arranged in a square, diamond, or vertically parallel arrangement, which is not limited in this disclosure.

[0098] In an exemplary embodiment, a plurality of sub-pixels sequentially arranged in a horizontal direction are referred to as pixel rows, and a plurality of sub-pixels sequentially arranged in a vertical direction are referred to as pixel columns. The plurality of pixel rows and the plurality of pixel columns constitute an array-arranged pixel array.

[0099] Figure 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of four sub-pixels within the display substrate. As shown in Figure 3, in a plane perpendicular to the display substrate, each sub-pixel within the display substrate may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the drive circuit layer 102 facing away from the substrate, and an encapsulation layer 104 disposed on a side of the light-emitting structure layer 103 facing away from the substrate.

[0100] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a pixel driving circuit composed of multiple transistors and storage capacitors. The light-emitting structure layer 103 of each sub-pixel may include a light-emitting device composed of multiple film layers, and the multiple film layers may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304. The anode 301 is connected to the pixel driving circuit, the organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits light of a corresponding color under the drive of the anode 301 and the cathode 304. The encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0101] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a light-emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be a common layer connected together, and the light-emitting layers of all sub-pixels may be a common layer connected together, or may be isolated from each other, and the light-emitting layers of adjacent sub-pixels may have a small amount of overlap. In some possible implementations, the display substrate may include other film layers, which are not limited in this disclosure.

[0102] In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG4 , the pixel driving circuit is a 3T1C structure and may include three transistors (a first transistor T1, a second transistor T2, and a third transistor T3), a storage capacitor C, and six signal lines (a data signal line D, a first scan signal line S1, a second scan signal line S2, a compensation signal line S, a first power line VDD, and a second power line VSS). In FIG4 , C_e is the intrinsic capacitance of the OLED.

[0103] In an exemplary embodiment, the first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensation transistor. A first electrode of a storage capacitor C is coupled to the control electrode of the second transistor T2, and a second electrode of the storage capacitor C is coupled to the second electrode of the second transistor T2. The storage capacitor C is used to store the potential of the control electrode of the second transistor T2. The control electrode of the first transistor T1 is coupled to a first scan signal line S1, a first electrode of the first transistor T1 is coupled to a data signal line D, and a second electrode of the first transistor T1 is coupled to the control electrode of the second transistor T2. Under the control of the first scan signal line S1, the first transistor T1 is used to receive a data signal transmitted by the data signal line D, so that the control electrode of the second transistor T2 receives the data signal. The control electrode of the second transistor T2 is coupled to the second electrode of the first transistor T1, a first electrode of the second transistor T2 is coupled to a first power line VDD, and a second electrode of the second transistor T2 is coupled to the first electrode of the light-emitting device. The second transistor T2 is used to generate a corresponding current at its second electrode under the control of the data signal received at its control electrode. The control electrode of the third transistor T3 is coupled to the second scan signal line S2, the first electrode of the third transistor T3 is coupled to the compensation signal line S, the second electrode of the third transistor T3 is coupled to the second electrode of the second transistor T2, and the third transistor T3 is used to extract the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing to compensate for the threshold voltage Vth.

[0104] In an exemplary embodiment, the light-emitting device can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), the first electrode of the OLED is coupled to the second electrode of the second transistor T2, the second electrode of the OLED is coupled to the second power line VSS, and the OLED is used to emit light of corresponding brightness in response to the current of the second electrode of the second transistor T2.

[0105] In an exemplary embodiment, the signal on the first power line VDD is continuously high, and the signal on the second power line VSS is low. The first through third transistors T1 through T3 can be P-type transistors or N-type transistors. Using the same type of transistors in the pixel drive circuit can simplify the process, reduce the manufacturing complexity of the display panel, and improve product yield.

[0106] In an exemplary embodiment, the first transistor T1 to the third transistor T3 may be low-temperature polysilicon thin-film transistors, or may be oxide thin-film transistors, or may be low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is oxide. Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. In an exemplary embodiment, low-temperature polysilicon thin-film transistors and oxide thin-film transistors can be integrated on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate, which can take advantage of the advantages of both, achieve high resolution (Pixel Per Inch, PPI), low-frequency driving, reduce power consumption, and improve display quality. In an exemplary embodiment, the light-emitting device can be an organic light-emitting diode (OLED), including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode).

[0107] In an exemplary embodiment, taking the case where all three transistors are N-type transistors as an example, the operation process of the pixel driving circuit illustrated in FIG4 may include:

[0108] In the first phase A1, the signals of the first scan signal line S1 and the second scan signal line S2 are high-level signals, the data signal line D outputs the data voltage, the compensation signal line S outputs the compensation voltage, the signal of the first power line VDD is high-level, and the signal of the second power line VSS is low-level. The signal of the first scan signal line S1 is high-level, turning on the first transistor T1. The data voltage output by the data signal line D is written into the first node N1, pulling the potential of the first node N1 high and charging the storage capacitor C. At this time, the potential of the first node N1 is V1=V data The signal of the second scanning signal line S2 is a high level signal, which turns on the third transistor T3, and the compensation voltage output by the compensation signal line S is written into the second node N2. At this time, the potential V2 of the second node N2 is V s Since the potential difference between the first node N1 and the second node N2 is greater than the threshold voltage V th , the second transistor T2 is turned on, and the power voltage output by the first power line VDD provides a driving voltage to the first electrode of the OLED through the turned-on second transistor T2, driving the OLED to emit light.

[0109] In the second stage A2, the signals of the first scan signal line S1 and the second scan signal line S2 are low-level signals, which turns off the first transistor T1 and the third transistor T3. The voltage in the storage capacitor C still turns on the second transistor T2. The power supply voltage output by the first power line VDD continues to pull up the potential of the second node N2. Due to the presence of the storage capacitor C, the potential of the first node N1 will increase as the potential of the second node N2 increases, and the OLED continues to emit light until the next data voltage is written.

[0110] In an exemplary embodiment, in order to drive the OLED to emit light normally, the OLED and the second transistor T2 are both forward biased. In the first stage, the power voltage output by the first power line VDD is greater than the data voltage output by the data signal line D, the data voltage output by the data signal line D is greater than the compensation voltage output by the compensation signal line S, and the compensation voltage output by the compensation signal line S is greater than the power voltage output by the second power line VSS.

[0111] As the size of the display substrate increases, the impact of in-plane resistance and capacitance (RC) on the charging rate increases, resulting in poor charging rate uniformity. The RCs that affect in-plane charging rate uniformity include at least one of the following: RC caused by the first power line (VDD RC), RC caused by the scan line (Gate RC), and RC caused by the data line (i.e., data signal line) (Data RC). Furthermore, the capacitor plates and circuit traces in the display substrate occupy a certain amount of space, resulting in a low aperture ratio and pixel density (pixels per inch, PPI) of the display substrate, which greatly affects the display quality of the display substrate. Anode vias are typically located at one end of a sub-pixel, resulting in uneven display at both ends of the sub-pixel.

[0112] An embodiment of the present disclosure provides a display substrate, which may include a base and a plurality of sub-pixels and a plurality of transparent conductive layers arranged on the base, each sub-pixel includes at least one transparent conductive layer, at least a portion of the sub-pixels include at least a second transistor and a third transistor, and the second electrode of the second transistor and the second electrode of the third transistor located in the same sub-pixel are electrically connected through at least one transparent conductive layer.

[0113] In the display substrate provided by this embodiment, the second electrode of the second transistor and the second electrode of the third transistor located in the same sub-pixel are electrically connected through at least one transparent conductive layer. The transparent conductive layer will not block the opening, which can improve the aperture ratio and PPI of the display substrate.

[0114] Figures 5a and 5b are schematic structural diagrams of a display substrate according to an exemplary embodiment of the present disclosure. The display substrate may include a substrate and a plurality of sub-pixels and a plurality of transparent conductive layers 300 arranged on the substrate. Each sub-pixel includes at least one transparent conductive layer 300, and at least a portion of the sub-pixels include at least a second transistor T2 and a third transistor T3. The second electrode of the second transistor T2 and the second electrode of the third transistor T3 located in the same sub-pixel are electrically connected through at least one transparent conductive layer 300.

[0115] In an exemplary embodiment, as shown in FIG12 b and FIG22 b , at least a portion of the transparent conductive layer 300 includes an anode 301, a first connection electrode 3011, and a second connection electrode 3012. In the same transparent conductive layer 300, the anode 301 is electrically connected to the first connection electrode 3011 and the second connection electrode 3012.

[0116] In the same sub-pixel, the second electrode of the second transistor T2 is electrically connected to the corresponding anode 301 through the first connection electrode 3011, the second electrode of the third transistor T3 is electrically connected to the corresponding anode 301 through the second connection electrode 3012, and the second electrode of the second transistor T2 and the second electrode of the third transistor T3 are electrically connected through the corresponding first connection electrode 3011, second connection electrode 3012, and anode 301.

[0117] In an exemplary embodiment, as shown in Figures 12b and 22b, the first connection electrode 3011 and the second connection electrode 3012 are integrally formed with the corresponding anode 301. In an exemplary embodiment, the first connection electrode 3011, the second connection electrode 3012, and the anode 301 in the transparent conductive layer 300 are all transparent conductive structures, which do not occupy the pixel aperture ratio and do not block the opening, thereby improving the aperture ratio and PPI of the display substrate.

[0118] In an exemplary embodiment, as shown in Figures 5a, 5b, 13b, and 23b, the display substrate may further include a pixel definition layer, which is located on the side of the transparent conductive layer away from the substrate. The pixel definition layer is formed with a plurality of pixel openings 302, and each sub-pixel includes at least one pixel opening 302. The orthographic projection of the pixel opening 302 on the substrate overlaps with the orthographic projection of the corresponding anode 301 on the substrate. The transparent conductive layer 300 is located in the light-emitting region of the corresponding sub-pixel. In the embodiment of the present disclosure, the transparent conductive layer 300 is located in the light-emitting region of the sub-pixel. Since the transparent conductive layer 300 is a transparent structure, it does not block the light emission of the sub-pixel. In an exemplary embodiment, the area corresponding to the pixel opening 302 in the sub-pixel can be the light-emitting region of the sub-pixel.

[0119] In an exemplary embodiment, as shown in Figures 11 and 21, the second electrode of the second transistor T2 is electrically connected to the corresponding first connection electrode 3011 through the first transfer via V21, and the orthographic projection of the first transfer via V21 on the substrate is located within the range of the orthographic projection of the first connection electrode 3011 on the substrate; the second electrode of the third transistor T3 is electrically connected to the corresponding second connection electrode 3012 through the second transfer via V20, and the orthographic projection of the second transfer via V20 on the substrate is located within the range of the orthographic projection of the second connection electrode 3012 on the substrate; the closest distance from the first transfer via V21 to the edge of the corresponding pixel opening 302 is smaller than the closest distance from the second transfer via V21 to the edge of the corresponding pixel opening 302, and the first transfer via V21 and the second transfer via V20 are located on both sides of the corresponding pixel opening 302. In the embodiment of the present disclosure, the first transfer via V21 and the second transfer via V20 are located on both sides of the corresponding pixel opening 302 as anode vias, which can avoid uneven display at both ends of the sub-pixel due to the transfer via being located on one side of the pixel opening 302, thereby improving display uniformity.

[0120] In an exemplary embodiment, as shown in Figures 11 and 21, multiple sub-pixels can be arranged along the row direction X and the column direction Y. In the row direction X, the distance between the first transfer vias V21 in two adjacent sub-pixels includes a first distance R1 and a second distance R2, the first distance R1 is greater than the second distance R2, and the first distance R1 and the second distance R2 are alternately arranged along the row direction X. As shown in Figure 11, the distance between the first transfer via V21 in the first sub-pixel P1 and the first transfer via V21 in the second sub-pixel P2, and the distance between the first transfer via V21 in the third sub-pixel P3 and the first transfer via V21 in the fourth sub-pixel P4 are the first distance R1, and the distance between the first transfer via V21 in the second sub-pixel P2 and the first transfer via V21 in the third sub-pixel P3 is the second distance R2; as shown in Figure 21, the distance between the first transfer via V21 in the first sub-pixel P1 and the first transfer via V21 in the second sub-pixel P2, and the distance between the first transfer via V21 in the third sub-pixel P3 and the first transfer via V21 in the fourth sub-pixel P4 are the second distance R2, and the distance between the first transfer via V21 in the second sub-pixel P2 and the first transfer via V21 in the third sub-pixel P3 is the first distance R1.

[0121] In an exemplary embodiment, as shown in Figures 11 and 21, in the row direction X, the distance between the second transfer vias V20 in two adjacent sub-pixels includes a third distance R3 and a fourth distance R4, the third distance R3 is greater than the fourth distance R4, and the third distance R3 and the fourth distance R4 are alternately arranged along the row direction X. As shown in Figure 11, the distance between the second transfer via V20 in the first sub-pixel P1 and the second transfer via V20 in the second sub-pixel P2, and the distance between the second transfer via V20 in the third sub-pixel P3 and the second transfer via V20 in the fourth sub-pixel P4 are the fourth distance R4, and the distance between the second transfer via V20 in the second sub-pixel P2 and the second transfer via V20 in the third sub-pixel P3 is the third distance R3; as shown in Figure 21, the distance between the second transfer via V20 in the first sub-pixel P1 and the second transfer via V20 in the second sub-pixel P2, and the distance between the second transfer via V20 in the third sub-pixel P3 and the second transfer via V20 in the fourth sub-pixel P4 are the third distance R3, and the distance between the second transfer via V20 in the second sub-pixel P2 and the second transfer via V20 in the third sub-pixel P3 is the fourth distance R4.

[0122] In an exemplary embodiment, as shown in Figures 5a and 5b, in the same sub-pixel, in the column direction X, the second transistor T2 and the third transistor T3 are located on both sides of the corresponding anode 301, and the distance between the second transistor T2 and the third transistor T3 is greater than 0.5 times the size of the sub-pixel along the column direction Y.

[0123] In exemplary embodiments, as shown in Figures 5a, 5b, 6, and 15, the display substrate may further include a first conductive layer positioned between the base and the transparent conductive layer 300. The sub-pixel may further include a capacitor. The first conductive layer may include a first plate 11 of the capacitor, which may be a transparent structure. In the disclosed embodiment, the transparent structure of the capacitor first plate 11 avoids obstruction of the pixel opening, thereby improving the aperture ratio and PPI of the display substrate.

[0124] In an exemplary embodiment, as shown in FIG25c, the anode 301 can be reused as the second plate of the capacitor. In the same sub-pixel, the orthographic projection of the first plate 11 on the substrate and the orthographic projection of the second plate on the substrate have a first overlapping area, and the first overlapping area is located in the light-emitting area of ​​the sub-pixel. The light-emitting area of ​​the sub-pixel corresponds to the corresponding pixel opening 302, or the orthographic projection of the light-emitting area on the substrate overlaps with the orthographic projection of the corresponding pixel opening 302 on the substrate. In the structure shown in FIG25c, the first plate 11 in the first conductive layer and the anode 301 reused as the second plate in the transparent conductive layer are both transparent structures, which can make the two plates of the capacitor not occupy the aperture ratio of the display substrate, thereby greatly improving the aperture ratio and PPI of the display substrate.

[0125] In an exemplary embodiment, as shown in Figures 24b and 24c , the display substrate may further include a gate metal layer. A transparent conductive layer 300 may be located within the gate metal layer. The transparent conductive layer 300 may also function as a second plate of the capacitor. The orthographic projections of the first plate 11 and the second plate on the substrate have a first overlapping region, with the first overlapping region located within the light-emitting region of the subpixel. In the structures shown in Figures 24b and 24c , both the first plate 11 within the first conductive layer and the transparent conductive layer 30, which functions as the second plate, are transparent. This allows the two plates of the capacitor to avoid occupying the display substrate's aperture ratio, thereby significantly improving the display substrate's aperture ratio and PPI.

[0126] In an exemplary embodiment, as shown in Figures 5a and 5b, the display substrate may further include a plurality of data signal lines 25 and a plurality of auxiliary data lines 45. The plurality of data signal lines 25 are electrically connected to the plurality of auxiliary data lines 45, respectively. The data signal lines 25 and the auxiliary data lines 45 are located in different conductive layers. In a direction perpendicular to the plane of the display substrate, the conductive layer where the data signal lines 25 and the auxiliary data lines 45 are located is located between the substrate and the transparent conductive layer 300, and the orthographic projections of the plurality of data signal lines 25 on the substrate at least partially overlap with the orthographic projections of the plurality of auxiliary data lines 45 on the substrate.

[0127] In the embodiment of the present disclosure, the data signal line and the auxiliary data line located in different conductive layers are electrically connected to reduce the RC of the data signal line and improve the charging uniformity of the display substrate.

[0128] Figures 5a and 5b are schematic diagrams of the structure of a display substrate of an exemplary embodiment of the present disclosure, illustrating the structure of a driving circuit layer in four sub-pixels (one pixel unit) of a bottom-emitting display substrate, and Figure 5c is a schematic diagram of an equivalent circuit of the pixel driving circuit in the four sub-pixels shown in Figures 5a and 5b. As shown in Figures 5a to 5c, in a direction parallel to the display substrate, at least one pixel unit may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 arranged in sequence along a first direction X, and each sub-pixel includes a pixel driving circuit and a storage capacitor. In the following description, sub-pixels refer to areas where pixel driving circuits are set. In an exemplary embodiment, at least one pixel unit may also include a first scanning signal line 41, two first power lines 21, four data signal lines 25, a compensation signal line 22, and four pixel driving circuits.

[0129] As shown in Figures 5a and 5b, the display substrate provided by the embodiment of the present disclosure may include: a substrate and a plurality of data signal lines 25 and a plurality of auxiliary data lines 45 arranged on the substrate, the plurality of data signal lines 25 are electrically connected to the plurality of auxiliary data lines 45, respectively, the data signal lines 25 and the auxiliary data lines 45 are located in different conductive layers, and the orthographic projections of the plurality of data signal lines 25 on the substrate at least partially overlap with the orthographic projections of the plurality of auxiliary data lines 45 on the substrate.

[0130] In an exemplary embodiment, as shown in FIG. 5 a and FIG. 5 b , the display substrate may include a gate metal layer disposed on a base, and at least a portion of the auxiliary data line 45 is located on the gate metal layer.

[0131] In an exemplary embodiment, as shown in Figures 5a, 7a-7b, and 10a-10b, the display substrate may further include a blocking metal layer. The gate metal layer is located on a side of the blocking metal layer away from the base, perpendicular to the plane of the display substrate. The plurality of data signal lines 25 may be located on the blocking metal layer. As shown in Figures 7a-7b and 10a-10b, the plurality of auxiliary signal lines 45 and the plurality of data signal lines 25 may extend along the second direction Y and be arranged along the first direction X.

[0132] In exemplary embodiments, as shown in Figures 5a, 7a-7b, and 10a-10b, the shielding metal layer may further include multiple first power lines 21, and the gate metal layer may further include multiple first power auxiliary lines 44. The multiple first power lines 21 are electrically connected to the multiple first power auxiliary lines 44, and the orthographic projections of the multiple first power lines 21 on the substrate at least partially overlap with the orthographic projections of the multiple first power auxiliary lines 44 on the substrate. In the disclosed embodiment, the multiple first power lines 21 are electrically connected to the multiple first power auxiliary lines 44 to form a double-layer power routing, ensuring reliable power signal transmission and reducing the resistance of the first power lines 21, thereby reducing the RC on the first power lines.

[0133] In an exemplary embodiment, as shown in Figures 5a, 7a to 7b, and 10a to 10b, the plurality of sub-pixels in the display substrate may form a plurality of pixel units arranged in an array, each pixel unit may include at least three sub-pixels (for example, each pixel unit may include four sub-pixels P1 to P4 arranged along a first direction X), the gate metal layer may further be provided with a plurality of first power connection lines 43, the same pixel unit includes two first power auxiliary lines 44, and the two ends of the first power connection line 43 located in the same pixel unit are respectively connected to the two first power auxiliary lines 44, on a plane parallel to the display substrate, the main portion of the first power auxiliary line 44 extends along the second direction Y, the main portion of the first power connection line 43 extends along the first direction X, and the first direction X intersects with the second direction Y.

[0134] In an exemplary embodiment, the first power connection line 43 located in the same pixel unit can be integrally formed with two first power auxiliary lines 44. In the disclosed embodiment, multiple first power lines 21 can extend along the second direction Y, and one first power line 21 can be electrically connected to multiple first power auxiliary lines 44 in a column of pixel units. Because the two first power auxiliary lines 44 located in the same pixel unit are electrically connected via the first power connection line 43, the first power lines 21 and the first power connection lines 43 can form a grid-like structure on the entire display substrate, reducing the load on the first power lines and ensuring that the first power voltage provided to multiple sub-pixels in the display substrate is as consistent as possible, which is beneficial for improving the uniformity of the panel, avoiding display defects on the display substrate, and ensuring the display effect of the display substrate.

[0135] In an exemplary embodiment, as shown in Figures 5a, 7a-7b, and 8a-8b, the display substrate may further include a semiconductor layer. The semiconductor layer is located on a side of the shielding metal layer away from the base, perpendicular to the plane of the display substrate. The semiconductor layer is provided with a plurality of compensation connection lines 35, and the shielding metal layer is also provided with a plurality of compensation signal lines 22. In a plane parallel to the display substrate, the compensation connection lines 35 are stripe-shaped structures extending along a first direction X, and the compensation signal lines 22 are stripe-shaped structures extending along a second direction Y. The first direction X intersects the second direction Y, and the compensation connection line 35 is electrically connected to at least one compensation signal line 22. As shown in Figures 7a and 7b, a pixel unit may include one compensation connection line 35, and the four sub-pixels in a pixel unit may be symmetrical with respect to the compensation signal line 22. Specifically, the first sub-pixel P1 and the fourth sub-pixel P4 in the same pixel unit may be symmetrical with respect to the compensation signal line 22, and the second sub-pixel P2 and the third sub-pixel P3 may be symmetrical with respect to the compensation signal line 22. In the embodiment of the present disclosure, the same compensation signal line 22 can be electrically connected to multiple compensation signal lines 22 located in the same column of pixel units. A compensation connection line 35 can be set in a pixel unit to transmit the signal of the compensation signal line 22 to the four sub-pixels in the pixel unit. Therefore, a network structure of compensation signal lines can be formed by multiple compensation signal lines 22 and multiple compensation connection lines 35, which reduces the load on the compensation signal line 22 and makes the compensation signals provided to multiple sub-pixels in the display substrate as consistent as possible, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0136] In exemplary embodiments, in the structures shown in Figures 5a, 6, and 13b, the display substrate may include a base and, in a direction perpendicular to the display substrate, a first conductive layer, a second conductive layer (blocking metal layer), a first insulating layer, a semiconductor layer, a second insulating layer, a third conductive layer (gate metal layer), a third insulating layer, a planarization layer, a fourth conductive layer, and a pixel definition layer, sequentially disposed on the base. The second conductive layer may serve as the blocking metal layer, and the third conductive layer may serve as the gate metal layer. In the disclosed embodiment, the data signal lines are disposed in the blocking metal layer, eliminating the source and drain metal layers, simplifying the process flow, and reducing the manufacturing cost of the display substrate.

[0137] In an exemplary embodiment, as shown in Figures 5b, 20a and 20b, the display substrate may further include a source-drain metal layer. In a direction perpendicular to the plane of the display substrate, the source-drain metal layer may be located on the side of the gate metal layer away from the substrate, and a plurality of data signal lines 25 may be located in the source-drain metal layer.

[0138] In an exemplary embodiment, as shown in Figures 5b, 16a, 16b, 18a, 18b, 20a and 20b, the display substrate may further include a second blocking metal layer. In a direction perpendicular to the plane of the display substrate, the second blocking metal layer may be located between the substrate and the gate metal layer. The plurality of auxiliary data lines 45 may include a plurality of first auxiliary data lines 451 and a plurality of second auxiliary data lines 452. The plurality of first auxiliary data lines 451 may be located in the second blocking metal layer, and the plurality of second auxiliary data lines 452 may be located in the gate metal layer. The orthographic projections of the plurality of first auxiliary data lines 451 and the plurality of second auxiliary data lines 452 on the substrate have an overlapping area with the orthographic projections of the corresponding plurality of data signal lines 25 on the substrate, and the plurality of first auxiliary data lines 451 and the plurality of second auxiliary data lines 452 are electrically connected to the corresponding plurality of data signal lines 25.

[0139] In exemplary embodiments, as shown in Figures 5b, 18a, 18b, 20a, and 20b, the source / drain metal layer further includes multiple first power lines 21, and the gate metal layer further includes multiple first auxiliary power lines 44. The multiple first power lines 21 are electrically connected to the multiple first auxiliary power lines 44, and the orthographic projections of the multiple first power lines 21 on the substrate at least partially overlap with the orthographic projections of the multiple first auxiliary power lines 44 on the substrate. In the disclosed embodiment, the multiple first power lines 21 are electrically connected to the multiple first auxiliary power lines 44 to form a double-layer power routing, ensuring reliable power signal transmission and reducing the resistance of the first power lines 21, thereby reducing the RC on the first power lines.

[0140] In an exemplary embodiment, as shown in Figures 5b and 16a to 20b, the multiple sub-pixels in the display substrate can form a plurality of pixel units arranged in an array, each pixel unit can include at least three sub-pixels (for example, each sub-pixel can include four sub-pixels arranged along the first direction X). The display substrate may further include a semiconductor layer. In a direction perpendicular to the plane of the display substrate, the semiconductor layer is located on a side of the second blocking metal layer away from the base, and the semiconductor layer is provided with a plurality of first power connection lines 43. The same pixel unit may include two first power lines, and the two ends of the first power connection line 43 located in the same pixel unit are electrically connected to the two first power lines 21, respectively. In a plane parallel to the display substrate, the main portion of the first power line 21 extends along the second direction Y, and the main portion of the first power connection line 43 extends along the first direction X, and the first direction X intersects with the second direction Y. In the embodiment of the present disclosure, multiple first power lines 21 can extend along the second direction Y, and one first power line 21 can be electrically connected to multiple first power auxiliary lines 44 in a column of pixel units. Since two first power lines 21 located in the same pixel unit are electrically connected through the first power connection line 43, the first power lines 21 and the first power connection lines 43 can form a grid structure on the display substrate as a whole, reducing the load on the first power line, so that the first power voltage provided to multiple sub-pixels in the display substrate is as consistent as possible, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0141] In an exemplary embodiment, as shown in Figures 5b and 16a to 20b, the second shielding metal layer may further include multiple compensation connection lines 35, and the source / drain metal layer may further include multiple compensation signal lines 22. In a plane parallel to the display substrate, the compensation connection lines 35 are stripe-shaped structures extending along a first direction X, and the compensation signal lines 22 are stripe-shaped structures extending along a second direction Y. The first direction X intersects the second direction Y, and the compensation connection line 35 is electrically connected to at least one compensation signal line 22. As shown in Figures 16a to 20b, a pixel unit may include one compensation connection line 35, and the four sub-pixels in a pixel unit may be symmetrical with respect to the compensation signal line 22. That is, the first sub-pixel P1 and the fourth sub-pixel P4 in the same pixel unit may be symmetrical with respect to the compensation signal line 22, and the second sub-pixel P2 and the third sub-pixel P3 may be symmetrical with respect to the compensation signal line 22. In the embodiment of the present disclosure, the same compensation signal line 22 can be electrically connected to multiple compensation signal lines 22 located in the same column of pixel units. A compensation connection line 35 can be set in a pixel unit to transmit the signal of the compensation signal line 22 to the four sub-pixels in the pixel unit. Therefore, a network structure of compensation signal lines can be formed by multiple compensation signal lines 22 and multiple compensation connection lines 35, which reduces the load on the compensation signal line 22 and makes the compensation signals provided to multiple sub-pixels in the display substrate as consistent as possible, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0142] In an exemplary embodiment, as shown in Figures 5b and 15, the display substrate may further include a first shielding metal layer. The first shielding metal layer may be located between the base and the second shielding metal layer in a direction perpendicular to the plane of the display substrate. The first shielding metal layer may be provided with a plurality of first scan signal lines 41, and the second shielding metal layer may be provided with a plurality of first scan signal auxiliary lines 410, each electrically connected to the plurality of first scan signal lines 41. The orthographic projections of the plurality of first scan signal lines 41 on the base at least partially overlap with the orthographic projections of the plurality of first scan signal auxiliary lines 410 on the base. In the disclosed embodiment, the plurality of first scan signal lines 41 are electrically connected to the plurality of first scan signal auxiliary lines 410, forming a double-layer power supply routing. This ensures the reliability of the first scan signal lines and reduces the resistance of the first scan signal lines 41, thereby reducing the RC on the first power supply lines.

[0143] In an exemplary embodiment, the orthographic projections of the plurality of first scan signal lines 41 on the substrate respectively cover the orthographic projections of the plurality of first scan signal auxiliary lines 410 on the substrate, thereby preventing damage to the first scan signal auxiliary lines 410 during a subsequent etching process. The first scan signal auxiliary lines 410 can protect the first scan signal lines 41.

[0144] In an exemplary embodiment, a thickness of the first blocking metal layer is greater than a thickness of the second blocking metal layer. That is, in a direction perpendicular to the plane where the display substrate is located, the size of the first scanning signal line 41 is larger than the size of the first scanning signal auxiliary line 410. On the one hand, the thickness of the first scanning signal line 41 is relatively thick, which can reduce the impedance of the first scanning signal line and reduce RC. On the other hand, the thickness of the second blocking metal layer is relatively small, which can prevent the semiconductor layer from being cut off due to the thick second blocking metal layer in the area where the semiconductor layer and the second blocking metal layer partially overlap. As shown in Figure 17b, the second blocking metal layer may include a blocking structure 23, and the positive projection of the blocking structure 23 on the substrate and the positive projection of the pattern in the semiconductor layer (such as the second plate 34 of the capacitor and the active layer 32 of the second transistor T2) on the substrate have an overlapping area. If the thickness of the blocking structure 23 is relatively thick, the second plate 34 and the active layer 32 of the second transistor T2 are easily disconnected at the edge portion overlapping with the blocking structure 23, resulting in a poor display substrate. Therefore, the thickness of the second blocking metal layer is relatively thin, which can prevent the semiconductor layer from being cut off in the area where the semiconductor layer and the second blocking metal layer partially overlap.

[0145] In an exemplary embodiment, in the structures shown in Figures 5b and 14 to 23b, in a direction perpendicular to the display substrate, the display substrate may include a base and a first conductive layer, a second conductive layer (first blocking metal layer), a third conductive layer (second blocking metal layer), a first insulating layer, a semiconductor layer, a second insulating layer, a fourth conductive layer (gate metal layer), a third insulating layer, a fifth conductive layer (source-drain metal layer), a fourth insulating layer, a flat layer, a sixth conductive layer and a pixel definition layer sequentially arranged on the base, wherein the second conductive layer can serve as the first blocking metal layer, the third conductive layer can serve as the second blocking metal layer, and the fourth conductive layer can serve as the gate metal layer.

[0146] In the embodiment of the present disclosure, in the structures shown in Figures 5b and 14 to 23b, the first conductive layer is provided with first plates of capacitors in multiple sub-pixels, and the semiconductor layer is provided with second plates of capacitors in multiple sub-pixels. The first scanning signal line 41 is provided in the blocking metal layer but not in the gate metal layer. On the one hand, the capacitance between the data signal line 25 in the source and drain metal layer and the gate metal layer can be reduced, thereby reducing RC. On the other hand, the thickness of the first insulating layer can be reduced, thereby increasing the capacitance value of the capacitor in the sub-pixel.

[0147] In an exemplary embodiment, as shown in Figures 5a to 5c, each pixel unit may include four sub-pixels arranged along a first direction X. Each sub-pixel may include a pixel driving circuit. The pixel driving circuit of each sub-pixel may include a first transistor T1, a second transistor T2, a third transistor T3, and a capacitor C. In a second direction Y, the third transistor T3, the first transistor T1, the capacitor C, and the second transistor T2 are arranged in sequence along the second direction Y. In the same pixel unit, the second sub-pixel P2 and the third sub-pixel P3 may be symmetrically arranged with respect to the compensation signal line 22, and the first sub-pixel P1 and the fourth sub-pixel P4 may be symmetrically arranged with respect to the compensation signal line 22. In the embodiment of the present disclosure, the display area of ​​the display substrate may include a plurality of sub-pixels arranged in an array, at least three sub-pixels may constitute a pixel unit, and the plurality of pixel units and the plurality of sub-pixels may be arranged in an array, and the plurality of signal lines 25 are respectively electrically connected to the plurality of columns of sub-pixels, and are configured to provide data signals to the sub-pixels connected thereto; the compensation signal line 22 may be electrically connected to the plurality of columns of pixel units, and is configured to provide compensation signals to the plurality of sub-pixels in the pixel units electrically connected thereto; the first power line 21 may be electrically connected to a column of pixel units, and is configured to provide a first power signal to the plurality of sub-pixels in the pixel units electrically connected thereto; the first scanning signal line 41 may be electrically connected to a row of sub-pixels, and is configured to provide a scanning signal to the sub-pixels connected thereto.

[0148] An embodiment of the present disclosure also provides a method for preparing a display substrate, which may include: forming a plurality of sub-pixels and a plurality of transparent conductive layers 300 on one side of a substrate, wherein at least a portion of the sub-pixels include at least a second transistor T2 and a third transistor T3, and the second electrode of the second transistor T2 and the second electrode of the third transistor T3 located in the same sub-pixel are electrically connected via at least one transparent conductive layer 300.

[0149] In an exemplary embodiment, the preparation method may further include: forming a plurality of data signal lines 25 and a plurality of auxiliary data lines 45 on one side of the substrate, wherein the plurality of data signal lines 25 are electrically connected to the plurality of auxiliary data lines 45, respectively, and the data signal lines 25 and the auxiliary data lines 45 are located in different conductive layers. In a direction perpendicular to the plane where the display substrate is located, the conductive layer where the data signal lines 25 and the auxiliary data lines 45 are located is located between the substrate and the transparent conductive layer 300, and the orthographic projections of the plurality of data signal lines 25 on the substrate at least partially overlap with the orthographic projections of the plurality of auxiliary data lines 45 on the substrate.

[0150] In an exemplary embodiment, forming a plurality of auxiliary data lines 45 on a substrate may include forming a gate metal layer on one side of the substrate, wherein at least a portion of the auxiliary data lines 45 is located in the gate metal layer.

[0151] In an exemplary embodiment, as shown in Figures 10c and 10d, Figure 10c is a schematic diagram of the cross-sectional structure at the A1-A1 position in Figure 10a, and Figure 10d is a schematic diagram of the cross-sectional structure at the A2-A2 position in Figure 10a. Before forming the gate metal layer on one side of the substrate, it may also include: forming a blocking metal layer SHL on the side of the substrate 101 close to the gate metal layer GT, in a direction perpendicular to the plane where the display substrate is located, the gate metal layer GT is located on the side of the blocking metal layer SHL away from the substrate 101, and a plurality of data signal lines 25 are located on the blocking metal layer SHL.

[0152] In exemplary embodiments, as shown in Figures 5a, 7a-7b, and 10a-10c, the shielding metal layer may further include multiple first power lines 21, and the gate metal layer may further include multiple first power auxiliary lines 44. The multiple first power lines 21 are electrically connected to the multiple first power auxiliary lines 44, and the orthographic projections of the multiple first power lines 21 on the substrate at least partially overlap with the orthographic projections of the multiple first power auxiliary lines 44 on the substrate. In the disclosed embodiment, the multiple first power lines 21 are electrically connected to the multiple first power auxiliary lines 44 to form a double-layer power routing, ensuring reliable power signal transmission and reducing the resistance of the first power lines 21, thereby reducing the RC on the first power lines.

[0153] In an exemplary embodiment, as shown in Figures 5a, 7a to 7b, and 10a to 10b, the display substrate may further include a plurality of pixel units arranged in an array on the substrate, each pixel unit may include four sub-pixels P1 to P4 arranged along the first direction X, the gate metal layer may further be provided with a plurality of first power connection lines 43, the same pixel unit includes two first power auxiliary lines 44, and the two ends of the first power connection line 43 located in the same pixel unit are respectively connected to the two first power auxiliary lines 44. On a plane parallel to the display substrate, the main portion of the first power auxiliary line 44 extends along the second direction Y, and the main portion of the first power connection line 43 extends along the first direction X, and the first direction X intersects with the second direction Y.

[0154] In an exemplary embodiment, after forming the blocking metal layer SHL on one side of the substrate 101 and before forming the gate metal layer GT on one side of the substrate 101, the method may further include: forming a semiconductor layer ACT on a side of the blocking metal layer SHL away from the substrate 101, the semiconductor layer ACT is provided with a plurality of compensation connection lines 35, and the blocking metal layer SHL is further provided with a plurality of compensation signal lines 22. On a plane parallel to the display substrate, the compensation connection lines 35 may be a bar structure extending along a first direction X, and the compensation signal lines 22 may be a bar structure extending along a second direction Y. The first direction X intersects with the second direction Y, and the compensation connection lines 35 are electrically connected to at least one compensation signal line 22.

[0155] In an exemplary embodiment, as shown in FIG. 10 c , forming a gate metal layer GT on one side of the substrate 101 may include:

[0156] forming a second insulating film on a side of the semiconductor layer ACT away from the substrate 101;

[0157] Patterning the second insulating film using a patterning process to form a second insulating layer c2 including a second insulating layer pattern, wherein the second insulating layer c2 pattern may include a plurality of first connection vias K1, and the plurality of first connection vias K1 expose the surface of the semiconductor layer ACT;

[0158] Conducting the semiconductor layer exposed by the first connection vias K1 to form a plurality of first conductive areas d1, wherein the orthographic projections of the plurality of first conductive areas d1 on the substrate 101 respectively cover the orthographic projections of the plurality of first connection vias K1 on the substrate 101;

[0159] A gate metal layer GT is formed on a side of the second insulating layer c2 away from the substrate 101 .

[0160] In an exemplary embodiment, as shown in FIG. 10 d , forming the semiconductor layer ACT on a side of the shielding metal layer SHL away from the substrate 101 may include:

[0161] forming a first insulating layer c1 on a side of the shielding metal layer SHL away from the substrate 101;

[0162] forming a semiconductor layer ACT on a side of the first insulating layer c1 away from the substrate 101;

[0163] The process of patterning the second insulating film to form the second insulating layer c2 including the second insulating layer pattern by using a patterning process may further include: patterning the first insulating film to form a plurality of second connecting vias K2 exposing the surface of the shielding metal layer SHL and the surface of the semiconductor layer ACT;

[0164] The process of conducting a conductor treatment on the semiconductor layer exposed by the first connection via K1 to form a plurality of first conductorized areas may also include conducting a conductor treatment on the semiconductor layer ACT exposed by the second connection via K2 to form a plurality of second conductorized areas d2, wherein the orthographic projections of the plurality of second conductorized areas d2 on the substrate 101 respectively cover the orthographic projections of the semiconductor layer ACT exposed in the plurality of second connection vias K2 on the substrate 101.

[0165] In an exemplary embodiment, after forming the gate metal layer GT on the side of the second insulating layer c2 away from the substrate, the following steps may be further included:

[0166] Removing the second insulating film c2 outside the area covered by the gate metal layer GT to expose the area to be conductive in the semiconductor layer ACT;

[0167] Conductive processing is performed on the area to be conductive in the semiconductor layer to form a third conductive area. The orthographic projections of the first conductive areas d1 and the second conductive areas d2 on the substrate at least partially overlap with the orthographic projection of the third conductive area on the substrate.

[0168] In the embodiment of the present disclosure, the third conductive region may be the semiconductor layer ACT not covered by the gate metal layer GT. The orthographic projections of the plurality of first conductive regions d1 and the second conductive regions d2 on the substrate at least partially overlap with the orthographic projections of the third conductive region on the substrate. This allows the first conductive regions d1 located in the plurality of first connection vias K1 and the second conductive regions d2 located in the plurality of second connection vias K2 to be electrically connected to the third conductive region (i.e., the first conductive regions d1 and the second conductive regions d2 can overlap with the third conductive region), thereby avoiding the presence of unconducted regions between the first conductive regions d1, the second conductive regions d2, and the third conductive region.

[0169] In the disclosed embodiment, the orthographic projections of the plurality of second conductive areas d2 on the substrate 101 overlap the orthographic projections of the semiconductor layer ACT exposed in the plurality of second connection vias K2 on the substrate 101, thereby electrically connecting the plurality of second conductive areas d2 with the third conductive area and preventing the presence of unconducted areas between the first conductive area d1, the second conductive area d2, and the third conductive area. The orthographic projections of the plurality of first conductive areas d1 on the substrate 101 overlap the orthographic projections of the plurality of first connection vias K1 on the substrate 101, thereby electrically connecting the first conductive area d1 located in the plurality of first connection vias K1 with the third conductive area (i.e., overlapping the first conductive area d1 with the third conductive area) and preventing the presence of unconducted areas between the first conductive area d1 and the third conductive area.

[0170] In an exemplary embodiment, as shown in FIG10c and FIG10d, the orthographic projection of the second conductive region d2 on the substrate at least partially overlaps with the orthographic projection of at least a portion of the gate metal layer GT on the substrate, so that the second conductive region d2 can be electrically connected to the gate metal layer GT, thereby improving the reliability of the electrical connection between the second conductive region d2 and the gate metal layer GT pattern.

[0171] In an exemplary embodiment, as shown in Figure 23c, Figure 23c is a schematic diagram of the cross-sectional structure at the A3-A3 position in Figure 23a. After the gate metal layer GT is formed on one side of the substrate 101, it can also include: forming a source-drain metal layer SD on the side of the gate metal layer GT away from the substrate 101, and a plurality of data signal lines 25 are located in the source-drain metal layer SD.

[0172] In an exemplary embodiment, before forming the gate metal layer GT on one side of the substrate 101, the following may also be included: forming a second blocking metal layer SHL2 on the side of the substrate 101 close to the gate metal layer GT, the plurality of auxiliary data lines 45 include a plurality of first auxiliary data lines 451 and a plurality of second auxiliary data lines 452, the plurality of first auxiliary data lines 451 are located in the second blocking metal layer SHL2, the plurality of second auxiliary data lines 452 are located in the gate metal layer GT, the orthographic projections of the plurality of first auxiliary data lines 451 and the plurality of second auxiliary data lines 452 on the substrate 101 have an overlapping area with the orthographic projections of the corresponding plurality of data signal lines 25 on the substrate 101, and the plurality of first auxiliary data lines 451 and the plurality of second auxiliary data lines 452 are electrically connected to the corresponding plurality of data signal lines 25.

[0173] In exemplary embodiments, as shown in Figures 5b, 18a, 18b, 20a, 20b, and 23c, the source / drain metal layer further includes multiple first power lines 21, and the gate metal layer further includes multiple first auxiliary power lines 44. The multiple first power lines 21 are electrically connected to the multiple first auxiliary power lines 44, and the orthographic projections of the multiple first power lines 21 on the substrate at least partially overlap with the orthographic projections of the multiple first auxiliary power lines 44 on the substrate. In the disclosed embodiment, the multiple first power lines 21 are electrically connected to the multiple first auxiliary power lines 44 to form a double-layer power routing, ensuring reliable power signal transmission and reducing the resistance of the first power lines 21, thereby reducing the RC on the first power lines.

[0174] In an exemplary embodiment, as shown in Figures 5b, 16a to 20b, and 23c, the display substrate may include a plurality of pixel units arranged in an array on a substrate, each pixel unit may include four sub-pixels arranged along a first direction X, and the display substrate may further include a semiconductor layer. In a direction perpendicular to the plane of the display substrate, the semiconductor layer is located on a side of the second blocking metal layer away from the substrate, and the semiconductor layer is provided with a plurality of first power connection lines 43. The same pixel unit may include two first power lines, and both ends of the first power connection line 43 located in the same pixel unit are electrically connected to the two first power lines 21, respectively. In a plane parallel to the display substrate, the main portion of the first power line 21 extends along the second direction Y, and the main portion of the first power connection line 43 extends along the first direction X, and the first direction X intersects with the second direction Y.

[0175] In an exemplary embodiment, as shown in Figures 5b, 16a to 20b, and 23c, the second blocking metal layer may further be provided with a plurality of compensation connection lines 35, and the source-drain metal layer may further be provided with a plurality of compensation signal lines 22. On a plane parallel to the display substrate, the compensation connection line 35 is a strip structure extending along the first direction X, and the compensation signal line 22 is a strip structure extending along the second direction Y. The first direction X intersects with the second direction Y, and the compensation connection line 35 is electrically connected to at least one compensation signal line 22.

[0176] In an exemplary embodiment, before forming the second blocking metal layer SHL2 on the side of the substrate 101 close to the gate metal layer GT, the method may further include: forming a first blocking metal layer SHL1 on the side of the substrate 101 close to the second blocking metal layer SHL2, in a direction perpendicular to the plane where the display substrate is located, the first blocking metal layer SHL1 is located between the substrate 101 and the second blocking metal layer SHL2, the first blocking metal layer SHL1 is provided with a plurality of first scanning signal lines 41, the second blocking metal layer SHL2 is provided with a plurality of first scanning signal auxiliary lines 410 respectively electrically connected to the plurality of first scanning signal lines 41, and the orthographic projections of the plurality of first scanning signal lines 41 on the substrate 101 at least partially overlap with the orthographic projections of the plurality of first scanning signal auxiliary lines 410 on the substrate 101.

[0177] In the embodiment of the present disclosure, as shown in FIG23c, c1 to c5 are the first to fifth insulating layers, ITO1 is the first conductive layer, ITO2 is the sixth conductive layer, the first conductive layer ITO1 and the sixth conductive layer ITO2 may be conductive glass, and SD is the source / drain metal layer. For a schematic planar structure diagram of the first conductive layer ITO1, reference may be made to FIG14, for a schematic planar structure diagram of the first shielding layer SHL1, reference may be made to FIG15, for a schematic planar structure diagram of the second shielding layer SHL2, reference may be made to FIG16b, for a schematic planar structure diagram of the semiconductor layer ACT, reference may be made to FIG17b, for a schematic planar structure diagram of the gate metal layer GT, reference may be made to FIG18b, for a schematic planar structure diagram of the second insulating layer c2 and the third insulating layer c3, reference may be made to FIG19, for a schematic planar structure diagram of the source / drain metal layer SD, reference may be made to FIG20b, for a schematic planar structure diagram of the fourth insulating layer c4 and the planar layer c5, reference may be made to FIG21, for a schematic planar structure diagram of the sixth conductive layer ITO2, reference may be made to FIG22b, and for a schematic planar structure diagram of the pixel definition layer PDL, reference may be made to FIG23b.

[0178] In the embodiment of the present disclosure, as shown in Figures 23c and 21, the orthographic projections of the vias on the fourth insulating layer c4 and the flat layer c5 on the substrate overlap. The vias on the fourth insulating layer c4 and the flat layer c5 can be formed by a single patterning process without the need for two preparation processes, thereby simplifying the preparation process and reducing the preparation cost of the display substrate.

[0179] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0180] In an exemplary embodiment, taking four sub-pixels (a first sub-pixel P1 , a second sub-pixel P2 , a third sub-pixel P3 , and a fourth sub-pixel P4 ) as an example, the preparation process of the driving circuit layer may include the following operations.

[0181] (11) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first conductive film on a substrate, patterning the first conductive film through a patterning process, and forming a first conductive layer pattern on the substrate, wherein the first conductive layer pattern includes at least a first electrode 11 formed in each sub-pixel, as shown in FIG6 . In an exemplary embodiment, the first conductive layer may be referred to as a first transparent (ITO1) layer.

[0182] In an exemplary embodiment, the first electrode plate 11 in each sub-pixel is configured as a transparent electrode plate forming a storage capacitor. The first electrode plate 11 may be rectangular, and edges of the rectangle may be fold lines.

[0183] (12) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film through a patterning process, and forming a second conductive layer pattern on the first conductive layer, wherein the second conductive layer pattern includes at least a first power line 21, a compensation signal line 22, and a shielding structure 23 and a data signal line 25 formed in each sub-pixel, as shown in Figures 7a and 7b, where Figure 7b is a planar schematic diagram of the second conductive layer in Figure 7a. In an exemplary embodiment, the second conductive layer may be referred to as a shielding metal (SHL) layer.

[0184] In an exemplary embodiment, the two first power lines 21 may be strip-shaped structures extending along the second direction Y and may be sequentially arranged along the first direction X. In a pixel unit, the first electrode 11 in a plurality of sub-pixels may be located between the two first power connection lines 21 in the first direction X. The two first power lines 21 are configured to be electrically connected to subsequently formed first power connection lines, respectively, and respectively provide power supply voltages to the second transistors T2 in the first to fourth sub-pixels P1 to P4.

[0185] In an exemplary embodiment, the compensation signal line 22 may be a strip-shaped structure extending along the second direction Y. The compensation signal line 22 is located between the two first power connection lines 21. In the first direction X, the two first power connection lines 21 may be symmetrical with respect to the compensation signal line 22, and the second subpixel P2 and the third subpixel P3 may be symmetrical with respect to the compensation signal line 22. The compensation signal line 22 is configured to be connected to subsequently formed compensation signal lines, respectively, and to provide a compensation voltage to the third transistors T3 of the first to fourth subpixels P1 to P3.

[0186] In an exemplary embodiment, the shielding structure 23 may be provided in each sub-pixel, the orthographic projection of the shielding structure 23 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate, and the shielding structure 23 is electrically connected to the first electrode plate 11 .

[0187] In an exemplary embodiment, a data signal line 25 is provided in each sub-pixel, and a main portion of the data signal line 25 extends along the second direction Y. The data signal line 25 can be connected to the first region 31 - 1 of the active layer of the first transistor formed subsequently through a via hole to write the data signal into the first transistor T1.

[0188] (13) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process to form a first insulating layer covering the second conductive layer, and a semiconductor layer pattern disposed on the first insulating layer, wherein the semiconductor layer pattern includes at least an active layer 31 of a first transistor T1, an active layer 32 of a second transistor T2, an active layer 33 of a third transistor T3, a second electrode 34, and a compensation connection line 35 formed in each sub-pixel, as shown in FIG8a and FIG8b, where FIG8b is a planar schematic diagram of the semiconductor layer in FIG8a.

[0189] In an exemplary embodiment, the orthographic projection of the second electrode plate 34 in each sub-pixel on the substrate overlaps with the orthographic projection of the first electrode plate 11 on the substrate, and the second electrode plate 34 is configured to form another transparent electrode plate of the storage capacitor, and the first electrode plate 11 and the second electrode plate 34 form a transparent storage capacitor.

[0190] In an exemplary embodiment, the second electrode plate 34 may be rectangular in shape, and edges of the rectangle may be fold lines.

[0191] In an exemplary embodiment, in each sub-pixel, the shape of the second electrode plate 34 may be similar to the shape of the first electrode plate 11 in the sub-pixel, and the orthographic projection of the second electrode plate 34 on the substrate may cover the orthographic projection of the first electrode plate 11 on the substrate.

[0192] In an exemplary embodiment, the active layer 31 of the first transistor T1 , the active layer 32 of the second transistor T2 , and the active layer 33 of the third transistor T3 each include a channel region and first and second regions located at both sides of the channel region.

[0193] In an exemplary embodiment, the active layer 31 of the first transistor T1 may be L-shaped. In the second direction Y, the active layer 31 of the first transistor T1 may be located on one side of the second electrode plate 34. In the first direction X, the first region 31-1 of the active layer 31 of the first transistor T1 is located on a side of the channel region away from the second electrode plate 34, and the second region 31-2 of the active layer 31 of the first transistor T1 is located on a side of the channel region closer to the second electrode plate 34. In each sub-pixel, the orthographic projection of the first region 31-1 of the active layer 31 of the first transistor T1 on the substrate at least partially overlaps with the orthographic projection of the data signal line 25 on the substrate.

[0194] In an exemplary embodiment, the second region 31 - 2 of the active layer 31 of the first transistor T1 may be connected to the second electrode plate 34 , and the active layer 31 and the second electrode plate 34 of the first transistor T1 are an integral structure connected to each other.

[0195] In an exemplary embodiment, the first region 31-1 of the active layer 31 of the first transistor T1 is a stripe-shaped structure extending along the first direction X. The stripe-shaped structure extends from the second region 31-2 of the active layer 31 of the first transistor T1 toward the adjacent subpixel. The stripe-shaped structure in the first subpixel P1 extends toward the second subpixel P2, and the stripe-shaped structure in the third subpixel P3 extends toward the fourth subpixel P4. The stripe-shaped structure in the second subpixel P2 extends toward the first subpixel P1, and the stripe-shaped structure in the fourth subpixel P3 extends toward the third subpixel P3. Because the second region 31-2 of the active layer 31 of the first transistor T1 is electrically connected to the gate electrode of the second transistor T2 via the subsequently formed second electrode of the first transistor T1, the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the second plate of the storage capacitor are interconnected.

[0196] In an exemplary embodiment, the active layer 32 of the second transistor T2 may be shaped like an "I." In the second direction Y, the second active layer 32 may be located on a side of the second electrode plate 34 away from the active layer 31 of the first transistor T1. The orthographic projection of the active layer 32 of the second transistor T2 on the substrate is spaced apart from the orthographic projection of the second electrode plate 34 on the substrate, i.e., there is no overlap between the second active layer 32 and the second electrode plate 34. This facilitates designing the channel width-to-length ratio of the second transistor according to relevant requirements. The first region 32-1 of the active layer 32 of the second transistor T2 is located on a side of the channel region away from the second electrode plate 34. The orthographic projection of the first region 32-1 of the active layer 32 of the second transistor T2 on the side closer to the channel region on the substrate overlaps with the orthographic projection of the shielding structure 23 on the substrate. The second region 32-2 of the active layer 32 of the second transistor T2 is located on the side of the channel region near the second electrode 34. The orthographic projection of the second region 32-2 of the active layer 32 of the second transistor T2 on the substrate overlaps with the orthographic projection of the shielding structure 23 on the substrate. Thus, the shielding structure 23 shields the channel region of the second active layer 32, preventing light from affecting the channel, reducing leakage current, and thus preventing the influence of light on transistor characteristics.

[0197] In an exemplary embodiment, the active layer 33 of the third transistor T3 may have an L-shaped zigzag structure. In the second direction Y, the active layer 33 of the third transistor T3 may be located on a side of the active layer 31 of the first transistor T1 away from the second electrode plate 34. The orthographic projection of the active layer 33 of the third transistor T3 on the substrate is spaced apart from the orthographic projection of the second electrode plate 34 on the substrate, i.e., there is no overlap between the third active layer 33 and the second electrode plate 42. This facilitates designing the channel width-to-length ratio of the third transistor according to relevant requirements. The first region 33-1 of the active layer 33 of the third transistor T3 is located on a side of the channel region away from the second electrode plate 34. The first region 33-1 of the active layer 33 of the third transistor T3 and the compensation connection line 35 may be an integrally connected structure.

[0198] In an exemplary embodiment, the compensation connection line 35 may be a strip-shaped structure extending along a first direction X. In a second direction Y, the compensation connection line 35 is located on a side of the active layer of the third transistor T3 that is away from the second electrode plate 34. The orthographic projection of the compensation connection line 35 on the substrate overlaps with the orthographic projection of the compensation signal line 22 on the substrate. The compensation connection line 35 may be connected to the first region 33-1 of the active layer 33 of the third transistor T3 and may be integrally formed with the active layer 33 of the third transistor T3.

[0199] In exemplary embodiments, the semiconductor layer may be formed of a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, an oxide containing indium, gallium, and zinc, etc. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0200] (14) Forming a second insulating layer pattern. In an exemplary embodiment, forming the second insulating layer pattern may include: depositing a second insulating film on the substrate on which the aforementioned pattern is formed, patterning the second insulating film using a patterning process to form a second insulating layer covering the semiconductor layer, wherein a plurality of vias are provided on the second insulating layer, and the plurality of vias include at least: a first via V1, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, and a ninth via V9, as shown in FIG. 9 .

[0201] In an exemplary embodiment, a first via hole V1 may be provided in each sub-pixel. The orthographic projection of the first via hole V1 on the substrate at least partially overlaps with the orthographic projection of the first region 31-1 of the active layer 31 of the first transistor T1 on the substrate, and at least partially overlaps with the orthographic projection of the data signal line 25 on the substrate. The second insulating layer and the first insulating layer within the first via hole V1 are etched away, simultaneously exposing the surface of the first region 31-1 of the active layer 31 of the first transistor T1 and the surface of the data signal line 25. The first via hole V1 is a transfer via hole, which consists of two half holes: one half hole is formed on the first region 31-1 of the active layer 31 of the first transistor T1, and the other half hole is formed on the data signal line 25. Such a transfer via hole, consisting of the two half holes, simultaneously exposes the surface of the first region 31-1 of the active layer 31 of the first transistor T1 and the surface of the data signal line 25. In an exemplary embodiment, the first via hole V1 is configured to connect the first electrode of the active layer 31 of the first transistor T1 formed subsequently to the data signal line 25 and the active layer 31 of the first transistor T1 through the via hole.

[0202] In an exemplary embodiment, a third via hole V3 may be provided in each sub-pixel. The orthographic projection of the third via hole V3 on the substrate is located within the orthographic projection of the first region 32-1 of the active layer 32 of the second transistor T2. The second insulating layer within the third via hole V3 is etched away, exposing the surface of the first region 32-1 of the active layer 32 of the second transistor T2. In an exemplary embodiment, the third via hole V3 is configured to connect a subsequently formed first power connection line to the active layer 32 of the second transistor T2 through the via hole.

[0203] In an exemplary embodiment, a fourth via hole V4 may be provided in each sub-pixel. The orthographic projection of the fourth via hole V4 on the substrate at least partially overlaps with the orthographic projection of the second region 32-2 of the active layer 32 of the second transistor T2 on the substrate, and at least partially overlaps with the orthographic projection of the blocking structure 23 on the substrate. The second insulating layer and the first insulating layer within the fourth via hole V4 are etched away, exposing the surface of the second region 32-2 of the active layer 32 of the second transistor T2 and the surface of the blocking structure 23. In an exemplary embodiment, the fourth via hole V4 is configured to connect the second electrode of the subsequently formed second transistor T2 to both the blocking structure 23 and the active layer 32 of the second transistor T2 through the via hole.

[0204] In an exemplary embodiment, a fifth via hole V5 may be provided between the second subpixel P2 and the third subpixel P3. The orthographic projection of the fifth via hole V5 on the substrate at least partially overlaps with the orthographic projection of the compensation connection line 35 on the substrate, and at least partially overlaps with the orthographic projection of the compensation signal line 22 on the substrate. The second insulating layer and the first insulating layer within the fifth via hole V5 are etched away, exposing the surfaces of the compensation connection line 35 and the compensation signal line 22. In an exemplary embodiment, the fifth via hole V5 is configured such that the first electrode of a subsequently formed third transistor T3 is connected to both the compensation signal line 22 and the compensation connection line 35 through the via hole.

[0205] In an exemplary embodiment, a sixth via hole V6 may be provided in each sub-pixel. The orthographic projection of the sixth via hole V6 on the substrate is located within the orthographic projection of the second region 33-2 of the active layer 33 of the third transistor T3 on the substrate. The second insulating layer within the sixth via hole V6 is etched away, exposing the surface of the second region 33-2 of the active layer 33 of the third transistor T3. In an exemplary embodiment, the sixth via hole V6 is configured to connect the second electrode of the subsequently formed third transistor T3 to the active layer 33 of the third transistor T3 through the via hole.

[0206] In an exemplary embodiment, the seventh via hole V7 may be provided in the first subpixel P1 and the fourth subpixel P4. The orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first power line 21 on the substrate. The second insulating layer within the seventh via hole V7 is etched away, exposing the surface of the first power line 21. In an exemplary embodiment, the seventh via hole V7 is configured to connect a subsequently formed first auxiliary power line to the first power line 21 through the via hole.

[0207] In an exemplary embodiment, an eighth via hole V8 may be provided in each sub-pixel, with the orthographic projection of the eighth via hole V8 on the substrate located within the range of the orthographic projection of the data signal line 25 on the substrate. The second insulating layer and the first insulating layer within the eighth via hole V8 are etched away, exposing the surface of the data signal line 25. In an exemplary embodiment, the eighth via hole V8 is configured to connect a subsequently formed auxiliary data line to the data signal line 25 through the via hole. In an exemplary embodiment, a plurality of eighth via holes V8 may be included, and the plurality of eighth via holes V8 may be arranged sequentially along the second direction Y to increase the reliability of the connection between the data signal line 25 and the auxiliary data line.

[0208] In an exemplary embodiment, a ninth via hole V9 may be provided in each sub-pixel, with the orthographic projection of the ninth via hole V9 on the substrate being within the range of the orthographic projection of the second electrode plate 34 on the substrate. The second insulating layer within the ninth via hole V9 is etched away, exposing the surface of the second electrode plate 25. In an exemplary embodiment, the ninth via hole V9 is configured to connect the gate electrode of a subsequently formed second transistor T2 to the second electrode plate 34 through the via hole.

[0209] In an exemplary embodiment, the plurality of first connection vias K1 may include a third via V3, a sixth via V6, and a ninth via V9, and the plurality of second connection vias K2 may include a first via V1, a fourth via V4, and a fifth via V5.

[0210] In an exemplary embodiment, this process also includes a conductive treatment. After forming the second insulating layer pattern, the conductive treatment is performed using the second insulating layer as a shield. The semiconductor layer in areas shielded by the second insulating layer is not conductively treated. The semiconductor layer in the plurality of vias not shielded by the second insulating layer is treated to form a conductive layer. The first conductive area d1 and the second conductive area d2 are conductively treated during this process.

[0211] (15) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film through a patterning process, and forming a third conductive layer pattern disposed on the second insulating layer, wherein the third conductive layer pattern includes at least a first scan signal line 41, a second gate electrode 42, a first power connection line 43, a first power auxiliary line 44, an auxiliary data line 45, a second transfer connection electrode 47, a third transfer connection electrode 48, and a fourth transfer connection electrode 411, as shown in FIG10a and FIG10b, FIG10b is a planar schematic diagram of the third conductive layer in FIG10a. In an exemplary embodiment, the third conductive layer may be referred to as a gate metal (GATE) layer.

[0212] In an exemplary embodiment, the first scan signal line 41 is a strip-shaped structure with its main portion extending along a first direction X. In the second direction Y, the first scan signal line 41 is located on a side of the second electrode 34 away from the active layer of the second transistor T2. The first scan signal line 41 spans the first through fourth subpixels P1 through P4. A first gate electrode 41-1 and a third gate electrode 41-3 are provided on the first scan signal line 41 of each subpixel. The first gate electrode 41-1 serves as the gate electrode of the first transistor T1, and its orthographic projection on the substrate overlaps with the orthographic projection of the active layer 31 of the first transistor T1. The third gate electrode 41-3 serves as the gate electrode of the third transistor T31, and its orthographic projection on the substrate overlaps with the orthographic projection of the active layer 33 of the third transistor T3. In an exemplary embodiment, the first gate electrode 41-1 and the third gate electrode 41-3 may be located on both sides of the main portion of the first scan signal line 41 in the second direction Y, and the third gate electrode 41-3 is located on a side of the main portion of the first scan signal line 41 away from the second electrode plate 34. In an exemplary embodiment, the first scan signal line 41 is provided to be shared by the third transistor T2 and the first transistor T1, which can save space.

[0213] In an exemplary embodiment, a second gate electrode 42 is formed within each subpixel, serving as the gate electrode of the second transistor T2. Within each subpixel, the orthographic projection of the second gate electrode 42 on the substrate overlaps with the orthographic projection of the active layer 32 of the second transistor T2 on the substrate, and also overlaps with the second electrode plate 34. The second gate electrode 42 is a strip-shaped structure extending along the first direction X. In the second direction Y, the second gate electrode 42 is located on the side of the second electrode plate 34 away from the first scan signal line 41. The second gate electrode 42 can be connected to the second electrode plate 34 via a ninth via V9, such that the second gate electrode 42 and the second electrode plate 34 have the same potential.

[0214] In an exemplary embodiment, the first power connection line 43 may be a strip-shaped structure extending along the first direction X. The first power connection line 43 may span the first to fourth subpixels P1 to P4 and be integrally formed with the first auxiliary power line 44. In the second direction Y, the first power connection line 43 may be located on a side of the second gate electrode 42 away from the second electrode plate 34. The orthographic projection of the first power connection line 43 on the substrate at least partially overlaps with the active layer 32 of the second transistor T2. The first power connection line 43 may be electrically connected to the active layer 32 of the second transistor T2 via a third via V3, providing a first power signal to the second transistor T2. In an exemplary embodiment, the first power connection line 43 may also serve as the first electrode of the second transistor T2.

[0215] In an exemplary embodiment, the first auxiliary power line 44 is formed within the first subpixel P1 and the fourth subpixel P4 and has a strip-shaped structure extending along the second direction Y. Within the first subpixel P1, the first auxiliary power line 44 is located on the side of the second electrode plate 34 away from the second subpixel P2 in the first direction X. Within the fourth subpixel P4, the first auxiliary power line 44 is located on the side of the second electrode plate 34 away from the third subpixel P3 in the first direction X. The first auxiliary power line 44 is connected to the first power line 21 through the seventh via V7, forming a double-layer routing pattern. This ensures reliable power signal transmission and reduces the resistance of the first power line 21.

[0216] In an exemplary embodiment, an auxiliary data line 45 is formed within each subpixel and has a strip-shaped structure extending along the second direction Y. In the first and third subpixels P1 and P3, the auxiliary data line 45 is located on one side of the second plate 34 in the first direction X. In the second and fourth subpixels P2 and P4, the auxiliary data line 45 is located on the side of the second plate 34 opposite the first direction X. The auxiliary data line 45 is configured to connect to the data signal line 25, forming a double-layer routing, ensuring reliable data signal transmission and reducing resistance of the data signal line.

[0217] In an exemplary embodiment, main portions of the first power auxiliary line 44 and the auxiliary data line 45 may be disposed in parallel.

[0218] In an exemplary embodiment, a second via-connecting electrode 47 is formed in each sub-pixel. The orthographic projection of the second via-connecting electrode 47 on the substrate at least partially overlaps with the orthographic projection of the second region 32-2 of the active layer 32 of the second transistor T2 on the substrate, and at least partially overlaps with the orthographic projection of the shielding structure 23 on the substrate. The second via-connecting electrode 47 is configured to connect to the second region 32-2 of the active layer 32 of the second transistor T2 and the shielding structure 23 through a second via hole V4. In an exemplary embodiment, the second via-connecting electrode 47 may serve as the second electrode of the second transistor T2.

[0219] In an exemplary embodiment, a third via-connecting electrode 48 is formed in each sub-pixel. An orthographic projection of the third via-connecting electrode 48 on the substrate at least partially overlaps an orthographic projection of the second region 33-2 of the active layer 33 of the third transistor T3 on the substrate. The third via-connecting electrode 48 is configured to be connected to the second region 33-2 of the active layer 33 of the third transistor T3 through a sixth via hole V6. In an exemplary embodiment, the third via-connecting electrode 48 may serve as a second electrode of the third transistor T3.

[0220] In an exemplary embodiment, the fourth transfer connection electrode 411 is arranged between the second sub-pixel P2 and the third sub-pixel P3. The orthographic projection of the fourth transfer connection electrode 411 on the substrate at least partially overlaps with the orthographic projection of the compensation signal line 22 on the substrate on the one hand, and at least partially overlaps with the orthographic projection of the compensation connection line 35 on the substrate on the other hand. The fourth transfer connection electrode 411 is configured to be connected to the compensation signal line 22 and the compensation connection line 35 through the fifth via hole V5. The fourth transfer connection electrode 411 can serve as the first electrode of the third transistor T3.

[0221] In an exemplary embodiment, this process also includes a conductive treatment. After forming the third conductive layer pattern, the conductive treatment is performed using the third conductive layer as a shield. The semiconductor layer in the area shielded by the first, second, and third gate electrodes serves as the channel region of the transistor. The semiconductor layer in the area not shielded by the third conductive layer is treated to form a conductive layer, forming a conductive second electrode 34 and conductive source and drain regions. The third conductive region is conductively treated during this process.

[0222] (16) Forming a third insulating layer and a planar layer pattern. In an exemplary embodiment, forming the planar layer pattern may include: sequentially coating a third insulating film and a planar film on the substrate on which the aforementioned pattern is formed, patterning the third insulating film and the planar film using a patterning process to form a third insulating layer and a planar layer pattern covering the third conductive layer, wherein the third insulating layer and the planar layer are provided with a plurality of via holes, the plurality of via holes including at least a twentieth via hole V20 and a twenty-first via hole V21 located in each sub-pixel, as shown in FIG. 11 .

[0223] In an exemplary embodiment, a twentieth via hole V20 may be provided in each sub-pixel, with the orthographic projection of the twentieth via hole V20 on the substrate being within the range of the orthographic projection of the third via connection electrode 48 on the substrate. The planar layer and the third insulating layer within the twentieth via hole V20 are removed, exposing the surface of the third via connection electrode 48. In an exemplary embodiment, the twentieth via hole V20 is configured to connect a subsequently formed anode to the third via connection electrode 48 through the via hole.

[0224] In an exemplary embodiment, a twenty-first via hole V21 may be provided in each sub-pixel, with the orthographic projection of the twenty-first via hole V21 on the substrate located within the orthographic projection of the second via connection electrode 47 on the substrate. The planar layer and the third insulating layer within the twenty-first via hole V21 are removed, exposing the surface of the second via connection electrode 47. In an exemplary embodiment, the twenty-first via hole V21 is configured to connect a subsequently formed anode to the second via connection electrode 47 through the via hole.

[0225] At this point, the drive circuit layer is completed on the substrate. In a plane parallel to the display substrate, the drive circuit layer may include multiple sub-pixels, each of which may include a pixel drive circuit, as well as a first scanning signal line, a first power line, a data signal line, and a compensation signal line connected to the pixel drive circuit. In a plane perpendicular to the display substrate, the drive circuit layer may include a first conductive layer, a second conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a third conductive layer, a third insulating layer, and a planar layer stacked sequentially on the substrate.

[0226] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer is prepared on the driving circuit layer. The preparation process of the light emitting structure layer may include the following operations.

[0227] (17) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process to form a fourth conductive layer pattern disposed on the flat layer, wherein the fourth conductive layer pattern includes at least: an anode 301 located in each sub-pixel, as shown in FIG12a and FIG12b , FIG12b being a planar schematic diagram of the fifth conductive layer in FIG12a . In an exemplary embodiment, the fourth conductive layer may be referred to as a second transparent (ITO2) layer.

[0228] In the embodiment of the present disclosure, the second transparent layer may be the transparent conductive layer described above.

[0229] In an exemplary embodiment, the fourth conductive layer pattern may include a first anode 301R located in the first subpixel P1, a second anode 301W located in the second subpixel P2, a third anode 301G located in the third subpixel P3, and a fourth anode 301B located in the fourth subpixel P4. The anode 301 in each subpixel is connected to the third transfer connection electrode 48 through the twentieth via hole V20. Since the third transfer connection electrode 48 serves as the second electrode of the third transistor T3, the anode 301 is connected to the third transistor T3. The anode 301 in each subpixel is connected to the second transfer connection electrode 47 through the twenty-first via hole V21. Since the second transfer connection electrode 47 serves as the second electrode of the second transistor T2, the anode 301 is connected to the second transistor T2.

[0230] In an exemplary embodiment, the first anode 301R, the second anode 301W, the third anode 301B, and the fourth anode 301G may be in the shape of a strip extending along the second direction Y. In the second direction Y, a first connection electrode 3011 and a second connection electrode 3012 are respectively provided on both sides of the anode in each sub-pixel. The first connection electrode 3011 is connected to the third transfer connection electrode 48 through the twentieth via hole V20, and the second connection electrode 3012 is electrically connected to the second transfer connection electrode 47 through the twenty-first via hole V21. The anode in each sub-pixel and the first connection electrode 3011 and the second connection electrode 3012 may be an integrally formed structure.

[0231] In an exemplary embodiment, the orthographic projection of the anode in each sub-pixel on the substrate includes the orthographic projection of the storage capacitor in the sub-pixel on the substrate.

[0232] In an exemplary embodiment, the twentieth via hole V20 may serve as the second transfer via hole, and the twenty-first via hole V21 may serve as the first transfer via hole.

[0233] (18) Forming a pixel definition layer pattern. In an exemplary embodiment, forming the pixel definition layer pattern may include: coating a pixel definition film on the substrate having the aforementioned pattern formed thereon, patterning the pixel definition film using a patterning process to form a pixel definition layer 302 pattern, wherein the pixel definition layer 302 pattern includes at least a pixel opening located in each sub-pixel, as shown in FIG13a and FIG13b , where FIG13b is a plan view schematic diagram of the pixel definition layer in FIG13a .

[0234] In an exemplary embodiment, the pixel definition layer 302 pattern may include a red pixel opening 302R located in the first sub-pixel P1 to expose the red anode 301R, a white pixel opening 302W located in the second sub-pixel P2 to expose the white anode 301W, a green opening 302G located in the third sub-pixel P3 to expose the green anode 301G, and a blue pixel opening 302B located in the fourth sub-pixel P4 to expose the blue anode 301B.

[0235] In exemplary embodiments, the shape and area of ​​the pixel openings of different sub-pixels can be different. By designing the four sub-pixels with different aperture ratios, the exemplary embodiments of the present disclosure can adapt to the transmittance of the color filter layers of different sub-pixels. This allows the light-emitting devices of the four sub-pixels to emit the same brightness at different currents, maximizing the lifespan of the light-emitting devices in the four sub-pixels and ensuring the product's lifespan.

[0236] In an exemplary embodiment, an orthographic projection of the pixel opening in each sub-pixel on the substrate at least partially overlaps with an orthographic projection of the storage capacitor in the sub-pixel on the substrate.

[0237] In an exemplary embodiment, the subsequent preparation process may include: forming an organic light-emitting layer using an evaporation or inkjet printing process, connecting the organic light-emitting layer to an anode through a pixel opening, forming a cathode on the organic light-emitting layer, and connecting the cathode to the organic light-emitting layer; forming an encapsulation layer, which may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of an organic material. The second encapsulation layer is disposed between the first and third encapsulation layers to prevent external moisture from entering the light-emitting structure layer.

[0238] In an exemplary embodiment, the first conductive layer and the fourth conductive layer can be made of transparent conductive materials, such as indium tin oxide ITO or indium zinc oxide IZO. The second conductive layer and the third conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, a multilayer or a composite layer. The first insulating layer is called a buffer layer, the second insulating layer is called a gate insulating (GI) layer, and the third insulating layer is called an interlayer insulating (PVX) layer. The flat layer can be made of an organic material, such as a resin. The pixel definition layer can be made of polyimide, acrylic or polyethylene terephthalate.

[0239] The display substrate prepared by the above steps (11) to (18) is composed of 6 array substrate mask plates (Array MASK) and 5 color filter substrate mask plates (CF MASK), wherein the Array MASK includes a sample of the first conductive layer (CF_ITO), the shielding metal layer (SHIELD), the semiconductor layer (ACT), the second insulating layer (GI), the gate metal layer (GT), and the sixth conductive layer (ITO), and the 5 CF MASKs include a flat layer (RESIN), a pixel definition layer (PDL), a red light-emitting layer (Red), a green light-emitting layer (Green), and a blue light-emitting layer (Blue). The number of mask plates used is small, and the preparation process is simplified to reduce the preparation cost. Compared with the pixel design in the related art, the routing of the data signal line and the first power line VDD is changed from the source and drain metal layer SD to the shielding layer SHIELD, and the mask of the source and drain metal layer SD layer is subtracted. In addition, the CNT hole and the ILD hole are removed, and the GI hole is added. The flat layer (RESIN) and the third insulating layer PVX layer share a mask, which greatly simplifies the preparation process and reduces the preparation cost. The GT layer and the ACT layer, as well as the GT layer and the SHIELD layer, are interconnected through GI holes. Furthermore, the data signal line uses SHIELD and GT dual-layer wiring to reduce the impedance of the data signal line. The first power line VDD uses SHIELD and GT dual-layer wiring in the longitudinal direction (second direction Y) to reduce impedance and reduce the RC of the first power line and the data signal line. The capacitor uses a transparent capacitor CF_ITO / SHIELD-ACT capacitor structure, in which the CF_ITO and SHIELD are directly in contact and conductively connected to each other, and the RGB capacitors are of the same size.

[0240] In an exemplary embodiment, taking four sub-pixels (a first sub-pixel P1 , a second sub-pixel P2 , a third sub-pixel P3 , and a fourth sub-pixel P4 ) as an example, another preparation process of the driving circuit layer may include the following operations.

[0241] (21) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first conductive film on a substrate, patterning the first conductive film through a patterning process, and forming a first conductive layer pattern on the substrate, wherein the first conductive layer pattern includes at least a first electrode 11 formed in each sub-pixel, as shown in FIG14 . In an exemplary embodiment, the first conductive layer may be referred to as a first transparent (ITO1) layer.

[0242] In an exemplary embodiment, the first electrode 11 in each sub-pixel is configured as a transparent electrode forming a storage capacitor. The first electrode 11 may be rectangular, and the edges of the rectangle may be fold lines. In an exemplary embodiment, the dimensions of the first electrode 11 in the second sub-pixel P2 and the third sub-pixel P3 along the second direction Y are smaller than the dimensions of the first electrode 11 in the first sub-pixel P1 and the fourth sub-pixel P4 along the second direction Y.

[0243] (22) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film through a patterning process to form a second conductive layer pattern covering the first conductive layer, wherein the second conductive layer pattern includes at least the first scan signal line 41, as shown in FIG15 , which is a plan view schematic diagram of the second conductive layer and the first conductive layer. In an exemplary embodiment, the second conductive layer may be referred to as a first blocking metal (SHL1) layer.

[0244] In an exemplary embodiment, the first scanning signal line 41 is a strip-shaped structure extending along a first direction X. The first scanning signal line 41 spans the first to fourth sub-pixels P1 to P4 in the first direction X. In the second direction Y, the first scanning signal line 41 is located on one side of the first electrode plate 11.

[0245] (23) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film through a patterning process, and forming a third conductive layer pattern on the substrate, wherein the third conductive layer pattern includes at least a shielding structure 23, a first scan signal auxiliary line 410, a compensation connection line 35, and a first auxiliary data line 451, as shown in Figures 16a and 16b, where Figure 16b is a planar schematic diagram of the third conductive layer in Figure 16a. In an exemplary embodiment, the third conductive layer may be referred to as a second shielding metal (SHL2) layer.

[0246] In an exemplary embodiment, a shielding structure 23 may be provided in each sub-pixel. The shielding structure 23 may be a rectangular structure, which may have chamfered corners. In the second direction Y, the shielding structure 23 may be located on a side of the first auxiliary data line 451 away from the first scan signal auxiliary line 410. In an exemplary embodiment, the orthographic projection of the shielding structure 23 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate, and the shielding structure 23 is connected to the first electrode plate.

[0247] In an exemplary embodiment, the first scan signal auxiliary line 410 is a strip-shaped structure extending along a first direction X. In the first direction X, the first scan signal line 41 spans the first subpixel P1 to the fourth subpixel P4. In the second direction Y, the first scan signal line 41 is located on one side of the first electrode plate 11 and between the first electrode plate 11 and the compensation connection line 35. In an exemplary embodiment, the orthographic projection of the first scan signal auxiliary line 410 on the substrate at least partially overlaps with the orthographic projection of the first scan signal line 41 on the substrate. The first scan signal auxiliary line 410 is configured to connect to the first scan signal line 41, forming a double-layer routing to reduce the resistance of the scan signal line 41.

[0248] In an exemplary embodiment, in the second direction Y, the compensation connection line 35 is located on a side of the first scanning signal auxiliary line 410 away from the first electrode plate 11, and the compensation connection line 35 can be a strip structure extending along the first direction X. In the first direction X, the compensation connection line 35 spans the first sub-pixel P1 to the fourth sub-pixel P4.

[0249] In an exemplary embodiment, a first auxiliary data line 451 is provided in each sub-pixel. The first auxiliary data line 451 may be a stripe structure extending along the second direction Y. In the second direction Y, the first auxiliary data line 451 may be located between the first scanning signal auxiliary line 410 and the shielding structure 23. In an exemplary embodiment, the first auxiliary data line 451 is configured to be electrically connected to a subsequently formed data signal line 25, forming a double-layer routing to reduce the resistance of the data signal line.

[0250] (24) Forming a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process to form a first insulating layer covering the third conductive layer, and a semiconductor layer pattern disposed on the first insulating layer, wherein the semiconductor layer pattern includes at least an active layer 31 of a first transistor T1, an active layer 32 of a second transistor T2, an active layer 33 of a third transistor T3, a second electrode 34, and a first power connection line 43 formed in each sub-pixel, as shown in FIG17 a and FIG17 b, where FIG17 b is a planar schematic diagram of the semiconductor layer in FIG17 a.

[0251] In an exemplary embodiment, the orthographic projection of the second electrode plate 34 in each sub-pixel on the substrate overlaps with the orthographic projection of the first electrode plate 11 on the substrate, and the second electrode plate 34 is configured to form another transparent electrode plate of the storage capacitor, and the first electrode plate 11 and the second electrode plate 34 form a transparent storage capacitor.

[0252] In an exemplary embodiment, the second electrode plate 34 may be rectangular in shape, and edges of the rectangle may be fold lines.

[0253] In an exemplary embodiment, in each sub-pixel, the shape of the second electrode plate 34 may be similar to the shape of the first electrode plate 11 in the sub-pixel, and the orthographic projection of the second electrode plate 34 on the substrate may cover the orthographic projection of the first electrode plate 11 on the substrate.

[0254] In an exemplary embodiment, the active layer 31 of the first transistor T1 , the active layer 32 of the second transistor T2 , and the active layer 33 of the third transistor T3 each include a channel region and first and second regions located at both sides of the channel region.

[0255] In an exemplary embodiment, the active layer 31 of the first transistor T1 may be in an L-shape. In the second direction Y, the active layer 31 of the first transistor T1 may be located on one side of the second electrode plate 34 .

[0256] In an exemplary embodiment, the second region 31 - 2 of the active layer 31 of the first transistor T1 may be connected to the second electrode plate 34 , and the active layer 31 and the second electrode plate 34 of the first transistor T1 are an integral structure connected to each other.

[0257] In an exemplary embodiment, the first region 31-1 of the active layer 31 of the first transistor T1 is a stripe-shaped structure extending along the first direction X. The stripe-shaped structure extends from the second region 31-2 of the active layer 31 of the first transistor T1 toward the adjacent subpixel. The stripe-shaped structure in the first subpixel P1 extends toward the second subpixel P2, and the stripe-shaped structure in the third subpixel P3 extends toward the fourth subpixel P4. The stripe-shaped structure in the second subpixel P2 extends toward the first subpixel P1, and the stripe-shaped structure in the fourth subpixel P3 extends toward the third subpixel P3. Because the second region 31-2 of the active layer 31 of the first transistor T1 is electrically connected to the gate electrode of the second transistor T2 via the subsequently formed second electrode of the first transistor T1, the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the second plate of the storage capacitor are interconnected.

[0258] In an exemplary embodiment, the active layer 32 of the second transistor T2 may be T-shaped. In the second direction Y, the second active layer 32 may be located on a side of the second electrode plate 34 away from the active layer 31 of the first transistor T1. The orthographic projection of the active layer 32 of the second transistor T2 on the substrate is spaced apart from the orthographic projection of the second electrode plate 34 on the substrate, i.e., there is no overlap between the second active layer 32 and the second electrode plate 34. This facilitates designing the channel width-to-length ratio of the second transistor according to relevant requirements. The first region 32-1 of the active layer 32 of the second transistor T2 is located on a side of the channel region away from the second electrode plate 34. The orthographic projection of the first region 32-1 of the active layer 32 of the second transistor T2 on the side closer to the channel region on the substrate overlaps with the orthographic projection of the shielding structure 23 on the substrate. The second region 32-2 of the active layer 32 of the second transistor T2 is located on the side of the channel region near the second electrode 34. The orthographic projection of the second region 32-2 of the active layer 32 of the second transistor T2 on the substrate overlaps with the orthographic projection of the shielding structure 23 on the substrate. In this way, the shielding structure 23 can shield the channel region of the second active layer 32, preventing light from affecting the channel, reducing leakage current, and thus preventing the impact of light on transistor characteristics. In an exemplary embodiment, the first region of the active layer 32 of the second transistor T2 of multiple sub-pixels in the same pixel unit can be an integrally formed structure interconnected with the first power connection line 43.

[0259] In an exemplary embodiment, the active layer 33 of the third transistor T3 may be I-shaped. In the second direction Y, the active layer 33 of the third transistor T3 may be located on a side of the active layer 31 of the first transistor T1 that is away from the second electrode plate 34. The orthographic projection of the active layer 33 of the third transistor T3 on the substrate is spaced apart from the orthographic projection of the second electrode plate 34 on the substrate. This means that there is no overlap between the third active layer 33 and the second electrode plate 42, facilitating the design of the channel width-to-length ratio of the third transistor according to requirements. In an exemplary embodiment, in the second direction Y, the active layer 31 of the first transistor T1 and the active layer 33 of the third transistor T3 are located on either side of the first scan signal auxiliary line 410.

[0260] In an exemplary embodiment, the first power connection line 43 can be a strip structure extending along the first direction X, and the first power connection point 43 can be arranged across the first sub-pixel P1 to the fourth sub-pixel P4 and be integrally formed with the active layer 33 of the third transistor T3; in the second direction Y, the first power connection line 43 can be located on a side of the active layer 32 of the second transistor T2 away from the second electrode 34.

[0261] In exemplary embodiments, the semiconductor layer may be formed of a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, an oxide containing indium, gallium, and zinc, etc. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0262] (25) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: sequentially depositing a second insulating film and a fourth conductive film on a substrate, patterning the second insulating film and the fourth conductive film through a patterning process to form a second insulating layer covering the semiconductor layer, and a fourth conductive layer pattern disposed on the second insulating layer, wherein the fourth conductive layer pattern includes at least a second gate electrode 42, a first power auxiliary line 44, a second auxiliary data line 452, and a first gate electrode 49, as shown in FIG18a and FIG18b, FIG18b is a planar schematic diagram of the fourth conductive layer in FIG18a. In an exemplary embodiment, the fourth conductive layer may be referred to as a gate metal (GATE) layer.

[0263] In the exemplary embodiment, a second gate electrode 42 is formed within each subpixel and serves as the gate electrode of the second transistor T2. Within each subpixel, the orthographic projection of the second gate electrode 42 on the substrate overlaps with the orthographic projection of the active layer 32 of the second transistor T2. Furthermore, the orthographic projection of the second gate electrode 42 on the substrate overlaps with the shielding structure 23. The second gate electrode 42 is a strip-shaped structure extending along the first direction X. In the second direction Y, the second gate electrode 42 is located on the side of the second plate 34 away from the first transistor T1.

[0264] In an exemplary embodiment, a first auxiliary power line 44 is formed within the first subpixel P1 and the fourth subpixel P4 and has a strip-shaped structure extending along the second direction Y. Within the first subpixel P1, in the first direction X, the first auxiliary power line 44 is located on the side of the second electrode plate 34 away from the second subpixel P2. Within the fourth subpixel P4, in the first direction X, the first auxiliary power line 44 is located on the side of the second electrode plate 34 closer to the third subpixel P3. The second auxiliary power line 452 is configured to connect to the subsequently formed first power line, forming a double-layer routing pattern to ensure reliable power signal transmission and reduce the resistance of the first power line.

[0265] In an exemplary embodiment, a second auxiliary data line 452 is formed within each subpixel and has a strip-shaped structure extending along the second direction Y. In the first and third subpixels P1 and P3, the second auxiliary data line 452 is located on one side of the second plate 34 in the first direction X. In the second and fourth subpixels P2 and P4, the second auxiliary data line 452 is located on the side of the second plate 34 opposite the first direction X. The second auxiliary data line 452 is configured to connect to the first auxiliary data line 451 and subsequently formed data signal lines, forming a three-layer routing structure. This ensures reliable data signal transmission and reduces resistance of the data signal lines. In an exemplary embodiment, the orthographic projection of the second auxiliary data line 452 on the substrate overlaps with the orthographic projection of the first auxiliary data line 451 on the substrate.

[0266] In an exemplary embodiment, main portions of the first power auxiliary line 44 and the second auxiliary data line 452 may be disposed in parallel.

[0267] In an exemplary embodiment, a first gate electrode 49 is formed within each subpixel, serving as the gate electrode for the first transistor T1 and the third transistor T3. Within each subpixel, the orthographic projection of the first gate electrode 49 on the substrate overlaps with the orthographic projection of the active layer 32 of the first transistor T1, and also overlaps with the active layer of the third transistor T3. The first gate electrode 49 has a stripe-shaped structure and a zigzag-line structure extending along the second direction Y. In the second direction Y, the first gate electrode 49 is located on the side of the second electrode plate 34 away from the second transistor T2. In the first and fourth subpixels P1 and P4, the first gate electrode 49 has a stripe-shaped structure, while in the second and third subpixels P2 and P3, the first gate electrode 49 has a zigzag-line structure.

[0268] In an exemplary embodiment, this process also includes a conductive treatment. After forming the third conductive layer pattern, the conductive treatment is performed using the third conductive layer as a shield for plasma treatment. The semiconductor layer in the area shielded by the first and second gate electrodes serves as the channel region of the transistor, while the semiconductor layer in the area not shielded by the third conductive layer is processed into a conductive layer, forming a conductive second electrode 34 and a conductive source and drain region.

[0269] (26) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer covering the fourth conductive layer, wherein a plurality of vias are provided on the third insulating layer, and the plurality of vias include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, and a twelfth via V12, as shown in FIG. 19 .

[0270] In an exemplary embodiment, a first via hole V1 may be provided in each sub-pixel. The orthographic projection of the first via hole V1 on the substrate is located within the orthographic projection of the first region 31-1 of the active layer 31 of the first transistor T1 on the substrate. The third insulating layer and the second insulating layer within the first via hole V1 are etched away, exposing the surface of the first region 31-1 of the active layer 31 of the first transistor T1. In an exemplary embodiment, the first via hole V1 is configured to connect a subsequently formed data signal line to the active layer 31 of the first transistor T1 through the via hole.

[0271] In an exemplary embodiment, a second via hole V2 may be provided in each sub-pixel. The orthographic projection of the second via hole V2 on the substrate is located within the orthographic projection of the second region 31-2 of the active layer 31 of the first transistor T1 on the substrate. The third insulating layer and the second insulating layer within the second via hole V2 are etched away, exposing the surface of the second region 31-2 of the first active layer 31. In an exemplary embodiment, the second via hole V2 is configured to connect the second electrode of the subsequently formed first transistor T1 to the active layer 31 of the first transistor T1 through the via hole.

[0272] In an exemplary embodiment, a third via hole V3 may be provided in each sub-pixel. The orthographic projection of the third via hole V3 on the substrate is located within the orthographic projection of the first region 32-1 of the active layer 32 of the second transistor T2. The third insulating layer and the second insulating layer within the third via hole V3 are etched away, exposing the surface of the first region 32-1 of the active layer 32 of the second transistor T2. In an exemplary embodiment, the third via hole V3 is configured to electrically connect a subsequently formed first power line to the active layer 32 of the second transistor T2.

[0273] In an exemplary embodiment, a fourth via hole V4 may be provided in each sub-pixel. The orthographic projection of the fourth via hole V4 on the substrate at least partially overlaps with the orthographic projection of the second region 32-2 of the active layer 32 of the second transistor T2 on the substrate, and at least partially overlaps with the orthographic projection of the blocking structure 23 on the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the fourth via hole V4 are etched away, exposing the surface of the second region 32-2 of the active layer 32 of the second transistor T2 and the surface of the blocking structure 23. In an exemplary embodiment, the second region 32-2 is configured such that the second electrode of the subsequently formed second transistor T2 is simultaneously connected to the blocking structure 23 and the active layer 32 of the second transistor T2 through the via hole.

[0274] In an exemplary embodiment, a fifth via hole V5 may be provided in each sub-pixel. The orthographic projection of the fifth via hole V5 on the substrate at least partially overlaps with the orthographic projection of the first region 33-1 of the active layer 33 of the third transistor T3 on the substrate. The third and second insulating layers within the fifth via hole V5 are etched away, exposing the surface of the first region 33-1 of the active layer 33 of the third transistor T3. In an exemplary embodiment, the fifth via hole V5 is configured to connect the first electrode of the subsequently formed third transistor T3 to the active layer 33 of the third transistor T2 through the via hole.

[0275] In an exemplary embodiment, a sixth via hole V6 may be provided in each sub-pixel. The orthographic projection of the sixth via hole V6 on the substrate at least partially overlaps with the orthographic projection of the second region 33-2 of the active layer 33 of the third transistor T3 on the substrate. The third and second insulating layers within the sixth via hole V6 are etched away, exposing the surface of the second region 33-2 of the active layer 33 of the third transistor T3. In an exemplary embodiment, the sixth via hole V6 is configured to connect the second electrode of the subsequently formed third transistor T3 to the active layer 33 of the third transistor T2 through the via hole.

[0276] In an exemplary embodiment, the seventh via hole V7 can be provided in the first sub-pixel P1 and the fourth sub-pixel P4, and the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first power auxiliary line 44 on the substrate. The third insulating layer within the seventh via hole V7 is etched away, exposing the surface of the first power auxiliary line 44. In an exemplary embodiment, the seventh via hole V7 is configured to connect a subsequently formed first power line to the first power auxiliary line 44 through the via hole. In an exemplary embodiment, a plurality of seventh via holes V7 can be provided, and the plurality of seventh via holes V7 can be arranged sequentially along the second direction Y to increase the reliability of the connection between the first power line and the first power auxiliary line 44.

[0277] In an exemplary embodiment, the eighth via hole V8 can be provided in the first sub-pixel P1 and the fourth sub-pixel P4. The orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the compensation connection line 35 on the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the eighth via hole V8 are etched away, exposing the surface of the compensation connection line 35. In an exemplary embodiment, the eighth via hole V8 is configured to connect the first electrode of the subsequently formed third transistor T3 to the compensation connection line 35 through the via hole.

[0278] In an exemplary embodiment, a ninth via hole V9 may be provided in each sub-pixel, with the orthographic projection of the ninth via hole V9 on the substrate being located within the range of the orthographic projection of the first scan signal auxiliary line 410 on the substrate, and within the range of the orthographic projection of the first gate electrode 49 on the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the ninth via hole V9 are etched away, exposing the surface of the first scan signal auxiliary line 410 and the surface of the first gate electrode 49. In an exemplary embodiment, the ninth via hole V9 is configured to allow a subsequently formed gate transfer connection electrode to be connected to the first scan signal auxiliary line 410 and the first gate electrode 49 through the via hole.

[0279] In an exemplary embodiment, a tenth via hole V10 may be provided in each sub-pixel. The orthographic projection of the tenth via hole V10 on the substrate is located within the orthographic projection of the second gate electrode 42 on the substrate, and within the orthographic projection of the second plate 34 on the substrate. The third insulating layer and the second insulating layer within the tenth via hole V10 are etched away, exposing the surfaces of the second plate 34 and the second gate electrode 42. In an exemplary embodiment, the tenth via hole V10 is configured to connect the second electrode of the subsequently formed second transistor T2 to the second gate electrode 42 and the second plate 34.

[0280] In an exemplary embodiment, an eleventh via hole V11 may be provided in each sub-pixel, with the orthographic projection of the eleventh via hole V11 on the substrate located within the orthographic projection of the second auxiliary data line 452 on the substrate. The third insulating layer within the eleventh via hole V11 is etched away, exposing the surface of the second auxiliary data line 452. In an exemplary embodiment, the eleventh via hole V11 is configured to connect a subsequently formed data signal line to the second auxiliary data line 452 through the via hole. In an exemplary embodiment, a plurality of the eleventh via holes V11 may be provided, and the plurality of the eleventh via holes V11 may be arranged sequentially along the second direction Y to increase the reliability of the connection between the data signal line and the second auxiliary data line 452.

[0281] In an exemplary embodiment, a twelfth via hole V12 may be provided in each sub-pixel, and an orthographic projection of the twelfth via hole V12 on the substrate is located within the range of an orthographic projection of the first auxiliary data line 451 on the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the twelfth via hole V12 are etched away, exposing the surface of the first auxiliary data line 451. In an exemplary embodiment, the twelfth via hole V12 is configured to connect a subsequently formed data signal line to the first auxiliary data line 451 through the via hole.

[0282] In an exemplary embodiment, the thirteenth via hole V13 may be disposed between the second sub-pixel P2 and the third sub-pixel P3. The orthographic projection of the thirteenth via hole V13 on the substrate is within the range of the orthographic projection of the compensation connection line 35 on the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the thirteenth via hole V13 are etched away, exposing the surface of the compensation connection line 35. In an exemplary embodiment, the thirteenth via hole V13 is configured to connect a subsequently formed compensation signal line to the compensation connection line 35 through the via hole.

[0283] (27) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the third insulating layer, wherein the fifth conductive layer includes at least: a first power line 21, a compensation signal line 22, a data signal line 25, a gate transfer connection electrode 26, a first transfer connection electrode 46, a second transfer connection electrode 47, a third transfer connection electrode 48, a fourth transfer connection electrode 411, and a fifth transfer connection electrode 412, as shown in FIG20a and FIG20b, FIG20b is a planar schematic diagram of the fifth conductive layer in FIG20a. In an exemplary embodiment, the fifth conductive layer may be referred to as a source-drain metal (SD) layer.

[0284] In an exemplary embodiment, a first power line 21 is provided in the first sub-pixel P1 and the fourth sub-pixel P4, with the main portion of the first power line 21 extending along the second direction Y. On one hand, the first power line 21 is connected to the first region 32-1 of the second active layer 32 via a third via V3, thereby writing a power signal into the second transistor T2. On the other hand, the first power line 21 is connected to the first power auxiliary line 44 via a plurality of seventh vias V7, so that the first power line 21 and the first power auxiliary line 44 form a double-layer routing. On the other hand, the first power line 21 is connected to the first power connection line 43 via a third via V3, so that the first power connection line 43 can transmit the power signal to the second sub-pixel P2 and the third sub-pixel P3, respectively.

[0285] In an exemplary embodiment, a data signal line 25 is provided in each sub-pixel, and a main portion of the data signal line 25 extends along the second direction Y. On one hand, the data signal line 25 is connected to the first region 31-1 of the first active layer 31 through a first via hole V1, thereby writing a data signal into the first transistor T1. On the other hand, the data signal line 25 is connected to the second auxiliary data line 452 through a plurality of eleventh via holes V11, so that the data signal line 25 and the second auxiliary data line 452 form a double-layer routing. On the other hand, the data signal line 25 is connected to the first auxiliary data line 451 through a plurality of twelfth via holes V12, so that the data signal line 25, the first auxiliary data line 451, and the second auxiliary data line 452 form a triple-layer routing.

[0286] In an exemplary embodiment, the compensation signal line 22 is disposed between the second subpixel P2 and the third subpixel P3, with the main portion of the compensation signal line 22 extending along the second direction Y. The compensation signal line 22 is connected to the compensation connection line 35 via a thirteenth via V13 and to the first region of the active layer of the third transistor T3 via a fifth via V5. The compensation signal line 22 is configured to write a compensation signal to the third transistor T3. In an exemplary embodiment, the compensation signal line 22 may serve as the first electrode of the third transistor T3. In the disclosed embodiment, the orthographic projection of the compensation signal line 22 on the substrate at least partially overlaps the orthographic projection of the first regions of two adjacent third transistors T3 on the substrate. The two adjacent third transistors T3 can share a common first electrode, effectively utilizing layout space and saving space on the display substrate.

[0287] In an exemplary embodiment, a gate transfer connection electrode 26 is provided in each sub-pixel and may be a rectangular structure. The gate transfer connection electrode 26 is connected to the first gate electrode 49 and the first scan signal auxiliary line 410 through a ninth via hole V9.

[0288] In an exemplary embodiment, a first via-connecting electrode 46 is formed in each sub-pixel. An orthographic projection of the first via-connecting electrode 46 on the substrate at least partially overlaps an orthographic projection of the second region 31-2 of the active layer 31 of the first transistor T1 on the substrate. The first via-connecting electrode 46 is configured to be connected to the second region 31-2 of the active layer 31 of the first transistor T1 through a second via hole V2. In an exemplary embodiment, the first via-connecting electrode 46 may serve as a second electrode of the first transistor T1.

[0289] In an exemplary embodiment, a second via-connecting electrode 47 is formed in each sub-pixel. The orthographic projection of the second via-connecting electrode 47 on the substrate at least partially overlaps with the orthographic projection of the second region 32-2 of the active layer 32 of the second transistor T2 on the substrate, and at least partially overlaps with the orthographic projection of the shielding structure 23 on the substrate. The second via-connecting electrode 47 is configured to connect to the second region 32-2 of the active layer 32 of the second transistor T2 and the shielding structure 23 through a second via hole V4. In an exemplary embodiment, the second via-connecting electrode 47 may serve as the second electrode of the second transistor T2.

[0290] In an exemplary embodiment, a third via-connecting electrode 48 is formed in each sub-pixel. An orthographic projection of the third via-connecting electrode 48 on the substrate at least partially overlaps an orthographic projection of the second region 33-2 of the active layer 33 of the third transistor T3 on the substrate. The third via-connecting electrode 48 is configured to be connected to the second region 33-2 of the active layer 33 of the third transistor T3 through a sixth via hole V6. In an exemplary embodiment, the third via-connecting electrode 48 may serve as a second electrode of the third transistor T3.

[0291] In an exemplary embodiment, the fourth transfer connection electrode 411 is arranged in the first sub-pixel P1 and the fourth sub-pixel P4. The orthographic projection of the fourth transfer connection electrode 411 on the substrate at least partially overlaps with the orthographic projection of the first area 33-1 of the active layer 33 of the third transistor T3 on the substrate on the one hand, and at least partially overlaps with the orthographic projection of the compensation connection line 35 on the substrate on the other hand. The fourth transfer connection electrode 411 is configured to be connected to the active layer 33 of the third transistor T3 through the fifth via V5 and to the compensation connection line 35 through the eighth via V8. The fourth transfer connection electrode 411 can serve as the first electrode of the third transistor T3.

[0292] In an exemplary embodiment, a fifth transfer connection electrode 412 is provided in each sub-pixel, and the orthographic projection of the fifth transfer connection electrode 412 on the substrate at least partially overlaps with the orthographic projection of the second gate electrode 42 on the substrate on the one hand, and at least partially overlaps with the orthographic projection of the second electrode plate 34 on the substrate on the other hand, and the fifth transfer connection electrode 412 is configured to be connected to the second gate electrode 42 and the second electrode plate 34 through the tenth via hole V10.

[0293] The exemplary embodiment of the present disclosure implements writing power signals to the second transistors T2 of each of the four subpixels by providing two first power lines 21 extending along the second direction Y and one power connection line 43 extending along the first direction X. In the first subpixel P1 and the fourth subpixel P4, the first power line 21 is directly connected to the second transistor T2 via a via. In the second subpixel P2 and the third subpixel P3, the first power line 21 is connected to the second transistor T2 via a power connection line 43.

[0294] The exemplary embodiment of the present disclosure implements the writing of compensation signals into the third transistors T3 of four sub-pixels by providing a compensation signal line 22, the main portion of which extends along the second direction Y, and a compensation connection line 35, which extends along the first direction X. In the second sub-pixel P2 and the third sub-pixel P3, the compensation signal line 22 is directly connected to the third transistor T3 via vias. In the first sub-pixel P1 and the fourth sub-pixel P4, the compensation signal line 21 is connected to the third transistor T3 via compensation connection lines 35. By providing a single compensation signal line to the four sub-pixels, the present disclosure ensures that the RC delay of the compensation signal before writing into the transistors is substantially the same, thus ensuring display uniformity.

[0295] In the exemplary embodiment of the present disclosure, a data signal line 25 extending along the second direction Y is provided in each sub-pixel. The data signal line 25 is connected to the first transistor T1 of the sub-pixel through a via hole, thereby writing data signals into the first transistors T1 of the four sub-pixels respectively.

[0296] In an exemplary embodiment, the first power line 21, the data signal line 25, and the compensation signal line 22 may be straight lines or zigzag lines of equal width, or straight lines or zigzag lines of unequal width. Using straight lines or zigzag lines of varying width for the first power line 21, the data signal line 25, and the compensation signal line 22 not only facilitates the layout of the pixel structure but also reduces parasitic capacitance.

[0297] (28) Forming a fourth insulating layer and a planar layer pattern. In an exemplary embodiment, forming the planar layer pattern may include: coating a fourth insulating layer film and a planar film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating layer film and the planar film using a patterning process to form a fourth insulating layer and a planar layer pattern covering the fifth conductive layer, wherein the fourth insulating layer and the planar layer are provided with a plurality of via holes, the plurality of via holes including at least a twentieth via hole V20 and a twenty-first via hole V21 located in each sub-pixel, as shown in FIG. 21 .

[0298] In an exemplary embodiment, a twentieth via hole V20 may be provided in each sub-pixel, with the orthographic projection of the twentieth via hole V20 on the substrate being within the range of the orthographic projection of the third via connection electrode 48 on the substrate. The planar layer and the fourth insulating layer within the twentieth via hole V20 are removed, exposing the surface of the third via connection electrode 48. In an exemplary embodiment, the twentieth via hole V20 is configured to connect a subsequently formed anode to the third via connection electrode 48 through the via hole.

[0299] In an exemplary embodiment, a twenty-first via hole V21 may be provided in each sub-pixel, with the orthographic projection of the twenty-first via hole V21 on the substrate located within the orthographic projection of the second via connection electrode 47 on the substrate. The planar layer and the fourth insulating layer within the twenty-first via hole V21 are removed, exposing the surface of the second via connection electrode 47. In an exemplary embodiment, the twenty-first via hole V21 is configured to connect a subsequently formed anode to the second via connection electrode 47 through the via hole.

[0300] In the embodiment of the present disclosure, the fourth insulating layer and the planar layer pattern are formed through a single patterning process, which simplifies the process, reduces the preparation cost, and improves the preparation efficiency.

[0301] At this point, the drive circuit layer is completed on the substrate. In a plane parallel to the display substrate, the drive circuit layer may include multiple sub-pixels, each of which may include a pixel drive circuit, as well as a first scanning signal line, a first power line, a data signal line, and a compensation signal line connected to the pixel drive circuit. In a plane perpendicular to the display substrate, the drive circuit layer may include a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a fourth conductive layer, a third insulating layer, a fifth conductive layer, a fourth insulating layer, and a planar layer stacked sequentially on the substrate.

[0302] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer is prepared on the driving circuit layer. The preparation process of the light emitting structure layer may include the following operations.

[0303] (29) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming the sixth conductive layer pattern may include: depositing a sixth conductive film on the substrate on which the aforementioned pattern is formed, patterning the sixth conductive film using a patterning process to form a sixth conductive layer pattern disposed on the flat layer, the sixth conductive layer pattern including at least: an anode 301 located in each sub-pixel, as shown in FIG22a and FIG22b , FIG22b being a planar schematic diagram of the sixth conductive layer in FIG22a . In an exemplary embodiment, the sixth conductive layer may be referred to as a second transparent (ITO2) layer.

[0304] In exemplary embodiments, the second transparent layer may serve as the transparent conductive layer described above.

[0305] In an exemplary embodiment, the sixth conductive layer pattern may include a first anode 301R located in the first subpixel P1, a second anode 301W located in the second subpixel P2, a third anode 301G located in the third subpixel P3, and a fourth anode 301B located in the fourth subpixel P4. The anode 301 in each subpixel is connected to the third transfer connection electrode 48 through the twentieth via hole V20. Since the third transfer connection electrode 48 serves as the second electrode of the third transistor T3, the anode 301 is connected to the third transistor T3. The anode 301 in each subpixel is connected to the second transfer connection electrode 47 through the twenty-first via hole V21. Since the second transfer connection electrode 47 serves as the second electrode of the second transistor T2, the anode 301 is connected to the second transistor T2.

[0306] In the embodiment of the present disclosure, the anode 301 in the sixth conductive layer is electrically connected to the second electrodes of the second transistor T2 and the third transistor T3, thereby effectively utilizing the layout space, saving the space of the display substrate, and increasing the light-emitting area of ​​the pixel unit in the bottom-emission display substrate.

[0307] In an exemplary embodiment, the first anode 301R, the second anode 301W, the fourth anode 301B, and the third anode 301G may be in the shape of a strip extending along the second direction Y. In the second direction Y, a first connection electrode 3011 and a second connection electrode 3012 are provided on both sides of the anode in each sub-pixel, respectively. The first connection electrode 3011 is connected to the third transfer connection electrode 48 through the twentieth via hole V20, and the second connection electrode 3012 is electrically connected to the second transfer connection electrode 47 through the twenty-first via hole V21. The anode in each sub-pixel and the first connection electrode 3011 and the second connection electrode 3012 may be an integrally formed structure.

[0308] In an exemplary embodiment, the orthographic projection of the anode in each sub-pixel on the substrate includes the orthographic projection of the storage capacitor in the sub-pixel on the substrate.

[0309] In an exemplary embodiment, the twentieth via hole V20 may serve as the second transfer via hole, and the twenty-first via hole V21 may serve as the first transfer via hole.

[0310] (210) Forming a pixel definition layer pattern. In an exemplary embodiment, forming the pixel definition layer pattern may include: coating a pixel definition film on the substrate having the aforementioned pattern formed thereon, patterning the pixel definition film using a patterning process to form a pixel definition layer 302 pattern, wherein the pixel definition layer 302 pattern includes at least a pixel opening located in each sub-pixel, as shown in FIG23a and FIG23b , FIG23b being a planar schematic diagram of the pixel definition layer in FIG23a .

[0311] In an exemplary embodiment, the pixel definition layer 302 pattern may include a red pixel opening 302R located in the first sub-pixel P1 to expose the red anode 301R, a white pixel opening 302W located in the second sub-pixel P2 to expose the white anode 301W, a green opening 302G located in the third sub-pixel P3 to expose the green anode 301G, and a blue pixel opening 302B located in the fourth sub-pixel P4 to expose the blue anode 301B.

[0312] In exemplary embodiments, the shape and area of ​​the pixel openings of different sub-pixels can be different. By designing the four sub-pixels with different aperture ratios, the exemplary embodiments of the present disclosure can adapt to the transmittance of the color filter layers of different sub-pixels. This allows the light-emitting devices of the four sub-pixels to emit the same brightness at different currents, maximizing the lifespan of the light-emitting devices in the four sub-pixels and ensuring the product's lifespan.

[0313] In an exemplary embodiment, an orthographic projection of the pixel opening in each sub-pixel on the substrate at least partially overlaps with an orthographic projection of the storage capacitor in the sub-pixel on the substrate.

[0314] In an exemplary embodiment, the subsequent preparation process may include: forming an organic light-emitting layer using an evaporation or inkjet printing process, connecting the organic light-emitting layer to an anode through a pixel opening, forming a cathode on the organic light-emitting layer, and connecting the cathode to the organic light-emitting layer; forming an encapsulation layer, which may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of an organic material. The second encapsulation layer is disposed between the first and third encapsulation layers to prevent external moisture from entering the light-emitting structure layer.

[0315] In an exemplary embodiment, the first conductive layer and the sixth conductive layer may be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer. The first insulating layer is called a buffer layer, the second insulating layer is called a gate insulating (GI) layer, the third insulating layer is called an interlayer insulating (ILD) layer, and the fourth insulating layer is called a passivation (PVX) layer. The flat layer may be made of an organic material, such as a resin. The pixel definition layer can be made of polyimide, acrylic or polyethylene terephthalate.

[0316] The RC of the data signal line and the scan signal line is the main limiting factor for whether the refresh frequency of the display substrate can be achieved, so reducing its RC is also a major requirement for the layout design of the display substrate. The display substrate obtained by the preparation method of the above steps (21) to (210) transmits the signal of the first scan line through the second shielding metal layer, and increases the distance from the source and drain metal layer to reduce the capacitance of the first scan signal line. In an exemplary embodiment, the first shielding metal layer adopts a thick Cu routing, which can reduce the resistance of the first scan signal line. In order to prevent the thick first shielding metal layer from cutting the active layer at the edge where the first shielding metal layer overlaps with the active layer, the shielding metal layer adopts a double-layer design and is deposited twice. The first scan signal line part adopts a thicker first shielding metal layer, and the shielding structure adopts a thinner second shielding metal layer. In the embodiment of the present disclosure, the data signal line adopts a three-layer structure of the second shielding metal layer, the gate metal layer, and the source and drain metal layer SD to reduce the RC of the data signal line so that it meets the refresh frequency realization standard. The shielding metal layer, the gate metal layer, and the source and drain metal layer can be made of copper to reduce impedance and be compatible with large-size design. The display substrate provided by the embodiment of the present disclosure adopts a three-layer routing structure of source-drain metal layer SD / gate metal layer GT / second shielding metal layer SHIELD for the data signal line, a double-layer routing structure of source-drain metal layer SD / gate metal layer GT for the first power line VDD, and a double-layer routing structure of first shielding layer and second shielding metal layer for the first scanning signal line. This can reduce the load on the data signal line, the first power line, and the first scanning signal line, and provides technical support for medium and large-sized high-PPI display substrates.

[0317] In an exemplary embodiment, the capacitor in the display substrate can be a transparent capacitor, that is, the first electrode plate and the second electrode plate can be a transparent structure, thereby improving the aperture ratio and PPI of the display substrate. In the display substrate prepared by steps (11) to (18) and steps (21) to (210), the two electrodes of the capacitor in the sub-pixel are located on the first conductive layer and the semiconductor layer, and the first electrode plate 11 and the second electrode plate 34 are both transparent structures. The two electrodes of the capacitor do not occupy the aperture ratio. Moreover, the second electrode of the second transistor T2 and the second electrode of the third transistor T3 are connected through the transparent conductive layer 300, so that the wiring connecting the two transistors does not occupy the aperture ratio, which can avoid blocking the pixel opening 302, increase the light-emitting area, and improve the aperture ratio and PPI of the display substrate.

[0318] In other embodiments, the semiconductor layer pattern formed in the above step (24) can be as shown in Figure 24a, that is, the second electrode 34 of the capacitor is not set in the semiconductor layer; the planar structure diagram after the fourth conductive layer pattern is formed in the above step (25) can be as shown in Figure 24b, and the fourth conductive layer pattern in Figure 24b can be as shown in Figure 24c, where the second electrode 34 of the capacitor is set in the fourth conductive layer, and the positive projection of the second electrode 34 on the substrate and the positive projection of the first electrode 11 on the substrate have an overlapping area, and the second electrode 34 and the second gate electrode 42 can be an integrally formed structure; the third insulating layer pattern formed in the above step (26) can be as shown in Figure 24d, and the difference between Figure 24d and Figure 19 is that the third insulating layer in the second via hole V2 and the tenth via hole V10 is etched away, The surface of the second electrode 34 is exposed; the structural diagram after the fifth conductive layer is formed in the above step (27) can be as shown in Figure 24e, and the planar structural diagram of the fifth conductive layer in Figure 24e can be as shown in Figure 24f. The difference between Figures 24e and 24f and Figures 20a and 20b is that: the first transfer connection electrode 46 and the third transfer connection electrode 48 can be an integrally formed structure, so that the second electrode 34 is electrically connected to the second electrode of the third transistor T3 through the first transfer connection electrode 46 and the third transfer connection electrode 48, so as to realize the electrical connection between the second electrode of the third transistor T3 and the second electrode plate 34; the second transfer connection electrode 47 can also be electrically connected to the second electrode plate 34 through the tenth via V10, so as to realize the electrical connection between the second electrode of the second transistor T2 and the second electrode plate 34. The structures of the first conductive layer pattern to the third conductive layer pattern are the same as those in steps (21) to (23) above. The fourth insulating layer and planar layer patterns, the sixth conductive layer pattern, and the pixel definition layer pattern are the same as those in steps (28) to (210) above. The present embodiment will not be described in detail here. In the present embodiment, the two plates of the capacitor are transparent structures disposed on the first conductive layer and the fourth conductive layer, which can avoid blocking the pixel opening 302 and improve the aperture ratio and PPI of the display substrate.

[0319] In other embodiments, the semiconductor layer pattern formed in the above step (24) can be as shown in Figure 24a, that is, the second electrode 34 of the capacitor is not set in the semiconductor layer; the planar structure diagram after the fourth conductive layer pattern is formed in the above step (25) can be as shown in Figure 25a, and the fourth conductive layer pattern in Figure 25a can be the same as the structure shown in Figure 18b; the planar structure schematic diagram after the fifth conductive layer pattern is formed in the above step (27) can be as shown in Figure 25b, and the planar structure schematic diagram of the fifth conductive layer pattern in Figure 25b can be as shown in Figure 20b; the planar structure schematic diagram after the sixth conductive layer pattern is formed in the above step (29) can be as shown in Figure 25c, and the planar structure schematic diagram of the sixth conductive layer in Figure 25c can be as shown in Figure 22b. In the embodiment of the present disclosure, the difference from the above steps (21) to (210) is that the second plate 34 of the capacitor in the semiconductor layer is removed, and the anode 301 is reused as the second plate of the capacitor, that is, the semiconductor layer formed is different from that in the above step (24), and the other structural film layers are the same as the above steps (21) to (23) and steps (25) to 210. In the embodiment of the present disclosure, the transparent conductive layer 300 is reused as the second plate of the capacitor, and the second electrode of the second transistor T2 and the second electrode of the third transistor T3 are connected through the transparent conductive layer, thereby saving layout space and improving the aperture ratio and PPI of the display substrate.

[0320] In the technical solution provided by the embodiment of the present disclosure, since the first connection via V21 and the second connection via V20 are located on both sides of the pixel opening 302, the problem of uneven display caused by one pixel opening being located on one side of the pixel opening 302 can be avoided.

[0321] The structure and fabrication process shown in this disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be modified and patterning processes can be added or removed based on actual needs. For example, a display area may include three sub-pixels. For example, the pixel driver circuit may be a 5T1C or 7T1C circuit, etc., which is not limited in this disclosure.

[0322] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0323] The present disclosure also provides a display device comprising the display substrate of the aforementioned embodiment. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0324] The display substrate, preparation method thereof, and display device provided in this embodiment are characterized in that the second electrode of the second transistor and the second electrode of the third transistor in the same sub-pixel of the display substrate are electrically connected via at least one transparent conductive layer. The transparent conductive layer does not block the opening, thereby improving the aperture ratio and PPI of the display substrate.

[0325] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the appended claims.

Claims

1. A display substrate, comprising a substrate, and a plurality of sub-pixels and a plurality of transparent conductive layers arranged on the substrate, each sub-pixel comprising at least one transparent conductive layer, at least a portion of the sub-pixels comprising at least a second transistor and a third transistor, and a second electrode of the second transistor and a second electrode of the third transistor in the same sub-pixel being electrically connected via at least one transparent conductive layer.

2. The display substrate according to claim 1, wherein: At least a portion of the transparent conductive layer includes an anode, a first connecting electrode, and a second connecting electrode, and in the same transparent conductive layer, the anode is electrically connected to the first connecting electrode and the second connecting electrode; In the same sub-pixel, the second electrode of the second transistor is electrically connected to the corresponding anode through the first connecting electrode, the second electrode of the third transistor is electrically connected to the corresponding anode through the second connecting electrode, and the second electrode of the second transistor and the second electrode of the third transistor are electrically connected through the corresponding first connecting electrode, second connecting electrode, and anode.

3. The display substrate according to claim 2, wherein: The first connecting electrode and the second connecting electrode are integrally formed with the corresponding anode.

4. The display substrate according to claim 2 further includes a pixel definition layer, wherein the pixel definition layer is located on a side of the transparent conductive layer away from the substrate, the pixel definition layer is formed with a plurality of pixel openings, each sub-pixel includes at least one pixel opening, an orthographic projection of the pixel opening on the substrate and an orthographic projection of a corresponding anode on the substrate have an overlapping area, and the transparent conductive layer is located in the light-emitting area of ​​the corresponding sub-pixel.

5. The display substrate according to claim 4, wherein: The second electrode of the second transistor is electrically connected to the corresponding first connection electrode through a first transfer via hole, and the orthographic projection of the first transfer via hole on the substrate is located within the range of the orthographic projection of the first connection electrode on the substrate; the second electrode of the third transistor is electrically connected to the corresponding second connection electrode through a second transfer via hole, and the orthographic projection of the second transfer via hole on the substrate is located within the range of the orthographic projection of the second connection electrode on the substrate; The shortest distance from the first transfer via to the edge of the corresponding pixel opening is smaller than the shortest distance from the second transfer via to the edge of the corresponding pixel opening, and the first transfer via and the second transfer via are located on both sides of the corresponding pixel opening.

6. The display substrate according to claim 5, wherein: The multiple sub-pixels are arranged along row and column directions. In the row direction, the distance between the first transfer vias in two adjacent sub-pixels includes a first distance and a second distance, the first distance is greater than the second distance, and the first distance and the second distance are alternately arranged along the row direction.

7. The display substrate according to claim 6, wherein: In the row direction, the distance between the second transfer vias in two adjacent sub-pixels includes a third distance and a fourth distance, the third distance is greater than the fourth distance, and the third distance and the fourth distance are alternately arranged along the row direction.

8. The display substrate according to claim 6, wherein: In the same sub-pixel, in the column direction, the second transistor and the third transistor are located on both sides of the corresponding anode, and the distance between the second transistor and the third transistor is greater than 0.5 times the size of the sub-pixel in the column direction.

9. The display substrate according to claim 2 further includes a plurality of data signal lines and a plurality of auxiliary data lines, the plurality of data signal lines are electrically connected to the plurality of auxiliary data lines, respectively, the data signal lines and the auxiliary data lines are located in different conductive layers, in a direction perpendicular to the plane where the display substrate is located, the conductive layer where the data signal lines and the auxiliary data lines are located is located between the substrate and the transparent conductive layer, and the orthographic projections of the plurality of data signal lines on the substrate are at least partially overlapped with the orthographic projections of the plurality of auxiliary data lines on the substrate, respectively.

10. The display substrate according to claim 9, wherein: The display substrate comprises a gate metal layer disposed on the base, and at least a portion of the auxiliary data lines is located on the gate metal layer.

11. The display substrate according to claim 10, wherein: The display substrate further comprises a shielding metal layer. In a direction perpendicular to the plane where the display substrate is located, the gate metal layer is located on a side of the shielding metal layer away from the base, and the plurality of data signal lines are located on the shielding metal layer.

12. The display substrate according to claim 11, wherein: The shielding metal layer is also provided with a plurality of first power lines, and the gate metal layer is also provided with a plurality of first power auxiliary lines, the plurality of first power lines are electrically connected to the plurality of first power auxiliary lines respectively, and the orthographic projections of the plurality of first power lines on the substrate at least partially overlap with the orthographic projections of the plurality of first power auxiliary lines on the substrate respectively.

13. The display substrate according to claim 12, wherein: The multiple sub-pixels form a plurality of pixel units arranged in an array, each pixel unit includes at least three sub-pixels, the gate metal layer is also provided with a plurality of first power connection lines, the same pixel unit includes two first power auxiliary lines, the two ends of the first power connection line located in the same pixel unit are respectively connected to the two first power auxiliary lines, on a plane parallel to the display substrate, the main part of the first power auxiliary line extends along the second direction, the main part of the first power connection line extends along the first direction, and the first direction intersects with the second direction.

14. The display substrate according to claim 11, wherein: The display substrate also includes a semiconductor layer. In a direction perpendicular to the plane where the display substrate is located, the semiconductor layer is located on a side of the shielding metal layer away from the base. The semiconductor layer is provided with a plurality of compensation connection lines. The shielding metal layer is also provided with a plurality of compensation signal lines. In a plane parallel to the display substrate, the compensation connection lines are strip structures extending along a first direction, and the compensation signal lines are strip structures extending along a second direction. The first direction intersects with the second direction, and the compensation connection lines are electrically connected to at least one compensation signal line.

15. The display substrate according to claim 9, wherein: The display substrate further comprises a source-drain metal layer, which is located on a side of the gate metal layer away from the base in a direction perpendicular to the plane of the display substrate, and the plurality of data signal lines are located on the source-drain metal layer.

16. The display substrate according to claim 15, wherein: The display substrate also includes a second blocking metal layer, and in a direction perpendicular to the plane where the display substrate is located, the second blocking metal layer is located between the base and the gate metal layer. The multiple auxiliary data lines include multiple first auxiliary data lines and multiple second auxiliary data lines, the multiple first auxiliary data lines are located in the second blocking metal layer, and the multiple second auxiliary data lines are located in the gate metal layer. The orthographic projections of the multiple first auxiliary data lines and the multiple second auxiliary data lines on the base have an overlapping area with the orthographic projections of the corresponding multiple data signal lines on the base, and the multiple first auxiliary data lines and the multiple second auxiliary data lines are electrically connected to the corresponding multiple data signal lines.

17. The display substrate according to claim 16, wherein: The source / drain metal layer is also provided with a plurality of first power lines, and the gate metal layer is also provided with a plurality of first power auxiliary lines, the plurality of first power lines are electrically connected to the plurality of first power auxiliary lines respectively, and the orthographic projections of the plurality of first power lines on the substrate at least partially overlap with the orthographic projections of the plurality of first power auxiliary lines on the substrate respectively.

18. The display substrate according to claim 17, wherein: The multiple sub-pixels form a plurality of pixel units arranged in an array, each pixel unit includes at least three sub-pixels, the display substrate also includes a semiconductor layer, in a direction perpendicular to the plane where the display substrate is located, the semiconductor layer is located on the side of the second shielding metal layer away from the base, the semiconductor layer is provided with a plurality of first power connection lines, the same pixel unit includes two first power lines, the two ends of the first power connection line located in the same pixel unit are electrically connected to the two first power lines respectively, on a plane parallel to the display substrate, the main part of the first power line extends along the second direction, the main part of the first power connection line extends along the first direction, and the first direction intersects with the second direction.

19. The display substrate according to claim 16, wherein: The second shielding metal layer is also provided with a plurality of compensation connection lines, and the source-drain metal layer is also provided with a plurality of compensation signal lines. On a plane parallel to the display substrate, the compensation connection lines are strip structures extending along a first direction, and the compensation signal lines are strip structures extending along a second direction. The first direction intersects with the second direction, and the compensation connection lines are electrically connected to at least one compensation signal line.

20. The display substrate according to claim 16, wherein: The display substrate also includes a first blocking metal layer. In a direction perpendicular to the plane where the display substrate is located, the first blocking metal layer is located between the base and the second blocking metal layer. The first blocking metal layer is provided with a plurality of first scanning signal lines, and the second blocking metal layer is provided with a plurality of first scanning signal auxiliary lines electrically connected to the plurality of first scanning signal lines, respectively. The orthographic projections of the plurality of first scanning signal lines on the base at least partially overlap with the orthographic projections of the plurality of first scanning signal auxiliary lines on the base.

21. The display substrate according to claim 20, wherein: The thickness of the first shielding metal layer is greater than the thickness of the second shielding metal layer.

22. The display substrate according to claim 2 further includes a first conductive layer, wherein the first conductive layer is located between the substrate and the transparent conductive layer, and the sub-pixel further includes a capacitor, wherein the first conductive layer includes a first electrode plate of the capacitor, wherein the first electrode plate is a transparent structure, and the anode is reused as a second electrode plate of the capacitor, and in the same sub-pixel, an orthographic projection of the first electrode plate on the substrate and an orthographic projection of the second electrode plate on the substrate have a first overlapping area, and the first overlapping area is located in a light-emitting area of ​​the sub-pixel.

23. The display substrate according to claim 1, further comprising a first conductive layer, wherein the first conductive layer is located between the substrate and the transparent conductive layer, the sub-pixel further comprises a capacitor, the first conductive layer comprises a first electrode plate of the capacitor, and the first electrode plate is a transparent structure; The display substrate also includes a gate metal layer, the transparent conductive layer is located on the gate metal layer, the transparent conductive layer is reused as the second electrode plate of the capacitor, the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the second electrode plate on the substrate have a first overlapping area, and the first overlapping area is located in the light-emitting area of ​​the sub-pixel.

24. A display device, wherein: Comprising the display substrate as claimed in any one of claims 1 to 23.

25. A method for preparing a display substrate, comprising: A plurality of sub-pixels and a plurality of transparent conductive layers are formed on one side of the substrate, wherein at least a portion of the sub-pixels include at least a second transistor and a third transistor, and a second electrode of the second transistor and a second electrode of the third transistor in the same sub-pixel are electrically connected via at least one transparent conductive layer.

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