Array substrate and display device

Abstract

The array substrate comprises a substrate base plate, a first electrode and a second electrode, the signal line is arranged on the substrate base plate; the buffer layer is positioned on one side, far away from the substrate, of the signal line; and the active layer is positioned on one side, far away from the substrate, of the buffer layer. The active layer comprises a first electrode region, a second electrode region and a channel region located between the first electrode region and the second electrode region. The first electrode region includes a first electrode. The second electrode region includes a second electrode. A first electrode extends through a via extending at least through the buffer layer to be connected to the signal line. The material of at least a portion of the second electrode and the first electrode is the same as the material of the channel region. A conductivity of the channel region is different from a conductivity of the first electrode and a conductivity of the second electrode.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to an array substrate and a display device. Background Art

[0002] Liquid crystal display panels have been widely used. Typically, a liquid crystal display panel includes an opposing substrate and an array substrate, which are arranged opposite each other. Thin-film transistors, gate lines, data lines, pixel electrodes, common electrodes, and common electrode signal lines are arranged on the array substrate and the opposing substrate. Liquid crystal material is injected between the two substrates to form a liquid crystal layer. A common problem associated with liquid crystal display panels is light leakage. To prevent light leakage, a black matrix is ​​provided on the opposing substrate. Liquid crystal display panels with a larger black matrix can better prevent light leakage. However, using a black matrix with a larger area reduces the aperture ratio of the liquid crystal display device.

[0003] Organic light-emitting diode (OLED) displays are driven by a drive current that needs to be kept constant to control illumination. The OLED display panel includes a plurality of pixel units configured with pixel drive circuits arranged in multiple rows and columns. Each pixel drive circuit includes a drive transistor having a gate terminal connected to a gate signal line for each row and a drain terminal connected to a data line for each column. When the row in which the pixel unit is selected is turned on, the switching transistor connected to the drive transistor is turned on, and a data voltage is applied from the data line to the drive transistor via the switching transistor, so that the drive transistor outputs a current corresponding to the data voltage to the OLED device. The OLED device is driven to emit light of corresponding brightness. Summary of the Invention

[0004] In one aspect, the present disclosure provides an array substrate comprising: a base substrate; a signal line on the base substrate; a buffer layer located on a side of the signal line away from the base substrate; and an active layer located on a side of the buffer layer away from the base substrate; the active layer comprising a first electrode region, a second electrode region, and a channel region between the first electrode region and the second electrode region; the first electrode region comprising a first electrode, and the second electrode region comprising a second electrode; wherein the first electrode extends through a via to connect to the signal line, the via extending at least through the buffer layer; the material of the second electrode and at least a portion of the first electrode is the same as the material of the channel region; and the conductivity of the channel region is different from the conductivity of the first electrode, and different from the conductivity of the second electrode.

[0005] Optionally, the material of at least a portion of the channel region, the second electrode and the first electrode includes M1O a N b, wherein M1 is a single metal or a combination of multiple metals, a>0, and b≥0, O represents oxygen element, and N represents nitrogen element.

[0006] Optionally, the channel region, the second electrode and at least a portion of the first electrode are an integrated structure.

[0007] Optionally, the channel region, the first electrode and the second electrode are an integrated structure and include M1O a N b , wherein M1 is a single metal or a combination of multiple metals, a>0, and b≥0, O represents oxygen element, and N represents nitrogen element.

[0008] Optionally, the first electrode includes a first electrode portion and a second electrode portion electrically connected to each other; and the first electrode portion and the second electrode portion are made of different materials.

[0009] Optionally, the material of the first electrode portion includes M1O a N b , wherein M1 is a single metal or a combination of multiple metals, a>0, and b≥0, O represents oxygen element, and N represents nitrogen element; the second electrode portion includes a metal material; and the first electrode portion, the second electrode and the channel region are an integrated structure.

[0010] Optionally, at least a portion of the second electrode portion is located in the via hole; and the orthographic projection of the second electrode portion on the base substrate at least partially overlaps with the orthographic projection of the signal line on the base substrate, and at least partially overlaps with the orthographic projection of the first electrode portion on the base substrate.

[0011] Optionally, the orthographic projection of the first electrode portion on the base substrate does not overlap with the orthographic projection of the signal line on the base substrate.

[0012] Optionally, the orthographic projection of the first electrode portion on the base substrate partially overlaps with the orthographic projection of the signal line on the base substrate.

[0013] Optionally, at least part of the first electrode portion extends into the second electrode portion.

[0014] Optionally, the array substrate further includes: an insulating layer located on a side of the channel region, the first electrode portion and the second electrode away from the base substrate; and a gate located on a side of the insulating layer away from the base substrate; wherein the second electrode portion and the gate are located on the same layer and include the same electrode material.

[0015] Optionally, in a cross-section along a plane perpendicular to the substrate and perpendicular to the direction extending the length of the signal line and intersecting the signal line and the via, the surface of the signal line other than the lower surface is exposed in the via; and the lower surface is the surface of the signal line in contact with the substrate.

[0016] Optionally, in the cross section, an upper surface of the signal line and two side surfaces respectively connecting the upper surface and the lower surface of the signal line are completely covered by the first electrode.

[0017] Optionally, in the cross section, only a portion of the upper surface of the signal line and only one of two side surfaces respectively connecting the upper surface and the lower surface of the signal line are covered by the first electrode.

[0018] Optionally, in a cross-section along a plane perpendicular to the substrate and perpendicular to the direction extending the length of the signal line and intersecting the signal line and the via, at least a portion of the upper surface of the signal line and at least one of the two side surfaces respectively connecting the upper surface and the lower surface of the signal line are not exposed in the via; and the lower surface is the surface of the signal line that contacts the substrate.

[0019] Optionally, in the cross section, only a portion of the upper surface of the signal line and at least one of two side surfaces respectively connecting the upper surface and the lower surface of the signal line are covered by the buffer layer.

[0020] Optionally, in the cross section, only a portion of the upper surface of the signal line and only one of two side surfaces respectively connecting the upper surface and the lower surface of the signal line are covered by the first electrode.

[0021] Optionally, in the cross section, only the upper surface of a central portion of the signal line is covered by the first electrode; and two side surfaces respectively connecting the upper surface and the lower surface of the signal line are covered by the buffer layer.

[0022] Optionally, the signal line is a data line configured to provide a data signal to the first electrode.

[0023] Optionally, the active layer includes a Hall mobility greater than or equal to 30 cm 2 / V·s metal oxide materials.

[0024] Optionally, the array substrate further includes: a light shading member located on the base substrate; and a gate line located on a side of the light shading member away from the base substrate; wherein the light shading member and the signal line are located on the same layer; and along the extension direction of the length of the signal line, the ratio of the line width of the gate line to the line width of the light shading member is in the range of 0.3 to 0.9.

[0025] In another aspect, the present disclosure provides a display device comprising the array substrate described herein and one or more integrated circuits connected to the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The following drawings are examples for illustration purposes only, in accordance with various disclosed embodiments, and are not intended to limit the scope of the invention.

[0027] Figure 1A is a plan view of an array substrate according to some embodiments of the present disclosure.

[0028] Figure 1B is a plan view of an array substrate according to some embodiments of the present disclosure.

[0029] Figure 1C is a plan view of an array substrate according to some embodiments of the present disclosure.

[0030] Figure 1D is a plan view of an array substrate according to some embodiments of the present disclosure.

[0031] Figure 1E is a plan view of an array substrate according to some embodiments of the present disclosure.

[0032] Figure 2A is a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0033] Figure 2B is a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0034] Figure 3A is a plan view of an array substrate according to some embodiments of the present disclosure.

[0035] Figure 3B is a plan view of an array substrate according to some embodiments of the present disclosure.

[0036] Figure 4 is a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0037] Figure 5 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0038] Figure 6is a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0039] Figure 7 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0040] Figure 8 is a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0041] Figure 9A is a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0042] Figure 9B is a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0043] Figure 10 is a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0044] Figure 11 is a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0045] Figure 12 is a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0046] Figure 13A is a plan view of an array substrate according to some embodiments of the present disclosure.

[0047] Figure 13B is a plan view of an array substrate according to some embodiments of the present disclosure.

[0048] Figure 14 is a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0049] Figure 15 It shows Figure 14 Schematic diagram of the structure of the first electrode of the array substrate described in .

[0050] Figure 16A is a plan view of an array substrate according to some embodiments of the present disclosure.

[0051] Figure 16B is a plan view of an array substrate according to some embodiments of the present disclosure.

[0052] Figure 17 is a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0053] Figure 18 It shows Figure 17 Schematic diagram of the structure of the first electrode of the array substrate described in .

[0054] Figure 19 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0055] Figure 20 is a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0056] Figure 21 It shows Figure 20 Schematic diagram of the structure of the first electrode of the array substrate described in .

[0057] Figure 22A is a plan view of an array substrate according to some embodiments of the present disclosure.

[0058] Figure 22B is a plan view of an array substrate according to some embodiments of the present disclosure.

[0059] Figure 23 is a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0060] Figure 24 It shows Figure 23 Schematic diagram of the structure of the first electrode of the array substrate described in .

[0061] Figures 25A to 25H Various arrangements of the second electrode portion relative to adjacent components in the array substrate according to some embodiments of the present disclosure are shown.

[0062] Figures 26A to 26C The process of manufacturing an array substrate according to some embodiments of the present disclosure is shown.

[0063] Figures 27A to 27C The process of manufacturing an array substrate according to some embodiments of the present disclosure is shown.

[0064] FIG. 28A to FIG. 28B The process of manufacturing an array substrate according to some embodiments of the present disclosure is shown.

[0065] Figures 29A to 29C The process of manufacturing an array substrate according to some embodiments of the present disclosure is shown.

[0066] Figures 30A to 30C The process of manufacturing an array substrate according to some embodiments of the present disclosure is shown.

[0067] Figures 31A to 31B The process of manufacturing an array substrate according to some embodiments of the present disclosure is shown.

[0068] Figures 32A to 32C The process of manufacturing an array substrate according to some embodiments of the present disclosure is shown.

[0069] Figures 33A to 33C The process of manufacturing an array substrate according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0070] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise forms disclosed.

[0071] The present disclosure particularly provides an array substrate and a display device, which substantially overcome one or more problems caused by the limitations and shortcomings of the prior art. In one aspect, the array substrate includes a base substrate; a signal line on the base substrate; a buffer layer, which is located on a side of the signal line away from the base substrate; and an active layer, which is located on a side of the buffer layer away from the base substrate; the active layer includes a first electrode region, a second electrode region, and a channel region between the first electrode region and the second electrode region; the first electrode region includes a first electrode, and the second electrode region includes a second electrode. Optionally, the first electrode extends through a via to connect to the signal line, and the via extends at least through the buffer layer. Optionally, the material of at least a portion of the second electrode and the first electrode is the same as the material of the channel region. Optionally, the conductivity of the channel region is different from the conductivity of the first electrode and different from the conductivity of the second electrode.

[0072] Figure 1A is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 2A is a cross-sectional view of an array substrate according to some embodiments of the present disclosure. Figure 2A Can be along Figure 1A Cross-sectional view of line A-A' in FIG. Figure 1A and Figure 2A In some embodiments, the array substrate includes a base substrate BS; a signal line SL (e.g., a data line configured to provide a data signal to a transistor) on the base substrate BS; a buffer layer BUF located on a side of the signal line SL away from the base substrate BS; and an active layer ACT located on a side of the buffer layer BUF away from the base substrate BS. The active layer ACT includes a first electrode region, a second electrode region, and a channel region CR between the first and second electrode regions. The first electrode region includes a first electrode E1, and the second electrode region includes a second electrode E2. In some embodiments, the array substrate further includes an insulating layer IN (e.g., a gate insulating layer) located on a side of the active layer ACT away from the buffer layer BUF (e.g., located on a side of the first electrode E1, the channel region CR, and the second electrode E2 away from the buffer layer BUF).

[0073] In some embodiments, the array substrate further includes a gate G located on a side of the insulating layer IN away from the channel region CR. The gate G defines the area of ​​the channel region CR. For example, the orthographic projection of the gate G on the base substrate substantially overlaps with the orthographic projection of the channel region CR on the base substrate BS.

[0074] In some embodiments, the array substrate further includes a light shielding member LS located on the base substrate BS. Optionally, the light shielding member LS is located on the same layer as the signal line SL, for example, formed using the same mask and / or the same material in the same patterning process. The light shielding member LS is configured to prevent light from irradiating the channel region CR. Optionally, the orthographic projection of the light shielding member LS on the base substrate BS overlaps at least partially (for example, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) with the orthographic projection of the channel region CR on the base substrate BS.

[0075] In some embodiments, the array substrate further includes a first passivation layer PVX1, which is located on the side of the gate G away from the base substrate BS; a planarization layer PLN, which is located on the side of the first passivation layer PVX1 away from the base substrate BS; a second passivation layer PVX2, which is located on the side of the planarization layer PLN away from the first passivation layer PVX1; and a pixel electrode PE, which is located on the side of the second passivation layer PVX2 away from the planarization layer PLN. The pixel electrode PE optionally extends through at least the second passivation layer PVX2, the planarization layer PLN and the first passivation layer PVX1 to connect to the second electrode E2. Optionally, as Figure 2A As shown, the pixel electrode PE also extends through the insulating layer IN. The array substrate includes a via hole extending through the second passivation layer PVX2, the planarization layer PLN, the first passivation layer PVX1 and the insulating layer IN, as shown in FIG. Figure 2A shown.

[0076] In some embodiments, the array substrate further includes a common electrode CE located on a side of the planarization layer PLN away from the first passivation layer PVX1 . Optionally, the common electrode CE is located on a side of the second passivation layer PVX2 close to the planarization layer PLN.

[0077] The array substrate can be implemented in various appropriate display panels. Suitable array substrates include liquid crystal display array substrates, organic light emitting diode array substrates, micro light emitting diode array substrates, and mini light emitting diode array substrates.

[0078] In some embodiments, the array substrate is a liquid crystal display array substrate. The pixel electrode PE is a pixel electrode in each of the multiple sub-pixels in the liquid crystal display array substrate. The common electrode CE is a common electrode in the liquid crystal display array substrate. In one example, the common electrode CE is an electrode extending over the multiple sub-pixels in the liquid crystal display array substrate.

[0079] In some embodiments, the array substrate is an LED display array substrate. The pixel electrode PE serves as the anode of each of the multiple LEDs in the LED display array substrate. The common electrode CE serves as the cathode in the LED display array substrate. In one example, the common electrode is a cathode extending over multiple sub-pixels in the LED display array substrate. In another example, the common electrode CE is located on a side of the light-emitting layer and the pixel electrode PE that is away from the base substrate BS.

[0080] Various suitable semiconductor materials and various suitable manufacturing methods can be used to manufacture the channel region CR. In some embodiments, the semiconductor material includes M1O a N b , where M1 is a single metal or a combination of multiple metals, a>0 and b≥0, O represents an oxygen element, and N represents a nitrogen element. For example, the semiconductor material is a metal oxide material or a metal oxynitride material. Examples of suitable metal oxide materials include, but are not limited to, indium gallium zinc oxide, zinc oxide, gallium oxide, indium oxide, HfInZnO (HIZO), amorphous InGaZnO (amorphous IGZO), InZnO, amorphous InZnO, ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O. Examples of suitable metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or combinations thereof. In one example, the channel region CR includes indium gallium zinc oxide.

[0081] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the first electrode E1 or the second electrode E2. Examples of suitable conductive materials include metals, alloys, metal oxides, and any combination thereof. Examples of suitable conductive materials for manufacturing the first electrode E1 or the second electrode E2 include, but are not limited to, molybdenum, aluminum, titanium, gold, copper, hafnium, tantalum, alloys (e.g., aluminum neodymium (AlNd), molybdenum niobium (MoNb)), and laminated materials, such as molybdenum-neodymium-copper laminated structures, molybdenum-niobium-titanium (MTD) laminated structures, molybdenum-nickel-titanium-copper laminated structures, molybdenum-nickel-titanium-copper-molybdenum-nickel-titanium laminated structures, molybdenum-neodymium-copper laminated structures, molybdenum-aluminum-aluminum laminated structures, molybdenum-aluminum-molybdenum laminated structures, MoNb-copper-MoNb laminated structures, and AlNd-molybdenum-AlNd laminated structures.

[0082] In some embodiments, the conductive material used to manufacture the first electrode E1 or the second electrode E2 includes M1O a N b , where M1 is a single metal or a combination of multiple metals, a>0 and b≥0, O represents an oxygen element, and N represents a nitrogen element. For example, the conductive material is a metal oxide material or a metal oxynitride material. Examples of suitable metal oxide materials include, but are not limited to, indium gallium zinc oxide, zinc oxide, gallium oxide, indium oxide, HfInZnO (HIZO), InGaZnO (IGZO), crystalline, InZnO, amorphous InZnO, ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O, InGaO (IGO), InGaZnSnO (IGZTO), and lanthanide-doped oxide semiconductors (Ln-OS). The crystallinity can be amorphous, partially crystalline, or crystalline. Examples of suitable metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or combinations thereof. In one example, the first electrode E1 or the second electrode E2 includes indium gallium zinc oxide.

[0083] In some embodiments, when the material of the channel region CR, the first electrode E1 or the second electrode E2 includes M1O a N b When the first electrode E1 or the second electrode E2 is different from the channel region CR in that the first electrode E1 or the second electrode E2 is subjected to a process to make it more conductive. The conductivity of the channel region CR is different from the conductivity of the first electrode E1 and different from the conductivity of the second electrode E2. In one example, when the material of the channel region CR, the first electrode E1 or the second electrode E2 includes M1O a N b When M1O in the first electrode E1 or the second electrode E2 a N b In another example, when the material of the channel region CR, the first electrode E1 or the second electrode E2 includes M1O a N b When M1O in the first electrode E1 or the second electrode E2 a N b In another example, when the material of the channel region CR, the first electrode E1 or the second electrode E2 includes M1O a N b When M1O in the first electrode E1 or the second electrode E2 a N bAlternatively, using a 1×10 15 atoms / cm 3 to about 1×10 20 atoms / cm 3 The doping concentration is within the range of about 1×10 15 atoms / cm 3 to about 1×10 16 atoms / cm 3 , about 1×10 16 atoms / cm 3 to about 1×10 17 atoms / cm 3 , about 1×10 17 atoms / cm 3 to about 1×10 18 atoms / cm 3 , about 1×10 18 atoms / cm 3 to about 1×10 20 atoms / cm 3 , and about 1×10 19 atoms / cm 3 to about 1×10 20 atoms / cm 3 , to perform a lightly doped drain process. Optionally, the lightly doped drain process is performed using an n-type dopant to enhance conductivity. Examples of n-type dopants include elements from Group VA of the periodic table, including nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi).

[0084] In some embodiments, the material of the channel region CR, the first electrode E1, and the second electrode E2 includes M1O a N b The channel region CR, the first electrode E1 and the second electrode E2 are an integrated structure. Figure 1A and Figure 2A shown.

[0085] In some embodiments, the active layer ACT includes a Hall mobility greater than or equal to 30 cm 2 / V·s metal oxide materials.

[0086] In some embodiments, the array substrate includes a via hole v extending at least through the buffer layer BUF. At least a portion of the first electrode E1 is located in the via hole v. Optionally, the first electrode E1 extends through the via hole v to be connected to the signal line SL.

[0087] In some embodiments, reference Figure 1A and Figure 2A, in a cross section (eg, along a plane perpendicular to the substrate BS and perpendicular to the direction LD extending the length of the signal line SL and intersecting the signal line SL and the via hole v) Figure 2A In the cross section shown in FIG, 2 , the surfaces of the signal line SL other than the surface in contact with the base substrate BS are exposed in the via v. For example, in the cross section, the upper surface of the signal line SL and the two side surfaces connecting the upper surface and the lower surface of the signal line SL are completely exposed in the via v. The lower surface is the surface of the signal line SL in contact with the base substrate BS.

[0088] In some embodiments, reference Figure 1A and Figure 2A , in a cross section (eg, along a plane perpendicular to the substrate BS and perpendicular to the direction LD extending the length of the signal line SL and intersecting the signal line SL and the via hole v) Figure 2A In the cross section shown in FIG, 2 , the first electrode E1 covers all surfaces of the signal line SL except the surface in contact with the base substrate BS. For example, in this cross section, the upper surface of the signal line SL and the two side surfaces connecting the upper surface and the lower surface of the signal line SL are completely covered by the first electrode E1. The lower surface is the surface of the signal line SL in contact with the base substrate BS.

[0089] The “overlap” and “coverage” mentioned herein may refer to the spatial positional relationship between the film layers themselves, or the positional relationship between the orthographic projections of the film layers on the substrate.

[0090] In some embodiments, reference Figure 1A The first electrode E1 intersects the signal line SL. The orthographic projection of the first electrode E1 on the base substrate intersects the orthographic projection of the signal line SL on the base substrate.

[0091] Figure 1B is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 2B is a cross-sectional view of an array substrate according to some embodiments of the present disclosure. Figure 2B Can be along Figure 1B Cross-sectional view of line BB' in FIG. Figure 1B and Figure 2B In some embodiments, the array substrate includes a via hole v passing through at least the buffer layer BUF. At least a portion of the first electrode E1 is located in the via hole v. Optionally, the first electrode E1 extends through the via hole v to be connected to the signal line SL.

[0092] In some embodiments, reference Figure 1B and Figure 2B , in a cross section (eg, along a plane perpendicular to the substrate BS and perpendicular to the direction LD extending the length of the signal line SL and intersecting the signal line SL and the via hole v) Figure 2BIn the cross section shown in FIG, 2 , the surfaces of the signal line SL other than the surface in contact with the base substrate BS are exposed in the via v. For example, in the cross section, the upper surface of the signal line SL and the two side surfaces connecting the upper and lower surfaces of the signal line SL are completely exposed in the via v. The lower surface is the surface of the signal line in contact with the base substrate BS.

[0093] In some embodiments, reference Figure 1B and Figure 2B , in a cross section (eg, along a plane perpendicular to the substrate BS and perpendicular to the direction LD extending the length of the signal line SL and intersecting the signal line SL and the via hole v) Figure 2B In the cross section shown in FIG, 2 , the surfaces of the signal line SL other than the surface in contact with the base substrate BS are exposed in the via v. For example, in the cross section, the upper surface of the signal line SL and the two side surfaces connecting the upper and lower surfaces of the signal line SL are completely exposed in the via v. The lower surface is the surface of the signal line in contact with the base substrate BS.

[0094] In some embodiments, reference Figure 1B and Figure 2B , in a cross section (eg, along a plane perpendicular to the substrate BS and perpendicular to the direction LD extending the length of the signal line SL and intersecting the signal line SL and the via hole v) Figure 2B In the cross section shown in FIG, 2 , the surface of the signal line SL, excluding the surface in contact with the base substrate BS, is only partially covered by the first electrode E1. For example, in this cross section, only a portion of the upper surface of the signal line SL and only one of the two side surfaces connecting the upper and lower surfaces of the signal line SL are covered by the first electrode E1. The lower surface is the surface of the signal line SL in contact with the base substrate BS.

[0095] In some embodiments, reference Figure 1B , the first electrode E1 only partially intersects the signal line SL. The orthographic projection of the first electrode E1 on the base substrate only partially intersects the orthographic projection of the signal line SL on the base substrate.

[0096] Reference Figure 1A and Figure 1B In some embodiments, the orthographic projection of the first electrode E1 on the base substrate only partially overlaps with the orthographic projection of the via v on the base substrate.

[0097] Figure 1C is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 2A Can be along Figure 1C Cross-sectional view of line C-C' in FIG. Figure 1C and Figure 2A In some embodiments, the orthographic projection of the first electrode E1 on the substrate completely covers the orthographic projection of the via v on the substrate.

[0098] Reference Figure 1A In some embodiments, the orthographic projection of the first electrode E1 on the base substrate overlaps with the orthographic projection of the middle portion of the via v on the base substrate, does not overlap with the orthographic projection of the upper portion of the via v on the base substrate, and does not overlap with the orthographic projection of the lower portion of the via v on the base substrate. The upper portion, the middle portion, and the lower portion are arranged sequentially along the length direction of the signal line SL.

[0099] Figure 1D is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 2A Can be along Figure 1D Cross-sectional view of line D-D' in FIG. Figure 1D and Figure 2A In some embodiments, the orthographic projection of the first electrode E1 on the substrate overlaps with the orthographic projection of the upper portion of the via v on the substrate, but does not overlap with the orthographic projection of the lower portion of the via v on the substrate. The upper portion and the lower portion are arranged sequentially along the length direction of the signal line SL.

[0100] Figure 1E is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 2A Can be along Figure 1E Cross-sectional view of line E-E' in FIG. Figure 1E and Figure 2A In some embodiments, the orthographic projection of the first electrode E1 on the substrate overlaps with the orthographic projection of the lower portion of the via v on the substrate, but does not overlap with the orthographic projection of the upper portion of the via v on the substrate. The upper portion and the lower portion are arranged sequentially along the length direction of the signal line SL.

[0101] Reference Figures 1A to 1E In some embodiments, the array substrate further includes a second signal line SL2. In some embodiments, the second signal line SL2 is a gate line configured to provide a gate drive signal to the transistor. In some embodiments, the gate is a portion of the gate line GL. The orthographic projection of the channel region CR on the base substrate overlaps with the orthographic projection of the gate on the base substrate.

[0102] In some embodiments, the array substrate includes a light shielding member LS located on a base substrate and a gate line (e.g., a second signal line SL2) located on a side of the light shielding member LS away from the base substrate. The light shielding member LS is located on the same layer as the signal line SL. Optionally, along the extension direction of the signal line length, the ratio of the line width of the gate line to the line width of the light shielding member is in the range of 0.3 to 0.9, for example, 0.3 to 0.4, 0.4 to 0.5, 0.5 to 0.6, 0.6 to 0.7, 0.7 to 0.8, or 0.8 to 0.9. The inventors of the present disclosure have found that, through this layout, it is possible to ensure light shielding, maintain the aperture ratio in the array substrate, and avoid a short circuit between the gate line and the light shielding member LS.

[0103] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, the light shielding member LS and the signal line SL are located in the same layer when they are formed as a result of one or more steps of the same patterning process performed on materials deposited in the same deposition process. In another example, the light shielding member LS and the signal line SL can be formed in the same layer by performing the steps of forming the light shielding member LS and forming the signal line SL simultaneously. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in a cross-sectional view is the same.

[0104] Figure 3A is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 3B is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 4 is a cross-sectional view of an array substrate according to some embodiments of the present disclosure. Figure 4 Can be along Figure 3A F-F' line or along Figure 3B Cross-sectional view of line G-G' in FIG. Figure 3A 、 Figure 3B and Figure 4 In some embodiments, in a cross section along a plane perpendicular to the substrate BS and perpendicular to the length of the signal line SL and intersecting the signal line SL and the via v (eg Figure 4 In the cross section shown in FIG, at least a portion of the signal line SL is covered by the buffer layer BUF, and at least a portion of the upper surface of the signal line SL is not exposed in the via v. For example, in this cross section, a first portion of the signal line SL is covered by the buffer layer BUF, while a second portion of the signal line SL is not. In this cross section, the upper surface of the first portion of the signal line SL is not exposed in the via v, while the upper surface of the second portion of the signal line SL is exposed by the via v. The first portion is located on a side of the second portion away from the channel region CR.

[0105] In some embodiments, reference Figure 3A 、 Figure 3B and Figure 4 , in a cross section (eg, along a plane perpendicular to the substrate BS and perpendicular to the direction LD extending the length of the signal line SL and intersecting the signal line SL and the via hole v) Figure 4 In the cross section shown in FIG, 2 , the surface of the signal line SL, excluding the surface in contact with the base substrate BS, is only partially covered by the first electrode E1. For example, in this cross section, only a portion of the upper surface of the signal line SL and only one of the two side surfaces connecting the upper and lower surfaces of the signal line SL are covered by the first electrode E1. The lower surface is the surface of the signal line SL in contact with the base substrate BS.

[0106] Figure 5 is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 6 is a cross-sectional view of an array substrate according to some embodiments of the present disclosure. Figure 6 Can be along Figure 5 Cross-sectional view of line H-H' in FIG. Figure 5 and Figure 6 In some embodiments, in a cross section along a plane perpendicular to the substrate BS and perpendicular to the length of the signal line SL and intersecting the signal line SL and the via v (eg Figure 6 In the cross section shown in FIG, at least a portion of the signal line SL is covered by the buffer layer BUF, and at least a portion of the upper surface of the signal line SL is not exposed in the via v. For example, in this cross section, the first portion of the signal line SL is not covered by the buffer layer BUF, while the second portion of the signal line SL is covered by the buffer layer BUF. In this cross section, the upper surface of the first portion of the signal line SL is exposed by the via v, while the upper surface of the second portion of the signal line SL is not exposed in the via v. The first portion is located on a side of the second portion away from the channel region CR.

[0107] In some embodiments, reference Figure 5 and Figure 6 , in a cross section (eg, along a plane perpendicular to the substrate BS and perpendicular to the direction LD extending the length of the signal line SL and intersecting the signal line SL and the via hole v) Figure 6 In the cross section shown in FIG, 2 , the surface of the signal line SL, excluding the surface in contact with the base substrate BS, is only partially covered by the first electrode E1. For example, in this cross section, only a portion of the upper surface of the signal line SL and only one of the two side surfaces connecting the upper and lower surfaces of the signal line SL are covered by the first electrode E1. The lower surface is the surface of the signal line SL in contact with the base substrate BS.

[0108] Figure 7 is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 8 is a cross-sectional view of an array substrate according to some embodiments of the present disclosure. Figure 8 Can be along Figure 7 Cross-sectional view of line I-I' in Fig. Figure 7 and Figure 8 In some embodiments, in a cross section along a plane perpendicular to the substrate BS and perpendicular to the length of the signal line SL and intersecting the signal line SL and the via v (eg Figure 6 ), at least a portion of the signal line SL is covered by the buffer layer BUF, and at least a portion of the upper surface of the signal line SL is not exposed in the via v. For example, in this cross section, the central portion of the signal line SL is not covered by the buffer layer BUF, while portions on both sides of the signal line SL are covered by the buffer layer BUF. In this cross section, the upper surface of the central portion of the signal line SL is exposed by the via v, while the upper surfaces of portions on both sides of the signal line SL are not exposed in the via v.

[0109] In some embodiments, reference Figure 7 and Figure 8 , in a cross section (eg, along a plane perpendicular to the substrate BS and perpendicular to the direction LD extending the length of the signal line SL and intersecting the signal line SL and the via hole v) Figure 8 In the cross-section shown in FIG, only a portion of the upper surface of the signal line SL is covered by the first electrode E1. The upper surface of the remaining portion of the signal line SL and the two side surfaces connecting the upper and lower surfaces of the signal line SL are not covered by the first electrode E1. The lower surface is the surface of the signal line SL that contacts the base substrate BS.

[0110] In some embodiments, the insulating layer IN extends substantially over the entire array substrate. Figures 1A to 1E 、 Figure 2A 、 Figure 2B 、 Figure 3A 、 Figure 3B as well as Figures 4 to 8 shown.

[0111] In some embodiments, the insulating layer does not substantially extend across the entire array substrate. For example, an orthographic projection of the insulating layer on the base substrate at least partially does not overlap with an orthographic projection of the signal line on the base substrate, and at least partially does not overlap with an orthographic projection of the first electrode or the second electrode on the base substrate.

[0112] Figure 9A is a cross-sectional view of an array substrate according to some embodiments of the present disclosure. Figure 9A The structure shown is Figure 2A Similar structure as shown, but with Figure 2A The difference of the structure shown is at least that the insulating layer IN does not substantially extend over the entire array substrate. Figure 9A shown.

[0113] Figure 9Bis a cross-sectional view of an array substrate according to some embodiments of the present disclosure. Figure 9B The structure shown is Figure 2B Similar structure as shown, but with Figure 2B The difference of the structure shown is at least that the insulating layer IN does not substantially extend over the entire array substrate. Figure 9B shown.

[0114] Figure 10 is a cross-sectional view of an array substrate according to some embodiments of the present disclosure. Figure 10 The structure shown is Figure 4 Similar structure as shown, but with Figure 10 The difference of the structure shown is at least that the insulating layer IN does not substantially extend over the entire array substrate. Figure 10 shown.

[0115] Figure 11 is a cross-sectional view of an array substrate according to some embodiments of the present disclosure. Figure 11 The structure shown is Figure 6 Similar structure as shown, but with Figure 11 The difference of the structure shown is at least that the insulating layer IN does not substantially extend over the entire array substrate. Figure 11 shown.

[0116] Figure 12 is a cross-sectional view of an array substrate according to some embodiments of the present disclosure. Figure 12 The structure shown is Figure 8 Similar structure as shown, but with Figure 12 The difference of the structure shown is at least that the insulating layer IN does not substantially extend over the entire array substrate. Figure 12 shown.

[0117] Figure 13A is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 14 is a cross-sectional view of an array substrate according to some embodiments of the present disclosure. Figure 15 It shows Figure 14 Schematic diagram of the structure of the first electrode of the array substrate described in . Figure 14 Can be along Figure 13A The cross-sectional view of the J-J' line in FIG. Figure 13A 、 Figure 14 and Figure 15 In some embodiments, the first electrode E1 includes a first electrode portion E1-1 and a second electrode portion E1-2 that are electrically connected to each other. The first electrode portion E1-1 and the second electrode portion E1-2 are made of different materials. Optionally, at least a portion of the first electrode portion E1-1 extends into the second electrode portion E1-2.

[0118] The first electrode portion E1-1 may be manufactured using various suitable conductive materials and various suitable manufacturing methods. In some embodiments, the conductive material used to manufacture the first electrode portion E1-1 includes M1O a N b , where M1 is a single metal or a combination of multiple metals, a>0 and b≥0, O represents oxygen, and N represents nitrogen. For example, the conductive material is a metal oxide material or a metal oxynitride material. In some embodiments, when the material of the channel region CR, the first electrode portion E1-1, and the second electrode E2 includes M1O a N b When the first electrode portion E1-1 or the second electrode E2 is different from the channel region CR in that the first electrode portion E1-1 or the second electrode E2 is subjected to a process to make it more conductive. The conductivity of the channel region CR is different from the conductivity of the first electrode E1 and different from the conductivity of the second electrode E2. In one example, when the material of the channel region CR, the first electrode portion E1-1 or the second electrode E2 includes M1O a N b When M1O in the first electrode portion E1-1 or the second electrode E2 a N b In another example, when the material of the channel region CR, the first electrode portion E1-1 or the second electrode E2 includes M1O a N b When M1O in the first electrode portion E1-1 or the second electrode E2 a N b In another example, when the material of the channel region CR, the first electrode portion E1-1 or the second electrode E2 includes M1O a N b When M1O in the first electrode portion E1-1 or the second electrode E2 a N b Undergoes an oxide replenishment process.

[0119] In some embodiments, the materials of the channel region CR, the first electrode portion E1-1, and the second electrode E2 include M1O a N b The channel region CR, the first electrode portion E1-1 and the second electrode E2 are an integrated structure. Figure 13A 、 Figure 14 and Figure 15 shown.

[0120] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second electrode portion E1-2. Examples of suitable conductive materials include metals, alloys, metal oxides, and any combination thereof. In one example, the second electrode portion E1-2 includes a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure, or an MTD-copper-MTD stacked structure.

[0121] In some embodiments, the array substrate includes a via hole v extending at least through the buffer layer BUF. At least a portion of the second electrode portion E1-2 is located in the via hole v. Optionally, the second electrode portion E1-2 extends through the via hole v to connect to the signal line SL. Figure 14 In one example shown, the via v extends through the insulating layer IN and the buffer layer BUF. In another example, the second electrode portion E1-2 and the gate G include the same conductive material and are formed in the same patterning process using the same mask.

[0122] Reference Figure 13A and Figure 14 , in a cross section (eg, along a plane perpendicular to the substrate BS and perpendicular to the direction LD extending the length of the signal line SL and intersecting the signal line SL and the via hole v) Figure 14 In the cross section shown in FIG, 2 , all surfaces of the signal line SL, except the surface in contact with the base substrate BS, are exposed in the via v. For example, in this cross section, the upper surface of the signal line SL and the two side surfaces connecting the upper and lower surfaces of the signal line SL are completely exposed in the via v. The lower surface is the surface of the signal line SL in contact with the base substrate BS. In the cross section, the second electrode portion E1-2 covers the upper surface of the signal line SL and the two side surfaces connecting the upper and lower surfaces of the signal line SL.

[0123] In some embodiments, reference Figure 13A The second electrode portion E1-2 intersects the signal line SL. The orthographic projection of the second electrode portion E1-2 on the base substrate intersects the orthographic projection of the signal line SL on the base substrate.

[0124] In some embodiments, reference Figure 13A , the maximum width of the second electrode portion E1-2 along the length direction LD is greater than the maximum width of the first electrode portion E1-1 along the length direction LD.

[0125] Figure 13B is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 14 Can be along Figure 13B Cross-sectional view of line K-K' in Fig. Figure 13B and Figure 14In some embodiments, the maximum width of the second electrode portion E1 - 2 along the length direction LD is less than or equal to the maximum width of the first electrode portion E1 - 1 along the length direction LD.

[0126] Figure 16A is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 16B is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 17 is a cross-sectional view of an array substrate according to some embodiments of the present disclosure. Figure 18 It shows Figure 17 Schematic diagram of the structure of the first electrode of the array substrate described in . Figure 17 Can be along Figure 16A L-L' line or along Figure 16B Cross-sectional view of the M-M' line in FIG. Figure 16A 、 Figure 16B and Figure 17 In some embodiments, in a cross section along a plane perpendicular to the substrate BS and perpendicular to the length of the signal line SL and intersecting the signal line SL and the via v (eg Figure 17 In the cross section shown in FIG, at least a portion of the signal line SL is covered by the buffer layer BUF, and at least a portion of the upper surface of the signal line SL is not exposed in the via v. For example, in this cross section, a first portion of the signal line SL is covered by the buffer layer BUF, while a second portion of the signal line SL is not. In this cross section, the upper surface of the first portion of the signal line SL is not exposed in the via v, while the upper surface of the second portion of the signal line SL is exposed by the via v. The first portion is located on a side of the second portion away from the channel region CR.

[0127] In a cross-section, the upper surface of the signal line SL is partially covered by the second electrode portion E1-2 and partially covered by the buffer layer BUF. In one example, in a cross-section, the upper surface of a first portion of the signal line SL is covered by the buffer layer BUF, while the upper surface of a second portion of the signal line SL is covered by the second electrode portion E1-2. The first portion is located on a side of the second portion away from the channel region CR.

[0128] In one example, in a cross section, a first side of the signal line SL is covered by the buffer layer BUF, and a second side of the signal line SL is covered by the second electrode portion E1-2. The first side is located on a side of the second side away from the channel region CR.

[0129] Figure 19 is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 20 is a cross-sectional view of an array substrate according to some embodiments of the present disclosure. Figure 21 It shows Figure 20Schematic diagram of the structure of the first electrode of the array substrate described in . Figures 19 to 21 In some embodiments, in a cross section along a plane perpendicular to the substrate BS and perpendicular to the length of the signal line SL and intersecting the signal line SL and the via v (eg Figure 20 In the cross section shown in FIG, at least a portion of the signal line SL is covered by the buffer layer BUF, and at least a portion of the upper surface of the signal line SL is not exposed in the via v. For example, in this cross section, the first portion of the signal line SL is not covered by the buffer layer BUF, while the second portion of the signal line SL is covered by the buffer layer BUF. In this cross section, the upper surface of the first portion of the signal line SL is exposed by the via v, while the upper surface of the second portion of the signal line SL is not exposed in the via v. The first portion is located on a side of the second portion away from the channel region CR.

[0130] In a cross-section, the upper surface of the signal line SL is partially covered by the second electrode portion E1-2 and partially covered by the buffer layer BUF. In one example, in a cross-section, the upper surface of a first portion of the signal line SL is covered by the second electrode portion E1-2, while the upper surface of a second portion of the signal line SL is covered by the buffer layer BUF. The first portion is located on a side of the second portion away from the channel region CR.

[0131] In one example, in a cross section, a first side of the signal line SL is covered by the second electrode portion E1-2, and a second side of the signal line SL is covered by the buffer layer BUF. The first side is located on a side of the second side away from the channel region CR.

[0132] Figure 22A is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 22B is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 23 is a cross-sectional view of an array substrate according to some embodiments of the present disclosure. Figure 24 It shows Figure 23 Schematic diagram of the structure of the first electrode of the array substrate described in . Figure 22A 、 Figure 22B 、 Figure 23 and Figure 24 In some embodiments, in a cross section along a plane perpendicular to the substrate BS and perpendicular to the length of the signal line SL and intersecting the signal line SL and the via v (eg Figure 23In the cross section shown in FIG, at least a portion of the signal line SL is covered by the buffer layer BUF, and at least a portion of the upper surface of the signal line SL is not exposed in the via hole. For example, in this cross section, the middle portion of the signal line SL is not covered by the buffer layer BUF, while the side portions of the signal line SL are covered by the buffer layer BUF. In this cross section, the upper surface of the middle portion of the signal line SL is exposed by the via hole v, while the upper surfaces of the side portions of the signal line SL are not exposed in the via hole v.

[0133] In a cross section, the upper surface of the signal line SL is partially covered by the second electrode portion E1-2 and partially covered by the buffer layer BUF. In one example, in a cross section, the upper surface of the middle portion of the signal line SL is covered by the second electrode portion E1-2, while the upper surfaces of the two side portions of the signal line SL are covered by the buffer layer BUF.

[0134] In one example, in the cross section, both side surfaces of the signal line SL are covered by the buffer layer BUF.

[0135] The second electrode portion may be arranged at various positions relative to the first electrode portion, the signal line, and the via. Figures 25A to 25H 1 shows various arrangements of the second electrode portion relative to adjacent components in the array substrate according to some embodiments of the present disclosure. Figures 25A to 25H , the orthographic projection of the second electrode portion E1-2 on the base substrate partially overlaps with the orthographic projection of the first electrode portion E1-1 on the base substrate, and also overlaps with the orthographic projection of the signal line SL on the base substrate. In some embodiments, referring to Figure 25B 、 Figure 25D 、 Figure 25F and Figure 25H , the orthographic projection of the first electrode portion E1-1 on the base substrate partially overlaps with the orthographic projection of the signal line SL on the base substrate. Figure 25A 、 Figure 25C 、 Figure 25E and Figure 25G , the orthographic projection of the first electrode portion E1 - 1 on the base substrate does not overlap with the orthographic projection of the signal line SL on the base substrate.

[0136] Reference Figures 25A to 25H , the orthographic projection of the via hole v on the base substrate partially overlaps with the orthographic projection of the first electrode portion E1-1 on the base substrate, and partially overlaps with the orthographic projection of the signal line SL on the base substrate. In some embodiments, referring to Figure 25D , the orthographic projection of the second electrode portion E1-2 on the substrate completely covers the orthographic projection of the via hole v on the substrate. In some embodiments, referring to Figure 25E and Figure 25F, the orthographic projection of the via hole v on the substrate completely covers the orthographic projection of the second electrode portion E1-2 on the substrate. Figure 25A 、 Figure 25B 、 Figure 25C 、 Figure 25G and Figure 25H , the orthographic projection of the second electrode portion E1 - 2 on the base substrate partially overlaps with the orthographic projection of the via hole v on the base substrate.

[0137] In conventional array substrates, parasitic capacitance along data lines significantly limits the pixel-per-inch resolution and refresh rate of the array substrate. The present disclosure provides an array substrate that eliminates these limitations. Furthermore, the present array substrate significantly reduces the resistance between the source and data lines, thereby improving the on-state current (Ion) parameter of the thin-film transistor.

[0138] In another aspect, the present invention provides a display device comprising an array substrate as described herein or manufactured by the methods described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo albums, GPS devices, and the like. Optionally, the display device is a liquid crystal display device. Optionally, the display device is an organic light-emitting diode display device. Optionally, the display device is a micro light-emitting diode display device. Optionally, the display device is a miniature light-emitting diode display device.

[0139] On the other hand, the present disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a signal line on a base substrate; forming a buffer layer on a side of the signal line away from the base substrate; forming a first electrode, and forming an active layer on a side of the buffer layer away from the base substrate; the active layer includes a first electrode region, a second electrode region, and a channel region located between the first electrode region and the second electrode region; the first electrode region includes a first electrode, and the second electrode region includes a second electrode. Optionally, the method also includes forming a via extending at least through the buffer layer; and the first electrode is formed to extend through the via to connect to the signal line. Optionally, the material of at least a portion of the second electrode and the first electrode is the same as the material of the channel region, and is subjected to a process to make them conductive. The conductivity of the channel region is different from the conductivity of the first electrode and different from the conductivity of the second electrode.

[0140] Figures 26A to 26C The process of manufacturing an array substrate according to some embodiments of the present disclosure is shown. Figure 26AA signal line SL and a light shielding member LS are formed on a substrate BS; a buffer layer BUF is formed on the side of the signal line SL and the light shielding member LS away from the substrate BS; a semiconductor material layer SML is formed on the side of the buffer layer BUF away from the substrate BS; an insulating layer IN is formed on the side of the semiconductor material layer SML away from the substrate BS; a photoresist layer PR is formed on the side of the insulating layer IN away from the substrate BS; and a lightly doped drain process is performed to make the portions of the semiconductor material layer SML corresponding to the first and second electrodes more conductive. The orthographic projection of the photoresist layer PR on the substrate BS overlaps with the orthographic projection of the portion of the semiconductor material layer SML corresponding to the channel region CR on the substrate BS. After the lightly doped drain process, the portions of the semiconductor material layer SML corresponding to the first and second electrodes become more conductive.

[0141] Reference Figure 26B , forming a via hole v, which extends through the insulating layer IN and the buffer layer BUF, exposing at least a portion of the signal line SL (eg Figure 26B The portion of the semiconductor material layer SML corresponding to the first electrode extends into the via hole v.

[0142] Reference Figure 26C An electrode material is deposited and patterned to form a gate G and a second electrode portion E1-2. The second electrode portion E1-2 and the first electrode portion E1-1 (a portion of the semiconductor material layer SML that has undergone a lightly doped drain process) constitute the first electrode E1.

[0143] Figures 27A to 27C The process of manufacturing an array substrate according to some embodiments of the present disclosure is shown. Figures 27A to 27C The process of manufacturing an array substrate using a half-tone mask is shown. Figure 27AA signal line SL and a light shielding member LS are formed on a substrate BS. A buffer layer BUF is formed on the side of the signal line SL and the light shielding member LS away from the substrate BS. A semiconductor material layer SML is formed on the side of the buffer layer BUF away from the substrate BS. An insulating layer IN is formed on the side of the semiconductor material layer SML away from the substrate BS. A first photoresist layer PR1 is formed on the side of the insulating layer IN away from the substrate BS. The first photoresist layer PR1 is exposed using a halftone mask and developed to form a photoresist pattern. The photoresist pattern includes a first portion corresponding to the via hole and a second portion outside the first portion. The first portion includes a first region corresponding to the channel region and a second region corresponding to the remaining portion of the first portion. The depth of the first region is greater than the depth of the second region. The photoresist material is removed from the second portion. The process also includes etching the insulating layer IN and the buffer layer BUF in the second portion to expose at least a portion of the upper surface of the signal line SL in the second portion, thereby forming a via hole v. The process further includes ashing the developed photoresist layer, thereby removing the photoresist material in the second region while retaining the photoresist material in the first region; thereby forming a second photoresist layer PR2 in the region corresponding to the channel region.

[0144] Reference Figure 27B A lightly doped drain process is performed to make the portions of the semiconductor material layer SML corresponding to the first and second electrodes more conductive. The orthographic projection of the second photoresist layer PR2 on the substrate BS overlaps with the orthographic projection of the portion of the semiconductor material layer SML corresponding to the channel region on the substrate BS. After the lightly doped drain process, the portions of the semiconductor material layer SML corresponding to the first and second electrodes become more conductive.

[0145] Reference Figure 27C An electrode material is deposited and patterned to form a gate G and a second electrode portion E1-2. The second electrode portion E1-2 and the first electrode portion E1-1 (a portion of the semiconductor material layer SML that has undergone a lightly doped drain process) constitute the first electrode E1.

[0146] FIG. 28A to FIG. 28B The process of manufacturing an array substrate according to some embodiments of the present disclosure is shown. Figure 28A A signal line SL and a light shielding member LS are formed on a base substrate BS; a buffer layer BUF is formed on a side of the signal line SL and the light shielding member LS away from the base substrate BS; a semiconductor material layer SML is formed on a side of the buffer layer BUF away from the base substrate BS; an insulating layer IN is formed on a side of the semiconductor material layer SML away from the base substrate BS; a via hole v is formed, which extends through the insulating layer IN and the buffer layer BUF, thereby exposing at least a portion of the signal line SL (for example, Figure 28AThe portion of the semiconductor material layer SML corresponding to the first electrode partially extends into the via hole v. A gate G is formed on a side of the insulating layer IN away from the substrate BS.

[0147] Reference Figure 28A Using gate G as a mask, a lightly doped drain process is then performed to make the portions of semiconductor material layer SML corresponding to the first and second electrodes more conductive. The orthographic projection of gate G on substrate BS overlaps with the orthographic projection of the portion of semiconductor material layer SML corresponding to the channel region on substrate BS. After the lightly doped drain process, the portions of semiconductor material layer SML corresponding to the first and second electrodes become more conductive.

[0148] Reference Figure 28B The electrode material is deposited and patterned to form a second electrode portion E1-2. The second electrode portion E1-2 and the first electrode portion E1-1 (the portion of the semiconductor material layer SML that has undergone the lightly doped drain process) constitute the first electrode E1.

[0149] In some embodiments, the insulating layer IN is formed to extend substantially over the entire array substrate. Figures 26A to 26C 、 Figures 27A to 27C and FIG. 28A to FIG. 28B shown.

[0150] In some embodiments, the insulating layer is not formed to extend substantially over the entire array substrate. For example, an orthographic projection of the insulating layer on the base substrate at least partially does not overlap with an orthographic projection of the signal line on the base substrate, and at least partially does not overlap with an orthographic projection of the first electrode or the second electrode on the base substrate.

[0151] Figures 29A to 29C The process of manufacturing an array substrate according to some embodiments of the present disclosure is shown. Figures 29A to 29C The process shown is similar to Figures 26A to 26C The process shown is similar, but with Figures 26A to 26C The process shown differs in at least one aspect in that the insulating layer is not formed to extend substantially across the entire array substrate.

[0152] Figures 30A to 30C The process of manufacturing an array substrate according to some embodiments of the present disclosure is shown. Figures 30A to 30C The process shown is similar to Figures 27A to 27C The process shown is similar, but Figures 27A to 27C The process shown differs in at least one aspect in that the insulating layer is not formed to extend substantially across the entire array substrate.

[0153] Figures 31A to 31B The process of manufacturing an array substrate according to some embodiments of the present disclosure is shown. Figures 31A to 31BThe process shown is similar to FIG. 28A to FIG. 28B The process shown is similar, but FIG. 28A to FIG. 28B The process shown differs in at least one aspect in that the insulating layer is not formed to extend substantially across the entire array substrate.

[0154] Figures 32A to 32C The process of manufacturing an array substrate according to some embodiments of the present disclosure is shown. Figures 32A to 32C The process shown is similar to Figures 26A to 26C The process shown is similar, but Figures 26A to 26C The difference of the process shown is at least that a lightly doped drain process is performed using a mask. In one example, the lightly doped drain process is performed only on a portion of the semiconductor material layer SML extending into the via v and a portion of the semiconductor material layer SML corresponding to the second electrode E2.

[0155] Figures 33A to 33C The process of manufacturing an array substrate according to some embodiments of the present disclosure is shown. Figures 33A to 33B The process shown is similar to Figures 32A to 32C The process shown is similar, but Figures 32A to 32C The process shown differs in at least one aspect in that the insulating layer is not formed to extend substantially across the entire array substrate.

[0156] Example 1: In one example, a method for manufacturing an array substrate includes: cleaning a base substrate; depositing an electrode material layer with a thickness between 100 nm and 1000 nm on the base substrate, wherein the electrode material includes a molybdenum-aluminum-aluminum stacked structure, a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure, or an MTD-copper-MTD stacked structure; patterning the electrode material layer to form a light shielding member LS and a signal line SL on the base substrate BS; depositing (for example, by a chemical vapor deposition process) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the base substrate to form a light shielding member LS and a signal line SL. sputtering indium gallium zinc oxide on the substrate to a thickness of between 10 nm and 80 nm; patterning the indium gallium zinc oxide material to form a semiconductor material layer; using a chemical vapor deposition process or an atomic layer deposition process and using silicon oxide as an insulating material to form an insulating layer on a side of the semiconductor material layer away from the substrate; performing a lightly doped drain process on the semiconductor material layer; etching the insulating layer and the buffer layer to form a via hole extending through the insulating layer and the buffer layer and exposing the upper surface of at least a portion of the signal line SL; and forming a through hole in the insulating layer and the buffer layer. Sputtering an electrode material layer with a thickness between 200 nm and 1200 nm on a side of the layer away from the substrate, the electrode material including a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure or an MTD-copper-MTD stacked structure; patterning the electrode material layer to form a second electrode portion and a gate; depositing (for example, by a plasma enhanced chemical vapor deposition process) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the substrate to form a first passivation layer with a thickness between 200 nm and 400 nm; coating a 2 μm to 3 μm thick layer on the first passivation layer. A resin layer between the two layers is formed; a conductive material layer with a thickness between 40 nm and 100 nm is deposited on the resin layer using indium gallium zinc oxide or indium zinc oxide, and the conductive material layer is patterned to form a common electrode; an insulating material (silicon oxide or silicon nitride / silicon oxide) is deposited on the substrate (for example, by a chemical vapor deposition process) to form a second passivation layer with a thickness between 100 nm and 300 nm; a conductive material layer with a thickness between 40 nm and 135 nm is deposited on the second passivation layer using indium zinc oxide, and the conductive material layer is patterned to form a pixel electrode. The process described in Example 1 corresponds to Figures 26A to 26C The process described in .

[0157] Example 2: In one example, a method for manufacturing an array substrate includes: cleaning a base substrate; depositing an electrode material layer with a thickness between 100 nm and 1000 nm on the base substrate, wherein the electrode material includes a molybdenum-aluminum-aluminum stacked structure, a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure, or an MTD-copper-MTD stacked structure; patterning the electrode material layer to form a light shielding member LS and a signal line SL on the base substrate BS; depositing (for example, by a chemical vapor deposition process) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the base substrate to form a buffer layer with a thickness between 100 nm and 700 nm; sputtering oxygen on the base substrate; Indium gallium zinc oxide is deposited to a thickness between 10 nm and 80 nm; the indium gallium zinc oxide material is patterned to form a semiconductor material layer; an insulating layer is formed on a side of the semiconductor material layer away from the substrate using a chemical vapor deposition process or an atomic layer deposition process and using silicon oxide as an insulating material; a lightly doped drain process is performed on the semiconductor material layer; the insulating layer and the buffer layer are etched to form a via hole extending through the insulating layer and the buffer layer and exposing an upper surface of at least a portion of the signal line SL; an electrode material layer with a thickness between 200 nm and 1200 nm is sputtered on a side of the insulating layer and the buffer layer away from the substrate, wherein the electrode material includes a molybdenum-neodymium-copper stacked structure, M TD-copper stacked structure or MTD-copper-MTD stacked structure; patterning the electrode material layer to form a second electrode portion and a gate; patterning the insulating material layer to form an insulating layer, wherein the insulating layer substantially does not extend over the entire array substrate, and the orthographic projection of the insulating layer on the base substrate does not overlap with the orthographic projection of the signal line on the base substrate at least in part, and does not overlap with the orthographic projection of the first electrode or the second electrode on the base substrate at least in part; depositing (for example, by plasma enhanced chemical vapor deposition) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the base substrate to form a layer with a thickness of 200 nm to 400 nm. m; a resin layer with a thickness of between 2 μm and 3 μm is coated on the first passivation layer; a conductive material layer with a thickness of between 40 nm and 100 nm is deposited on the resin layer using indium gallium zinc oxide or indium zinc oxide, and the conductive material layer is patterned to form a common electrode; an insulating material (silicon oxide or silicon nitride / silicon oxide) is deposited on the substrate (for example, by a chemical vapor deposition process) to form a second passivation layer with a thickness of between 100 nm and 300 nm; a conductive material layer with a thickness of between 40 nm and 135 nm is deposited on the second passivation layer using indium zinc oxide, and the conductive material layer is patterned to form a pixel electrode. The process described in Example 2 corresponds to Figures 29A to 29C The process described in .

[0158] Example 3: In one example, a method for manufacturing an array substrate includes: cleaning a base substrate; depositing an electrode material layer with a thickness between 100 nm and 1000 nm on the base substrate, the electrode material including a molybdenum-aluminum-aluminum stacked structure, a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure, or an MTD-copper-MTD stacked structure; patterning the electrode material layer to form a light shielding member LS and a signal line SL on the base substrate BS; depositing (for example, by a chemical vapor deposition process) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the base substrate to form a buffer layer with a thickness between 100 nm and 700 nm; Indium gallium zinc oxide is sputtered on a substrate to a thickness of 10 nm to 80 nm; the indium gallium zinc oxide material is patterned to form a semiconductor material layer; an insulating layer is formed on a side of the semiconductor material layer away from the substrate using a chemical vapor deposition process or an atomic layer deposition process and using silicon oxide as an insulating material; a first photoresist layer is formed on a side of the insulating layer away from the substrate; the first photoresist layer is exposed and developed using a halftone mask; the insulating layer and the buffer layer are etched to form a via hole extending through the insulating layer and the buffer layer to expose the upper surface of at least a portion of the signal line; a second photoresist layer is formed in a region corresponding to the channel region; and Using the second photoresist layer as a mask, a lightly doped drain process is performed on the semiconductor material layer; an electrode material layer with a thickness between 200 nm and 1200 nm is sputtered on a side of the insulating layer and the buffer layer away from the substrate, the electrode material including a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure, or an MTD-copper-MTD stacked structure; the electrode material layer is patterned to form a second electrode portion and a gate; and an insulating material (silicon oxide or silicon nitride / silicon oxide) is deposited on the substrate (for example, by a plasma enhanced chemical vapor deposition process) to form a first passivation layer with a thickness between 200 nm and 400 nm. ; Coating a resin layer with a thickness of 2 μm to 3 μm on the first passivation layer; Depositing a conductive material layer with a thickness of 40 nm to 100 nm on the resin layer using indium gallium zinc oxide or indium zinc oxide, and patterning the conductive material layer to form a common electrode; Depositing (for example, by a chemical vapor deposition process) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the substrate to form a second passivation layer with a thickness of 100 nm to 300 nm; Depositing a conductive material layer with a thickness of 40 nm to 135 nm on the second passivation layer using indium zinc oxide, and patterning the conductive material layer to form a pixel electrode. The process described in Example 3 corresponds to Figures 27A to 27C The process described in .

[0159] Example 4: In one example, a method for manufacturing an array substrate includes: cleaning a base substrate; depositing an electrode material layer with a thickness between 100 nm and 1000 nm on the base substrate, the electrode material including a molybdenum-aluminum-aluminum stacked structure, a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure or an MTD-copper-MTD stacked structure; patterning the electrode material layer to form a light shielding member LS and a signal line SL on the base substrate BS; depositing (for example, by a chemical vapor deposition process) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the base substrate to form a buffer layer with a thickness between 100 nm and 700 nm; sputtering indium gallium zinc oxide on the base substrate to a thickness between 10 nm and 80 nm; FIG. The method comprises the following steps: patterning an indium gallium zinc oxide material to form a semiconductor material layer; forming an insulating layer on a side of the semiconductor material layer away from the substrate by using a chemical vapor deposition process or an atomic layer deposition process and using silicon oxide as an insulating material; forming a first photoresist layer on a side of the insulating layer away from the substrate; exposing and developing the first photoresist layer using a halftone mask; etching the insulating layer and the buffer layer to form a via extending through the insulating material layer and the buffer layer to expose an upper surface of at least a portion of the signal line; forming a second photoresist layer in a region corresponding to the channel region; performing a lightly doped drain process on the semiconductor material layer using the second photoresist layer as a mask; and sputtering a thick layer of silicon on the side of the insulating material layer and the buffer layer away from the substrate. an electrode material layer having a thickness between 200 nm and 1200 nm, wherein the electrode material comprises a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure or an MTD-copper-MTD stacked structure; patterning the electrode material layer to form a second electrode portion and a gate; patterning the insulating material layer to form an insulating layer, wherein the insulating layer substantially does not extend over the entire array substrate, and an orthographic projection of the insulating layer on the base substrate at least partially does not overlap with an orthographic projection of the signal line on the base substrate, and at least partially does not overlap with an orthographic projection of the first electrode or the second electrode on the base substrate; depositing (for example, by a plasma enhanced chemical vapor deposition process) an insulating material (silicon oxide or silicon nitride / silicon nitride) on the base substrate. A first passivation layer having a thickness of 200 nm to 400 nm is formed by depositing a resin layer having a thickness of 2 μm to 3 μm on the first passivation layer; a conductive material layer having a thickness of 40 nm to 100 nm is deposited on the resin layer using indium gallium zinc oxide or indium zinc oxide, and the conductive material layer is patterned to form a common electrode; an insulating material (silicon oxide or silicon nitride / silicon oxide) is deposited on the substrate (for example, by a chemical vapor deposition process) to form a second passivation layer having a thickness of 100 nm to 300 nm; a conductive material layer having a thickness of 40 nm to 135 nm is deposited on the second passivation layer using indium zinc oxide, and the conductive material layer is patterned to form a pixel electrode. The process described in Example 4 corresponds to. Figures 30A to 30C The process described in .

[0160] Example 5: In one example, a method for manufacturing an array substrate includes: cleaning a base substrate; depositing an electrode material layer with a thickness between 100 nm and 1000 nm on the base substrate, the electrode material including a molybdenum-aluminum-aluminum stacked structure, a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure, or an MTD-copper-MTD stacked structure; patterning the electrode material layer to form a light shielding member LS and a signal line SL on the base substrate BS; depositing (for example, by a chemical vapor deposition process) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the base substrate to form a layer with a thickness between 100 nm and 700 nm. sputtering indium gallium zinc oxide on the substrate to a thickness of 10 nm to 80 nm; patterning the indium gallium zinc oxide material to form a semiconductor material layer; using a chemical vapor deposition process or an atomic layer deposition process and using silicon oxide as an insulating material to form an insulating layer on a side of the semiconductor material layer away from the substrate; etching the insulating layer and the buffer layer using a mask to form a via hole extending through the insulating layer and the buffer layer and exposing the upper surface of at least a portion of the signal line SL; using the same mask used to form the via hole v, etching the portion of the semiconductor material layer extending into the via hole v. The method further comprises the following steps: performing a lightly doped drain process; sputtering an electrode material layer with a thickness between 200 nm and 1200 nm on a side of the insulating material layer and the buffer layer away from the substrate, wherein the electrode material comprises a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure or an MTD-copper-MTD stacked structure; patterning the electrode material layer to form a second electrode portion and a gate; depositing (for example, by a plasma chemical vapor deposition process) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the substrate to form a first passivation layer with a thickness between 200 nm and 400 nm; and coating the first passivation layer with a silicon nitride film. A resin layer with a thickness of 2 μm to 3 μm is deposited; a conductive material layer with a thickness of 40 nm to 100 nm is deposited on the resin layer using indium gallium zinc oxide or indium zinc oxide, and the conductive material layer is patterned to form a common electrode; an insulating material (silicon oxide or silicon nitride / silicon oxide) is deposited on the substrate (for example, by a chemical vapor deposition process) to form a second passivation layer with a thickness of 100 nm to 300 nm; a conductive material layer with a thickness of 40 nm to 135 nm is deposited on the second passivation layer using indium zinc oxide, and the conductive material layer is patterned to form a pixel electrode. The process described in Example 5 corresponds to Figures 32A to 32C The process described in .

[0161] Example 6: In one example, a method for manufacturing an array substrate includes: cleaning a base substrate; depositing an electrode material layer with a thickness between 100 nm and 1000 nm on the base substrate, the electrode material including a molybdenum-aluminum-aluminum stacked structure, a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure or an MTD-copper-MTD stacked structure; patterning the electrode material layer to form a light shielding member LS and a signal line SL on the base substrate BS; depositing (for example, by a chemical vapor deposition process) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the base substrate to form a buffer layer with a thickness between 100 nm and 700 nm; sputtering indium gallium zinc oxide on the base substrate to a thickness between 10 nm and 700 nm; 80nm; patterning an indium gallium zinc oxide material to form a semiconductor material layer; using a chemical vapor deposition process or an atomic layer deposition process and using silicon oxide as an insulating material to form an insulating layer on a side of the semiconductor material layer away from the substrate; etching the insulating layer and the buffer layer using a mask to form a via hole extending through the insulating layer and the buffer layer and exposing the upper surface of at least a portion of the signal line SL; using the same mask used to form the via hole v, performing a lightly doped drain process on a portion of the semiconductor material layer extending into the via hole v; sputtering an electrode material with a thickness between 200nm and 1200nm on a side of the insulating layer and the buffer layer away from the substrate layer, the electrode material includes a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure or an MTD-copper-MTD stacked structure; patterning the electrode material layer to form a second electrode portion and a gate; patterning the insulating material layer to form an insulating layer, the insulating layer substantially does not extend over the entire array substrate, the orthographic projection of the insulating layer on the base substrate does not overlap with the orthographic projection of the signal line on the base substrate at least in part, and does not overlap with the orthographic projection of the first electrode or the second electrode on the base substrate at least in part; depositing (for example, by a plasma enhanced chemical vapor deposition process) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the base substrate to form a thickness of A first passivation layer between 200nm and 400nm; a resin layer with a thickness between 2μm and 3μm is coated on the first passivation layer; a conductive material layer with a thickness between 40nm and 100nm is deposited on the resin layer using indium gallium zinc oxide or indium zinc oxide, and the conductive material layer is patterned to form a common electrode; an insulating material (silicon oxide or silicon nitride / silicon oxide) is deposited on the substrate (for example, by a chemical vapor deposition process) to form a second passivation layer with a thickness between 100nm and 300nm; a conductive material layer with a thickness between 40nm and 135nm is deposited on the second passivation layer using indium zinc oxide, and the conductive material layer is patterned to form a pixel electrode. The process described in Example 6 corresponds to Figures 33A to 33C The process described in .

[0162] Example 7: In one example, a method for manufacturing an array substrate includes: cleaning a base substrate; depositing an electrode material layer with a thickness between 100 nm and 1000 nm on the base substrate, wherein the electrode material includes a molybdenum-aluminum-aluminum stacked structure, a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure, or an MTD-copper-MTD stacked structure; patterning the electrode material layer to form a light shielding member LS and a signal line SL on the base substrate BS; depositing (for example, by a chemical vapor deposition process) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the base substrate to form a buffer layer with a thickness between 100 nm and 700 nm; sputtering an oxide layer on the base substrate; Indium gallium zinc is deposited to a thickness between 10nm and 80nm; Indium gallium zinc oxide material is patterned to form a semiconductor material layer; an insulating layer is formed on the side of the semiconductor material layer away from the substrate using a chemical vapor deposition process or an atomic layer deposition process and using silicon oxide as an insulating material; the insulating layer and the buffer layer are etched to form a via hole extending through the insulating layer and the buffer layer and exposing the upper surface of at least a portion of the signal line SL; an electrode material layer with a thickness between 200nm and 1200nm is sputtered on the side of the insulating material layer and the buffer layer away from the substrate, the electrode material including a molybdenum-neodymium-copper laminate structure, an MTD-copper laminate structure, and a quartz-copper laminate structure. structure or MTD-copper-MTD stacked structure; patterning an electrode material layer to form a gate; using the gate as a mask, performing a lightly doped drain process on the semiconductor material layer; sputtering an electrode material layer with a thickness between 200nm and 1200nm, wherein the electrode material includes a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure or an MTD-copper-MTD stacked structure; patterning the electrode material layer to form a second electrode portion at least partially in the via hole v; depositing (for example, by a plasma enhanced chemical vapor deposition process) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the substrate to form a second electrode with a thickness between 200nm and 400nm. m; a resin layer with a thickness of between 2 μm and 3 μm is coated on the first passivation layer; a conductive material layer with a thickness of between 40 nm and 100 nm is deposited on the resin layer using indium gallium zinc oxide or indium zinc oxide, and the conductive material layer is patterned to form a common electrode; an insulating material (silicon oxide or silicon nitride / silicon oxide) is deposited on the substrate (for example, by a chemical vapor deposition process) to form a second passivation layer with a thickness of between 100 nm and 300 nm; a conductive material layer with a thickness of between 40 nm and 135 nm is deposited on the second passivation layer using indium zinc oxide, and the conductive material layer is patterned to form a pixel electrode. The process described in Example 7 corresponds to FIG. 28A to FIG. 28B The process described in .

[0163] The foregoing description of the embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and various modifications as are suited to the particular use or implementation contemplated. The scope of the present invention is intended to be defined by the appended claims and their equivalents, in which all terms are to be used in their broadest reasonable sense unless otherwise indicated. Therefore, the terms "the invention," "the present invention," etc. do not necessarily limit the scope of the claims to specific embodiments, and reference to exemplary embodiments of the present invention is not intended to limit the invention, and no such limitation should be inferred. The present invention is limited solely by the spirit and scope of the appended claims. Furthermore, the claims may use the terms "first," "second," etc., followed by a noun or element. These terms should be understood as nomenclature and should not be construed as limiting the number of elements to which they refer unless a specific number is provided. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, no element or component in this disclosure is intended to be dedicated to the public, regardless of whether the element or component is explicitly stated in the appended claims.

Claims

1. An array substrate, comprising: substrate substrate; a signal line on the substrate; A buffer layer, located on a side of the signal line away from the substrate; as well as an active layer located on a side of the buffer layer away from the base substrate; the active layer comprises a first electrode region, a second electrode region and a channel region between the first electrode region and the second electrode region; the first electrode region comprises a first electrode, and the second electrode region comprises a second electrode; wherein the first electrode extends through a via hole to be connected to the signal line, and the via hole at least extends through the buffer layer; The material of at least a portion of the second electrode and the first electrode is the same as the material of the channel region; and The conductivity of the channel region is different from the conductivity of the first electrode and is different from the conductivity of the second electrode.

2. The array substrate according to claim 1, wherein: The material of the channel region, the second electrode, and at least a portion of the first electrode includes M1O a N b , wherein M1 is a single metal or a combination of multiple metals, a>0, and b≥0, O represents oxygen element, and N represents nitrogen element.

3. The array substrate according to claim 1, wherein: The channel region, the second electrode and at least a portion of the first electrode are an integrated structure.

4. The array substrate according to claim 3, wherein: The channel region, the first electrode and the second electrode are an integrated structure and include M1O a N b , wherein M1 is a single metal or a combination of multiple metals, a>0, and b≥0, O represents oxygen element, and N represents nitrogen element.

5. The array substrate according to claim 3, wherein: The first electrode includes a first electrode portion and a second electrode portion electrically connected to each other; and The first electrode portion and the second electrode portion are made of different materials.

6. The array substrate according to claim 5, wherein: The material of the first electrode portion includes M1O a N b , wherein M1 is a single metal or a combination of multiple metals, a>0, and b≥0, O represents oxygen, and N represents nitrogen; The second electrode portion includes a metal material; and The first electrode portion, the second electrode and the channel region are an integrated structure.

7. The array substrate according to claim 5, wherein: At least a portion of the second electrode portion is located in the via hole; and The orthographic projection of the second electrode portion on the base substrate at least partially overlaps with the orthographic projection of the signal line on the base substrate, and at least partially overlaps with the orthographic projection of the first electrode portion on the base substrate.

8. The array substrate according to claim 7, wherein: The orthographic projection of the first electrode portion on the base substrate does not overlap with the orthographic projection of the signal line on the base substrate.

9. The array substrate according to claim 7, wherein: The orthographic projection of the first electrode portion on the base substrate partially overlaps with the orthographic projection of the signal line on the base substrate.

10. The array substrate according to any one of claims 5 to 9, wherein: At least a portion of the first electrode portion extends into the second electrode portion.

11. The array substrate according to any one of claims 5 to 10, further comprising: an insulating layer, which is located on a side of the channel region, the first electrode portion, and the second electrode away from the substrate; as well as A gate, which is located on a side of the insulating layer away from the substrate; The second electrode portion and the gate are located in the same layer and include the same electrode material.

12. The array substrate according to any one of claims 1 to 11, wherein: In a cross section along a plane perpendicular to the substrate and perpendicular to the direction in which the signal line extends in length and intersecting the signal line and the via hole, a surface of the signal line other than a lower surface is exposed in the via hole; The lower surface refers to a surface of the signal line that contacts the base substrate.

13. The array substrate according to claim 12, wherein: In the cross section, an upper surface of the signal line and two side surfaces respectively connecting the upper surface and the lower surface of the signal line are completely covered by the first electrode.

14. The array substrate according to claim 12, wherein: In the cross section, only a portion of the upper surface of the signal line and only one of two side surfaces respectively connecting the upper surface and the lower surface of the signal line are covered by the first electrode.

15. The array substrate according to any one of claims 1 to 11, wherein: In a cross section along a plane perpendicular to the substrate and perpendicular to the direction in which the signal line extends in length and intersecting the signal line and the via hole, at least a portion of the upper surface of the signal line and at least one of two side surfaces respectively connecting the upper surface and the lower surface of the signal line are not exposed in the via hole; as well as The lower surface refers to a surface of the signal line that contacts the base substrate.

16. The array substrate according to claim 15, wherein: In the cross section, only a portion of the upper surface of the signal line and at least one of two side surfaces respectively connecting the upper surface and the lower surface of the signal line are covered by the buffer layer.

17. The array substrate according to claim 15, wherein: In the cross section, only a portion of the upper surface of the signal line and only one of two side surfaces respectively connecting the upper surface and the lower surface of the signal line are covered by the first electrode.

18. The array substrate according to claim 15, wherein: In the cross section, only the upper surface of the middle portion of the signal line is covered by the first electrode; as well as Two side surfaces of the upper surface and the lower surface respectively connected to the signal line are covered by the buffer layer.

19. The array substrate according to any one of claims 1 to 18, wherein: The signal line is a data line that provides a data signal to the first electrode.

20. The array substrate according to claim 1, wherein: The active layer includes a Hall mobility greater than or equal to 30 cm 2 / V·s metal oxide materials.

21. The array substrate according to claim 1, further comprising: a light shielding member located on the substrate; and a gate line located at a side of the light shielding member away from the substrate; Wherein, the light shielding member and the signal line are located in the same layer; as well as Along the extension direction of the signal line, the ratio of the line width of the gate line to the line width of the light shielding member is in the range of 0.3 to 0.

9.

22. A display device comprising the array substrate according to any one of claims 1 to 19; and one or more integrated circuits connected to the array substrate.

Images