Asynchronous FIFO data transmission method and asynchronous FIFO data buffer

Abstract

The present application provides an asynchronous FIFO data transmission method and an asynchronous FIFO data buffer for data transmission between a write user side and a read user side. The method includes: when performing data transmission, obtaining the configuration bit of the asynchronous FIFO, if the configuration bit is equal to a first configuration value, the read user side detects whether there is an error in the data read by the read side FIFO, if there is erroneous data, then the reading of the data is stopped, and the read user side feeds back an error flag signal to the write user side; the error flag signal includes at least a pause signal and a read address corresponding to the erroneous data; the write user side pauses the writing of the write side FIFO according to the pause signal, and transmits the corresponding correct data according to the read address corresponding to the erroneous data to replace the erroneous data. The present application can improve the efficiency and accuracy of data transmission by detecting the erroneous data of the read side FIFO and retransmitting the corresponding erroneous data.

Description

Technical Field

[0001] The present application belongs to the technical field of data transmission, and in particular relates to an asynchronous FIFO data transmission method and an asynchronous FIFO data buffer. Background Art

[0002] A FIFO (First In First Out) is a first-in, first-out data buffer. Data is written into one end and read out the other, in the same order it was written. FIFO reading and writing are controlled by writing and reading signals, which are designed to generate write and read enable signals. When the FIFO is full, writing is disabled, and when the FIFO is empty, data cannot be read.

[0003] For asynchronous FIFOs, data is written into the FIFO by a control signal from one clock domain, and read out of the FIFO by a control signal from another clock domain. In other words, the changes in the read and write pointers are generated by different clocks. Therefore, the judgment of whether the FIFO is empty or full is across clock domains. However, due to the asynchrony of the write and read clock domains, or the mismatch between the read data and the FIFO empty signal, or errors in the control signals, the data read on the read side may be inconsistent or erroneous. In traditional asynchronous FIFO designs, once an error is detected, all data is usually retransmitted starting from the write side. Although this method can detect and correct errors, it has low flexibility and poor multiplexing because once an error occurs, the entire FIFO needs to be retransmitted from the beginning, resulting in wasted resources and low efficiency.

[0004] Therefore, an efficient retransmission solution is urgently needed to solve the problem of asynchronous FIFO data transmission errors. Summary of the Invention

[0005] The present application discloses an asynchronous FIFO data transmission method and an asynchronous FIFO data buffer, which can improve the efficiency and accuracy of data transmission by detecting erroneous data in the read-side FIFO and retransmitting the corresponding erroneous data.

[0006] Other purposes and advantages of this application can be further understood from the technical features disclosed in this application.

[0007] In order to achieve one or part or all of the above-mentioned purposes or other purposes, in a first aspect, the present application provides a data transmission method of an asynchronous FIFO, wherein the asynchronous FIFO includes a write-side FIFO for connecting to a write user side to write data, a storage body for accessing data, and a read-side FIFO for connecting to a read user side to read data, so that the asynchronous FIFO transmits data between the write user side and the read user side. The method includes: when the asynchronous FIFO performs data transmission, obtaining the configuration bit of the asynchronous FIFO; if the configuration bit is equal to a first configuration value, the read user side detects whether there is an error in the data read by the read side FIFO; if there is error data, the reading of the data is stopped, and the read user side feeds back an error flag signal to the write user side; wherein the error flag signal includes at least a pause signal and a read address corresponding to the error data; the write user side pauses the writing of data by the write side FIFO according to the pause signal, and transmits the corresponding correct data according to the read address corresponding to the error data to replace the error data.

[0008] In one implementation, the writing user side determines, in response to the first preset information, a write address corresponding to the error data in the write-side FIFO according to the read address corresponding to the error data;

[0009] The write user side instructs the write pointer of the write side FIFO to point to the write address corresponding to the erroneous data again. The write side FIFO recovers the write data starting from the write address corresponding to the erroneous data, rewrites the erroneous data and the data after the erroneous data, and replaces the erroneous data and the data after the erroneous data with correct data.

[0010] In one implementation, after recovering the written data, the writing user side feeds back a resolution flag signal to the reading user side;

[0011] The reading user side responds to the resolution flag signal and instructs the reading side FIFO to restart reading data from the read address corresponding to the erroneous data.

[0012] In one implementation, the writing user side responds to the second preset information, determines the correct data corresponding to the erroneous data according to the read address corresponding to the erroneous data, writes the correct data into the storage body, and only replaces the erroneous data with the correct data.

[0013] In one implementation, after replacing the erroneous data with the correct data, the writing user side performs a handshake with the reading user side to notify the reading user side that the data has been updated;

[0014] The writing user side instructs the writing side FIFO to resume writing data from the address at the time of suspension; the reading user side responds to the data being updated and resumes reading data after re-reading the correct data.

[0015] In one implementation, when the asynchronous FIFO is transmitting data, the asynchronous FIFO obtains a write flag of the write-side FIFO and a read flag of the read-side FIFO, wherein the write flag includes a write-full flag, a nearly full flag, a half-full flag, and an empty flag, and the read flag includes a full flag, a half-empty flag, a nearly empty flag, and a read-empty flag.

[0016] If the configuration bit is equal to the second configuration value, the asynchronous FIFO transmits data between different clock domains according to the write flag and the read flag.

[0017] In one implementation, if the configuration bit is equal to the first configuration value, there is error data and the write flag is a non-full-empty flag, the write user side assigns the read address corresponding to the error data to the write address of the write side FIFO, so as to stop writing data to the write side FIFO according to the pause signal;

[0018] If the configuration bit is equal to the first configuration value, there is error data and the read flag is not a read empty flag, the reading user side stops reading data from the read side FIFO according to the read address corresponding to the error data.

[0019] In the second aspect, the present application also provides an asynchronous FIFO data buffer, including a write-side FIFO for connecting to a write user side for writing data, a storage body for accessing data, and a read-side FIFO for connecting to a read user side for reading data. The data buffer is used to transmit data between the write user side and the read user side to implement an asynchronous FIFO data transmission method as described in any one of the first aspects. The write-side FIFO also includes a data correction module, which is used to transmit corresponding correct data to replace the erroneous data when erroneous data exists.

[0020] In one implementation, the write-side FIFO includes a full judgment module, which is used to judge the write flag of the write-side FIFO; the read-side FIFO includes an empty judgment module, which is used to judge the read flag of the read-side FIFO, wherein the write flag includes full, nearly full, half full, and empty flags, and the read flag includes full flag, half empty, nearly empty, and read empty.

[0021] In a third aspect, the present application provides a computer-readable storage medium, in which program code is stored. The program code is called by a processor to implement an asynchronous FIFO data buffer according to the second aspect and to execute an asynchronous FIFO data transmission method according to any one of the first aspects.

[0022] In a fourth aspect, the present application also provides an electronic device comprising one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute an asynchronous FIFO data transmission method as described in any one of the first aspects.

[0023] The above-mentioned asynchronous FIFO data transmission method and asynchronous FIFO data buffer obtain the configuration bit of the asynchronous FIFO when the asynchronous FIFO performs data transmission. If the configuration bit is equal to the first configuration value, the reading user side detects whether there is an error in the data read by the read side FIFO. If there is erroneous data, the reading of the data is stopped, and the reading user side feeds back an error flag signal to the writing user side. The writing user side pauses the writing of data in the write side FIFO according to the pause signal, and transmits the corresponding correct data to replace the erroneous data according to the read address corresponding to the erroneous data, thereby realizing the improvement of the efficiency and accuracy of data transmission by detecting the erroneous data in the read side FIFO and retransmitting the corresponding erroneous data.

[0024] In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0026] Figure 1 This is a first flow chart of the asynchronous FIFO data transmission method according to an embodiment of the present application.

[0027] Figure 2 This is a schematic diagram of data transmission using an asynchronous FIFO according to an embodiment of the present application.

[0028] Figure 3 This is a second flow chart of the asynchronous FIFO data transmission method according to an embodiment of the present application.

[0029] Figure 4 This is a third flow chart of the asynchronous FIFO data transmission method according to an embodiment of the present application.

[0030] Figure 5 This is a fourth flow chart of the asynchronous FIFO data transmission method according to an embodiment of the present application.

[0031] Figure 6 This is a structural block diagram of an asynchronous FIFO data buffer according to an embodiment of the present application. DETAILED DESCRIPTION

[0032] The aforementioned and other technical contents, features, and functions of the present application will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The terms "first," "second," and the like in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, and this is merely a way of distinguishing objects of the same attributes when describing them in the embodiments of the present application.

[0033] In traditional asynchronous FIFO designs, once an error is detected, all data is typically retransmitted starting from the write side. While this approach can detect and correct errors, it suffers from low flexibility and poor reusability. Once an error occurs, the entire FIFO must be retransmitted from the beginning, resulting in wasted resources and low efficiency.

[0034] In order to improve the efficiency and accuracy of data transmission, an embodiment of the present application provides an asynchronous FIFO data transmission method, in which the asynchronous FIFO performs data transmission between a writing user side and a reading user side. The asynchronous FIFO includes a write-side FIFO for connecting to the writing user side to write data, a storage body for accessing data, and a read-side FIFO for connecting to the reading user side to read data. The data transmission method implemented in this embodiment includes: when the asynchronous FIFO performs data transmission, obtaining the configuration bit of the asynchronous FIFO; if the configuration bit is equal to the first configuration value, the reading user side detects whether there is an error in the data read by the reading side FIFO; if there is erroneous data, the reading of the data is stopped, and the reading user side feeds back an error flag signal to the writing user side; the writing user side transmits the corresponding correct data according to the error flag signal to replace the erroneous data. This method can insert and replace data in the RAM (random access memory) port by modifying the write address waddr of the write-side FIFO. This eliminates the need to rewrite the entire data, replacing only the write data wdata or subsequent data in the current bank. This method is applicable to any data scenario. This method can also replace all subsequent data after replacing erroneous data, making it suitable for scenarios where subsequent data depends on previous data. This method meets the diverse needs of various users, offers high performance, and improves data transmission efficiency and reliability.

[0035] The present application is described in detail below with reference to the accompanying drawings.

[0036] refer to Figure 1 and Figure 2 , an embodiment of the present application provides an asynchronous FIFO data transmission method, comprising the following steps:

[0037] Step S1: When the asynchronous FIFO is transmitting data, the configuration bit of the asynchronous FIFO is obtained. If the configuration bit is equal to the first configuration value, the reading user side detects whether there is an error in the data read by the read side FIFO. If there is error data, the reading of data is stopped, and the reading user side feeds back an error flag signal to the writing user side.

[0038] Among them, the configuration bit is used to control the working mode of the asynchronous FIFO, and the specific configuration value can be set according to user needs. It should be noted that this application is mainly aimed at the problem that the data read by the read-side FIFO is erroneous due to data transmission errors on the write side FIFO. The erroneous data includes but is not limited to data chaos, data missing, etc. Therefore, when erroneous data occurs, the reading user side feeds back an error flag signal to the writing user side so that the writing user side can control the writing of the write side FIFO to correct the data.

[0039] Specifically, when the configuration bit is equal to the first configuration value (e.g., 1), the asynchronous FIFO enters data insertion and replacement mode, also known as data correction mode. In this mode, the read user side detects whether there are errors in the data read by the read FIFO. For example, erroneous data is detected by CRC check. The detection method is not specifically limited here. If erroneous data exists, the read FIFO stops reading data to avoid reading more erroneous data or generating anomalies. In addition, the read user side feeds back an error flag signal to the write user side to notify the write user side of the error in the data transmission so that the corresponding error correction mechanism can be implemented. The error flag signal can be synchronized by dual triggers to ensure the stability and reliability of cross-clock domain signal synchronization.

[0040] At the same time, the error flag signal includes at least a pause signal and the read address corresponding to the error data, so that the user side can more accurately locate the error data and the correct data corresponding to the error data. The error flag signal can also be transmitted through the cross-clock domain synchronization module within the asynchronous FIFO to ensure the correct synchronous conversion of the read address.

[0041] Step S2: The writing user side pauses writing data to the write side FIFO according to the pause signal, and transmits corresponding correct data according to the read address corresponding to the erroneous data to replace the erroneous data.

[0042] Specifically, the write user side pauses writing data to the write side FIFO based on the pause signal to prevent more erroneous data from being written when the data being transmitted is associated with the previous erroneous data. The write user side can also determine the corresponding correct data based on the read address corresponding to the erroneous data, and the write user side instructs the write side FIFO to rewrite the corresponding correct data into the asynchronous FIFO, thereby replacing the erroneous data. It should be noted that the replacement here can mean inserting correct data in the case of data missing errors, overwriting erroneous data in the case of data confusion, etc., to retransmit the correct data.

[0043] According to the above description, the data transmission method of the asynchronous FIFO of the present application obtains the configuration bit of the asynchronous FIFO when the asynchronous FIFO performs data transmission. If the configuration bit is equal to the first configuration value, the reading user side detects whether there is an error in the data read by the read side FIFO. If there is erroneous data, the reading of the data is stopped, and the reading user side feeds back an error flag signal to the writing user side. The writing user side suspends the writing of data in the write side FIFO according to the pause signal, and transmits the corresponding correct data to replace the erroneous data according to the read address corresponding to the erroneous data, thereby achieving the transmission efficiency and data accuracy of real-time data transmission.

[0044] It should be noted that, although the above embodiment emphasizes that the method performs detection and retransmission during data transmission, in actual application, the method is not limited to performing detection and retransmission after data transmission is completed.

[0045] In some embodiments, reference Figure 3 , the data transmission method of the present application also includes:

[0046] Step S101: When the asynchronous FIFO is transmitting data, the asynchronous FIFO obtains the write flag of the write-side FIFO and the read flag of the read-side FIFO, wherein the write flag includes full, nearly full, half full, and empty flags, and the read flag includes full, half empty, nearly empty, and full flags.

[0047] Specifically, asynchronous FIFO is used for data transmission between different clock domains. Writing data is controlled by the write clock signal, and the write pointer indicates the location of the write data. Reading data is controlled by the read clock signal, and the read pointer indicates the location of the read data. The write flag of the write-side FIFO can be determined by comparing the write pointer with the temporary write address:

[0048] If the write pointer is different from the first slice of the temporary write address, and the write pointer is the same as the second slice of the temporary write address, it is determined to be a full flag;

[0049] If the write pointer is the same as the first slice of the temporary write address, and the value of the second slice of the write pointer minus the second slice of the temporary write address is greater than or equal to the half-full threshold, and the value of the second slice of the temporary write address minus the second slice of the write pointer is less than or equal to the half-full threshold, then it is determined to be a half-full flag;

[0050] If the write pointer is the same as the first slice of the temporary write address, and the difference between the write pointer and the second slice of the temporary write address is greater than the near-full low threshold, and the value of the second slice of the temporary write address minus the second slice of the write pointer is less than the half-full threshold, then it is determined to be a near-full flag;

[0051] If the write pointer is the same as the first slice of the temporary write address, and the difference between the write pointer and the second slice of the temporary write address is less than the half-full threshold, and the value of the second slice of the temporary write address minus the second slice of the write pointer is greater than the half-full threshold, it is determined to be an empty flag.

[0052] Similarly, the read flag of the read-side FIFO can be determined by comparing the read pointer with the temporary read address:

[0053] If the read pointer is the same as the temporary read address, it is determined to be a read empty flag;

[0054] If the read pointer is the same as the first slice of the temporary read address, and the second slice of the temporary read address minus the second slice of the read pointer is less than or equal to the half-empty threshold, and the second slice of the read pointer minus the second slice of the temporary read address is greater than the half-empty threshold, then it is determined to be a half-empty flag;

[0055] If the read pointer is the same as the first slice of the temporary read address, and the second slice of the temporary read address minus the second slice of the read pointer is less than or equal to the near-empty low threshold, and the second slice of the read pointer minus the second slice of the temporary read address is greater than the near-empty high threshold, then it is determined to be a near-empty flag;

[0056] If the read pointer is the same as the first slice of the temporary read address, and the second slice of the temporary read address minus the second slice of the read pointer is greater than the half-empty threshold, and the second slice of the read pointer minus the second slice of the temporary read address is less than or equal to the half-empty threshold, it is determined to be a read full flag.

[0057] The first slice represents the total bit width of the write pointer / temporary write address / read pointer / temporary read address minus 1; the second slice represents the continuous bits starting from bit 0 of the bit vector and ending at the total bit width of the write pointer / temporary write address / read pointer / temporary read address minus 2 bits.

[0058] Furthermore, the asynchronous FIFO's empty and full flags better coordinate data reads and writes: data is written when the write enable signal is valid and the write-side FIFO is not full, and data is read when the read enable signal is valid and the read-side FIFO is not empty. Furthermore, the real-time empty and full flags can be updated at the rising edge of the clock or reset signal to more accurately coordinate data reads and writes. Thus, when the asynchronous FIFO is transmitting data, obtaining the write flag of the write-side FIFO and the read flag of the read-side FIFO ensures the validity of data transmission.

[0059] At the same time, the control logic for the empty flag of the write-side FIFO and the full flag of the read-side FIFO can also be designed according to the specific needs of the user to enhance the flexibility of the control logic of the present application. Among them, the generation of the empty flag and the full flag can be, but is not limited to, based on a few additional cycles after the clock beats.

[0060] Step S102: If the configuration bit is equal to the second configuration value, the asynchronous FIFO performs data transmission between different clock domains according to the write flag and the read flag.

[0061] Specifically, when configured to be equal to the second configuration value (such as 0), the asynchronous FIFO transmits data between different clock domains according to the write flag and the speed flag, that is, at this time there is no data error in the read side FIFO, the data correction mode is not triggered, and the asynchronous FIFO performs normal data transmission according to the write flag and the read flag.

[0062] Step S103: If the configuration bit is equal to the first configuration value, there is error data and the write flag is not a full flag, the write user side assigns the read address corresponding to the error data to the write address of the write side FIFO to stop writing data to the write side FIFO according to the pause signal.

[0063] Specifically, when writing data, the write pointer indicates the current data location. Each time data is written to the FIFO, the write pointer increments to point to the next available location. Therefore, the write pointer points to the write address corresponding to the erroneous data in the write-side FIFO, and the write pointer is controlled not to increment, thereby suspending subsequent data write operations.

[0064] More specifically, the write reset signal and the write clock signal can be used to control whether the write pointer is updated:

[0065] If the write reset signal is low (i.e. reset state), the write pointer is cleared;

[0066] Otherwise, if the configuration bit is equal to the second configuration value, and the write enable signal is high and the write full flag is low (i.e., the FIFO is not full), the write pointer is incremented;

[0067] Otherwise, if the configuration bit is equal to the first configuration value, the write enable signal is high, and the write full flag is low, then the error flag signal is determined: if the error flag signal is high, the write pointer is updated to the value of the read pointer corresponding to the error data; if the error flag signal is low, the write pointer is incremented;

[0068] Otherwise, the write pointer remains unchanged.

[0069] In this way, accurate control of the write pointer is ensured.

[0070] Step S104: If the configuration bit is equal to the first configuration value, there is error data and the read flag is not a read empty flag, the user side stops reading data from the read side FIFO according to the read address corresponding to the error data.

[0071] Specifically, when reading data, the read pointer indicates the current read data location. Each time data is read out, the read pointer increments to point to the next readable location. Therefore, the reading user side controls the read pointer not to increment according to the read address corresponding to the erroneous data, so as to suspend subsequent data reading operations of the read side FIFO.

[0072] More specifically, the read pointer can be controlled to update by reading the reset signal and the read clock signal:

[0073] If the read reset signal is low, the read address is reset;

[0074] Otherwise, if the configuration bit is equal to the first configuration value, the read enable signal is high, and the read empty flag is low, then the error flag signal is determined: if the error flag signal is high, the read pointer is updated to the read pointer corresponding to the error data; if the error flag signal is low, the read pointer is incremented;

[0075] Otherwise, the read pointer remains unchanged.

[0076] In this way, accurate control of the read pointer is ensured, and the flexibility of the control logic of this application is improved.

[0077] As described above, by more precisely controlling the read and write pointers, the fullness or empty state of the asynchronous FIFO can be more accurately determined, resulting in more accurate reading and writing of data. This ensures that erroneous data is accurately located and corrected through precise read and write pointers without affecting the normal transmission of the asynchronous FIFO. Furthermore, this prevents the writing of more erroneous data into the FIFO, thus avoiding wasting internal space in the asynchronous FIFO. This further improves the efficiency and accuracy of data transmission, maintaining the accuracy of the data in the asynchronous FIFO and the stability of the system.

[0078] In order to adapt to the application scenario where the data transmitted before and after are related, in some embodiments, reference Figure 4 , step S2 includes:

[0079] Step S201: The writing user side determines the write address corresponding to the error data in the write-side FIFO according to the read address corresponding to the error data in response to the first preset information.

[0080] The first preset information is used to identify an application scenario in which the data transmitted before and after are related. That is, under the first preset information, it is indicated that the erroneous data and the data after the erroneous data need to be rewritten. For example, in a video stream processing system, if there is an error in the video frame data, the erroneous video frame and the video frames after it can be retransmitted. For another example, data interaction between systems within certain enterprises is usually highly correlated. If an error occurs, the erroneous data and the data after it need to be resynchronized.

[0081] Specifically, in an asynchronous FIFO, data reading and writing occur in different clock domains. A pre-set mapping relationship can be used to map the read address space to the write address space. For example, each time data is written, the corresponding write address and read address are recorded and stored to establish a mapping relationship between the read and write addresses. This allows the user side of the write to use the pre-set mapping relationship to locate the corresponding write address of the erroneous data in the write-side FIFO based on the read address corresponding to the erroneous data.

[0082] Step S202: The write user side instructs the write pointer of the write side FIFO to point to the write address corresponding to the erroneous data again. The write side FIFO starts to recover the write data from the write address corresponding to the erroneous data, rewrites the erroneous data and the data after the erroneous data, and replaces the erroneous data and the data after the erroneous data with correct data.

[0083] Specifically, the write pointer of the write side FIFO can be reset through the state machine or control logic, so that the write pointer of the write side FIFO is reset to the write address corresponding to the erroneous data, and the write user side recovers the write data and starts writing the correct data to overwrite the erroneous data and the data after the erroneous data, thereby ensuring the accuracy of the data.

[0084] Step S203: After recovering the write data, the writing user side feeds back a resolution flag signal to the reading user side to inform the reading user side that the error has been corrected.

[0085] Step S204: The reading user side responds to the resolution flag signal and instructs the reading side FIFO to restart reading data from the read address corresponding to the erroneous data, thereby continuing to read data after the erroneous data to ensure that the corrected data is re-read.

[0086] Through the above method, in a scenario where the data transmitted before and after are related, the erroneous data and the data after the erroneous data in the asynchronous FIFO can be effectively detected and repaired, and after correction, the data can be re-read from the read address corresponding to the original erroneous data to ensure the consistency and integrity of the data, while improving the flexibility and reusability of this method.

[0087] In some embodiments, reference Figure 5 , step S2 may further include:

[0088] Step S211: The write user side determines the correct data corresponding to the erroneous data based on the read address corresponding to the erroneous data in response to the second preset information. The second preset information indicates that only the erroneous data is corrected, including but not limited to only inserting and replacing missing data, only overwriting and correcting the erroneous data, that is, not retransmitting data after the erroneous data.

[0089] Step S212: The write user writes the correct data into the memory bank to replace the erroneous data with the correct data. Specifically, when only the erroneous data is replaced, the write side FIFO does not need to be used for rewriting. Only the correct data needs to be retransmitted through the memory bank, thereby saving FIFO resources.

[0090] Step S213: After replacing the erroneous data with the correct data, the writing user side performs a handshake with the reading user side to notify the reading user side that the data has been updated.

[0091] Step S214: the writing user side instructs the writing side FIFO to resume writing data from the address at which it was paused; the reading user side responds to the data being updated and resumes reading data after re-reading the correct data.

[0092] After re-reading the correct data, the reading user side resumes reading the data from the read address at the time of suspension.

[0093] In this way, in the scenario where only erroneous data is replaced, erroneous data in the asynchronous FIFO can be effectively and quickly detected and repaired, and after correction, it can be synchronously read from the user side through handshake to prevent asynchronous FIFO data overflow and ensure the correct transmission of data between different clock domains, while further improving the practicality, flexibility and multiplexing of this method.

[0094] It should be understood that, although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0095] Based on the same inventive concept, the present application also provides an asynchronous FIFO data buffer for implementing the aforementioned problem. The implementation solution provided by the asynchronous FIFO data buffer is similar to the implementation solution described in the aforementioned method. Therefore, the specific limitations of the asynchronous FIFO data buffer embodiment provided below can be found in the above-mentioned limitations on the data transmission method for an asynchronous FIFO, and will not be repeated here.

[0096] The embodiment of the present application provides an asynchronous FIFO data buffer, referring to Figure 6 The asynchronous FIFO data buffer (abbreviated as "asynchronous FIFO") includes a write-side FIFO for connecting to a write user side to write data, a storage body for accessing data, and a read-side FIFO for connecting to a read user side to read data. The asynchronous FIFO data buffer is used to transmit data between the write user side and the read user side, thereby implementing an asynchronous FIFO data transmission method as described in any of the above embodiments. The data correction module is used to transmit corresponding correct data to replace erroneous data when erroneous data exists.

[0097] In some embodiments, the asynchronous FIFO data buffer also includes a cross-clock domain synchronization module for implementing synchronous address conversion from the write-side FIFO to the read-side FIFO, and from the read-side FIFO to the write-side FIFO. The write-side FIFO includes a write pointer, a full determination module, a data conversion module, and a data correction module. The write pointer is used to indicate the location of the current write data. The data conversion module is used to convert between Gray code data and binary code data. The full determination module is used to receive synchronized write pointer and read pointer signals to determine the write flag of the write-side FIFO. The write flag includes full, nearly full, half full, and empty flags. The full determination module feeds the write flag signal back to the write user side and the write pointer to control the data write operation. The write pointer is also synchronized with the write clock and connected to the write address input of the storage body to write data to the storage body. The data write operation is performed on the rising edge of the write clock. The data correction module is used to transmit corresponding correct data to replace the erroneous data when erroneous data exists. This improves data consistency and prevents errors during data transmission.

[0098] The read-side FIFO includes a read pointer, an empty detection module, and a data conversion module. The read pointer indicates the current data location. The data conversion module converts Gray code data into binary code and vice versa. The empty detection module determines the read flag of the read-side FIFO, which includes full, half empty, nearly empty, and read empty. The empty detection module feeds the read flag signal back to the read user and the read pointer to control data read operations.

[0099] Through the collaborative work of these modules and signals, the asynchronous FIFO data buffer can reliably transmit data between different clock domains and has the function of correcting erroneous data, thereby improving the accuracy and efficiency of data transmission.

[0100] In one embodiment, the present application also provides a computer-readable storage medium, characterized in that program code is stored in the computer-readable storage medium, and the program code is called by a processor to call any of the above-mentioned asynchronous FIFO data buffers to execute an asynchronous FIFO data transmission method as in any of the above-mentioned embodiments.

[0101] In one embodiment, the present application also provides an electronic device comprising one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute an asynchronous FIFO data transmission method as in any of the above embodiments.

[0102] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference will be made to the corresponding or similar parts of the various embodiments. The devices / apparatus / systems disclosed in the embodiments are described briefly because they correspond to the methods disclosed in the embodiments. For relevant details, refer to the methods section.

[0103] It should be noted that, for those skilled in the art, various improvements and modifications may be made to the present invention without departing from the principles of the present invention, and such improvements and modifications also fall within the scope of protection of the claims of the present invention. It should be understood that certain features of the present invention described in the context of separate embodiments for the sake of clarity may also be provided in combination in a single embodiment. Conversely, various features of the present invention described in the context of a single embodiment for the sake of clarity may also be provided individually or in any suitable combination or as any other described embodiment of the present invention.

Claims

1. A data transmission method of an asynchronous FIFO, characterized in that: The asynchronous FIFO includes a write-side FIFO for connecting to a write user side to write data, a storage body for accessing data, and a read-side FIFO for connecting to a read user side to read data, so that the asynchronous FIFO performs data transmission between the write user side and the read user side. The method includes: When the asynchronous FIFO is transmitting data, obtaining the configuration bit of the asynchronous FIFO, obtaining the write flag of the write-side FIFO and the read flag of the read-side FIFO, wherein the write flag includes a write-full flag, a nearly full flag, a half-full flag, and an empty flag, and the read flag includes a full flag, a half-empty flag, a nearly empty flag, and a read-empty flag; If the configuration bit is equal to the first configuration value, the read user side detects whether there is an error in the data read by the read side FIFO; if there is error data and the read flag is not a read empty flag, the read user side stops reading data from the read side FIFO according to the read address corresponding to the error data, and the read user side feeds back an error flag signal to the write user side; wherein, the error flag signal at least includes a pause signal and the read address corresponding to the error data; if there is error data and the write flag is not a write full flag, the write user side pauses writing data to the write side FIFO according to the pause signal, and the write user side responds to the first preset information and, based on the read address corresponding to the error data, determines the write address corresponding to the error data in the write side FIFO, instructs the write pointer of the write side FIFO to point to the write address corresponding to the error data again, and the write side FIFO resumes writing data from the write address corresponding to the error data, rewrites the error data and the data after the error data, and replaces the error data and the data after the error data with correct data.

2. The data transmission method of an asynchronous FIFO according to claim 1, characterized in that: After recovering the written data, the writing user side feeds back a resolution flag signal to the reading user side; The reading user side instructs the reading side FIFO to restart reading data from the reading address corresponding to the erroneous data in response to the resolution flag signal.

3. The data transmission method of an asynchronous FIFO according to claim 1, characterized in that: The writing user side determines correct data corresponding to the erroneous data according to the read address corresponding to the erroneous data in response to the second preset information, and writes the correct data into the storage body, replacing only the erroneous data with correct data.

4. The data transmission method of an asynchronous FIFO according to claim 3, characterized in that: After replacing the erroneous data with correct data, the writing user side performs a handshake with the reading user side to notify the reading user side that the data has been updated; The writing user side instructs the writing side FIFO to resume writing data from the address at the time of suspension; the reading user side resumes reading data after re-reading the correct data in response to the data being updated.

5. The data transmission method of an asynchronous FIFO according to claim 1, characterized in that: If the configuration bit is equal to a second configuration value, the asynchronous FIFO transmits data between different clock domains according to the write flag and the read flag.

6. An asynchronous FIFO data buffer, characterized in that include: a write-side FIFO for connecting to a write user side for writing data, a storage body for accessing data, and a read-side FIFO for connecting to a read user side for reading data, wherein the asynchronous FIFO is used to transmit data between the write user side and the read user side, so as to implement the asynchronous FIFO data transmission method according to any one of claims 1 to 5, wherein the write-side FIFO further comprises: a data correction module, wherein the data correction module is used to transmit corresponding correct data to replace the erroneous data when erroneous data exists; The write-side FIFO includes a full judgment module, which is used to judge the write flag of the write-side FIFO; the read-side FIFO includes an empty judgment module, which is used to judge the read flag of the read-side FIFO, wherein the write flag includes full, nearly full, half full, and empty flags, and the read flag includes full flag, half empty, nearly empty, and read empty.

7. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a program code, and the program code is called by a processor to implement the asynchronous FIFO data buffer according to claim 6 to execute the asynchronous FIFO data transmission method according to any one of claims 1 to 5.

8. An electronic device comprising one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the asynchronous FIFO data transmission method according to any one of claims 1 to 5.

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