Security bus architecture for multi-core Chiplet chip system

Abstract

The invention belongs to the field of security in a multi-core system chip, and discloses a security bus architecture for a multi-core Chiplet chip system, which comprises five parts, namely an active intermediate layer, a functional chip, a storage chip, a Core chip and a security chiplet, and is characterized in that the Core chip comprises a CPU core of the chip system; the storage chip comprises a memory for storing data and codes; the functional chip comprises most peripherals and functional IPs; the active interposer is used for connecting all the chiplets and realizing access control of each chiplet, and the security chiplet is used for managing and controlling security configuration of the whole chip system. When a chiplet provided by a supplier cannot be trusted, the secure bus architecture can isolate and restrict access to non-secure chiplets. A bus architecture is realized in a secure active interposer, and the access authority of each small chip in a chip system is configured by a secure small chip, so that the data access of other small chips can be ensured to be controlled, and the system security is enhanced.

Description

Technical Field

[0001] The present invention belongs to the field of security in multi-core system chips, and in particular to a secure bus architecture for multi-core chiplet chip systems. Background Art

[0002] As chip performance and functionality continue to increase, chip design and manufacturing are facing more and more challenges, especially in terms of power consumption, thermal management, manufacturing costs, and design complexity. Chiplet is a design concept that integrates multiple small chips into a chip system. Its advantage is that it can combine chips with different functions or different manufacturing processes, providing flexibility and scalability, and is expected to improve manufacturing yield and reduce design and manufacturing costs.

[0003] However, the flexibility and scalability of the chiplet system will also bring new security issues. If the purchased chiplet has security vulnerabilities, the entire chip system may not work properly. At present, some researchers have proposed a chip bus architecture for 2.5D integration. The specific implementation method is to implement a secure bus and a secure CPU in the active interposer. The secure CPU is responsible for configuring the security policy of the entire chip system, and the secure bus implements the storage access control of the entire chip system. However, this secure bus architecture has two obvious problems. First of all, considering the cost, the bus architecture needs to implement the secure bus, secure CPU, and register group for configuring the security policy in the active interposer, which occupies a large number of resources and may greatly reduce the manufacturing yield of the active interposer, which has a large cost for the chip system. This secure bus architecture also has loopholes in security. Since the security of the chiplet where the memory is located cannot be ensured, these factors indirectly affect the credibility of the security policy configured by the secure CPU. Although the secure CPU in the interposer has no security issues in the bus access phase, the code and data obtained by accessing the memory may not be credible. Attackers may attack the entire chip system based on this point. In addition, the clock reset signal of the bus also has security risks, which needs to be solved by a dedicated secure chiplet. Summary of the invention

[0004] The present invention proposes a secure bus architecture for multi-core chiplet chip systems, which solves the following technical problems: When the chiplets provided by the supplier cannot be trusted, the secure bus architecture can isolate and restrict access to non-secure chiplets. Implementing the bus architecture in a secure active interposer and configuring the access rights of each chiplet in the chip system by a secure chiplet can ensure that data access to the remaining chiplets is controlled, thereby enhancing system security while retaining flexibility.

[0005] In order to solve the above technical problems, the specific technical solution of a secure bus architecture for a multi-core chiplet chip system of the present invention is as follows: A secure bus architecture for a multi-core chiplet chip system includes five parts: an active intermediary layer, a functional chip, a storage chip, a Core chip, and a secure chiplet. The Core chip includes a CPU core of the chip system; the storage chip includes a memory for storing data and code; the functional chip includes most peripherals and functional IPs; the active intermediary layer is used to connect all chiplets and implement access control of each chiplet, and the secure chiplet is used to manage the security configuration of the overall chip system.

[0006] Furthermore, the components in the active interposer layer include: a data transmission bus, a bus access controller and a special signal controller. The data transmission bus is a means of data communication for the entire chip system. For each host interface of the data transmission bus, a bus access controller is equipped. The bus access controller records the security control strategies for different address segments and limits data transmission according to the security control strategies. The special signal controller records the security attributes of different chiplets, and also compares the security attributes of the special signal input and output chiplets. Connection is allowed only when the security attributes of the two match.

[0007] Furthermore, the data transmission bus adopts an AHB bus.

[0008] Furthermore, the bus access controller includes two modules, one is a transmission controller, and the other is a control policy register group. The control policy register group stores all control policies of the bus interface, each control policy includes an address range and the read and write permissions of the address range, and the control policy register group can only be modified by the CPU in the security chip; the transmission controller is responsible for limiting the access operations of the bus according to the control information provided by the control policy register group.

[0009] Furthermore, whenever the bus host interface initiates a transmission, the transmission controller compares the transmission address and operation type with the policy in the control policy register group. If the comparison result indicates a legal access, the access request is transmitted to the data bus in the active interposer layer; if the comparison result indicates an illegal access, the access request is cut off, the transmission cannot reach the data bus in the active interposer layer, and an alarm signal is output to inform the CPU in the security chip.

[0010] Furthermore, the special signal controller includes two modules, one is a connectivity controller and the other is a security attribute configurator. The security attribute configurator stores the security attributes of each small chip and can only be configured through the security CPU; the connectivity controller controls the connectivity of the special signal by searching for relevant configurations in the security attribute configurator and comparing the security attributes of the small chip at the input end and the small chip at the output end of the special signal. If the security attributes of the small chip at the input end are consistent with the security attributes of the small chip at the output end, the connectivity controller directly connects the input signal to the output port; if the security attributes of the two do not match, the output port will be clamped to 0, blocking the connectivity of the signal.

[0011] Furthermore, the security chip controls the secure startup and security policy configuration of the entire chip system, so a security CPU and a configuration bus are integrated in the security chip. The configuration bus will provide a series of configuration interfaces connected to the bus access controller and special signal controller in the active interposer layer. The security CPU accesses and modifies the register groups in these controllers.

[0012] Furthermore, the bus in the active interposer requires clock and reset signals, and a clock control unit and a reset control unit are implemented in the secure chiplet.

[0013] The secure bus architecture for a multi-core chiplet system of the present invention has the following advantages: 1. Only the bus and controller are implemented in the active interposer to reduce the impact on the yield of the interposer; 2. Contains a controller for bus access and can generate a warning signal for illegal access; 3. Contains a controller for special signals and can generate a warning signal for illegal access; 4. The control strategy for special signals is simplified, and only needs to be judged based on the security attributes of the small chips at both ends to achieve the purpose of reducing register overhead; 5. The clock and reset control units are placed in the security chip to prevent targeted malicious attacks; 6. An independent configuration bus is arranged for the security CPU to prevent bus resources from being occupied when configuring the security policy; 7. An independent memory is arranged for the security CPU to prevent the chip where the memory is located from being maliciously attacked; 8. The bus access controller is implemented at the interface of the bus host to prevent malicious hosts from occupying the bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a schematic diagram of the effect of applying the security solution to the Chilpet chip system.

[0015] Figure 2 This is a diagram of the internal structure of the bus access controller.

[0016] Figure 3 This is the internal structure diagram of the special signal controller.

[0017] Figure 4 This is a diagram of the internal structure of the security chip. DETAILED DESCRIPTION

[0018] In order to better understand the purpose, structure and function of the present invention, the following further describes in detail a secure bus architecture for a multi-core chiplet chip system of the present invention in conjunction with the accompanying drawings.

[0019] Attached Figure 1 This is a schematic diagram of the effect of applying the security solution to the Chilpet chip system.

[0020] The present invention discloses a secure bus architecture for a multi-core chiplet system, which includes an active intermediary layer, a functional chip, a memory chip, a Core chip, and a secure chiplet. The Core chip contains the CPU core of the chip system, which can be manufactured using a higher process technology to meet performance requirements; the memory chip contains a memory for storing data and code; the functional chip contains most peripherals and functional IPs; the active intermediary layer is used to connect all the chiplets and implement access control of each chiplet, and the secure chiplet is used to manage the security configuration of the overall chip system.

[0021] The components in the active interposer layer include: 1. Data transmission bus; 2. Bus access controller; 3. Special signal controller. The data transmission bus can use the AHB bus as a means of data communication for the entire chip system. For each host interface of the data transmission bus, a bus access controller is required, which records the security control strategies for different address segments and limits data transmission according to the security control strategies. The special signal controller records the security attributes of different chiplets, and also compares the security attributes of the chiplets at the special signal input and output ends. Only when the security attributes of the two match can the connection be allowed.

[0022] Attached Figure 2 This is a diagram of the internal structure of the bus access controller.

[0023] The bus access controller consists of two modules, a transmission controller and a control policy register group. The control policy register group stores all control policies of the bus interface. Each control policy contains an address range and the read and write permissions of the address range. In order to ensure that the control policy cannot be changed at will, the control policy register group needs to be designed to be modifiable only by the CPU in the secure chiplet. The transmission controller is responsible for limiting the access operation of the bus according to the control information provided by the control policy register group.

[0024] Whenever the bus host interface initiates a transfer, the transfer controller compares the transfer address and operation type with the policy in the control policy register group. If the comparison result indicates a legal access, the access request is transmitted to the data bus in the active interposer. If the comparison result indicates an illegal access, the access request is cut off, the transfer cannot reach the data bus in the active interposer, and an alarm signal is output to inform the CPU in the security chiplet.

[0025] Attached Figure 3 This is the internal structure diagram of the special signal controller.

[0026] Similar to the bus access controller, the special signal controller includes two modules, one is the connectivity controller and the other is the security attribute configurator. The security attribute configurator stores the security attributes of each chiplet and can only be configured through the security CPU. The connectivity controller controls the connectivity of special signals by looking up the relevant configuration in the security attribute configurator and comparing the security attributes of the chiplets at the input end and the output end of the special signal. If the security attributes of the chiplet at the input end are consistent with the security attributes of the chiplet at the output end, the connectivity controller directly connects the input signal to the output port; if the security attributes of the two do not match, the output port will be clamped to 0, blocking the connectivity of the signal.

[0027] Attached Figure 4 This is a diagram of the internal structure of the security chip.

[0028] The secure chiplet needs to control the secure startup and security policy configuration of the entire chip system, so a secure CPU and a configuration bus need to be integrated into the secure chiplet. The secure CPU has basically no performance requirements, so a CPU with a smaller area and power consumption can be used. The configuration bus will provide a series of configuration interfaces, connected to the bus access controller and special signal controller in the active interposer, so that the secure CPU can access and modify the register groups in these controllers. In addition, the bus in the active interposer requires clock and reset signals. In order to ensure the security of data access, a clock control unit and a reset control unit need to be implemented in the secure chiplet.

[0029] In the chiplet system security solution proposed in the present invention, the bus needs to be implemented on the active interposer, and the configuration of the security policy in the bus requires an additional secure chiplet to implement. All chiplets are integrated on the active interposer, and signal transmission will pass through the active interposer, so the security of the active interposer is very important and requires the chip supplier to design it by itself and manufacture it by a trustworthy foundry. Also, since the overall security policy is controlled by the secure chiplet, the manufacturing of the secure chiplet and its connection with the interposer also need to be focused on. The functions implemented by the security solution proposed in the present invention on the active interposer are: 1. Bus and bus access controller; 2. Special signal controller. Each chiplet can be mounted on the bus of the active interposer through one or more groups of bus interfaces. At the same time, the bus interface of each chiplet is subject to access restrictions of the bus access controller, and the remaining signals transmitted in the active interposer are supervised by the special signal controller. The bus access controller contains a configurable access policy corresponding to each bus host interface. The access policy defines the address range that the bus host interface can access and the read and write permissions of the data within the range, which are stored in a series of register groups. All access policy registers can only be modified by the CPU in the secure chiplet, and other malicious modifications will cause interrupts. In addition to bus signals, there are also some special signals transmitted through the active intermediary layer, such as interrupt indication signals and event reception and output signals. For these signals, a special signal controller is designed in the active intermediary layer to control them according to the security attributes of the signal sender and receiver. The security attributes of the sender and receiver are defined by the register group in the special signal controller, which can also only be modified by the secure CPU core in the secure chiplet, and malicious modifications will cause interrupts. In addition to the CPU used to configure the security policy, the secure chiplet also needs to include memory that can only be accessed by the CPU, secure boot components such as boot ROM, and bus clock and reset control components.

[0030] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of the present invention.

Claims

1. A secure bus architecture for a multi-core chiplet system, characterized in that: It includes five parts: active interposer, functional chip, storage chip, Core chip and security chiplet. The Core chip contains the CPU core of the chip system; the storage chip contains a memory for storing data and code; the functional chip contains most peripherals and functional IPs; the active interposer is used to connect all chiplets and implement access control of each chiplet, and the security chiplet is used to manage the security configuration of the overall chip system.

2. The secure bus architecture for multi-core chiplet chip systems according to claim 1, characterized in that: The components in the active interposer layer include: a data transmission bus, a bus access controller and a special signal controller. The data transmission bus is a means of data communication for the entire chip system. For each host interface of the data transmission bus, a bus access controller is equipped. The bus access controller records the security control strategies for different address segments and limits data transmission according to the security control strategies. The special signal controller records the security attributes of different chiplets, and also compares the security attributes of the special signal input and output chiplets. Only when the security attributes of the two match can the connection be allowed.

3. The secure bus architecture for multi-core chiplet chip systems according to claim 2, characterized in that: The data transmission bus adopts AHB bus.

4. The secure bus architecture for multi-core chiplet chip systems according to claim 2, characterized in that: The bus access controller includes two modules, one is a transmission controller and the other is a control policy register group. The control policy register group stores all control policies of the bus interface. Each control policy includes an address range and the read and write permissions of the address range. The control policy register group can only be modified by the CPU in the security chip; the transmission controller is responsible for limiting the access operations of the bus according to the control information provided by the control policy register group.

5. The secure bus architecture for multi-core chiplet chip systems according to claim 2, characterized in that: Whenever the bus host interface initiates a transmission, the transmission controller compares the transmission address and operation type with the strategy in the control strategy register group. If the comparison result indicates a legal access, the access request is transmitted to the data bus in the active interposer layer. If the comparison result indicates an illegal access, the access request is cut off, the transmission cannot reach the data bus in the active interposer layer, and an alarm signal is output to inform the CPU in the security chip.

6. The secure bus architecture for multi-core chiplet chip systems according to claim 1, characterized in that: The special signal controller includes two modules, one is a connectivity controller and the other is a security attribute configurator. The security attribute configurator stores the security attributes of each chiplet and can only be configured through the security CPU. The connectivity controller searches for relevant configurations in the security attribute configurator, compares the security attributes of the special signal input chiplet and the output chiplet, and controls the connectivity of the special signal. If the security attributes of the input chiplet are consistent with the security attributes of the output chiplet, the connectivity controller directly connects the input signal to the output port. If the security attributes of the two do not match, the output port will be clamped to 0, blocking the connectivity of the signal.

7. The secure bus architecture for multi-core chiplet chip systems according to claim 1, characterized in that: The secure chip controls the secure startup and security policy configuration of the entire chip system, so a secure CPU and a configuration bus are integrated in the secure chip. The configuration bus will provide a series of configuration interfaces connected to the bus access controller and special signal controller in the active interposer layer. The secure CPU accesses and modifies the register groups in these controllers.

8. The secure bus architecture for multi-core chiplet chip systems according to claim 1, characterized in that: The bus in the active interposer requires clock and reset signals, and a clock control unit and a reset control unit are implemented in the secure chiplet.

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