Universal verification system and method for AHB interface in chip design

Abstract

The invention relates to an AHB interface general verification system and method in chip design, the AHB interface general verification system is constructed by designing a verification means of a code integration AHB assertion check module, an AHB is connected with each component, the integrated AHB assertion check module automatically checks whether each AHB interface function meets an AHB protocol requirement or not after a CPU component starts to work, and the AHB assertion check module is used for checking whether each AHB interface function meets the AHB protocol requirement or not. And when the function of any AHB interface is detected not to meet the AHB protocol requirement, a detection error is generated, so that the problems in the AHB bus design can be found in time, accurately and conveniently. Compared with the prior art, the method has the advantages of being low in threshold, high in adaptability, convenient to position and the like, can be applied to the AHB interface verification environment in the existing chip design in a barrier-free mode, achieves efficient verification of the AHB interface in the universal chip design, and improves the verification efficiency even under the condition that verification personnel are lack of the capacity of building a complex verification environment. And effective AHB bus function verification can also be carried out.

Description

Technical Field

[0001] The invention belongs to the technical field of chip verification, and relates to a universal verification system and method for an AHB interface in chip design. Background Art

[0002] AHB bus protocol is one of the bus protocols that most chip designs on the market need to use. The AHB bus is mainly used for high-performance and high-clock frequency chip systems. The AHB bus can connect the CPU, RAM memory, FLASH memory and other peripherals to form a complete data processing system. It is important to verify the AHB bus function in the chip design through simulation. At present, most cases will use AHB VIP (verification IP, IP is the intellectual property module) to verify the AHB interface. However, the AHB VIP currently used is a commercial IP, and most of the IP code is encrypted and protected, making it impossible for users to understand the specific implementation method and inspection mechanism of the IP, thereby increasing the difficulty of the AHB interface verification and debugging process. It is also difficult to quickly locate the core problem after the AHB VIP check reports an error. Therefore, it is urgent to develop an efficient and universal AHB interface verification technology. Summary of the invention

[0003] In view of the problems existing in the above-mentioned traditional technologies, the present invention proposes a universal verification system for AHB interface in chip design and a universal verification method for AHB interface in chip design, which can realize efficient verification of AHB interface in universal chip design.

[0004] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a general verification system for an AHB interface in chip design is provided, including a verification platform and a chip top layer developed based on the SystemVerilog language, wherein the verification platform is used to provide the required clock signal, reset signal and test case for the chip top layer to run; The top layer of the chip includes instantiated CPU components, IP1 components, IP2 components and IP3 components. The CPU components, IP1 components, IP2 components and IP3 components are all integrated with AHB assertion checking modules, and the components are connected through AHB bus. The AHB assertion checking module is used to connect the AHB interface signals of the components to which it belongs and automatically check whether the AHB interface function meets the AHB protocol requirements. If so, the verification passes, otherwise an error is reported; the AHB assertion checking module includes the designed AHB bus HWDATA, HTRANS and HADDR signal check assertions, AHB bus HSIZE signal check assertions, AHB bus HBURST signal check assertions and AHB bus HREADY signal check assertions.

[0005] On the other hand, a general verification method for an AHB interface in a chip design is also provided, which is applied to a general verification system for an AHB interface in a chip design, including a verification platform and a chip top layer developed based on the SystemVerilog language, wherein the verification platform is used to provide the required clock signal, reset signal and test case for the chip top layer to run; The top layer of the chip includes instantiated CPU components, IP1 components, IP2 components and IP3 components. The CPU components, IP1 components, IP2 components and IP3 components are all integrated with AHB assertion check modules, and the components are connected through the AHB bus. The AHB assertion check module is used to connect the AHB interface signals of the components to which it belongs and automatically check whether the AHB interface function meets the AHB protocol requirements. If so, the verification is passed, otherwise an error is reported; the AHB assertion check module includes the designed AHB bus HWDATA, HTRANS and HADDR signal check assertions, the AHB bus HSIZE signal check assertion, the AHB bus HBURST signal check assertion and the AHB bus HREADY signal check assertion; The general verification method of the AHB interface in the above chip design includes the following steps: The test program developed based on C language drives the CPU component to initiate read and write requests through the AHB bus, and controls the work of IP1 component, IP2 component and IP3 component respectively; The AHB assertion check module integrated in each component is used to automatically perform AHB bus timing checks to check whether the AHB interface function meets the AHB protocol requirements; If the AHB interface function meets the AHB protocol requirements, the verification passes; otherwise, an error is reported.

[0006] One of the above technical solutions has the following advantages and beneficial effects: The AHB interface universal verification system and method in the above chip design, by designing the code to integrate the verification means of the AHB bus assertion check module, constructs an AHB interface universal verification system, and connects each component by the AHB bus. After the CPU component starts working, the integrated AHB assertion check module will automatically perform the check whether each AHB interface function meets the AHB protocol requirements, and generate a check error when it is checked that any AHB interface function does not meet the AHB protocol requirements, so that problems in the AHB bus design can be discovered in a timely, accurate and convenient manner. Compared with traditional technologies, it has the advantages of low threshold, strong adaptability and convenient positioning, and can be applied to the AHB interface verification environment in existing chip designs without obstacles, realizing efficient verification of the AHB interface in universal chip design, and even in the case where the verification personnel lack the ability to build a complex verification environment, effective AHB bus function verification can be performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0008] Figure 1 A structural block diagram of a general verification system for an AHB interface in chip design in an embodiment; Figure 2 A structural block diagram of the top layer of a chip in one embodiment; Figure 3 A schematic diagram of an AHB bus HWDATA assertion check timing in one embodiment; Figure 4 A schematic diagram of an AHB bus HBURST assertion check timing in one embodiment; Figure 5 A schematic diagram of AHB bus HREADY assertion check timing in one embodiment; Figure 6 The figure is a flow chart of a general verification method of an AHB interface in chip design in one embodiment. DETAILED DESCRIPTION

[0009] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0010] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification of the present invention and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0011] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0012] In one embodiment, Figure 1 As shown, a general verification system for AHB interface in chip design is provided, including a verification platform and a chip top layer developed based on SystemVerilog language, and the verification platform is used to provide the required clock signal, reset signal and test case for the chip top layer when it is running. The chip top layer includes instantiated CPU components, IP1 components, IP2 components and IP3 components. The CPU components, IP1 components, IP2 components and IP3 components are all integrated with AHB assertion check modules, and the components are connected through AHB buses. The AHB assertion check module is used to connect the AHB interface signals of the components to which it belongs and automatically check whether the AHB interface function meets the AHB protocol requirements. If so, the verification passes, otherwise an error is reported. The AHB assertion check module includes the designed AHB bus HWDATA, HTRANS and HADDR signal check assertions, the AHB bus HSIZE signal check assertion, the AHB bus HBURST signal check assertion and the AHB bus HREADY signal check assertion.

[0013] It can be understood that the design of the verification platform and the chip top layer in the AHB interface general verification system in the above chip design follows the existing UVM verification methodology and is developed using SystemVerilog (high-level modeling language). The chip top layer testbench is as follows: Figure 2 As shown in dig_top, the verification platform is used to provide the clock signal and reset signal required by dig_top. The check performed by the AHB assertion check module is designed and developed based on the AHB bus interface signal list in the chip design according to the requirements of the AHB bus protocol. Corresponding test cases can be developed during system design. For example, a test program (called by the test case) can be developed in C language to drive the CPU component to initiate read and write requests to other slaves (such as IP1 components, IP2 components, and IP3 components) through the AHB bus, thereby controlling the operation of the IP1 component, IP2 component, and IP3 component respectively. Generally, after the system is powered on, the test case will automatically load the test program into the CPU component. After the CPU component works normally, the AHB assertion check module developed and integrated in each of the aforementioned components will automatically perform an AHB bus timing check to verify whether the functions of each AHB interface in the chip design meet the AHB protocol requirements. The AHB bus interface signals are shown in Table 1: Table 1

[0014] After the test case of the AHB interface of the startup function module developed in the verification system is run, the AHB assertion check module will automatically check whether the AHB interface function meets the AHB protocol requirements, and report an error if it does not meet the requirements. In this way, after the code design of the above-mentioned host (such as CPU) and each slave module with an AHB interface is completed, the AHB assertion check module can be integrated into the code of each module, so that the corresponding AHB interface signal in the component is connected to the AHB assertion check module for automatic inspection, and users no longer need to understand the specific implementation method and inspection mechanism of commercial IP.

[0015] The AHB interface universal verification system in the above chip design is constructed by integrating the verification means of the AHB bus assertion check module in the design code. The AHB bus connects various components. After the CPU component starts working, the integrated AHB assertion check module will automatically perform the check of whether each AHB interface function meets the requirements of the AHB protocol, and generate a check error when it is found that any AHB interface function does not meet the requirements of the AHB protocol, so that problems in the AHB bus design can be discovered in a timely, accurate and convenient manner. Compared with traditional technologies, it has the advantages of low threshold, strong adaptability and convenient positioning, and can be applied to the AHB interface verification environment in existing chip designs without obstacles, realizing efficient verification of the AHB interface in the universal chip design, and even in the case where the verification personnel lack the ability to build a complex verification environment, effective AHB bus function verification can be performed.

[0016] In one embodiment, the AHB assertion check module monitors whether the HREADY signal is 0 when waiting for the rising edge of the bus clock signal to arrive during the process of checking and asserting the HWDATA, HTRANS and HADDR signals of the AHB bus. If not, the HREADY signal continues to be monitored. If yes, the HREADY signal is monitored after one clock cycle to see whether it is 0. If the HREADY signal is 0 after one clock cycle, check whether the HWDATA signal, HTRANS signal and HADDR signal remain stable. If they remain stable, the check is determined to be passed, otherwise a check error is generated; If the HREADY signal is not 0 after one clock cycle, continue to monitor the HREADY signal.

[0017] It is understandable that Figure 3 As shown, in the process of executing the AHB bus HWDATA, HTRANS, and HADDR signal check assertions using the designed AHB assertion check module, when the CPU component initiates a write request, if the slave does not return a completion flag (that is, HREADY is 0), HWDATA needs to remain stable. If HWDATA jumps, a check error is generated.

[0018] In one embodiment, during the process of checking and asserting the HSIZE signal of the AHB bus, when the CPU component initiates any read or write request, the AHB assertion checking module checks whether the HSIZE signal is less than or equal to 2 and greater than or equal to 0. If so, it is determined that the check passes, otherwise a check error is generated.

[0019] It can be understood that when the designed AHB assertion check module is used to execute the AHB bus HSIZE signal check assertion, taking the HSIZE signal description in Table 1 as an example, when the CPU component initiates any read or write request, HSIZE should be less than or equal to 2 and greater than or equal to 0, otherwise a check error is generated.

[0020] In one embodiment, during the process of checking and asserting the HBURST signal of the AHB bus, the AHB assertion checking module waits for the rising edge of the bus clock signal to arrive and checks whether the current HBURST is in INCR mode and whether the state is NOSEQUENTIAL. If not, continue to check the current HBURST. If yes, check whether the next state of the current HBURST jumps to SEQUENTIAL. If the next state of the current HBURST jumps to SEQUENTIAL, check whether the HADDR signal increases in units of HSIZE. If so, the check is confirmed to pass, otherwise a check error is generated; If the next state of the current HBURST does not jump to SEQUENTIAL, continue to check the current HBURST.

[0021] It is understandable that Figure 4 As shown, when the designed AHB assertion check module is used to execute the AHB bus HBURST signal check assertion, if the current HBURST is in INCR mode, HADDR should be incremented according to the size of HSIZE, otherwise a check error is generated.

[0022] In one embodiment, during the process of checking and asserting the HREADY signal of the AHB bus, the AHB assertion checking module monitors whether the HREADY signal is 0 while waiting for the rising edge of the bus clock signal to arrive. If not, the counter is cleared and continues to wait for the rising edge of the bus clock signal to arrive. If yes, the low level time of the HREADY signal is counted and the counter is incremented by 1. When the count value of the counter is greater than the set time upper limit, a check error is generated, otherwise it continues to wait for the rising edge of the bus clock signal to arrive.

[0023] It is understandable that Figure 5As shown, when the designed AHB assertion check module is used to perform the AHB bus HREADY signal check assertion, if the HREADY signal continues to be at a low level for more than the set time limit, a check error is generated. The specific size of the set time limit can be set by the verification personnel or other test users according to the specific chip design requirements. The AHB assertion check module can usually exist in the form of a monitor, which can maintain a counter for specific counting in certain inspection processes, such as the counter used in this embodiment.

[0024] Each component in the AHB interface universal verification system in the above chip design can be fully or partially implemented by software, hardware and their combination. The above components can be embedded in or independent of a device with data processing functions in the form of hardware, or can be stored in the memory of the above device in the form of software, so that the processor can call and execute the operations corresponding to the above modules. The above device can be, but is not limited to, various types of chip verification computers available in the art.

[0025] In one embodiment, a general verification method for an AHB interface in a chip design is provided, which is applied to a general verification system for an AHB interface in a chip design. The system includes a verification platform and a chip top layer developed based on the SystemVerilog language, and the verification platform is used to provide the required clock signal, reset signal and test case for the chip top layer when it is running. The chip top layer includes instantiated CPU components, IP1 components, IP2 components and IP3 components. The CPU components, IP1 components, IP2 components and IP3 components are all integrated with an AHB assertion check module, and the components are connected through an AHB bus. The AHB assertion check module is used to connect the AHB interface signal of the component to which it belongs and automatically check whether the AHB interface function meets the AHB protocol requirements. If so, the verification is passed, otherwise an error is reported. The AHB assertion check module includes the designed AHB bus HWDATA, HTRANS and HADDR signal check assertions, the AHB bus HSIZE signal check assertion, the AHB bus HBURST signal check assertion and the AHB bus HREADY signal check assertion.

[0026] like Figure 6 As shown, the general verification method of the AHB interface in chip design includes the following steps S10 to S14: S10, driving the CPU component to initiate read and write requests through the AHB bus through a test program developed based on C language, and controlling the IP1 component, IP2 component and IP3 component to work respectively; S12, using the AHB assertion check module integrated in each component to automatically perform an AHB bus timing check to check whether the AHB interface function meets the AHB protocol requirements; S14: If the AHB interface function meets the AHB protocol requirements, the verification passes; otherwise, an error is reported.

[0027] The AHB interface universal verification method in the above chip design, through the verification means of the AHB bus assertion check module integrated in the design code, constructs an AHB interface universal verification system, and connects various components by the AHB bus. After the CPU component starts working, the integrated AHB assertion check module will automatically perform the check whether each AHB interface function meets the requirements of the AHB protocol, and generate a check error when it is checked that any AHB interface function does not meet the requirements of the AHB protocol, so that problems in the AHB bus design can be discovered in a timely, accurate and convenient manner. Compared with traditional technologies, it has the advantages of low threshold, strong adaptability and convenient positioning, and can be applied to the AHB interface verification environment in existing chip designs without obstacles, realizing efficient verification of the AHB interface in the universal chip design, and even in the case where the verification personnel lack the ability to build a complex verification environment, effective AHB bus function verification can be performed.

[0028] In one embodiment, the process of the AHB assertion checking module checking the assertions of the AHB bus HWDATA, HTRANS and HADDR signals may include the following steps: When waiting for the rising edge of the bus clock signal to arrive, monitor whether the HREADY signal is 0. If not, continue to monitor the HREADY signal. If yes, monitor whether the HREADY signal is 0 after one clock cycle. If the HREADY signal is 0 after one clock cycle, check whether the HWDATA signal, HTRANS signal and HADDR signal remain stable. If they remain stable, the check is determined to be passed, otherwise a check error is generated; If the HREADY signal is not 0 after one clock cycle, continue to monitor the HREADY signal.

[0029] In one embodiment, the process of the AHB assertion checking module performing the AHB bus HSIZE signal checking assertion may include the following steps: When the CPU component initiates any read or write request, it checks whether the HSIZE signal is less than or equal to 2 and greater than or equal to 0. If so, the check is determined to be passed, otherwise a check error is generated.

[0030] In one embodiment, the process of the AHB assertion checking module performing the AHB bus HBURST signal checking assertion may include the following steps: When waiting for the rising edge of the bus clock signal, check whether the current HBURST is in INCR mode and whether the state is NOSEQUENTIAL. If not, continue to check the current HBURST. If yes, check whether the next state of the current HBURST jumps to SEQUENTIAL. If the next state of the current HBURST jumps to SEQUENTIAL, check whether the HADDR signal increases in units of HSIZE. If so, the check is confirmed to pass, otherwise a check error is generated; If the next state of the current HBURST does not jump to SEQUENTIAL, continue to check the current HBURST.

[0031] In one embodiment, the process of the AHB assertion checking module performing the AHB bus HREADY signal checking assertion may include the following steps: While waiting for the rising edge of the bus clock signal to arrive, monitor whether the HREADY signal is 0. If not, the counter is cleared and continues to wait for the rising edge of the bus clock signal to arrive. If yes, the low level time of the HREADY signal is counted and the counter is incremented by 1. When the count value of the counter is greater than the set time upper limit, a check error is generated, otherwise it continues to wait for the rising edge of the bus clock signal to arrive.

[0032] For the specific limitations of the AHB interface universal verification method in chip design, please refer to the corresponding limitations of the AHB interface universal verification system in chip design above, which will not be repeated here.

[0033] It should be understood that although Figure 6 The steps in the method are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figure 6 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0034] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (RambusDRAM, referred to as RDRAM) and interface dynamic random access memory (DRDRAM).

[0035] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0036] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A universal verification system for AHB interface in chip design, characterized in that: It includes developing a verification platform and a chip top layer based on SystemVerilog language, wherein the verification platform is used to provide a required clock signal, a reset signal and a test case for the chip top layer to run; The top layer of the chip includes instantiated CPU components, IP1 components, IP2 components and IP3 components. The CPU components, IP1 components, IP2 components and IP3 components are all integrated with AHB assertion checking modules, and the components are connected through AHB buses. The AHB assertion checking module is used to connect the AHB interface signals of the components to which it belongs and automatically check whether the AHB interface function meets the AHB protocol requirements. If so, the verification is passed, otherwise an error is reported; the AHB assertion checking module includes designed AHB bus HWDATA, HTRANS and HADDR signal check assertions, AHB bus HSIZE signal check assertions, AHB bus HBURST signal check assertions and AHB bus HREADY signal check assertions.

2. The AHB interface universal verification system in chip design according to claim 1, characterized in that: The AHB assertion check module monitors whether the HREADY signal is 0 when waiting for the rising edge of the bus clock signal to arrive during the AHB bus HWDATA, HTRANS and HADDR signal check assertion process, and if not, continues to monitor the HREADY signal, and if yes, monitors whether the HREADY signal is 0 after one clock cycle; If the HREADY signal is 0 after one clock cycle, check whether the HWDATA signal, HTRANS signal and HADDR signal remain stable. If they remain stable, the check is determined to be passed, otherwise a check error is generated; If the HREADY signal is not 0 after one clock cycle, the HREADY signal continues to be monitored.

3. The AHB interface universal verification system in chip design according to claim 1, characterized in that: During the process of the AHB bus HSIZE signal check assertion performed by the AHB assertion check module, when the CPU component initiates any read or write request, it is checked whether the HSIZE signal is less than or equal to 2 and greater than or equal to 0. If so, it is determined that the check is passed, otherwise a check error is generated.

4. The AHB interface universal verification system in chip design according to claim 1, characterized in that: The AHB assertion check module performs an AHB bus HBURST signal check assertion process, and checks whether the current HBURST is in INCR mode and whether the state is NOSEQUENTIAL when waiting for the clock rising edge of the bus clock signal to arrive. If not, continue to check the current HBURST, and if so, check whether the next state of the current HBURST jumps to SEQUENTIAL; If the next state of the current HBURST jumps to SEQUENTIAL, check whether the HADDR signal increases in units of HSIZE. If so, the check is confirmed to pass, otherwise a check error is generated; If the next state of the current HBURST does not jump to SEQUENTIAL, continue to check the current HBURST.

5. The AHB interface universal verification system in chip design according to any one of claims 1 to 4, characterized in that: During the process of the AHB bus HREADY signal check assertion performed by the AHB assertion check module, the HREADY signal is monitored to see if it is 0 while waiting for the rising edge of the bus clock signal to arrive. If not, the counter is cleared and the rising edge of the bus clock signal to arrive is continued. If yes, the low level time of the HREADY signal is counted and the counter is incremented by 1. When the count value of the counter is greater than the set time upper limit, a check error is generated, otherwise it continues to wait for the rising edge of the bus clock signal to arrive.

6. A general verification method for AHB interface in chip design, characterized in that: The invention is applied to a general verification system of an AHB interface in a chip design, including a verification platform and a chip top layer developed based on the SystemVerilog language, wherein the verification platform is used to provide the required clock signal, reset signal and test case for the operation of the chip top layer; The top layer of the chip includes instantiated CPU components, IP1 components, IP2 components and IP3 components. The CPU components, IP1 components, IP2 components and IP3 components are all integrated with AHB assertion checking modules, and the components are connected through AHB buses. The AHB assertion checking module is used to connect the AHB interface signals of the components to which it belongs and automatically check whether the AHB interface function meets the AHB protocol requirements. If so, the verification is passed, otherwise an error is reported; the AHB assertion checking module includes designed AHB bus HWDATA, HTRANS and HADDR signal check assertions, AHB bus HSIZE signal check assertions, AHB bus HBURST signal check assertions and AHB bus HREADY signal check assertions; The general verification method of AHB interface in chip design comprises the following steps: The CPU component is driven by a test program developed based on C language to initiate a read and write request through the AHB bus, and the IP1 component, IP2 component and IP3 component are controlled to work respectively; The AHB assertion check module integrated in each component is used to automatically perform an AHB bus timing check to check whether the AHB interface function meets the AHB protocol requirements; If the AHB interface function meets the AHB protocol requirements, the verification passes; otherwise, an error is reported.

7. The universal verification method for AHB interface in chip design according to claim 6, characterized in that: The process of the AHB assertion check module checking and asserting the AHB bus HWDATA, HTRANS and HADDR signals includes: When waiting for the rising edge of the bus clock signal to arrive, monitor whether the HREADY signal is 0, if not, continue to monitor the HREADY signal, and if yes, monitor whether the HREADY signal is 0 after one clock cycle; If the HREADY signal is 0 after one clock cycle, check whether the HWDATA signal, HTRANS signal and HADDR signal remain stable. If they remain stable, the check is determined to be passed, otherwise a check error is generated; If the HREADY signal is not 0 after one clock cycle, the HREADY signal continues to be monitored.

8. The universal verification method for AHB interface in chip design according to claim 6, characterized in that: The process of the AHB assertion check module performing the AHB bus HSIZE signal check assertion includes: When the CPU component initiates any read or write request, it checks whether the HSIZE signal is less than or equal to 2 and greater than or equal to 0. If so, it is determined that the check is passed, otherwise a check error is generated.

9. The general verification method of AHB interface in chip design according to claim 6, characterized in that: The process of the AHB assertion check module performing the AHB bus HBURST signal check assertion includes: When waiting for the rising edge of the bus clock signal, check whether the current HBURST is in INCR mode and whether the state is NOSEQUENTIAL. If not, continue to check the current HBURST. If yes, check whether the next state of the current HBURST jumps to SEQUENTIAL. If the next state of the current HBURST jumps to SEQUENTIAL, check whether the HADDR signal increases in units of HSIZE. If so, the check is confirmed to pass, otherwise a check error is generated; If the next state of the current HBURST does not jump to SEQUENTIAL, continue to check the current HBURST.

10. The universal verification method for AHB interface in chip design according to any one of claims 6 to 9, characterized in that: The process of the AHB assertion check module performing the AHB bus HREADY signal check assertion includes: When waiting for the rising edge of the bus clock signal to arrive, monitor whether the HREADY signal is 0, if not, clear the counter and continue to wait for the rising edge of the bus clock signal to arrive, if yes, count the low level time of the HREADY signal and increase the counter by 1; When the count value of the counter is greater than the set time upper limit, a check error is generated, otherwise it continues to wait for the rising edge of the bus clock signal to arrive.

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