Circuit and equipment for FPGA prototype verification of NFC chip

Abstract

The invention relates to the technical field of NFC chip verification, and discloses a circuit and equipment for NFC chip FPGA prototype verification, and the circuit comprises a power conversion module, an SE interface verification circuit, and an RF interface verification circuit. The power supply conversion module is configured to reduce external power supply voltage and output working voltage of the SE interface verification circuit and the RF interface verification circuit; the SE interface verification circuit is configured to be connected with an SE related digital interface; and the RF interface verification circuit is configured to be connected with RF signal receiving equipment. The SE interface verification circuit and the RF interface verification circuit are integrated in the same circuit, the circuit is used for FPGA prototype verification of an NFC chip, verification can cover related scenes where SE and RF work at the same time, comprehensive verification is carried out on a related digital interface module and an RF module of the SE before chip tape-out, verification efficiency is improved, and verification coverage rate is increased.

Description

Technical Field

[0001] The present application relates to the technical field of NFC chip verification, for example, to a circuit and device for NFC chip FPGA prototype verification. Background Art

[0002] NFC (Near Field Communication) is a technology that allows wireless communication within a short distance and is commonly used in applications such as mobile payment and data transmission. The NFC chip can send digital signals through the transmitting circuit and can also resolve the analog signals of the receiving circuit into digital signals. NFC chips usually include an SE (Secure Element) module and an RF (Radio Frequency) module. SE is a security module that can realize functions such as data security storage, encryption and decryption operations. RF is a radio frequency module that can realize the sending and receiving of wireless signals. In the NFC chip FPGA (Field-Programmable Gate Array) prototype verification, it is very important to verify the SE and RF modules. Only through effective verification can the stability and reliability of the chip in various practical application scenarios be ensured, thereby improving product quality and meeting market demand.

[0003] In the related art, different adapter boards and various types of circuit boards are used to verify the SE and RF modules respectively.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] The working environments of different types of circuit boards are different, so it is difficult to verify the relevant scenarios where SE / RF work simultaneously, and the verification coverage is low.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide a circuit and a device for NFC chip FPGA prototype verification, so as to improve the verification coverage of the NFC chip.

[0009] In some embodiments, the circuit used for NFC chip FPGA prototype verification includes: a power conversion module, an SE interface verification circuit, and an RF interface verification circuit; the power conversion module is configured to step down the external power supply voltage and output the working voltage of the SE interface verification circuit and the RF interface verification circuit; the SE interface verification circuit is configured to be connected to the SE-related digital interface; the RF interface verification circuit is configured to be connected to the RF signal receiving device.

[0010] Optionally, the power conversion module includes: a first LDO (Low DropOut Voltage Regulator) chip, a second LDO chip, and a voltage reference chip; the first LDO chip is configured to step down the external power supply voltage to a first target voltage; the second LDO chip is configured to step down the first target voltage to a second target voltage; the voltage reference chip is configured to step down the external power supply voltage to a reference voltage.

[0011] Optionally, the SE interface verification circuit includes: a SWP (Single Wire Protocol Interface) interface verification circuit and a 7816 interface verification circuit; the SWP interface verification circuit is configured to convert the level of the FPGA output into a SWP communication master-slave signal; the 7816 interface verification circuit is configured to convert the level of the FPGA output into a clock signal and a data signal in 7816 communication.

[0012] Optionally, the SWP interface verification circuit includes: a sending path, a receiving path, and a card slot power supply circuit; the sending path is configured to convert the level sent by the FPGA into a signal level on the SWP bus and send it to the SIM card; the receiving path is configured to convert the reply signal of the SIM card into a signal on the SWP bus so that the FPGA receives the signal; the card slot power supply circuit is configured to power the SIM card in the SIM card slot.

[0013] Optionally, the sending path includes: a first output buffer, a differential amplifier, a symmetrical output driver, and a second output buffer; the TX pin of the SWP bus in the FPGA is connected to the input of the first output buffer; the output of the first output buffer is connected to the +IN pin of the differential amplifier; the -IN pin of the differential amplifier device is connected to the VPP pin of the SIM card slot; the output pin of the differential amplifier is connected to the +INA and +INB pins of the symmetrical output driver; the output pin of the symmetrical output driver is connected to the input of the second output buffer; and the output of the second output buffer is connected to the RX pin of the SWP bus in the FPGA.

[0014] Optionally, the card slot power supply circuit includes: a voltage stabilizing device; a pin in the FPGA that controls the SIM power supply is connected to a control pin of the voltage stabilizing device; and an output pin of the voltage stabilizing device is connected to a power port of the SIM card slot.

[0015] Optionally, the 7816 interface verification circuit includes: a clock output circuit, a reset circuit and a data path; the clock output circuit includes a first level isolation chip, the input pin of the first level isolation chip is connected to the pin providing the clock in the FPGA, and the output pin of the first level isolation chip is connected to the CLK pin of the 7816; the reset circuit includes a second level isolation chip, the input pin of the second level isolation chip is connected to the pin providing the reset level in the FPGA, and the output pin of the second level isolation chip is connected to the RST pin of the 7816; the data path includes a bidirectional level isolation chip, the IO / VL2 pin of the bidirectional level isolation chip is connected to the pin for sending data in the FPGA; the IO / VCC2 pin of the bidirectional level isolation chip is connected to the I / O pin of the 7816 bus.

[0016] Optionally, the RF interface verification circuit includes: an RF antenna board and a security chip; the RF antenna board is connected to the FPGA chip; the analog signal received by the RF antenna board can be transmitted to the FPGA chip for processing, and the data of the FPGA chip can also be sent through the RF antenna board; the security chip is configured to control data communication between the RF antenna board and the FPGA chip.

[0017] Optionally, the RF interface verification circuit further includes: a first row of pins; a SWD interface of the first row of pins is connected to the security chip and is configured to download a program to the RF antenna board through the SWD interface.

[0018] In some embodiments, a device for NFC chip FPGA prototype verification includes: a circuit for NFC chip FPGA prototype verification as described above.

[0019] The circuit and device for NFC chip FPGA prototype verification provided by the embodiments of the present disclosure can achieve the following technical effects:

[0020] The circuit for NFC chip FPGA prototype verification provided by the embodiment of the present disclosure includes a power conversion module, an SE interface verification circuit, and an RF interface verification circuit. The power conversion module can step down the external power supply voltage to obtain the working voltage of the SE interface verification circuit and the RF interface verification circuit. The SE interface verification circuit and the RF interface verification circuit are integrated in the same circuit, and the circuit is used to perform FPGA prototype verification of the NFC chip, so that the verification covers the relevant scenarios of SE / RF working at the same time, and the relevant digital interface modules and RF modules of SE are fully verified before the chip is taped out, thereby improving the verification efficiency and increasing the verification coverage. In addition, only one circuit board is needed in the verification process, which simplifies the verification process, and also helps to speed up the time to market, improve product quality, and reduce overall development costs.

[0021] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0023] Figure 1 It is a circuit block diagram of a circuit for NFC chip FPGA prototype verification provided by an embodiment of the present disclosure;

[0024] Figure 2 It is a circuit block diagram of a power conversion module in a circuit for NFC chip FPGA prototype verification provided by an embodiment of the present disclosure;

[0025] Figure 3 It is a circuit diagram of a peripheral circuit of a first LDO chip in a circuit for NFC chip FPGA prototype verification provided by an embodiment of the present disclosure;

[0026] Figure 4 It is a circuit diagram of a peripheral circuit of a second LDO chip in a circuit for NFC chip FPGA prototype verification provided by an embodiment of the present disclosure;

[0027] Figure 5 It is a circuit diagram of a peripheral circuit of a voltage reference chip in a circuit for NFC chip FPGA prototype verification provided by an embodiment of the present disclosure;

[0028] Figure 6 It is a circuit block diagram of a sending path in a circuit for NFC chip FPGA prototype verification provided by an embodiment of the present disclosure;

[0029] Figure 7It is a circuit diagram of a peripheral circuit of a first output buffer in a circuit for NFC chip FPGA prototype verification provided by an embodiment of the present disclosure;

[0030] Figure 8 It is a circuit diagram of a peripheral circuit of a differential amplifier in a circuit for NFC chip FPGA prototype verification provided by an embodiment of the present disclosure;

[0031] Fig. 9 It is a circuit diagram of a peripheral circuit of a symmetrical output driver in a circuit for NFC chip FPGA prototype verification provided by an embodiment of the present disclosure;

[0032] Fig.10 It is a circuit diagram of a peripheral circuit of a second output buffer in a circuit for NFC chip FPGA prototype verification provided by an embodiment of the present disclosure;

[0033] Fig.11 It is a circuit diagram of a peripheral circuit of a voltage stabilizing device in a circuit for NFC chip FPGA prototype verification provided by an embodiment of the present disclosure;

[0034] Fig.12 This is a connection diagram of pins of a SIM card slot in a circuit for NFC chip FPGA prototype verification provided by an embodiment of the present disclosure;

[0035] Fig.13 It is a circuit block diagram of a 7816 interface verification circuit in a circuit for NFC chip FPGA prototype verification provided by an embodiment of the present disclosure;

[0036] Fig.14 It is a circuit diagram of a peripheral circuit of a first level isolation chip in a circuit for NFC chip FPGA prototype verification provided by an embodiment of the present disclosure;

[0037] Fig.15 It is a circuit diagram of a peripheral circuit of a second level isolation chip in a circuit for NFC chip FPGA prototype verification provided by an embodiment of the present disclosure;

[0038] Fig.16 It is a circuit diagram of a peripheral circuit of a bidirectional level isolation chip in a circuit for NFC chip FPGA prototype verification provided by an embodiment of the present disclosure;

[0039] Fig.17 (a) and Fig.17 (b) is a schematic diagram of the connection pins of a THN31 chip in a circuit for NFC chip FPGA prototype verification provided by an embodiment of the present disclosure;

[0040] Fig.18This is a connection diagram of pins of the first row of pins in a circuit for NFC chip FPGA prototype verification provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0042] The terms "first", "second", etc. in the technical solutions described in this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the disclosed embodiments described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0043] Unless otherwise stated, the term "plurality" means two or more.

[0044] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0045] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0046] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0047] Combination Figure 1 As shown, the embodiment of the present disclosure provides a circuit for NFC chip FPGA prototype verification, including a power conversion module 10, an SE interface verification circuit 20, and an RF interface verification circuit 30. The power conversion module 10 is configured to step down the external power supply voltage and output the working voltage of the SE interface verification circuit 20 and the RF interface verification circuit 30. The SE interface verification circuit 20 is configured to be connected to the SE-related digital interface. The RF interface verification circuit 30 is configured to be connected to the RF signal receiving device.

[0048] In the disclosed embodiment, the power conversion module 10 can step down the external power supply voltage to obtain the operating voltage of the SE interface verification circuit 20 and the RF interface verification circuit 30. The SE interface verification circuit 20 and the RF interface verification circuit 30 are integrated in the same circuit, and the circuit is used to verify the FPGA prototype of the NFC chip, so that the verification covers the relevant scenarios of SE / RF working at the same time, and the relevant digital interface modules and RF modules of the SE are fully verified before the chip is taped out, thereby improving the verification efficiency and increasing the verification coverage. In addition, only one circuit board is needed in the verification process, which simplifies the verification process, helps to speed up the time to market, improve product quality, and reduce the overall development cost.

[0049] Optionally, combined Figure 2 As shown, the power conversion module 10 includes: a first LDO chip U1, a second LDO chip U2, and a voltage reference chip U3. The first LDO chip U1 is configured to step down the external power supply voltage to a first target voltage. The second LDO chip U2 is configured to step down the first target voltage to a second target voltage. The voltage reference chip U3 is configured to step down the external power supply voltage to a reference voltage.

[0050] In this embodiment, the external power supply voltage is stepped down to a first target voltage through the first LDO chip U1, and the first target voltage is stepped down to a second target voltage through the second LDO chip U2. The external power supply voltage outputs a reference voltage through the voltage reference chip U3.

[0051] Optionally, the external power supply voltage is 5V, the first target voltage is 3.3V, the second target voltage is 1.8V, the reference voltage includes a first reference voltage and a second reference voltage, the first reference voltage is 2.5V, and the second reference voltage is 2V.

[0052] In this embodiment, the first target voltage and the second target voltage are used as power supply voltages of electronic devices in the interface verification circuit; the first reference voltage and the second reference voltage are used as reference voltages in the interface verification circuit.

[0053] Optionally, the models of the first LDO chip U1 and the second LDO chip U2 are LM117.

[0054] Optionally, combined Figure 3As shown, the peripheral circuit of the first LDO chip U1 includes: a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a second row of pins J2, a first resistor R1, a second resistor R2, a third resistor R3, and a first light emitting diode D1. The external power supply voltage is connected to the first end of the first capacitor C1, the first end of the second capacitor C2, the first end of the second row of pins J2, and the VIN pin of the first LDO chip U1; the second end of the first capacitor C1 and the second end of the second capacitor C2 are grounded; the first end of the second row of pins J2 is grounded; the VOUT pin of the first LDO chip U1 is connected to the TAB pin of the first LDO chip U1, the first end of the third capacitor C3, the first end of the fourth capacitor, the first end of the first resistor R1, the first end of the second resistor R2, and the first end of the third resistor R3; the second end of the third capacitor C3 and the second end of the fourth capacitor are grounded; the second end of the first resistor R1 is connected to the positive electrode of the first light-emitting diode D1; the negative electrode of the first light-emitting diode D1 is grounded; the second end of the second resistor R2 outputs a voltage signal VDDIO_IN; the second end of the third resistor R3 outputs a first target voltage 3.3VDD.

[0055] Optionally, combined Figure 4 As shown, the peripheral circuit of the second LDO chip U2 includes: a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The voltage signal VDDIO_IN is connected to the first end of the fifth capacitor C5, the first end of the sixth capacitor C6, and the VIN pin of the second LDO chip U2; the second end of the fifth capacitor C5 and the second end of the sixth capacitor C6 are grounded; the VOUT pin of the second LDO chip U2 is connected to the TAB pin of the second LDO chip U2, the first end of the seventh capacitor C7, the first end of the eighth capacitor C8, the first end of the fourth resistor R4, the first end of the fifth resistor R5, and the first end of the sixth resistor R6; the second end of the seventh capacitor C7 and the second end of the eighth capacitor C8 are grounded; the second end of the fourth resistor R4 outputs the voltage signal VDDIO; the second end of the fifth resistor R5 outputs the second target voltage 1.8VDD; the second end of the sixth resistor R6 outputs the voltage signal VDDIO_SE.

[0056] Optionally, the capacitance of the first capacitor C1, the third capacitor C3, the fifth capacitor C5, and the seventh capacitor C7 is 10 μF, and the capacitance of the second capacitor C2, the fourth capacitor C6, the sixth capacitor C6, and the eighth capacitor C8 is 0.1 μF.

[0057] In the peripheral circuits of the first LDO chip U1 and the second LDO chip U2, the VIN pin of the first LDO chip U1 is connected to the first capacitor C1 and the second capacitor C2, and the VIN pin of the second LDO chip U2 is connected to the fifth capacitor C5 and the sixth capacitor C6 to filter out high-frequency and low-frequency noise. The VOUT pin of the first LDO chip U1 is connected to the third capacitor C3 and the fourth capacitor, and the VOUT pin of the second LDO chip U2 is connected to the seventh capacitor C7 and the eighth capacitor C8 to filter out output noise.

[0058] Optionally, combined Figure 5 As shown, the surrounding circuit of the voltage reference chip U3 includes: a ninth capacitor C9, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a tenth resistor R10; the first end of the ninth capacitor C9 and the first end of the seventh resistor R7 are connected to the external power supply voltage; the second end of the ninth capacitor C9 is grounded; the second end of the seventh resistor R7, the output pin of the voltage reference chip U3, and the first end of the eighth resistor R8 are connected, and the reference voltage REF is output; the second end of the eighth resistor R8, the feedback pin of the voltage reference chip U3, and the first end of the ninth resistor R9 are connected; the second end of the ninth resistor R9 is connected to the first end of the tenth resistor R10; the second end of the tenth resistor R10 and the ground pin of the voltage reference chip U3 are grounded.

[0059] In this embodiment, the calculation formula of the reference voltage REF is:

[0060]

[0061] Wherein, r10 is the resistance value of the tenth resistor R10, r9 is the resistance value of the ninth resistor R9, and r8 is the resistance value of the eighth resistor R8. The reference voltage REF can be adjusted by modifying the resistance value. Therefore, when it is necessary to obtain a first reference voltage REF_2.5V of 2.5V, r10=22KΩ, r9=100KΩ, r8=120KΩ can be adjusted; and when it is necessary to obtain a second reference voltage REF_2.0V of 2V, r10=5.6KΩ, r9=68KΩ, r8=120KΩ can be adjusted.

[0062] Optionally, combined Figure 1 As shown, the SE interface verification circuit 20 includes: an SWP interface verification circuit 21 and a 7816 interface verification circuit 22. The SWP interface verification circuit 21 is configured to convert the level output by the FPGA into a SWP communication master-slave signal. The 7816 interface verification circuit 22 is configured to convert the level output by the FPGA into a clock signal and a data signal in the 7816 communication.

[0063] In this embodiment, the verification of the relevant digital interfaces of the SE module mainly includes the verification of the SWP interface and the 7816 interface. Through level conversion processing, the SWP interface verification circuit 21 and the 7816 interface verification circuit 22 can convert the level output by the FPGA into a signal adapted to the corresponding interface, thereby verifying the relevant interfaces.

[0064] Optionally, the SWP interface verification circuit 21 includes: a sending path, a receiving path, and a card slot power supply circuit. The sending path is configured to convert the level sent by the FPGA into a signal level on the SWP bus and send it to the SIM card. The receiving path is configured to convert the reply signal of the SIM card into a signal on the SWP bus so that the FPGA receives the signal. The card slot power supply circuit is configured to power the SIM card in the SIM card slot.

[0065] In this embodiment, when performing SWP interface verification, it is necessary to insert the SIM card into the card slot to send data to the SIM card and receive a recovery signal from the SIM card, thereby performing SWP interface verification.

[0066] Optionally, combined Figure 6 As shown, the transmission path includes: a first output buffer U4, a differential amplifier U5, a symmetrical output driver U6, and a second output buffer U7. The TX pin FPGA_TX of the SWP bus in the FPGA is connected to the input of the first output buffer U4; the output of the first output buffer U4 is connected to the +IN pin of the differential amplifier U5; the -IN pin of the differential amplifier U5 is connected to the VPP pin of the SIM card slot SIM1; the output pin of the differential amplifier U5 is connected to the +INA and +INB pins of the symmetrical output driver U6; the output pin of the symmetrical output driver U6 is connected to the input of the second output buffer U7; and the output of the second output buffer U7 is connected to the RX pin FPGA_RX of the SWP bus in the FPGA.

[0067] Optionally, combined Figure 7 As shown, the peripheral circuit of the first output buffer U4 includes: the tenth capacitor C10 and the eleventh capacitor C11. The second target voltage 1.8VDD is connected to the first end of the tenth capacitor C10, the first end of the eleventh capacitor C11, and the V+ pin of the first output buffer U4; the second end of the tenth capacitor C10 and the second end of the eleventh capacitor C11 are grounded; the A pin of the first output buffer U4 is connected to the TX pin HSMA_TX_D_P7 of the SWP bus in the FPGA; the Y pin of the first output buffer U4 outputs the signal SWP_IO_CH_I.

[0068] Optionally, the first output buffer U4 has a high drive output.

[0069] Optionally, combined Figure 8 As shown, the peripheral circuit of the differential amplifier U5 includes: a twelfth capacitor C12, a thirteenth capacitor C13, an eleventh resistor R11, and a twelfth resistor R12. The V+ pin of the differential amplifier U5, the first end of the twelfth capacitor C12, and the first end of the thirteenth capacitor C13 are connected to the first target voltage 3.3VDD; the second end of the twelfth capacitor C12 and the second end of the thirteenth capacitor C13 are grounded; the output signal SWP_IO_CH_I of the first output buffer U4 is connected to the first end of the eleventh resistor R11 and the +IN pin of the differential amplifier U5; the reply signal SWP_IO_CH_O of the SIM card is connected to the first end of the twelfth resistor R12 and the -IN pin of the differential amplifier U5; the second end of the eleventh resistor R11 is connected to the second end of the twelfth resistor R12; the VREF1 pin and the VREF2 pin of the differential amplifier U5 are connected to the second reference voltage REF_2.0V; the OUT pin of the differential amplifier U5 outputs the signal IO_AD_OUT.

[0070] In this embodiment, the SIM card generates a pull current when it responds, and generates a voltage difference in the loop composed of the signals SWP_IO_CH_I and SWP_IO_CH_O. When the SIM card responds to "1", the voltage difference is greater than the second reference voltage REF_2.0V, and when it responds to "0", the voltage difference is less than the second reference voltage REF_2.0V. The voltage difference and the second reference voltage REF_2.0V are input to the differential amplifier U5, and the output signal IO_AD_OUT is amplified.

[0071] Optionally, combined Fig. 9As shown, the peripheral circuit of the symmetrical output driver U6 includes: a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a fourteenth capacitor C14, and a fifteenth capacitor C15. The first end of the thirteenth resistor R13 and the first end of the fourteenth resistor R14 are both connected to the output signal IO_AD_OUT of the differential amplifier U5; the second end of the thirteenth resistor R13 is connected to the +INA pin of the symmetrical output driver U6; the second end of the fourteenth resistor R14 is connected to the +INB pin of the symmetrical output driver U6; the -INA and -INB pins of the symmetrical output driver U6 are connected to the first reference voltage REF_2.5V; the VCC pin of the symmetrical output driver U6, the first end of the fourteenth capacitor C14, and the second end of the fifteenth capacitor C15 are connected to the first target voltage 3.3VDD; the second end of the fourteenth capacitor C14 and the second end of the fifteenth capacitor C15 are grounded; the OUTA pin of the symmetrical output driver U6 outputs the signal SWP_IO_CH_IN; the OUTA pin of the symmetrical output driver U6 is connected to the first end of the fifteenth resistor R15; the OUTB pin of the symmetrical output driver U6 is connected to the first end of the sixteenth resistor R16; the second end of the fifteenth resistor R15 and the second end of the sixteenth resistor R16 are connected to the first target voltage 3.3VDD.

[0072] In this embodiment, the symmetrical output driver U6 is used to compare the output signal IO_AD_OUT of the differential amplifier U5 with the first reference voltage REF_2.5V, and output a signal SWP_IO_CH_IN according to the comparison result.

[0073] Optionally, combined Fig.10 As shown, the peripheral circuit of the second output buffer U7 includes: a sixteenth capacitor C16, a seventeenth capacitor C17, and a seventeenth resistor R17. The V+ pin of the second output buffer U7, the first end of the sixteenth capacitor C16, and the first end of the seventeenth capacitor C17 are connected to the first target voltage 3.3VDD; the second end of the sixteenth capacitor C16 and the second end of the seventeenth capacitor C17 are grounded; the output signal SWP_IO_CH_IN of the symmetrical output driver U6 is connected to the A pin of the second output buffer U7 and the first end of the seventeenth resistor R17; the Y pin of the second output buffer U7 is connected to the second end of the seventeenth resistor R17, and is connected to the RX pin HSMA_RX_D_N1 of the SWP bus in the FPGA.

[0074] Optionally, the card slot power supply circuit includes: a voltage stabilizing device; a pin in the FPGA that controls the SIM power supply is connected to a control pin of the voltage stabilizing device; and an output pin of the voltage stabilizing device is connected to a power port of the SIM card slot SIM1.

[0075] Optionally, combined Fig.11As shown, the surrounding circuit of the voltage stabilizer U8 includes: an eighteenth capacitor C18, a nineteenth capacitor C19, a twentieth capacitor C20, and an eighteenth resistor R18. The VIN pin of the voltage stabilizer U8 and the first end of the eighteenth capacitor C18 are connected to the external power supply voltage; the second end of the eighteenth capacitor C18 is grounded; the CE pin of the voltage stabilizer U8 is connected to the first end of the eighteenth resistor R18; the second end of the eighteenth resistor R18 is connected to the FPGA pin HSMA_RX_D_N7; the VOUT pin of the voltage stabilizer U8 is connected to the first end of the nineteenth capacitor C19 and the first end of the twentieth capacitor C20, and outputs the working voltage SWP_18VDD3 of the SIM card; the second end of the nineteenth capacitor C19 and the second end of the twentieth capacitor C20 are grounded.

[0076] In this embodiment, the power supply of the SIM card is controlled by the FPGA pin HSMA_RX_D_N7. When a high level is output, the voltage regulator U8 outputs the working level SWP_18VDD3 of the SIM card.

[0077] Optionally, the SIM card slot SIM1 is as follows Fig.12 As shown, the VCC pin of the SIM card slot SIM1 is connected to the VOUT pin of the voltage regulator U8; the VPP pin of the SIM card slot SIM1 is used to output the reply signal SWP_IO_CH_O of the SIM card.

[0078] Optionally, combined Fig.13 As shown, the 7816 interface verification circuit 22 includes: a clock output circuit 40, a reset circuit 50 and a data path 60. The clock output circuit 40 includes a first level isolation chip U9, the input pin of the first level isolation chip U9 is connected to the pin providing the clock in the FPGA, and the output pin of the first level isolation chip U9 is connected to the CLK pin of the 7816. The reset circuit 50 includes a second level isolation chip U10, the input pin of the second level isolation chip U10 is connected to the pin providing the reset level in the FPGA, and the output pin of the second level isolation chip U10 is connected to the RST pin of the 7816. The data path 60 includes a bidirectional level isolation chip U11, the IO / VL2 pin of the bidirectional level isolation chip U11 is connected to the pin sending data in the FPGA; the IO / VCC2 pin of the bidirectional level isolation chip U11 is connected to the I / O pin of the 7816 bus.

[0079] In this embodiment, the 7816 interface verification circuit 22 includes multiple 7816 interfaces. The pins providing the clock and the pins providing the reset level on the FPGA are connected to the level isolation chip and then output. The pins sending data on the FPGA are connected to the bidirectional level isolation chip U11. The I / O signal level output by the bidirectional level isolation chip U11 can be recognized by another device on the 7816 bus, and the data sent by another device on the 7816 bus can also be sent to the FPGA for parsing through the bidirectional level isolation chip U11.

[0080] Optionally, the models of the first level isolation chip U9 and the second level isolation chip U10 are SN74LVC1T45.

[0081] Optionally, combined Fig.14 As shown, the peripheral circuit of the first level isolation chip U9 includes: a 21st capacitor C21 and a 22nd capacitor C22. The VCCA pin of the first level isolation chip U9 and the first end of the 21st capacitor C21 are connected to the first target voltage 3.3VDD; the second end of the 21st capacitor C21 is grounded; the VCCB pin of the first level isolation chip U9 and the first end of the 22nd capacitor C22 are connected to IOS_VCC2; the second end of the 22nd capacitor C22 is grounded; the A pin of the first level isolation chip U9 is connected to the pin providing the clock in the FPGA; the B pin of the first level isolation chip U9 is connected to the CLK pin ISO7816_CLK of 7816.

[0082] Optionally, the pins in the FPGA that provide the clock include: a HSMA_TX_D_P1 pin and a HSMA_TX_D_N4 pin.

[0083] Optionally, combined Fig.15 As shown, the peripheral circuit of the second level isolation chip U10 includes: a twenty-third capacitor C23 and a twenty-fourth capacitor C24. The VCCA pin of the second level isolation chip U10 and the first end of the twenty-third capacitor C23 are connected to the first target voltage 3.3VDD; the second end of the twenty-third capacitor C23 is grounded; the VCCB pin of the second level isolation chip U10 and the first end of the twenty-fourth capacitor C24 are connected to IOS_VCC2; the second end of the twenty-fourth capacitor C24 is grounded; the A pin of the second level isolation chip U10 is connected to the pin providing the reset level in the FPGA; the B pin of the second level isolation chip U10 is connected to the RST pin ISO7816_RST of 7816.

[0084] Optionally, the pins in the FPGA that provide a reset level include: a HSMA_TX_D_P2 pin and a HSMA_TX_D_N1 pin.

[0085] Optionally, combined Fig.16As shown, the surrounding circuit of the bidirectional level isolation chip U11 includes: a nineteenth resistor R19, a twentieth resistor R20, a twenty-fifth capacitor C25, and a twenty-sixth capacitor C26; the IO / VL2 pin of the bidirectional level isolation chip U11 is connected to the pin for sending data in the FPGA and the first end of the twentieth resistor R20; the second end of the twentieth resistor R20, the first end of the twenty-sixth capacitor C26, and the VL pin of the bidirectional level isolation chip U11 are connected to the first target voltage 3.3VDD; the second end of the twenty-sixth capacitor C26 is grounded; the EN pin of the bidirectional level isolation chip U11 is connected to the first target voltage 3.3VDD; the IO / VCC2 pin of the bidirectional level isolation chip U11 is connected to the I / O pin of the 7816 bus and the first end of the nineteenth resistor R19; the second end of the nineteenth resistor R19, the IO / VCC pin of the bidirectional isolation chip, and the first end of the twenty-fifth capacitor C25 are connected to IOS_VCC3; the second end of the twenty-fifth capacitor C25 is grounded.

[0086] Optionally, the RF interface verification circuit 30 includes: an RF antenna board and a security chip. The RF antenna board is connected to the FPGA chip; the analog signal received by the RF antenna board can be transmitted to the FPGA chip for processing, and the data of the FPGA chip can also be sent through the RF antenna board. The security chip is configured to control the data communication between the RF antenna board and the FPGA chip.

[0087] In this embodiment, the FPGA is directly connected to the RF antenna board for power supply, realizing the bridge connection between the RF antenna board and the FPGA chip. The analog signal received by the RF antenna board can be directly transmitted to the FPGA chip for processing, and the data of the FPGA chip can also be sent through the RF antenna board. The security chip is the main control chip that controls the data communication between the RF antenna board and the FPGA chip, and is connected to the RF antenna board and the FPGA chip through corresponding pins.

[0088] Optionally, the security chip is a THN31 chip. Fig.17 As shown, Fig.17 (a) and Fig.17 (b) Pin diagrams corresponding to two different modules in the THN31 chip.

[0089] Optionally, combined Fig.18 As shown, the RF interface verification circuit 30 further includes: a first row of pins P8. The SWD interface of the first row of pins P8 is connected to the security chip and is configured to download a program to the RF antenna board through the SWD interface.

[0090] The circuit for NFC chip FPGA prototype verification provided by the embodiment of the present disclosure is compatible with 7816, SWP interface and RF interface in SE interface. The SE module and CLF module in the NFC chip can communicate through the SWP interface circuit with the SIM card as a bridge, thereby improving the coverage of NFC chip verification. In addition, the embodiment of the present disclosure integrates different verification functions into one circuit board, reducing development costs.

[0091] The above description and accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent possible changes only. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the technical solutions recorded in this application. As used in the technical solutions recorded in this application, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

Claims

1. A circuit for NFC chip FPGA prototype verification, characterized in that: include: Power conversion module, SE interface verification circuit, RF interface verification circuit; A power conversion module is configured to step down the external power supply voltage and output the working voltage of the SE interface verification circuit and the RF interface verification circuit; The SE interface verification circuit is configured to be connected to a digital interface associated with the SE; The RF interface verification circuit is configured to be connected to an RF signal receiving device.

2. The circuit according to claim 1, characterized in that The power conversion module includes: a first LDO chip, a second LDO chip, and a voltage reference chip; A first LDO chip is configured to step down an external power supply voltage to a first target voltage; A second LDO chip is configured to step down the first target voltage to a second target voltage; The voltage reference chip is configured to step down an external power supply voltage into a reference voltage.

3. The circuit according to claim 1, characterized in that The SE interface verification circuit includes: SWP interface verification circuit and 7816 interface verification circuit; The SWP interface verification circuit is configured to convert the level output by the FPGA into a SWP communication master-slave signal; The 7816 interface verification circuit is configured to convert the level of the FPGA output into the clock signal and data signal in the 7816 communication.

4. The circuit according to claim 3, characterized in that The SWP interface verification circuit includes: a sending path, a receiving path, and a card slot power supply circuit; The sending path is configured to convert the level sent by the FPGA into the signal level on the SWP bus and send it to the SIM card; A receiving path, configured to convert a reply signal of the SIM card into a signal on the SWP bus so that the FPGA receives the signal; The card slot power supply circuit is configured to supply power to the SIM card in the SIM card slot.

5. The circuit according to claim 4, characterized in that The transmission path includes: a first output buffer, a differential amplifier, a symmetrical output driver, and a second output buffer; The TX pin of the SWP bus in the FPGA is connected to the input of the first output buffer; the output of the first output buffer is connected to the +IN pin of the differential amplifier; the -IN pin of the differential amplifier device is connected to the VPP pin of the SIM card slot; the output pin of the differential amplifier is connected to the +INA and +INB pins of the symmetrical output driver; the output pin of the symmetrical output driver is connected to the input of the second output buffer; and the output of the second output buffer is connected to the RX pin of the SWP bus in the FPGA.

6. The circuit according to claim 4, characterized in that The card slot power supply circuit includes: a voltage stabilizing device; The pin for controlling the SIM power supply in the FPGA is connected to the control pin of the voltage stabilizing device; and the output pin of the voltage stabilizing device is connected to the power port of the SIM card slot.

7. The circuit according to claim 3, characterized in that The 7816 interface verification circuit includes: a clock output circuit, a reset circuit and a data path; The clock output circuit includes a first level isolation chip, the input pin of the first level isolation chip is connected to the pin providing the clock in the FPGA, and the output pin of the first level isolation chip is connected to the CLK pin of the 7816; The reset circuit includes a second level isolation chip, the input pin of the second level isolation chip is connected to the pin providing the reset level in the FPGA, and the output pin of the second level isolation chip is connected to the RST pin of the 7816; The data path includes a bidirectional level isolation chip, the IO / VL2 pin of the bidirectional level isolation chip is connected to the pin for sending data in the FPGA; the IO / VCC2 pin of the bidirectional level isolation chip is connected to the I / O pin of the 7816 bus.

8. The circuit according to any one of claims 1 to 7, characterized in that: The RF interface verification circuit includes: an RF antenna board and a security chip; The RF antenna board is connected to the FPGA chip; the analog signal received by the RF antenna board can be transmitted to the FPGA chip for processing, and the data of the FPGA chip can also be sent through the RF antenna board; The security chip is configured to control data communication between the RF antenna board and the FPGA chip.

9. The circuit according to claim 8, characterized in that The RF interface verification circuit also includes: a first row of pins; The SWD interface of the first row of pins is connected to the security chip and is configured to download programs to the RF antenna board through the SWD interface.

10. A device for NFC chip FPGA prototype verification, characterized in that: include: A circuit for NFC chip FPGA prototype verification as claimed in any one of claims 1 to 9.

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