Pixel circuit, driving method thereof and display panel

Abstract

The application discloses a pixel circuit, a driving method thereof and a display panel. The pixel circuit comprises a driving transistor which is an N-type transistor; a compensation module, a first end of which is electrically connected to a first node at a gate of the driving transistor, and a second end of which is electrically connected to a second node at a first pole of the driving transistor; a writing module, a first end of which is electrically connected to a data voltage end, and a second end of which is electrically connected to a first pole plate of a first capacitor, and a second pole plate of the first capacitor is electrically connected to the gate of the driving transistor; a first light-emitting control module, a first end of which is electrically connected to a first power voltage end, and a second end of which is electrically connected to the second node; a second light-emitting control module, a first end of which is electrically connected to the second pole of the driving transistor at a third node, and a second end of which is electrically connected to a light-emitting element at a fourth node; and a second capacitor, a first pole plate of which is electrically connected to the first node, and a second pole plate of which is electrically connected to the fourth node. By using the technical scheme, the residual image and the screen flicker caused by the hysteresis of the driving transistor can be improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a pixel circuit and its driving method, and a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently the mainstream technology for monitors in mobile phones, televisions, computers, and other devices. Compared with traditional liquid crystal displays (LCDs), OLEDs have advantages such as low energy consumption, low cost, self-illumination, wide viewing angle, and fast response time.

[0003] Organic light-emitting displays (OLEDs) are driven by electric current, requiring a stable driving current to control their light emission. The magnitude and stability of the driving current in OLEDs primarily depend on the magnitude and stability of the gate-source voltage and threshold voltage of the driving transistors in the pixel circuit.

[0004] However, due to the hysteresis effect of the driving transistor, the threshold voltage will drift, resulting in unstable driving current and easy occurrence of ghosting or screen flickering. Summary of the Invention

[0005] This invention provides a pixel circuit and its driving method, as well as a display panel, to improve the problems of ghosting and screen flickering caused by the hysteresis of the driving transistor.

[0006] According to one aspect of the present invention, a pixel circuit is provided, comprising: a driving transistor, a light-emitting element, a compensation module, a writing module, a first light-emitting control module, a second light-emitting control module, a first capacitor, and a second capacitor;

[0007] The first end of the compensation module is electrically connected to the gate of the driving transistor at the first node, and the second end of the compensation module is electrically connected to the first electrode of the driving transistor at the second node; the first end of the write module is electrically connected to the data voltage terminal, the second end of the write module is electrically connected to the first plate of the first capacitor, and the second plate of the first capacitor is electrically connected to the gate of the driving transistor.

[0008] The first terminal of the first light-emitting control module is electrically connected to the first power supply voltage terminal, and the second terminal of the first light-emitting control module is electrically connected to the second node.

[0009] The first terminal of the second light-emitting control module is electrically connected to the second electrode of the driving transistor at the third node, and the second terminal of the second light-emitting control module is electrically connected to the light-emitting element at the fourth node.

[0010] The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the fourth node.

[0011] The driving transistor is an N-type transistor.

[0012] According to another aspect of the present invention, a method for driving a pixel circuit is provided, for driving the aforementioned pixel circuit; the driving method includes:

[0013] During the reset phase, the first power supply voltage terminal is connected to the second node, and the first node is connected to the second node.

[0014] During the compensation phase, the second node is connected to the first node, the first power supply voltage terminal is connected to the second node, or the third node is connected to the fourth node.

[0015] During the writing phase, the data voltage terminal is connected to the first plate of the first capacitor;

[0016] During the light-emitting stage, the first power supply voltage terminal is connected to the second node, and the third node is connected to the fourth node.

[0017] According to another aspect of the present invention, a display panel is provided, comprising: a plurality of the above-described pixel circuits arranged in an array.

[0018] The technical solution of this invention, by setting the driving transistor as an N-type transistor, makes the charge carriers in the driving transistor electrons, resulting in higher mobility and lower sensitivity to threshold voltage, thus improving the hysteresis and threshold voltage drift of the driving transistor. By setting the writing module coupled to the gate of the driving transistor and the compensation module connected between the gate and the first electrode of the driving transistor, the compensation stage and the writing stage can be separated, allowing sufficient time for the threshold voltage compensation process. This is beneficial for improving the charging rate during the threshold voltage compensation process. Even if the pixel circuit is at a fixed gray level for a long time or the refresh rate is low, and the threshold voltage shifts, the compensation module can completely compensate the shifted threshold voltage to the driving transistor, improving the light emission accuracy and reducing the problems of image retention and low gray level flicker. In addition, a first capacitor and a second capacitor are also set. The first node and the third node can be coupled through the first capacitor and the second capacitor, thereby achieving precise control of the gate-source voltage of the driving transistor, which is beneficial for light emission accuracy. At the same time, the magnitude of the driving current can be adjusted through the first capacitor and the second capacitor, thereby achieving the range control of the data signal, which helps to reduce the gate voltage drop of the driving transistor, further improving the hysteresis and threshold voltage drift of the driving transistor, and improving the display quality.

[0019] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the circuit structure of a pixel circuit provided in an embodiment of the present invention;

[0022] Figure 2 This is a top view structural diagram of a display panel provided in an embodiment of the present invention;

[0023] Figure 3 This is a timing diagram of a pixel circuit provided in an embodiment of the present invention;

[0024] Figure 4 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention;

[0025] Figure 5 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention;

[0026] Figure 6 This is a timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0027] Figure 7 This is a timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0028] Figure 8 This is a schematic diagram of a pixel circuit refresh provided in an embodiment of the present invention;

[0029] Figure 9 This is a timing diagram of a display panel provided in an embodiment of the present invention;

[0030] Figure 10 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention;

[0031] Figure 11 This is a timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0032] Figure 12 This is a timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0033] Figure 13 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention;

[0034] Figure 14This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention;

[0035] Figure 15 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention;

[0036] Figure 16 This is a timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0037] Figure 17 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention;

[0038] Figure 18 This is a timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0039] Figure 19 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention;

[0040] Figure 20 This is a flowchart of a pixel circuit driving method provided in an embodiment of the present invention;

[0041] Figure 21 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0042] Figure 22 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0043] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0044] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0045] The above is the core idea of ​​this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings.

[0046] Figure 1 This is a schematic diagram of a pixel circuit structure provided in an embodiment of the present invention. (Reference) Figure 1 The pixel circuit 10 includes a driving transistor M3, a light-emitting element OLED, a compensation module 11, a writing module 12, a first light-emitting control module 13, a second light-emitting control module 14, a first capacitor C1, and a second capacitor C2, wherein the driving transistor M3 is an N-type transistor.

[0047] The first terminal of the compensation module 11 is electrically connected to the gate of the driving transistor M3 at the first node N1, and the second terminal of the compensation module 11 is electrically connected to the first electrode of the driving transistor M3 at the second node N2. The first terminal of the write module 12 is electrically connected to the data voltage terminal, and the second terminal of the write module 12 is electrically connected to the first plate of the first capacitor C1. The second plate of the first capacitor C1 is electrically connected to the gate of the driving transistor M3. The first terminal of the first light-emitting control module 13 is electrically connected to the first power supply voltage terminal, and the second terminal of the first light-emitting control module 13 is electrically connected to the second node N2. The first terminal of the second light-emitting control module 14 is electrically connected to the second electrode of the driving transistor M3 at the third node N3, and the second terminal of the second light-emitting control module 14 is electrically connected to the light-emitting element OLED at the fourth node N4. The first plate of the second capacitor C2 is electrically connected to the first node N1, and the second plate of the second capacitor C2 is electrically connected to the fourth node N4.

[0048] Specifically, the first end of the writing module 12 can be electrically connected to the data voltage terminal via the data line Data_L to receive the data signal Data from the data voltage terminal; when the writing module 12 is turned on, the data signal Data can be transmitted to the first plate of the first capacitor C1 through the writing module 12. The first end of the first light-emitting control module 13 can be electrically connected to the first power supply voltage terminal via the first power line PV1_L to receive the first power signal PV1 from the first power supply voltage terminal.

[0049] Furthermore, the control terminal of the writing module 12 can be electrically connected to the first scan line SP_L to receive the first scan signal SP; the level of the first scan signal SP can control the on / off state of the writing module 12. The control terminal of the compensation module 22 can be electrically connected to the second scan line S2N_L to receive the second scan signal S2N; the level of the second scan signal S2N can control the on / off state of the compensation module 11. The control terminal of the first light emission control module 13 can be electrically connected to the first light emission control line EM1_L to receive the first light emission control signal EM1; the level of the first light emission control signal EM1 can control the on / off state of the first light emission control module 13. The control terminal of the second light emission control module 14 can be electrically connected to the second light emission control line EM2_L to receive the second light emission control signal EM2; the level of the second light emission control signal EM2 can control the on / off state of the second light emission control module 14.

[0050] For example, the pixel circuit 10 can be applied to a display panel. Figure 2 This is a top view structural diagram of a display panel provided in an embodiment of the present invention. (Reference) Figure 2 The display area AA of the display panel 01 can be configured with multiple pixel circuits 10 arranged in an array, multiple first scan lines SP_L, multiple second scan lines S2N_L, multiple first light emission control lines EM1_L, and multiple second light emission control lines EM2_L. The non-display area NA of the display panel 01 can be configured with a first driving circuit 20, which includes a first shift register VSR1, a second shift register VSR2, a third shift register VSR3, and a fourth shift register VSR4. Each of the first shift register VSR1, second shift register VSR2, third shift register VSR3, and fourth shift register VSR4 includes multiple cascaded shift register units.

[0051] refer to Figure 1 and Figure 2The first shift register VSR1 can output a sequentially shifted first scan signal SP. At least one shift register unit of the first shift register VSR1 can be electrically connected to a first scan line SP_L. The first scan line SP_L can be electrically connected to the control terminal of the write module 12 of the pixel circuit 10. The second shift register VSR2 can output a sequentially shifted second scan signal S2N. At least one shift register unit of the second shift register VSR2 can be electrically connected to a second scan line S2N_L. The second scan line S2N_L can be electrically connected to the control terminal of the compensation module 11 of the pixel circuit 10. The third shift register VSR3 can output a sequentially shifted first light emission control signal EM1. At least one shift register unit of the third shift register VSR3 can be electrically connected to a first light emission control line EM1_L. The first light emission control line EM1_L can be electrically connected to the control terminal of the first light emission control module 13 of the pixel circuit 10. The fourth shift register VSR4 can output the second light emission control signal EM2, which is shifted sequentially. At least one shift register unit of the fourth shift register VSR4 can be electrically connected to a second light emission control line EM2_L. The second light emission control line EM2_L can be electrically connected to the control terminal of the second light emission control module 14 of the pixel circuit 10.

[0052] The display area AA of the display panel 01 can also be configured with multiple data lines Data_L, and the non-display area NA can also be configured with a second driving circuit 30. The second driving circuit 30 includes multiple data voltage terminals Do, which can be electrically connected to at least one data line Data_L, and the data line Data_L can be electrically connected to the first terminal of the writing module 12 of the pixel circuit 10.

[0053] In addition, the display area AA of the display panel 01 can also be equipped with multiple first power lines PV1_L and multiple second power lines PV2_L. Figure 2 (Not shown in the image), the display panel 01 may also include a first power supply voltage terminal and a second power supply voltage terminal (not shown in the image). Figure 2 (Not shown in the image) The first power supply voltage terminal is used to provide a first power signal PV1 to the first power line PV1_L, which can be electrically connected to the first terminal of the first light-emitting control module 13 of the pixel circuit 10. The second power supply voltage terminal is used to provide a second power signal PV2 to the second power line PV2_L, which can be electrically connected to the light-emitting element OLED.

[0054] It should be noted that the figure only exemplifies how the shift register unit in the shift register is electrically connected to only one scan line or one light emission control line, and how the data voltage terminal is electrically connected to only one data line. In other embodiments, at least some of the shift register units in the shift register may be electrically connected to multiple scan lines or multiple light emission control lines, and the data voltage terminal may be electrically connected to multiple data lines via a gating switch (not shown in the figure).

[0055] It should also be noted that the figure only exemplifies the location of the first, second, third, and fourth shift registers, which are all located on both sides of the display area. The embodiments of the present invention do not limit the location of the shift registers. In an optional embodiment, at least some of the shift registers may be located only on one side of the display area. In yet another optional embodiment, at least some of the shift registers may be located within the display area.

[0056] The working principle of the pixel circuit provided in the embodiments of this application will be explained below with reference to timing.

[0057] For example, Figure 3 This is a timing diagram of a pixel circuit provided in an embodiment of the present invention. Figure 3 Specifically, it can be corresponded to Figure 1 In one embodiment of the driving timing of the pixel circuit shown, the second plate of the first capacitor C1 can be directly electrically connected to the gate of the driving transistor M3 at the first node N1. That is, no device or component is disposed between the second plate of the first capacitor C1 and the gate of the driving transistor M3, but they can be electrically connected through conductive structures (not shown in the figure) such as metal wires, lap holes, and lap electrodes.

[0058] like Figure 3 As shown, the operating period of the pixel circuit 10 includes a refresh phase tf, and each refresh phase tf includes a reset phase t1, a compensation phase t2, a write phase t3, and a light emission phase t4. For ease of understanding, this embodiment uses a high level as the enable level and a low level as the disable level; in other embodiments, each module can also use a low level as the enable level and a high level as the disable level. It should be noted that the enable level referred to here is the potential that controls the conduction between the first and second terminals of each module, and the disable level is the potential that controls the cutoff or disconnection between the first and second terminals of each module.

[0059] refer to Figures 1-3During the reset phase t1, the first light-emitting control signal EM1 is enabled, the second light-emitting control signal EM2 is disabled, the first scan signal SP is disabled, and the second scan signal S2N is enabled. This enables the first light-emitting control module 13 and the compensation module 11, while the second light-emitting control module 14 and the writing module 12 are disabled. The pixel circuit 10 stops providing driving current to the OLED. The first power supply voltage terminal and the second node N2 are connected, and the first power signal PV1 at the first power supply voltage terminal can be transmitted to the second node N2 through the first light-emitting control module 13. The first node N1 and the second node N2 are connected, and the first power signal PV1 at the second node N2 can be transmitted to the first node N1, resetting the gate and first electrode of the driving transistor M3. This ensures that the voltages of both the first node N1 and the second node N2 are the same as the first power signal PV1, i.e., VN1 = VN2 = PV1.

[0060] During compensation phase t2, the first light-emitting control signal EM1 and the second scanning signal S2N remain enabled, while the second light-emitting control signal EM2 and the first scanning signal SP remain disabled. At the beginning stage when both the first light-emitting control signal EM1 and the second scanning signal S2N are enabled, the first light-emitting control module 13 and the compensation module 11 can be simultaneously in the on state. The signals of the first node N1 and the second node N2 are identical, and the difference between the voltage VN1 of the first node N1 and the voltage VN3 of the third node N3 is greater than the threshold voltage VTH of the driving transistor M3, i.e., VN1 = VN2 > VN3 + VTH. The gate-source voltage VGS of the driving transistor M3 = VN1 - VN3 > VTH, and the driving transistor M3 is in the on state. When the first power supply signal PV1 of the second node N2 is transmitted to the third node N3 through the driving transistor M3, the gate-source voltage VGS of the driving transistor M3 is continuously reduced until VGS = VN1 - VN3 = VTH. The driving transistor M3 is in a transitional state between conduction and cutoff, and the current in the driving transistor M3 is reduced to zero. The signal of the first node N1 is no longer transmitted to the third node N3, and the voltage of the third node N3 is stable. At this time, VN3 = VN1 - VTH = PV1 - VTH, and the threshold voltage is compensated to the third node N3.

[0061] Before the signal from the first node N1 is transmitted to the third node N3 through the compensation module 11 and the driving transistor M3, i.e. before the reset phase t1, the first light-emitting control module 13, the driving transistor M3, and the second light-emitting control module 14 can be turned on simultaneously, so that the pixel circuit 10 provides driving current to the light-emitting element OLED and controls the light-emitting element OLED to emit light. At this time, the driving transistor M3 is in a saturated state, and the on-state voltage drop of the driving transistor M3 VN2-VN3>VTH, so that the voltage of the third node N3 VN3<VN2-VTH, i.e., VN3<PV1-VTH. Therefore, in the reset phase t1, VN1=VN2=PV1, VGS=VN1-VN3>VTH, and the driving transistor M3 can be turned on. In the threshold compensation phase t2, the first power supply signal PV1 of the second node N2 can be transmitted to the third node N3 through the driving transistor M3, continuously reducing the gate-source voltage VGS of the driving transistor M3 until VGS=VN1-VN3=VTH, so that the threshold voltage is compensated to the third node N3.

[0062] During the writing phase t3, the second light emission control signal EM2 remains disabled, while the first light emission control signal EM1 and the second scan signal S2N switch to disabled levels. The first light emission control module 13 can be turned off under the control of the first light emission control signal EM1, thus cutting off the connection between the first power supply voltage terminal and the second node N2, and stopping the transmission of the first power supply signal PV1 from the first power supply voltage terminal to the second node N2. The compensation module 11 can be turned off under the control of the second scan signal S2N, thus cutting off the connection between the first node N1 and the second node N2, preventing the first node N1 from receiving signals from the second node N2, and allowing the voltage of the first node N1 to maintain the voltage from the previous moment.

[0063] After both the first light emission control signal EM1 and the second scan signal S2N switch to the disabled level, the first scan signal SP on the first scan line SP_L switches to the enabled level. The writing module 12 can be turned on under the control of the first scan signal SP, so that the data voltage terminal Do is connected to the first plate of the first capacitor C1. The data signal Data on the data line Data_L can be transmitted to the first plate of the first capacitor C1 through the writing module 12. The voltage of the first plate of the first capacitor C1 is Data, and the voltage change of the first plate of the first capacitor C1 is ΔC1 = Data - Data', where Data' is the data signal Data written by the pixel circuit 10 in the previous working period. Through the first capacitor C1 and the second capacitor C2, the voltage change ΔC1 of the first plate of the first capacitor C1 can be partially coupled to the first node N1. The voltage change ΔN1 of the first node N1 is ΔC1*C1 / (C1+C2) = (Data-Data')*C1 / (C1+C2). The voltage of the third node N3 remains unchanged. At this time, the voltage of the first node N1 is VN1 = PV1 + ΔN1 = PV1 + (Data-Data')*C1 / (C1+C2), and the voltage of the third node N3 is VN3 = PV1 - VTH. The gate-source voltage VGS of the driving transistor M3 is VN1 - VN3 = (Data-Data')*C1 / (C1+C2) + VTH.

[0064] During the light-emitting phase t4, the second scan signal S2N remains at an disabled level, while the first scan signal SP switches to an disabled level. The write module 12 can be cut off under the control of the first scan signal SP, causing a cutoff between the data voltage terminal Do and the first node N1. The data signal Data on the data line Data_L stops transmitting to the first plate of the first capacitor C1, and the first plate of the first capacitor C1 stops receiving the data signal Data. The voltage of the first plate of the first capacitor C1 can maintain the voltage of the previous moment, and the voltage of the first node N1 can also maintain the voltage of the previous moment.

[0065] After the first scan signal SP transitions to an enabled level, both the first light emission control signal EM1 and the second light emission control signal EM2 transition to an enabled level. The first light emission control module 13 can be turned on under the control of the first light emission control signal EM1, and the second light emission control module 14 can be turned on under the control of the second light emission control signal EM2. When the first light emission control module 13, the driving transistor M3, and the second light emission control module 14 are simultaneously turned on, a path can be formed between the first power supply voltage terminal and the second power supply voltage terminal, and the pixel circuit 10 can provide driving current to the light-emitting element OLED. Furthermore, since the second light-emitting control module 14 is turned on, the third node N3 and the fourth node N4 are connected. The voltage of the third node N3 is equal to the voltage of the fourth node N4. The voltage change of the third node N3 can be coupled to the first node N1 through the fourth node N4 and the second capacitor C2. That is, the voltage changes of the first node N1 and the third node N3 can be the same. The gate-source voltage of the driving transistor M3 remains unchanged, still VGS=(Data-Data')*C1 / (C1+C2)+VTH, and the driving current Id=k*[(Data-Data')*C1 / (C1+C2)] 2 The OLED light-emitting element can display corresponding brightness according to the driving current Id. The display grayscale of the pixel circuit 10 can be controlled by controlling the brightness and emission duration of the OLED light-emitting element. Here, k is the current coefficient of the driving transistor M3, which is related to the material properties and size parameters of the driving transistor M3.

[0066] The pixel circuit provided in this embodiment of the invention uses an N-type transistor as the driving transistor, making electrons the carriers in the driving transistor. This results in higher mobility and lower sensitivity to threshold voltage, improving hysteresis and threshold voltage drift. By coupling the writing module to the gate of the driving transistor and connecting the compensation module between the gate and the first electrode of the driving transistor, the compensation and writing phases can be separated. This allows sufficient time for the threshold voltage compensation process, improving the charging rate. Even if the pixel circuit remains at a fixed grayscale or has a low refresh rate for an extended period, causing threshold voltage shift, the compensation module can fully compensate the shifted threshold voltage to the driving transistor, improving light emission accuracy and reducing ghosting and low-grayscale flicker. Furthermore, a first capacitor and a second capacitor are provided. These capacitors couple the first and third nodes, enabling precise control of the gate-source voltage of the driving transistor, further improving light emission accuracy. Simultaneously, the first and second capacitors can adjust the driving current, thereby controlling the range of the data signal. This helps reduce the gate voltage drop of the driving transistor, further improving hysteresis and threshold voltage drift, and enhancing display quality.

[0067] Optional, Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. (Reference) Figure 4 The compensation module 11 includes a compensation transistor M4, the writing module 12 includes a writing transistor M5, the first light-emitting control module 13 includes a first light-emitting control transistor M1, and the second light-emitting control module 14 includes a second light-emitting control transistor M6; the compensation transistor M4, the writing transistor M5, the first light-emitting control transistor M1, and the second light-emitting control transistor M6 are all N-type transistors.

[0068] For example, all transistors in the pixel circuit 10 are N-type transistors, and the active layers of all transistors in the pixel circuit 10 can be arranged on the same layer, reducing the fabrication process and reducing the fabrication cost; moreover, the enable level of the gate of all transistors is high level, and when the pulse width of the enable level is the same, signal multiplexing between different transistors can also be performed.

[0069] In an alternative embodiment, the active layer of the driving transistor M3 comprises a metal oxide material.

[0070] The metal oxide material may include one or more oxides of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), hafnium (Hf), titanium (Ti), and zinc (Zn). Thus, when fabricating the active layer of the driving transistor M3, crystallization is unnecessary, resulting in a lower defect density and higher carrier mobility in the active layer, as well as lower temperature sensitivity. This leads to better voltage stability and switching characteristics of the driving transistor M3, further reducing hysteresis and threshold voltage drift.

[0071] For example, the active layers of all transistors in the pixel circuit 10 may all comprise one or more oxide materials selected from indium (In), gallium (Ga), tin (Sn), zirconium (Zr), hafnium (Hf), titanium (Ti), and zinc (Zn), such as indium gallium zinc oxide (IGZO). In an optional embodiment, at least some transistors in the pixel circuit 10 may have a dual-gate structure, which is beneficial for improving the stability and mobility of the transistors.

[0072] Optional, continue to refer to Figure 4 The first electrode of the OLED is electrically connected to the fourth node N4, and the second electrode of the OLED is connected to the second power supply voltage terminal. The voltage of the second power supply voltage terminal is less than the voltage of the first power supply voltage terminal.

[0073] Specifically, the second electrode of the OLED light-emitting element can be electrically connected to the second power supply voltage terminal via the second power supply line PV2_L. In an optional embodiment, the first power signal PV1 provided by the first power supply voltage terminal can be a DC high-level signal, for example, the voltage of the first power supply voltage terminal can be the power supply voltage VDD, which is generally a positive value. The second power signal PV2 provided by the second power supply voltage terminal can be a DC low-level signal, for example, the voltage of the second power supply voltage terminal can be the negative power supply voltage VEE, which is generally grounded or a negative value.

[0074] For example, the first electrode of the OLED is the anode of the OLED, and the second electrode is the cathode of the OLED. The OLED is unidirectionally conductive. When the first light-emitting control module 13, the driving transistor M3, and the second light-emitting control module 14 are simultaneously turned on, a path can be formed between the first power supply voltage terminal and the second power supply voltage terminal. Current can be generated in the OLED. The current can pass through the first light-emitting control module 13, the driving transistor M3, and the second light-emitting control module 14 in sequence, and then through the OLED.

[0075] Optional, continue to refer to Figure 4 The second plate of the first capacitor C1 is directly electrically connected to the gate of the driving transistor M3.

[0076] In this embodiment, no device or component is disposed between the second plate of the first capacitor C1 and the gate of the driving transistor M3, but conductive structures such as metal wires, lap holes, and lap electrodes can be used. Figure 4 Electrical connection (not shown in the image).

[0077] Optional, Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. (Reference) Figure 5 The second plate of the first capacitor C1 is electrically connected to the gate of the driving transistor M3 through the compensation module 11, and the second plate of the first capacitor C1 can be directly electrically connected to the second node N2.

[0078] The second plate of the first capacitor C1 and the gate of the driving transistor M3 can be electrically connected via devices and / or components, such as through the compensation module 11; no devices or components are disposed between the second plate of the first capacitor C1 and the second node N2, but conductive structures such as metal wires, lap holes, and lap electrodes can be used. Figure 5 Electrical connection (not shown in the image).

[0079] For example, Figure 6 This is a timing diagram of another pixel circuit provided in an embodiment of the present invention. Figure 6 Specifically, it can be corresponded to Figure 5The driving timing diagram of the pixel circuit is shown. (Reference) Figure 5 and Figure 6 The pixel circuit 10 includes a refresh stage tf. Figure 6 Zhongyu Figure 3 The similarities will not be repeated; only the differences will be explained.

[0080] During the write phase t3 of the refresh phase tf, the first light emission control signal EM1 and the second light emission control signal EM2 are at the disabled level, the second scan signal S2N continues to be at the enabled level, and the first scan signal SP on the first scan line SP_L jumps to the enabled level. The first light-emitting control module 13 and the second light-emitting control module 14 are turned off, and the compensation module 11 and the writing module 12 are turned on, so that the data signal Data on the data line Data_L can be transmitted to the first plate of the first capacitor C1 through the writing module 12. The voltage change of the first plate of the first capacitor C1 is ΔC1, which can be coupled to the second node N2. The first node N1 and the second node N2 are connected, and the signal of the second node N2 can be transmitted to the first node N1, such that ΔN1=ΔN2=ΔC1*C1 / (C1+C2)=(Data-Data')*C1 / (C1+C2), where Data' is the data signal Data written by the pixel circuit 10 in the previous working period. At this time, the voltage VN1 of the first node N1=PV1+ΔN1=PV1+(Data-Data')*C1 / (C1+C2).

[0081] Based on the above embodiments, Figure 7 This is a timing diagram of another pixel circuit provided in an embodiment of the present invention. Figure 7 Specifically, it can be corresponded to Figure 5 The driving timing diagram of the pixel circuit is shown. (Reference) Figure 5 and Figure 7 The pixel circuit 10 includes multiple display cycles DP, and the display cycle DP includes a refresh phase tf and a hold phase tk. Figure 7 Zhongyu Figure 6 The similarities will not be repeated; only the differences will be explained. During the holding phase tk, the second node N2 is cut off from the first node N1; and, during a portion of the holding phase tk, the first power supply voltage terminal is cut off from the second node N2, while the data voltage terminal is connected to the first plate of the first capacitor C1.

[0082] Specifically, during the holding phase tk, the compensation module 11 is turned off; the writing module 12 can be turned on during the partial period when the pixel circuit 10 stops providing driving current to the light-emitting element OLED, and the bias of the driving transistor M3 is adjusted.

[0083] For example, during the holding phase tk, there are periods when the first light emission control signal EM1 and the second light emission control signal EM2 are at a disabled level, and the first scan signal SP is at an enabled level. This causes the first light emission control module 13 and the second light emission control module 4 to be turned off, the write module 12 to be turned on, the pixel circuit 10 to stop providing driving current to the light emission element OLED, and the first plate of the first capacitor C1 to receive the data signal Data at the data voltage terminal. At the same time, under the coupling effect of the first capacitor C1, the voltage of the second node N2 changes, the gate voltage of the driving transistor M3 remains unchanged, the driving transistor M3 is turned on, and the data of the second node N2 can be transmitted to the third node N3 through the driving transistor M3, so that VN2 = VN3, so as to adjust the bias of the first and second plates of the driving transistor M3 and improve the problems of afterimage and low-frequency flicker.

[0084] The display period DP refers to the refresh cycle of the grayscale display of the pixel circuit 10. During the refresh phase tf of the display period DP, the pixel circuit 10 can write a data signal data, and the driving current Id can be adjusted through the data signal data to refresh the grayscale display. During the hold phase tk of the display period DP, the pixel circuit 10 can continue to write the data signal data, but the driving current Id remains unchanged, and the grayscale display is not refreshed. In other optional embodiments, the display period DP may only include the refresh phase tf and exclude the hold phase tk.

[0085] For example, the duration of both the refresh phase tf and the hold phase tk can be 1 / 120s, and 120 refresh phases tf and / or hold phases tk can be included within 1s. The display cycle DP of the pixel circuit 10 can include one refresh phase tf and 0, 1, 3, or 119 hold phases tk, such that the refresh frequency of the pixel circuit 10 can be 120Hz, 60Hz, 30Hz, or 1Hz, as shown below. Figure 8 As shown. When the pixel circuit 10 is at a fixed gray level or a low refresh rate for a long time, the gate, first electrode, and second electrode of the driving transistor M3 are at a fixed potential for a long time. The driving transistor M3 may hysteresis, resulting in threshold voltage drift. The pixel circuit 10 provided in this embodiment of the invention can compensate for the drifted threshold voltage in the compensation stage t2 of the refresh stage tf of the next display cycle DP, so as to improve the problems of image retention and low-frequency flicker.

[0086] It is understood that when the duration of the refresh phase tf and the hold phase tk are both 1 / 120s, the refresh frequency of the pixel circuit 10 can also be 40Hz, 24Hz, 20Hz, 15Hz, 12Hz, 10Hz, 8Hz, 6Hz, 4Hz, 3Hz, 2Hz, etc., which will not be shown one by one in the embodiments of the present invention.

[0087] It is also understood that in other alternative implementations, the duration of the refresh phase tf and the hold phase tk can be other values. In this case, the refresh frequency of the pixel circuit 10 can also be other frequencies, which will not be described in detail in this embodiment of the invention.

[0088] For example, taking the display cycle DP of all pixel circuits 10 in the display panel 01 as including a refresh phase tf and a hold phase tk, and all pixel circuits 10 having the same refresh frequency as an example, Figure 9 This is a timing diagram of a display panel provided in an embodiment of the present invention. (Reference) Figure 9 The display panel 01 includes a first display mode, in which the display panel 01 includes a refresh frame DAF and a hold frame DAk. The display panel 01 may also include M rows of pixel circuits 10. In the refresh frame DAF, each row of pixel circuits 10 can be reset, threshold compensated, and data signal Data written. The gate-source voltage of the driving transistor M3 can change according to the data Data, so that the display grayscale of each row of pixel circuits 10 is refreshed sequentially. In the hold frame DAk, each row of pixels 10 stops resetting and stops threshold compensation, but still writes data signal data. However, the data signal data does not cause the gate-source voltage of the driving transistor M3 to change, so that the display grayscale of each row of pixel circuits 10 is not refreshed, and the display grayscale of the previous frame can continue to be displayed, so as to realize the whole-screen frequency reduction of the display panel 01.

[0089] In other embodiments, the display period DP of some pixel circuits 10 in the display panel 01 may only include the refresh phase tf, or the display period DP of some pixel circuits 10 may include both the refresh phase tf and the hold phase tk. The refresh frequencies of the pixel circuits 10 in the same display panel 01 may be different. The display panel 01 may also include a second display mode. In the second display mode, the display panel 01 may include a refresh frame DAf and a frequency division frame ( Figure 9 (Not shown in the image) In the frequency division frame, some row pixel circuits 10 can refresh the display grayscale, while some row pixel circuits 10 can not refresh the display grayscale, so as to realize the frequency division of the display panel 01.

[0090] Optional, Figure 10 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention, for reference. Figure 10 The pixel circuit 10 also includes a first reset module 15, the first end of which is electrically connected to the first reference voltage terminal, and the second end of which is electrically connected to the fourth node N4.

[0091] The first reference voltage terminal can provide a first reference signal VREF1 for resetting the fourth node N4 to the pixel circuit 10. In an optional embodiment, the first reference signal VREF1 at the first reference voltage terminal is less than zero.

[0092] For example, the first reset module 15 includes a first reset transistor M7. The first terminal of the first reset transistor M7 can be connected to the first reference voltage terminal via the first reference line VREF1_L to receive the first reference signal VREF1; the second terminal of the first reset transistor M7 is electrically connected to the fourth node N4; the gate of the first reset transistor M7 can be electrically connected to the shift register unit of the fifth shift register via the third scan line SPX_L to receive the third scan signal SPX. Figure 2 (Not shown in the image). The first reset transistor M7 can be turned on and off under the control of the third scan signal SPX. When the first reset transistor M7 is turned on, the first reference signal VREF1 at the first reference voltage terminal can be transmitted to the fourth node N4 through the first reset transistor M7 to reset the fourth node N4.

[0093] In an alternative embodiment, Figure 11 This is a timing diagram of another pixel circuit provided in an embodiment of the present invention. Figure 11 Specifically, it can be corresponded to Figure 10 The driving timing diagram of the pixel circuit is shown. (Reference) Figure 10 and Figure 11 The pixel circuit 10 includes a refresh phase tf, and during the reset phase t1 of the refresh phase tf, the fourth node N4 is connected to the first reference voltage terminal.

[0094] For example, in the reset phase t1 of the refresh phase tf, the first light emission control signal EM1 is enabled, the second light emission control signal EM2 is disabled, the second scan signal S2N is enabled, and the third scan signal SPX is enabled, so that the first light emission control module 13, the compensation module 11 and the first reset module 15 are turned on, and the second light emission control module 14 is turned off. The pixel circuit 10 stops providing driving current to the light-emitting element OLED; the first power signal PV1 at the first power supply voltage terminal is transmitted to the second node N2 through the first light-emitting control module 13, and the first power signal PV1 at the second node N2 is transmitted to the first node N1 through the compensation module 11, driving the transistor M3 to turn on. The first power signal PV1 at the second node N2 can also be transmitted to the third node N3. The first power signal PV1 can be used to reset the first node N1, the second node N2 and the third node N3, clearing the residual electrical signal from the previous working period; the first reference signal VREF1 at the first reference voltage terminal is transmitted to the fourth node N4 through the first reset module 15, which can reset the fourth node N4 and clear the residual electrical signal from the previous working period.

[0095] In yet another alternative embodiment, reference continues to... Figure 10 and Figure 11During the compensation phase t2 of the refresh phase tf, the first power supply voltage terminal is cut off from the second node N2, the first node N1 is connected to the second node N2, the third node N3 is connected to the fourth node N4, and the fourth node N4 is connected to the first reference voltage terminal.

[0096] Specifically, during the compensation phase t2 of the refresh phase tf, the first light-emitting control module 13 is turned off, and the compensation module 11, the second light-emitting control module 14 and the first reset module 15 are turned on. The first reference signal VREF1 at the first reference voltage terminal is used to perform threshold compensation on the driving transistor M3.

[0097] For example, during the compensation phase t2 of the refresh phase tf, the first light emission control signal EM1 is disabled, while the second light emission control signal EM2, the second scan signal S2N, and the third scan signal SPX are all enabled. This causes the first light emission control module 13 to be turned off, while the second light emission control module 14, the compensation module 11, and the first reset module 15 are turned on. The pixel circuit 10 continues to stop providing driving current to the light-emitting element OLED, and the first power signal PV1 at the first power supply voltage terminal stops transmitting to the second node N2.

[0098] During the compensation phase t2, the first reference signal VREF1 at the first reference voltage terminal can be transmitted to the third node N3 through the first reset module 15 and the second light-emitting control module 14. The first reference signal VREF1 of the third node N3 can also be transmitted to the second node N2 through the driving transistor M3, and the signal of the second node N2 can be transmitted to the first node N1 through the compensation module 11. The gate-source voltage VGS of the driving transistor M3 is continuously reduced until VGS = VN1 - VN3 = VTH. The driving transistor M3 is in a transitional state between conduction and cutoff, and the current in the driving transistor M3 is reduced to zero. The first reference signal VREF1 of the third node N3 is no longer transmitted to the second node N2 and the first node N1. The voltages of the first node N1 and the second node N2 are stable. At this time, VN1 = VN2 = VN3 + VTH = VREF1 + VTH, and the threshold voltage is compensated to the first node N1.

[0099] During the writing phase t3, the first light emission control signal EM1 and the second light emission control signal EM2 are disabled, while the first scan signal SP and the second scan signal S2N are enabled. The first light emission control module 13 can be turned off under the control of the first light emission control signal EM1, the second light emission control module 14 can be turned off under the control of the second light emission control signal EM2, the first reset module 15 can be turned off under the control of the third scan signal SPX, the compensation module 11 can be turned on under the control of the second scan signal S2N, and the writing module 12 can be turned on under the control of the first scan signal SP. The data signal Data on the data line Data_L can be transmitted to the first plate of the first capacitor C1 through the writing module 12. The voltage VN1 of the first node N1 is VN1 = VREF1 + VTH + ΔN1 = VREF1 + VTH + ΔC1*C1 / (C1 + C2) = VREF1 + VTH + (Data - Data')*C1 / (C1 + C2). The gate-source voltage VGS of the driving transistor M3 is VN1 - VN3 = [VREF1 + VTH + (Data - Data')*C1 / (C1 + C2)] - VREF1 = (Data - Data')*C1 / (C1 + C2) + VTH.

[0100] In yet another alternative embodiment, reference continues to... Figure 10 and Figure 11 The pixel circuit 10 includes a refresh phase tf. During the write phase t3 of the refresh phase tf, the second plate of the first capacitor C1 is connected to the gate of the driving transistor, and the first reference voltage terminal is connected to the fourth node N4.

[0101] Specifically, during the write phase t3 of the refresh phase tf, the compensation module 11 and the write module 12 are turned on, and the first reset module 15 is also turned on, so that the fourth node N4 is at a fixed potential. The gate voltage of the driving transistor M3 can be precisely controlled by the first capacitor C1 and the second capacitor C2, which is beneficial to accurately control the gate-source voltage and driving current of the driving transistor M3, thereby achieving precise control of the display grayscale.

[0102] For example, during the write phase t3 of the refresh phase tf, the first light emission control signal EM1 and the second light emission control signal EM2 are at the disabled level, the first scan signal SP, the second scan signal S2N and the third scan signal SPX are at the enabled level, the first light emission control module 13 and the second light emission control module 14 are turned off, and the compensation module 11, the write module 12 and the first reset module 15 are turned on, so that the second plate of the first capacitor C1 is connected to the second node N2, the second node N2 is connected to the first node N1, and the first reference voltage terminal is connected to the fourth node N4.

[0103] When the data signal Data on the data line Data_L is transmitted to the first plate of the first capacitor C1 through the writing module 12, the first reference signal VREF1 at the first reference voltage terminal can be transmitted to the second plate of the second capacitor C2 through the first reset module 15. When the voltage of the first plate of the first capacitor C1 changes, the voltage of the second plate of the second capacitor C2 can remain unchanged. Under the action of the first capacitor C1 and the second capacitor C2, the voltage change ΔC1 of the first plate of the first capacitor C1 can be partially coupled to the first node N1, such that the voltage change ΔN1 of the first node N1 = ΔC1*C1 / (C1+C2). By adjusting the size of the first capacitor C1 and the second capacitor C2, the magnitude of the driving current can be adjusted, thereby realizing the control of the range of the data signal Data. This is beneficial for reducing the gate voltage drop of the driving transistor M3, improving the hysteresis and threshold voltage drift of the driving transistor, and also beneficial for the low power consumption of the display panel.

[0104] In yet another alternative embodiment, Figure 12 This is a timing diagram of another pixel circuit provided in an embodiment of the present invention. Figure 12 Specifically, it can be corresponded to Figure 10 The driving timing diagram of the pixel circuit is shown. (Reference) Figure 10 and Figure 12 The pixel circuit 10 includes multiple display cycles DP, which include a refresh phase tf and a hold phase tk. During a portion of the hold phase tk, the first reference voltage terminal is connected to the fourth node N4.

[0105] Specifically, during the holding phase tk, the first reset module 15 can turn on during a partial period when the pixel circuit 10 stops providing driving current to the light-emitting element OLED, thereby adjusting the bias of the light-emitting element OLED.

[0106] For example, during the holding phase tk, there are periods when the first light emission control signal EM1 and the second light emission control signal EM2 are disabled, and the third scan signal SPX is enabled. This causes the first light emission control module 13 and the second light emission control module 4 to be turned off, the first reset module 15 to be turned on, and the pixel circuit 10 to stop providing driving current to the light-emitting element OLED. The first reference signal VREF1 at the first reference voltage terminal is transmitted to the fourth node N4 through the first reset module 15, which can adjust the bias of the light-emitting element OLED. At the same time, through the second capacitor C2, the fourth node N4 can also be biased. The voltage change of 4 is coupled to the first node N1 to adjust the bias of the gate of the driving transistor M3. When the pixel circuit 10 provides driving current to the light-emitting element OLED, the fourth node N4 returns to the voltage when the pixel circuit 10 is working. Under the coupling effect of the second capacitor C2, the first node N1 can also return to the voltage when the pixel circuit 10 is working. The driving current remains unchanged, and the light-emitting element OLED can continue to emit light in the holding phase tk. In the same display cycle DP, the luminous brightness of the light-emitting element OLED in the holding phase tk can be the same as the luminous brightness of the light-emitting element OLED in the refresh phase tf.

[0107] It is understood that when the second plate of the first capacitor C1 is electrically connected to the gate of the driving transistor M3 through the compensation module 11, the data voltage terminal and the first plate of the first capacitor C1 can also be connected during a portion of the holding phase tk. During the holding phase tk, the conduction period between the first reference voltage terminal and the fourth node N4 and the conduction period between the data voltage terminal and the first plate of the first capacitor C1 may or may not overlap. That is, during the holding phase tk, the conduction period of the first reset module 15 and the conduction period of the write module 12 may or may not overlap; this embodiment of the invention does not impose any limitations on this.

[0108] Optional, Figure 13 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention, for reference. Figure 13 The pixel circuit 10 also includes a second reset module 16. The first end of the second reset module 16 is electrically connected to the second reference voltage terminal, and the second end of the second reset module 16 is electrically connected to the first plate of the first capacitor C1 at the fifth node N5.

[0109] The second reference voltage terminal can provide the pixel circuit 10 with a second reference signal VREF2 for resetting the fifth node N5. The second reference signal VREF2 at the second reference voltage terminal can be zero, greater than zero, or less than zero. This embodiment of the invention does not limit the second reference signal VREF2.

[0110] For example, the second reset module 16 includes a second reset transistor M2. The first terminal of the second reset transistor M2 can be connected to the second reference voltage terminal via the second reference line VREF2_L to receive the second reference signal VREF2; the second terminal of the second reset transistor M2 is electrically connected to the fifth node N5; the gate of the second reset transistor M2 can be electrically connected to the shift register unit of the sixth shift register via the fourth scan line SP*_L to receive the fourth scan signal SP*( Figure 2 (Not shown in the image). The second reset transistor M2 can be turned on and off under the control of the fourth scan signal SP*. When the second reset transistor M2 is turned on, the second reference signal VREF2 at the second reference voltage terminal can be transmitted to the fifth node N5 through the second reset transistor M2 to reset the fifth node N5.

[0111] In an alternative embodiment, Figure 14 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention, for reference. Figure 14 The second reference voltage terminal can be electrically connected to the first power supply voltage terminal.

[0112] For example, the first terminal of the first light-emitting control module 13 and the first terminal of the second reset module 16 of the same pixel circuit 10 can be connected to the same signal line and receive the same signal; or, the first terminal of the first light-emitting control module 13 and the first terminal of the second reset module 16 of the same pixel circuit 10 can also be connected to different signal lines, but electrically connected to the voltage terminal through different power supply lines. Figure 2 (not shown in the image); or, the first terminal of the first light-emitting control module 13 and the first terminal of the second reset module 16 of the same pixel circuit 10 can be connected to different signal lines, and electrically connected to different voltage terminals through different signal lines, but the different voltage terminals can be electrically connected to or receive the same signal. Figure 2 (Not shown in the image). This helps reduce signal lines and simplify timing control.

[0113] In yet another alternative embodiment, Figure 15 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention, for reference. Figure 15 The pixel circuit 10 also includes a first reset module 15. The first terminal of the first reset module 15 is electrically connected to the first reference voltage terminal, and the second terminal of the first reset module 15 is electrically connected to the fourth node N4. The second reference voltage terminal can reuse the first reference voltage terminal. The first terminal of the second reset module 16 is electrically connected to the fourth node N4, which also helps to reduce signal lines and simplify timing control.

[0114] For example, the first reset module 15 includes a first reset transistor M7, and the second reset module 16 includes a second reset transistor M2. The first terminal of the first reset transistor M7 is electrically connected to a first reference voltage terminal via a first reference line VREF1_L to receive a first reference signal VREF1. The second terminal of the first reset transistor M7 is electrically connected to the first terminal of the second reset transistor M2 at a fourth node N4, and the second terminal of the second reset transistor M2 is electrically connected to a fifth node N5. The gate of the first reset transistor M7 is electrically connected to a third scan line SPX_L to receive a third scan signal SPX. The gate of the second reset transistor M2 is electrically connected to a fourth scan line SP*_L to receive a fourth scan signal SP*. In an optional embodiment, during a portion of the time when the pixel circuit 10 stops providing driving current to the light-emitting element OLED, the enable level of the third scan line SPX_L overlaps with the enable level of the fourth scan signal SP*.

[0115] Based on the above embodiments, Figure 16 This is a timing diagram of another pixel circuit provided in an embodiment of the present invention. Figure 16 Specifically, it can be corresponded to Figure 15 The driving timing diagram of the pixel circuit is shown. (Reference) Figure 15 and Figure 16 The pixel circuit 10 includes a refresh phase tf, and during the compensation phase t2 of the refresh phase tf, the fifth node N5 is connected to the second reference voltage terminal.

[0116] For example, in the compensation phase t2 of the refresh phase tf, the first light emission control signal EM1 is at an enabled level, while the second light emission control signal EM2, the second scan signal S2N, the third scan signal SPX, and the fourth scan signal SP* are all at enabled levels. This can turn off the first light emission control module 13 and turn on the second light emission control module 14, the compensation module 11, the first reset module 15, and the second reset module 16. When the first light-emitting control module 13 is turned off and the second light-emitting control module 14, compensation module 11, and first reset module 15 are turned on, the threshold voltage can be compensated to the first node N1. At this time, VN1 = VN2 = VN3 + VTH = VREF1 + VTH. At the end stage when the first light-emitting control module 13 is turned off and the second light-emitting control module 14, compensation module 11, and first reset module 15 are turned on, the second reset module 16 is turned on. At this time, the voltages of the first node N1 and the second node N2 tend to stabilize. The first reference signal VREF1 of the fourth node N4 is transmitted to the fifth node N5 through the second reset module 16. The voltage of the fifth node N5 also tends to stabilize, which can avoid the voltage change of the second node N2 from affecting the accurate reset of the fifth node N5.

[0117] During the writing phase t3, the first light emission control signal EM1, the second light emission control signal EM2, and the fourth scan signal SP* are at the disabled level, while the first scan signal SP, the second scan signal S2N, and the third scan signal SPX are at the enabled level. The first light emission control module 13, the second light emission control module 14, and the second reset module 16 are turned off, while the compensation module 11, the writing module 12, and the first reset module 15 are turned on. When the data signal Data on the data line Data_L is transmitted to the first plate of the first capacitor C1 through the writing module 12, the voltage change of the first plate of the first capacitor C1 is ΔC1 = Data - VREF1, making the voltage VN1 of the first node N1 = VREF1 + VTH + ΔN1 = VREF1 + VTH + ΔC1*C1 / (C1 + C2) = VREF1 + VTH + (Data - VREF1)*C1 / (C1 + C2). The gate-source voltage VGS of the driving transistor M3 is VN1 - VN3 = [VREF1 + VTH + (Data - VREF1)*C1 / (C1 + C2)] - VREF1 = (Data - VREF1)*C1 / (C1 + C2) + VTH. During the light-emitting stage t4, the driving current Id = k*(VGS - VTH). 2 =k*[(Data-VREF1)*C1 / (C1+C2)] 2 .

[0118] Thus, by resetting the fifth node N5 during the compensation phase t2 of the refresh phase tf, the voltage change of the first plate of the first capacitor C1 during the writing phase can be controlled, thereby precisely controlling the gate-source voltage and driving current of the driving transistor M3 and achieving accurate display.

[0119] In an optional implementation, the first shift register VSR1 includes M levels of shift register units. The fourth scan line SP*_L electrically connected to the same pixel circuit 10 can be electrically connected to the i-th level shift register unit of the first shift register VSR1, and the first scan line SP_L can be electrically connected to the j-th level shift register unit of the first shift register VSR1. The i-th signal output by the first shift register VSR1 is received as the fourth scan signal SP*, and the j-th signal output by the first shift register VSR1 is received as the first scan signal SP, where 1≤i≤j≤M, and i and j are both integers. In other words, the fourth scan line SP*_L electrically connected to the j-th row pixel circuit 10 and the first scan line SP_L electrically connected to the i-th row pixel circuit 10 can be electrically connected and electrically connected to the output terminal of the same shift register unit of the first shift register VSR1. The fourth scan line SP*_L and the first scan line SP_L electrically connected to the same row pixel circuit 10 can be electrically connected to different shift register units of the third shift register VSR3. Figure 2(Not shown in the image). Thus, the fourth scan signal SP* and the first scan signal SP received by the pixel circuit 10 can both come from the first shift register VSR1, eliminating the need for a sixth shift register, which is beneficial for making the display panel 01 thinner and lighter.

[0120] It is understandable that when the second plate of the first capacitor C1 is electrically connected to the gate of the driving transistor M3 through the compensation module 11, the data voltage terminal and the first plate of the first capacitor C1 can continue to conduct during a portion of the holding phase tk. The fourth scan signal SP* and the first scan signal SP received by the pixel circuit 10 come from the same shift register, and the fifth node and the second reference voltage terminal can also conduct during a portion of the holding phase tk.

[0121] It is also understood that during a portion of the holding phase tk, when the first reference voltage terminal and the fourth node N4 are conducting, the conducting time between the first reference voltage terminal and the fourth node N4 and the fifth node and the second reference voltage terminal may or may not overlap. That is, during the holding phase tk, the conducting time of the first reset module 15 and the conducting time of the second reset module 16 may or may not overlap. This embodiment of the invention does not impose any limitations on this.

[0122] Optional, Figure 17 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention, for reference. Figure 17 The pixel circuit 10 also includes a third reset module 17, the first end of which is electrically connected to the first power supply voltage terminal, and the second end of which is electrically connected to the first node N1.

[0123] For example, the third reset module 17 includes a third reset transistor M8. The first terminal of the third reset transistor M8 can be electrically connected to the first power supply voltage terminal via the first power supply line PV1_L to receive the first power supply signal PV1; the second terminal of the third reset transistor M8 is electrically connected to the first node N1; the gate of the third reset transistor M8 can be electrically connected to the shift register unit of the seventh shift register via the fifth scan line S1N_L to receive the fifth scan signal S1N ( Figure 2 (Not shown in the image). The third reset transistor M8 can be turned on and off under the control of the fifth scan signal S1N. When the third reset transistor M8 is turned on, the first power supply signal PV1 at the first power supply voltage terminal can be transmitted to the first node N1 through the third reset transistor M8 to reset the first node N1.

[0124] In an alternative embodiment, Figure 18 This is a timing diagram of another pixel circuit provided in an embodiment of the present invention. Figure 18 Specifically, it can be corresponded to Figure 17 The driving timing diagram of the pixel circuit is shown. (Reference) Figure 17 and Figure 18 The pixel circuit 10 includes a refresh phase tf, and during the refresh phase tf, a reset phase t1 and a compensation phase t2, the first power supply voltage terminal is connected to the first node N1.

[0125] For example, in the reset phase t1, the fifth scan signal S1N is enabled, turning on the third reset module 17. The first power signal PV1 at the first power supply voltage terminal can be transmitted to the first node N1 through the third reset module 17 to reset the first node N1. In the compensation phase t2, the fifth scan signal S1N and the second scan signal S2N are enabled, turning on the third reset module 17 and the compensation module 11. The first power signal PV1 can be transmitted to the second node N2 through the third reset module 17 and the compensation module 11. The first power signal PV1 of the second node N2 is transmitted to the third node N3, and the threshold voltage can be compensated to the third node N3. At this time, VN3 = VN1 - VTH = PV1 - VTH.

[0126] In an optional embodiment, the second shift register VSR2 includes M-stage shift register units. The fifth scan line S1N_L, electrically connected to the same pixel circuit 10, can be electrically connected to the i-th stage shift register unit of the second shift register VSR2, and the second scan line S2N_L can be electrically connected to the j-th stage shift register unit of the second shift register VSR2. The i-th signal output from the second shift register VSR2 is received as the fifth scan signal S1N, and the j-th signal output from the second shift register VSR2 is received as... The second scan signal S2N, where 1≤i≤j≤M, and i and j are both integers; in other words, the fifth scan line S1N_L electrically connected to the j-th row pixel circuit 10 and the second scan line S2N_L electrically connected to the i-th row pixel circuit 10 can be electrically connected and electrically connected to the output of the same shift register unit of the second shift register VSR2. The fifth scan line S1N_L and the second scan line S2N_L electrically connected to the same row pixel circuit 10 can be electrically connected to different shift register units of the second shift register VSR2. Figure 2 (Not shown in the image). Thus, the fifth scan signal S1N and the second scan signal S2N received by the pixel circuit 10 can both come from the second shift register VSR2, eliminating the need for a seventh shift register, which is beneficial for making the display panel 01 thinner and lighter.

[0127] In yet another alternative embodiment, reference continues to... Figure 17 and Figure 18 The conduction period between the fifth node N5 and the second reference voltage terminal overlaps with the conduction period between the first power supply voltage terminal and the first node N1, and / or the conduction period between the fifth node N5 and the second reference voltage terminal does not overlap with the conduction period between the second node N2 and the first node N1.

[0128] Specifically, the conduction period of the second reset module 16 overlaps with that of the third reset module 17, and / or, the conduction period of the second reset module 16 does not overlap with that of the compensation module 11. Thus, when the second reset module 16 resets the fifth node N5, the first node N1 can receive the first power signal PV1 from the first power supply voltage terminal, and / or, when the second reset module 16 resets the fifth node N5, the first node N1 stops receiving signals from the second node N2, ensuring that voltage fluctuations at the fifth node N5 do not affect the voltage at the first node N1. This facilitates precise control of the gate-source voltage and drive current of the driving transistor M3, achieving accurate light emission.

[0129] In yet another alternative embodiment, Figure 19 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention, for reference. Figure 19 The control terminal of the first light-emitting control module 13 is electrically connected to the control terminal of the second light-emitting control module.

[0130] Specifically, there is no need to reset the driving transistor M3 through the first light-emitting control module 13. The first light-emitting control module 13 and the second light-emitting control module 14 of the same pixel circuit 10 can be turned on or off simultaneously under the control of the same light-emitting control signal.

[0131] For example, the control terminals of the first light-emitting control module 13 and the second light-emitting control module 14 of the same pixel circuit 10 can be directly electrically connected to the same control line, receiving the same signal as the first light-emitting control signal EM1 and the second light-emitting control signal EM2; or, the control terminals of the first light-emitting control module 13 and the second light-emitting control module 14 of the same pixel circuit 10 can also be electrically connected through signal lines, respectively connected to different light-emitting control lines, but connected to the same shift register unit of the shift register through different light-emitting control lines. Figure 2 (not shown in the image), and receive the same light emission control signal as the first light emission control signal EM1 and the second light emission control signal EM2.

[0132] Thus, the first light-emitting control module 13 and the second light-emitting control module 14 of the same pixel circuit 10 can be turned on or off simultaneously under the control of the same light-emitting control signal. When adjusting the light-emitting duration of the light-emitting element OLED of the pixel circuit 10, only one light-emitting control signal needs to be adjusted, which helps to simplify the dimming process and dimming timing. In addition, it also helps to reduce the number of shift registers in the display panel 01, thereby achieving a thinner and lighter display panel 01.

[0133] Based on the same inventive concept, this embodiment of the invention also provides a driving method for a pixel circuit, used to drive the pixel circuit 10 provided in any embodiment of the invention. Figure 20 This is a flowchart of a pixel circuit driving method provided in an embodiment of the present invention, see reference. Figure 20 The driving methods include:

[0134] S110, Reset phase: The first power supply voltage terminal is connected to the second node, and the first node is connected to the second node.

[0135] S120, during the compensation phase, the second node is connected to the first node, the first power supply voltage terminal is connected to the second node, or the third node is connected to the fourth node.

[0136] S130, during the writing phase, the data voltage terminal is connected to the first plate of the first capacitor.

[0137] S140, Light-emitting stage: The first power supply voltage terminal is connected to the second node, and the third node is connected to the fourth node.

[0138] The pixel circuit driving method provided in this embodiment of the invention allows for the following steps: During the reset phase, a first light-emitting control module can be turned on using a first light-emitting control signal. A first power signal at the first power supply voltage terminal can be transmitted to the second node through the first light-emitting control module to reset the potential of the second node. Alternatively, a second scan signal can be used to turn on a compensation module. A first power signal from the second node can be transmitted to the first node through the compensation module to reset the potential of the first node, thus controlling the driving transistor to be in a conducting state. During the compensation phase, the first light-emitting control module and the compensation module can continue to conduct using the first light-emitting control signal and the second scan signal to compensate the threshold voltage of the driving transistor. During the writing phase, the writing module can be turned on using the first scan signal. A data signal at the data voltage terminal can be transmitted to the first capacitor through the writing module and coupled to the gate of the driving transistor. The second capacitor can store the gate-source voltage of the driving transistor. During the light-emitting phase, the first light-emitting control module and the second light-emitting control module can be turned on using the first light-emitting control signal and the second light-emitting control signal. The driving current of the pixel circuit can be provided to the light-emitting element, causing the light-emitting element to emit light. When this pixel circuit is applied to a display panel, it can improve the problems of image retention and low-frequency flicker in the display panel.

[0139] The pixel circuit driving method provided in the embodiments of the present invention drives the pixel circuit provided in any embodiment of the present invention, and has the corresponding technical features and beneficial effects of the pixel circuit. For the contents not described in detail in the embodiments of the pixel circuit driving method, please refer to the description of the pixel circuit above, and will not be repeated here. Similarly, the pixel circuit of the embodiments of the present invention also has functional modules and beneficial effects that can execute the pixel circuit driving method provided in the embodiments of the present invention. For the contents not described in detail in the embodiments of the pixel circuit, please refer to the description of the pixel circuit driving method above, and will not be repeated here.

[0140] Based on the same inventive concept, embodiments of the present invention also provide a display panel. Figure 21 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, for reference. Figure 21 The display panel 01 includes a plurality of pixel circuits 10 arranged in an array. The pixel circuits 10 can be the pixel circuits 10 provided in any embodiment of the present invention.

[0141] For example, the display panel 01 also includes multiple first scan lines SP_L, multiple second scan lines S2N_L, multiple data lines Data_L, multiple first light emission control lines EM1_L, and multiple second light emission control lines EM2_L connected to multiple pixel circuits 10. It may also include multiple first power lines, multiple second power lines, etc. Figure 21 (Not shown in the image). The first scan line SP_L can be connected to the control terminal of the write module in the pixel circuit 10, the second scan line S2N_L can be connected to the control terminal of the compensation module in the pixel circuit 10, the first light emission control line EM1_L can be connected to the control terminal of the first light emission control module in the pixel circuit 10, and the second light emission control line EM2_L can be connected to the control terminal of the second light emission control module in the pixel circuit 10.

[0142] The display panel provided in the embodiments of the present invention includes multiple pixel circuits arranged in an array as provided in any embodiment of the present invention, and has the corresponding technical features and beneficial effects of pixel circuits. For the contents not described in detail in the embodiments of the display panel, please refer to the description of the pixel circuits above, and will not be repeated here.

[0143] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 22 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 22 As shown, the display device 02 includes a display panel 01 provided in any embodiment of the present invention. The display device 02 provided in the embodiments of the present invention can be... Figure 22The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, in-vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc. The embodiments of the present invention do not make any special limitations on this.

[0144] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A pixel circuit, characterized in that, include: The components include a driving transistor, a light-emitting element, a compensation module, a writing module, a first light-emitting control module, a second light-emitting control module, a first capacitor, and a second capacitor. The first end of the compensation module is electrically connected to the gate of the driving transistor at a first node, and the second end of the compensation module is electrically connected to the first electrode of the driving transistor at a second node; the first end of the writing module is electrically connected to the data voltage terminal, the second end of the writing module is electrically connected to the first plate of the first capacitor, and the second plate of the first capacitor is electrically connected to the gate of the driving transistor. The first terminal of the first light-emitting control module is electrically connected to the first power supply voltage terminal, and the second terminal of the first light-emitting control module is electrically connected to the second node. The first terminal of the second light-emitting control module is electrically connected to the second electrode of the driving transistor at the third node, and the second terminal of the second light-emitting control module is electrically connected to the light-emitting element at the fourth node; The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the fourth node; The driving transistor is an N-type transistor; The pixel circuit further includes a second reset module; the first end of the second reset module is electrically connected to the second reference voltage terminal, and the second end of the second reset module is electrically connected to the first plate of the first capacitor at the fifth node; the signal of the second reference voltage terminal is a fixed potential. The pixel circuit includes a refresh phase; The refresh phase includes a reset phase, a compensation phase, a write phase, and a light emission phase; the compensation phase includes a first time period and a second time period, with the second time period following the first time period; Specifically, during the first time period, the fifth node is cut off from the second reference voltage terminal; during the second time period, the fifth node is connected to the second reference voltage terminal.

2. The pixel circuit according to claim 1, characterized in that, The compensation module includes a compensation transistor, the writing module includes a writing transistor, the first light-emitting control module includes a first light-emitting control transistor, and the second light-emitting control module includes a second light-emitting control transistor. The compensation transistor, the write transistor, the first light-emitting control transistor, and the second light-emitting control transistor are all N-type transistors.

3. The pixel circuit according to claim 1, characterized in that, The first electrode of the light-emitting element is electrically connected to the fourth node; the second electrode of the light-emitting element is electrically connected to the second power supply voltage terminal. The voltage at the first power supply voltage terminal is greater than the voltage at the second power supply voltage terminal.

4. The pixel circuit according to claim 1, characterized in that, The second plate of the first capacitor is directly electrically connected to the gate of the driving transistor.

5. The pixel circuit according to claim 1, characterized in that, The second plate of the first capacitor is electrically connected to the gate of the driving transistor through the compensation module; The second plate of the first capacitor is directly electrically connected to the second node.

6. The pixel circuit according to claim 5, characterized in that, The pixel circuit includes multiple display cycles; the display cycle includes a refresh phase and a hold phase; During the holding phase, the second node is disconnected from the first node; Furthermore, during a portion of the holding phase, the first power supply voltage terminal is cut off from the second node, while the data voltage terminal is connected to the first plate of the first capacitor.

7. The pixel circuit according to claim 1, characterized in that, Also includes: First reset module; The first terminal of the first reset module is electrically connected to the first reference voltage terminal, and the second terminal of the first reset module is electrically connected to the fourth node.

8. The pixel circuit according to claim 7, characterized in that, The pixel circuit includes a refresh phase; During the compensation phase of the refresh phase, the first power supply voltage terminal is cut off from the second node, the first node is connected to the second node, the third node is connected to the fourth node, and the fourth node is connected to the first reference voltage terminal.

9. The pixel circuit according to claim 7, characterized in that, The pixel circuit includes a refresh phase; During the write phase of the refresh phase, the second plate of the first capacitor is connected to the gate of the driving transistor, and the first reference voltage terminal is connected to the fourth node.

10. The pixel circuit according to claim 7, characterized in that, The pixel circuit includes multiple display cycles; the display cycle includes a refresh phase and a hold phase; During a portion of the holding phase, the first reference voltage terminal is connected to the fourth node.

11. The pixel circuit according to claim 1, characterized in that, The second reference voltage terminal is electrically connected to the first power supply voltage terminal; Alternatively, the pixel circuit may further include a first reset module, wherein a first terminal of the first reset module is electrically connected to a first reference voltage terminal, and a second terminal of the first reset module is electrically connected to the fourth node; the second reference voltage terminal reuses the first reference voltage terminal.

12. The pixel circuit according to claim 1, characterized in that, It also includes a third reset module; The first end of the third reset module is electrically connected to the first power supply voltage terminal, and the second end of the third reset module is electrically connected to the first node.

13. The pixel circuit according to claim 12, characterized in that, The control terminal of the first light-emitting control module is electrically connected to the control terminal of the second light-emitting control module.

14. A driving method for a pixel circuit, characterized in that, For driving the pixel circuit according to any one of claims 1-13; the driving method includes: During the reset phase, the first power supply voltage terminal is connected to the second node, and the first node is connected to the second node. During the first and second periods of the compensation phase, the second node is connected to the first node, and the first power supply voltage terminal is connected to the second node or the third node is connected to the fourth node; wherein, during the second period, the fifth node is connected to the second reference voltage terminal. During the writing phase, the data voltage terminal is connected to the first plate of the first capacitor; During the light-emitting phase, the first power supply voltage terminal is connected to the second node, and the third node is connected to the fourth node.

15. A display panel, characterized in that, include: A plurality of pixel circuits arranged in an array as described in any one of claims 1-13.

Images