Memory block layout structure and memory

Abstract

The present disclosure relates to the field of semiconductor structure design, in particular to a memory block layout structure and a memory. The memory block layout structure comprises: a plurality of memory array layout structures, the plurality of memory array layout structures are arranged in a first direction and are continuously arranged in a second direction to form the memory block layout structure; each memory array layout structure is used to form a memory array in the memory block, the first direction and the second direction are perpendicular to each other; the memory array layout structure is configured as a parallelogram region arranged based on a third direction and a fourth direction; an angle α between the second direction and the fourth direction is less than 90°, and an angle β between the third direction and the fourth direction is greater than 0° and less than 90°; a plurality of word lines and a plurality of bit lines are arranged in each memory array layout structure, one of the plurality of word lines and the plurality of bit lines is arranged at intervals in the third direction and extends in the fourth direction, and the other is arranged at intervals in the fourth direction and extends in the third direction.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor structure design, and in particular to a memory block layout structure and a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. Its main working principle is to use the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0.

[0003] refer to Figure 1 In a 4F2 DRAM layout, word lines (WL) and bit lines (BL) are arranged vertically, and the intersection of the word lines WL and the bit lines BL is used to set the cell capacitor (Cell Cap). The cell capacitor couples the word lines WL and the bit lines BL at the intersection. Therefore, it can be seen that in order to adapt to the arrangement of the word lines WL and the bit lines BL, the cell capacitor is arranged in a square stacking manner. Summary of the Invention

[0004] The embodiments of the present disclosure provide a memory block layout structure and a memory to increase the storage capacity of DRAM under the same area.

[0005] An embodiment of the present disclosure provides a memory block layout structure for forming a memory block in a memory, comprising: a plurality of memory array layout structures, wherein the plurality of memory array layout structures are arranged in a first direction and are continuously arranged in a second direction to form a memory block layout structure; wherein each memory array layout structure is used to form a memory array in the memory block, and the first direction and the second direction are perpendicular to each other; the memory array layout structure is configured as a parallelogram area arranged based on a third direction and a fourth direction; wherein the angle α between the second direction and the fourth direction is less than 90°, and the angle 0 between the third direction and the fourth direction is less than β and less than 90°; each memory array layout structure is provided with a plurality of word lines and a plurality of bit lines, wherein one of the plurality of word lines and the plurality of bit lines is arranged at intervals in the third direction and extends in the fourth direction, and the other is arranged at intervals in the fourth direction and extends in the third direction.

[0006] In the memory block layout structure provided in this embodiment, a new arrangement of word lines WL and bit lines BL is provided, so that the arrangement of unit capacitors is honeycomb-shaped, thereby achieving high-density stacking of unit capacitors and improving the storage capacity of DRAM under the same area.

[0007] Optionally, a plurality of storage array layout structures are arranged in the first direction to form a storage block layout structure, including: the plurality of storage array layout structures arranged in the first direction have the same position in the second direction.

[0008] Optionally, between every two storage array layout structures arranged in the first direction, there are also: multiple supplementary word line structures; each supplementary word line structure is configured to connect a word line in the storage array layout structures on both sides and couple to the word line driver of the memory through a conductive node; wherein the conductive node is set on the supplementary word line structure.

[0009] Optionally, the supplementary word line structure is configured to connect word lines with the same position relationship in the storage array layout structures on both sides.

[0010] Optionally, a plurality of memory array layout structures are arranged in the first direction to form a memory block layout structure, including: N memory array layout structures arranged in the first direction and continuously arranged in the third direction, N≥2.

[0011] Optionally, the memory array layout structures continuously arranged in the third direction share a common word line, and the word line is coupled to a word line driver of the memory through a conductive node; wherein the conductive node is arranged on the word line at an edge position of any memory array layout structure.

[0012] Optionally, N storage array layout structures are arranged in the first direction and are continuously arranged in the third direction, including: two storage array layout structures continuously arranged in the third direction constitute a storage array layout structure group; the storage array layout structure group is arranged in the first direction and continuously arranged in the second direction to constitute a storage block layout structure, and the multiple storage array layout structure groups arranged in the first direction have the same position in the second direction.

[0013] Optionally, two memory array layout structures in the memory array layout structure group share a word line, and the word line is coupled to a word line driver of the memory through a conductive node; wherein the conductive node is arranged on the word line between the two memory array layout structures.

[0014] Optionally, all storage array layout structures arranged in the first direction are continuously arranged in the third direction.

[0015] Optionally, each memory array layout structure includes a plurality of unit capacitor layout structures, and the plurality of unit capacitor layout structures are continuously arranged in the third direction and the fourth direction.

[0016] Optionally, the angle α between the second direction and the fourth direction is 0.

[0017] Optionally, the angle β between the third direction and the fourth direction is 60°.

[0018] Another embodiment of the present disclosure further provides a memory, in which each memory block of the memory is arranged based on the memory block layout structure provided in the above embodiment to increase the storage capacity of DRAM under the same area. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 A method for arranging square-stacked cell capacitors, word lines, and bit lines in a DRAM.

[0021] Figure 2 Another method for arranging cell capacitors, word lines, and bit lines in a honeycomb pattern in a DRAM.

[0022] Figure 3 A schematic diagram of a memory layout structure provided in an embodiment of the present disclosure;

[0023] Figure 4 A schematic structural diagram of a storage array layout structure in a storage block layout structure provided in an embodiment of the present disclosure;

[0024] Figure 5 A schematic diagram illustrating "arrangement" and "continuous arrangement" according to an embodiment of the present disclosure;

[0025] Figure 6 A schematic structural diagram of a storage array layout structure in another storage block layout structure provided in an embodiment of the present disclosure;

[0026] Figure 7 A schematic diagram of a layout structure of a first storage block layout structure provided in an embodiment of the present disclosure;

[0027] Figure 8 An embodiment of the present disclosure provides Figure 7 A schematic diagram of the conductive node arrangement of the word line and word line driver in the structure shown;

[0028] Figure 9 A schematic diagram of a layout structure of a second storage block layout structure provided in an embodiment of the present disclosure;

[0029] Figure 10 An embodiment of the present disclosure provides Figure 9 A schematic diagram of the conductive node arrangement of the word line and word line driver in the structure shown;

[0030] Figure 11 A layout structure diagram of a third storage block layout structure provided by an embodiment of the present disclosure is shown in the figure;

[0031] Figure 12 A layout structure diagram of a fourth storage block layout structure provided by an embodiment of the present disclosure is shown in the figure. Figure 11 A diagram showing the arrangement of the conductive nodes of the word lines and the word line drivers in the structure is shown in the figure.

[0032] Figure 13 A layout structure diagram of a fourth storage block layout structure provided by an embodiment of the present disclosure is shown in the figure. DETAILED DESCRIPTION

[0033] As can be known from the background, in a 4F2 layout DRAM, the word lines (WL) and the bit lines (BL) are arranged vertically, and the intersection position of the word lines WL and the bit lines BL is used to set a cell capacitor, which is coupled to the word lines WL and the bit lines BL at the intersection position. It can be known that, in order to adapt to the arrangement mode of the word lines WL and the bit lines BL, the arrangement mode of the cell capacitor adopts a square stacking.

[0034] At present, with the progress of technology, the requirement for the storage capacity of the DRAM is higher and higher, that is, the number of the cell capacitors integrated in the DRAM is increased, and the cell capacitors adopting the square stacking have a smaller utilization rate of the limited layout structure area of the memory, which affects the improvement of the storage capacity of the DRAM to some extent.

[0035] Compared with the square stacking, the honeycomb arrangement has a higher utilization rate of space. In an example, referring to Figure 2 By adjusting the included angle between the word lines WL and the bit lines BL, the arrangement mode of the cell capacitors is adjusted to the honeycomb arrangement without changing the layout structure of the cell capacitors. The cell capacitors adopting the honeycomb arrangement have a larger utilization rate of the limited layout structure area of the memory, and by increasing the stacking density, the number of the cell capacitors set in the limited area is increased, which improves the storage capacity of the DRAM to some extent. However, referring to Figure 2 It can be found that the lengths of the word lines WL and the bit lines BL corresponding to different cell capacitors are different, which causes a certain electrical performance difference between the word lines WL and the bit lines BL in the memory, and improves the design difficulty of the subsequent driving of the word lines WL and the bit lines BL in the memory.

[0036] Based on this technical problem, an embodiment of the present disclosure provides a storage block layout structure for forming a storage block in a memory to improve the storage capacity of the DRAM in the same area.

[0037] Those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments may be combined and referenced with each other as long as there is no contradiction.

[0038] Figure 3 A schematic diagram of the memory layout structure provided in this embodiment, Figure 4 A schematic diagram of a storage array layout structure in a storage block layout structure provided in this embodiment is shown. Figure 5 The schematic diagram for explaining the "arrangement" and "continuous arrangement" provided in this embodiment is as follows: Figure 6 A schematic diagram of a storage array layout structure in another storage block layout structure provided in this embodiment is shown. Figure 7 A schematic diagram of the layout structure of the first storage block layout structure provided in this embodiment, Figure 8 Provided for this embodiment Figure 7 Schematic diagram of the conductive node arrangement of the word line and word line driver in the structure shown, Figure 9 A schematic diagram of the layout structure of the second storage block layout structure provided in this embodiment, Figure 10 Provided for this embodiment Figure 9 Schematic diagram of the conductive node arrangement of the word line and word line driver in the structure shown, Figure 11 A schematic diagram of the layout structure of the third storage block layout structure provided in this embodiment, Figure 12 Provided for this embodiment Figure 11 Schematic diagram of the conductive node arrangement of the word line and word line driver in the structure shown, Figure 13 This is a schematic diagram of the layout structure of the fourth storage block layout structure provided in this embodiment. The storage block layout structure provided in this embodiment is described in detail below with reference to the accompanying drawings, as follows:

[0039] It should be noted that the present disclosure mentions memory, storage block and storage array. The relationship between memory, storage block and storage array is described as follows: In one example, for the same memory, the memory includes multiple storage blocks, reference Figure 3 , multiple memory blocks are arranged in two rows on opposite sides of the memory, and the remaining area after the memory blocks are arranged (the area between the two rows of memory blocks and the outer area of ​​the memory blocks) is used as the peripheral circuit area of ​​the memory; for the same memory block, the memory block includes multiple memory arrays arranged in an array, and each memory array is composed of multiple word lines and multiple bit lines; In addition, it should be noted that, Figure 3The example structure is only used by those skilled in the art to understand the inclusion relationship among the memory, storage block and storage array mentioned in this disclosure, and does not constitute a specific location limitation.

[0040] refer to Figure 4 The memory block layout structure 100 provided in this embodiment is used to form a memory block in a memory, including:

[0041] Multiple memory array layout structures 200 are arranged in a first direction X0 and continuously arranged in a second direction Y0 to form a memory block layout structure 100; wherein each memory array layout structure 200 is used to form a memory array in a memory block, and the first direction X0 and the second direction Y0 are perpendicular to each other.

[0042] The memory array layout structure 200 is configured as a parallelogram area based on the third direction X1 and the fourth direction Y1; wherein the angle α between the second direction Y0 and the fourth direction Y1 is less than 90°, and the angle 0 between the third direction X1 and the fourth direction Y1 is less than 90°.

[0043] Each memory array layout structure 200 is provided with a plurality of word lines WL and a plurality of bit lines BL. Among the plurality of word lines WL and the plurality of bit lines BL, one is arranged at intervals in the third direction X1 and extends in the fourth direction Y1, and the other is arranged at intervals in the fourth direction Y1 and extends in the third direction X1.

[0044] It should be noted that the description of the storage block layout structure 100 mentioned above and in the following includes two layouts: “arrangement” and “continuous arrangement”. Figure 4 For the storage array layout structure 200 in the parallelogram area, the storage array layout structure 200 in the parallelogram area includes two groups of parallel edges, the two groups of parallel edges are respectively A and B edges set parallel to the third direction X1, and C and D edges set parallel to the fourth direction Y1.

[0045] For the layout mode of “arrangement”, “arrangement” refers to setting a plurality of storage array layout structures in corresponding directions, and there is no specific position limitation between the plurality of storage array layout structures.

[0046] In one example, refer to Figure 5 The storage array layout structure 200 arranged in the third direction X1 includes Z1, Z2 and Z4. Since there is no specific position requirement, it can be said that Z1, Z2 and Z4 are "arranged" in the third direction X1; the storage array layout structure 200 arranged in the fourth direction Y1 includes Z1, Z3 and Z5. Since there is no specific position requirement, it can be said that Z1, Z3 and Z5 are "arranged" in the fourth direction Y1.

[0047] For the "continuous arrangement", it means that multiple storage array layout structures are arranged in a corresponding direction, and the edges in a non-corresponding direction of the multiple storage array layout structures are aligned with each other.

[0048] In one example, referring to Figure 5 The storage array layout structure 200 arranged in the third direction X1 includes Z1, Z2 and Z4, and the "continuous arrangement" requires that the edges in the non-parallel direction (non-third direction X1) are aligned with each other. The D edge of the storage array layout structure Z2 is aligned with the C edge of the storage array layout structure Z1, that is, the storage array layout structures Z1 and Z2 are in the "continuous arrangement" relationship, and the D edge of the storage array layout structure Z1 is not aligned with the C edge of the storage array layout structure Z4, that is, the storage array layout structures Z1 and Z4 are only in the "arrangement" relationship, and do not meet the "continuous arrangement" relationship. The storage array layout structure 200 arranged in the fourth direction Y1 includes Z1, Z3 and Z5, and the "continuous arrangement" requires that the edges in the non-parallel direction (non-fourth direction Y1) are aligned with each other. The B edge of the storage array layout structure Z1 is aligned with the A edge of the storage array layout structure Z3, that is, the storage array layout structures Z1 and Z3 are in the "continuous arrangement" relationship, and the B edge of the storage array layout structure Z5 is not aligned with the A edge of the storage array layout structure Z1, that is, the storage array layout structures Z1 and Z5 are only in the "arrangement" relationship, and do not meet the "continuous arrangement" relationship.

[0049] For the storage block layout structure 100 provided by the embodiment, a new arrangement mode of the word line WL and the bit line BL is provided, the included angle between the word line WL and the bit line BL is an acute angle, in addition, the arrangement mode of the unit capacitor coupled with the word line WL and the bit line BL is adjusted from the square arrangement mode to the honeycomb arrangement mode, and the honeycomb arrangement mode has a higher packing density than the square arrangement mode, so as to realize high-density packing of the unit capacitor and improve the number of the unit capacitor of the DRAM in the same area, that is, improve the storage capacity of the DRAM in the same area.

[0050] Continuing to refer to Figure 4 In the storage array layout structure 200 provided by the embodiment, each storage array layout structure 200 includes multiple unit capacitor layout structures 20, and the multiple unit capacitor layout structures 20 are arranged continuously in the third direction X1 and the fourth direction Y1, so as to form a parallelogram region of the storage array layout structure 200. The unit capacitor layout structure 20 is used to form a unit capacitor in the storage array, and the unit capacitor layout structure is arranged in the parallelogram region based on the third direction X1 and the fourth direction Y1, and the lengths of the unit capacitor layout structure arranged in the third direction X1 and the fourth direction Y1 are equal.

[0051] By setting the unit capacitor layout structure 20 as a parallelogram region parallel to the word line WL and the bit line BL to fit the parallelogram region of the storage array layout structure 200; in addition, the unit capacitor layout structure 20 is set to have equal lengths in the third direction X1 and the fourth direction Y1, so that the unit capacitor layout structure 20 contacts the bit line BL and the word line WL with the same length, and the length of the word line corresponding to each unit capacitor and the length of the bit line are uniform, facilitating the subsequent driving design of the word line WL and the bit line BL of the memory.

[0052] In some embodiments, with reference to Figure 6 , the angle α between the second direction Y0 and the fourth direction Y1 is 0, and the angle β between the third direction X1 and the fourth direction Y1 is 60°; in addition, the word line WL extends in the third direction X1, and the bit line BL extends in the second direction Y0 to satisfy the row-column relationship of the word line WL and the bit line BL.

[0053] It should be noted that in the subsequent description of the present embodiment, the example is described as an example, and is only used to understand the storage block layout structure 100 provided by the present disclosure by those skilled in the art. Those skilled in the art can replace the corresponding angles with other α and β, thereby obtaining other storage block layout structures.

[0054] For the storage array layout structure 200 arranged in the first direction X0, in one example, with reference to Figure 7 , the plurality of storage array layout structures 200 arranged in the first direction X0 have the same position in the second direction Y0.

[0055] Specifically, the plurality of storage array layout structures 200 arranged in the first direction X0 have the same position of the C side of each storage array layout structure 200 in the second direction Y0, and the same position of the D side of each storage array layout structure 200 in the second direction Y0.

[0056] It should be noted that for the "same position", that is, after establishing a plane index coordinate system with the first direction X0 and the second direction Y0 as the axes on the corresponding diagram of the storage array layout structure 200, the coordinates of the corresponding axes in the second direction Y0 are consistent, that is, the positions in the second direction Y0 are the same; similarly, the coordinates of the corresponding axes in the first direction X0 are consistent, that is, the positions in the first direction X0 are the same.

[0057] For Figure 7 the schematic storage block layout structure 100, with reference to Figure 8In addition, between each two storage array layout structures 200 arranged in the first direction X0, a plurality of supplemental word line structures 301 are further included, each of the supplemental word line structures 301 is configured to connect a word line WL in the two storage array layout structures 200, and is coupled to a word line driver of the memory through a conductive node 302 disposed on the supplemental word line structure 301.

[0058] For the conductive node 302, in one example, a plurality of wafers can be included in a memory, and the plurality of wafers include an array wafer and a logic wafer, wherein only word lines WL, bit lines BL and cell capacitors Cell Cap are disposed on the array wafer, and the logic wafer is used to control and read and write the array wafer; in a specific application, the array wafer and the logic wafer are connected by hybrid bonding, and the word line driver SWD is connected to the conductive node 302 which is a connection node of the word line WL in the array transistor through hybrid bonding.

[0059] Further, the supplemental word line structure 301 is configured to connect the word lines WL in the same position relationship in the two storage array layout structures 200.

[0060] For the understanding of the "same position relationship", the "same position relationship" refers to the word lines in the same position in different storage array layout structures 200, for example, the storage array includes 200 word lines WL, which are sequentially arranged in the second direction Y0 as the first word line, the second word line, …, and the 200th word line; the word lines WL in the same position are connected, that is, the ith word line in the two storage arrays is connected.

[0061] For the memory, the conduction / cutoff of the word line WL needs to be controlled by the word line driver, and the word line driver is disposed between the storage array layout structures 200 in the extension direction of the word line WL; since the plurality of storage array layout structures 200 in the third direction X1 are not continuously arranged, there is no intersection between the word lines WL in the same position relationship in the adjacent storage array layout structures 200, which cannot be connected to the same word line driver, and therefore the supplemental word line structure 301 is needed to connect the word lines WL in the same position relationship, so as to be connected to the same word line driver.

[0062] Reference Figure 3 And Figure 7 Since the layout structure of the storage block is still rectangular, the storage block layout structure formed based on the parallelogram region of the storage array layout structure 200 cannot realize Figure 3The rectangular layout structure shown, thus the storage block layout structure 100, has no edge area where the storage array layout structure 200 can be arranged. In some embodiments, the edge area of the storage block layout structure 100 can be incorporated into a peripheral circuit area, which is arranged as a peripheral circuit area of the memory.

[0063] For the example of Figure 7 Assuming that the length of the A side of the storage array layout structure 200 is a, the length of the C side is c, the number of the storage array layout structure 200 arranged in the first direction X0 of the storage block layout structure 100 is x, and the number of the storage array layout structure 200 arranged in the second direction Y0 of the storage block layout structure 100 is y, the area of the edge area S1 = 2x * asin60° * acos60° / 2 = xa 2 sin60°cos60°, the area of the storage block layout structure 100 S2 = axsin60° * (cy + acos60°), and the ratio of the area of the edge area to the area of the storage block layout structure 100 Z = xa 2 sin60°cos60° / 2[axsin60° * (cy + acos60°)], where the size of acos60° is negligible compared to the size of c*y, i.e., the ratio of the area of the edge area to the area of the storage block layout structure 100 Z is about a / 2cy.

[0064] For the storage array layout structure 200 arranged in the first direction X0, in one example, referring to Figure 9 , N storage array layout structures 200 arranged in the first direction X0 are arranged in the third direction X1, and N ≥ 2. Specifically, the N storage array layout structures 200 are arranged in the third direction X1, and the N+1th storage array layout structure 200 is arranged at the same position as the 1st storage array layout structure 200 in the second direction Y0.

[0065] For the example of Figure 9 Referring to Figure 10 Since the N storage array layout structures 200 are arranged in the third direction X1, and the word line WL extends in the third direction X1, the arrangement of the word line WL is the same as that of the N storage array layout structures 200 arranged in the third direction X1. At this time, the N storage array layout structures 200 arranged in the third direction X1 share the word line WL, and the word line WL is coupled to the word line driver of the memory through the conductive node 302; wherein the conductive node 302 is arranged on the word line WL at the edge position of any storage array layout structure 200.

[0066] Compared with Figure 7 For the example of Figure 9In the example memory block layout structure 100, the introduction of the supplementary word line structure is avoided, and the wiring of the memory block layout structure 100 is relatively simple. However, since N memory array layout structures 200 are continuously arranged in the third direction X1, the area of ​​the edge region in the memory block is larger.

[0067] for Figure 9 For example, assuming that the length of side A of the memory array layout structure 200 is a, the length of side C is c, the number of memory array layout structures 200 arranged in the first direction X0 of the memory block layout structure 100 is x, and the number of memory array layout structures 200 continuously arranged in the second direction Y0 is y, then the area of ​​the edge region S1 = 2x / N*aNsin60°*aNcos60° / 2 = xNa 2 sin60°cos60°, the area of ​​the memory block layout structure 100 S2=axsin60°*(cy+aNcos60°), the proportion of the edge area to the area of ​​the memory block layout structure 100 Z=xNa 2 sin60°cos60° / [axsin60°*(cy+aNcos60°)], wherein the size of aNcos60° is negligible relative to the size of c*y, that is, the proportion Z of the edge area in the area of ​​the storage block layout structure 100 is approximately aN / 2cy.

[0068] In some embodiments, reference Figure 11 , N memory array layout structures 200 are arranged in the first direction X0 and are continuously arranged in the third direction X1, including: two memory array layout structures 200 continuously arranged in the third direction X1 constitute a memory array layout structure group 400, the memory array layout structure group 400 is arranged in the first direction X0 and continuously arranged in the second direction Y0 to constitute a memory block layout structure 100, and the multiple memory array layout structure groups 400 arranged in the first direction X0 are at the same position in the second direction Y0.

[0069] for Figure 10 Schematic memory block layout structure 100, refer to Figure 12 The two memory array layout structures 200 in the memory array layout structure group 400 share a word line WL, and the word line WL is coupled to a word line driver of the memory through a conductive node 302, wherein the conductive node 302 is set on the word line WL between the two memory array layout structures 200.

[0070] Compared to Figure 9 Example, Figure 11In the exemplary memory layout structure 100 , every two memory array layout structures 200 are consecutively arranged in the third direction X1 . The number of memory array layout structures 200 consecutively arranged in the third direction X1 is relatively small, and the area of ​​the edge region is also relatively small.

[0071] for Figure 11 For example, assuming that the length of side A of the memory array layout structure 200 is a, the length of side C is c, the number of memory array layout structures 200 arranged in the first direction X0 of the memory block layout structure 100 is x, and the number of memory array layout structures 200 continuously arranged in the second direction Y0 is y, then the area of ​​the edge region S1 = 2x / 2*2asin60°*2acos60° / 2 = 2xa 2 sin60°cos60°, the area of ​​the memory block layout structure 100 S2=axsin60°*(cy+aNcos60°), the proportion of the edge area to the area of ​​the memory block layout structure 100 Z=2xa 2 sin60°cos60° / axsin60°*(cy+aNcos60°), wherein the size of aNcos60° is negligible relative to the size of c*y, that is, the proportion Z of the edge area to the area of ​​the storage block layout structure 100 is approximately a / cy.

[0072] In some embodiments, reference Figure 13 All the memory array layout structures 200 arranged in the first direction X0 are continuously arranged in the third direction X1. It should be noted that there are many specific combinations of the N memory array layout structures 200 arranged in the first direction X0 and continuously arranged in the third direction X1. This embodiment will not give examples one by one, and the examples in this embodiment do not limit the number N.

[0073] The memory block layout structure 100 provided in this embodiment provides a new arrangement of word lines WL and bit lines BL, wherein the angle between the word lines WL and the bit lines BL is an acute angle. In addition, the arrangement of the cell capacitors coupled to the word lines WL and the bit lines BL is adjusted from a square arrangement to a honeycomb arrangement. The honeycomb arrangement has a higher stacking density than the square arrangement, thereby achieving high-density stacking of cell capacitors, increasing the number of cell capacitors of the DRAM under the same area, that is, increasing the storage capacity of the DRAM under the same area.

[0074] In addition, the unit capacitor layout structure 20 is arranged as a parallelogram region parallel to the word line WL and the bit line BL to match the parallelogram region of the constructed memory array layout structure 200. In addition, the lengths of the unit capacitor layout structure 20 in the third direction X1 and the fourth direction Y1 are equal, so that the lengths of the bit line BL and the word line WL contacted by the unit capacitor layout structure 20 are the same, and the lengths of the word line and the bit line corresponding to each unit capacitor are unified, which facilitates the subsequent drive design of the word line WL and the bit line BL of the memory.

[0075] It should be noted that the features disclosed in the memory block layout structure provided in the above embodiments can be arbitrarily combined without conflict to obtain a new memory block layout structure embodiment.

[0076] Another embodiment of the present disclosure provides a memory, in which each memory block of the memory is arranged based on the memory block layout structure provided in the above embodiment to increase the storage capacity of DRAM under the same area.

[0077] Specifically, refer to Figure 3 For the same memory, the memory includes multiple memory blocks, and the multiple memory blocks are arranged in two rows on opposite sides of the memory. The remaining area after the memory blocks are arranged (the area between the memory blocks and the outer area of ​​the memory blocks) is used as the peripheral circuit area of ​​the memory; for the same memory block, the memory block includes multiple memory arrays, and each memory array is composed of multiple word lines and multiple bit lines.

[0078] In some examples, the memory may be a storage unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory, such as a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), a graphics double data rate synchronous dynamic random access memory (GDDR SDRAM), a double data rate type dual synchronous dynamic random access memory (DDR2 SDRAM), a double data rate type triple synchronous dynamic random access memory (DDR3 SDRAM), a double data rate fourth generation synchronous dynamic random access memory (DDR4 SDRAM), a thyristor random access memory (TRAM), etc.; or may be a non-volatile memory, such as a phase change random access memory (PRAM), a magnetic random access memory (MRAM), a resistive random access memory (RRAM), etc.

[0079] Each memory block is formed based on the memory block layout structure 100 provided in the above embodiment, for details, refer to Figure 4The memory block layout structure 100 includes: a plurality of memory array layout structures 200, which are arranged in a first direction X0 and continuously arranged in a second direction Y0 to form the memory block layout structure 100; wherein each memory array layout structure 200 is used to form a memory array in the memory block, and the first direction X0 and the second direction Y0 are perpendicular to each other. The memory array layout structure 200 is configured as a parallelogram region arranged based on a third direction X1 and a fourth direction Y1; wherein the angle α between the second direction Y0 and the fourth direction Y1 is less than 90°, and the angle θ between the third direction X1 and the fourth direction Y1 is less than 90°. Each memory array layout structure 200 is provided with a plurality of word lines WL and a plurality of bit lines BL, wherein one of the plurality of word lines WL and the plurality of bit lines BL is arranged alternately in the third direction X1 and extends in the fourth direction Y1, and the other is arranged alternately in the fourth direction Y1 and extends in the third direction X1.

[0080] For each storage block, a new arrangement of word lines WL and bit lines BL is provided, in which the angle between the word lines WL and the bit lines BL is an acute angle. In addition, the arrangement of cell capacitors coupled to the word lines WL and the bit lines BL is adjusted from a square arrangement to a honeycomb arrangement. The honeycomb arrangement has a higher stacking density than the square arrangement, thereby achieving high-density stacking of cell capacitors, increasing the number of cell capacitors of the DRAM under the same area, that is, increasing the storage capacity of the DRAM under the same area.

[0081] In some embodiments, reference Figure 4 Each memory array layout structure 200 includes a plurality of unit capacitor layout structures 20. The plurality of unit capacitor layout structures 20 are continuously arranged in the third direction X1 and the fourth direction Y1, thereby forming a parallelogram-shaped memory array layout structure 200. The unit capacitor layout structure 20 is used to form unit capacitors in the memory array. The unit capacitor layout structure is configured as a parallelogram-shaped area arranged in the third direction X1 and the fourth direction Y1. The lengths of the unit capacitor layout structures arranged in the third direction X1 and the fourth direction Y1 are equal.

[0082] By arranging the unit capacitor layout structure 20 into a parallelogram region parallel to the word lines WL and the bit lines BL, the unit capacitor layout structure 20 is aligned with the parallelogram region of the constructed memory array layout structure 200. In addition, the unit capacitor layout structure 20 is arranged with equal lengths in the third direction X1 and the fourth direction Y1, so that the bit lines BL and word lines WL contacted by the unit capacitor layout structure 20 have the same lengths. This unifies the lengths of the word lines and bit lines corresponding to each unit capacitor, facilitating the subsequent drive design of the word lines WL and bit lines BL of the memory.

[0083] For the memory array layout structure 200 arranged in the first direction X0, in one example, refer to Figure 7 The plurality of memory array layout structures 200 arranged in the first direction X0 have the same position in the second direction Y0.

[0084] for Figure 7 For example, assuming that the length of side A of the memory array layout structure 200 is a, the length of side C is c, the number of memory array layout structures 200 arranged in the first direction X0 of the memory block layout structure 100 is x, and the number of memory array layout structures 200 continuously arranged in the second direction Y0 is y, then the area of ​​the edge region S1 = 2x*asin60°*acos60° / 2 = x a 2 sin60°cos60°, the area of ​​the memory block layout structure 100 S2=axsin60°*(cy+acos60°), the proportion of the edge area to the area of ​​the memory block layout structure 100 Z=xa 2 sin60°cos60° / [axsin60°*(cy+acos60°)], wherein the size of acos60° is negligible relative to the size of c*y, that is, the proportion Z of the edge area in the area of ​​the storage block layout structure 100 is approximately a / 2cy.

[0085] In addition, for Figure 7 For example, refer to Figure 8 Since the multiple memory array layout structures 200 in the third direction X1 are not arranged continuously, there are parallel word lines WL in adjacent memory array layout structures 200. The parallel word lines WL have no intersection and cannot be connected to the same word line driver. Therefore, it is necessary to introduce a supplementary word line structure 301 to connect the parallel word lines WL and thus connect them to the same word line driver.

[0086] For the memory array layout structure 200 arranged in the first direction X0, in one example, refer to Figure 9 , N memory array layout structures 200 are arranged in the first direction X0 and are continuously arranged in the third direction X1, N≥2.

[0087] for Figure 9 For example, assuming that the length of side A of the memory array layout structure 200 is a, the length of side C is c, the number of memory array layout structures 200 arranged in the first direction X0 of the memory block layout structure 100 is x, and the number of memory array layout structures 200 continuously arranged in the second direction Y0 is y, then the area of ​​the edge region S1 = 2x / N*aNsin60°*aNcos60° / 2 = xNa 2sin60°cos60°, the area of ​​the memory block layout structure 100 S2=axsin60°*(cy+aNcos60°), the proportion of the edge area to the area of ​​the memory block layout structure 100 Z=xNa 2 sin60°cos60° / [axsin60°*(cy+aNcos60°)], wherein the size of aNcos60° is negligible relative to the size of c*y, that is, the proportion Z of the edge area in the area of ​​the storage block layout structure 100 is approximately aN / 2cy.

[0088] In addition, for Figure 9 For example, refer to Figure 10 Since N consecutive memory array layout structures 200 are arranged continuously in the third direction X1, and the word lines WL extend in the third direction X1, the arrangement of the word lines WL is the same as that of the consecutively arranged memory array layout structures 200. At this time, the memory array layout structures 200 arranged continuously in the third direction X1 share the word lines WL, avoiding the introduction of a supplementary word line structure, and the wiring of the memory block layout structure 100 is relatively simple.

[0089] In some embodiments, reference Figure 11 , N memory array layout structures 200 are arranged in the first direction X0 and are continuously arranged in the third direction X1, including: two memory array layout structures 200 continuously arranged in the third direction X1 constitute a memory array layout structure group 400, the memory array layout structure group 400 is arranged in the first direction X0 and continuously arranged in the second direction Y0 to constitute a memory block layout structure 100, and the multiple memory array layout structure groups 400 arranged in the first direction X0 are at the same position in the second direction Y0.

[0090] for Figure 11 For example, assuming that the length of side A of the memory array layout structure 200 is a, the length of side C is c, the number of memory array layout structures 200 arranged in the first direction X0 of the memory block layout structure 100 is x, and the number of memory array layout structures 200 continuously arranged in the second direction Y0 is y, then the area of ​​the edge region S1 = 2x / 2*2asin60°*2acos60° / 2 = 2xa 2 sin60°cos60°, the area of ​​the memory block layout structure 100 S2=axsin60°*(cy+aNcos60°), the proportion of the edge area to the area of ​​the memory block layout structure 100 Z=2xa 2 sin60°cos60° / axsin60°*(cy+aNcos60°), wherein the size of aNcos60° is negligible relative to the size of c*y, that is, the proportion Z of the edge area to the area of ​​the storage block layout structure 100 is approximately a / cy.

[0091] In addition, for Figure 11 Examples, references Figure 12 The two memory array layout structures 200 in the memory array layout structure group 400 share a word line WL, avoiding the introduction of a supplementary word line structure. The wiring of the memory block layout structure 100 is relatively simple, and the proportion Z of the edge area in the area of ​​the memory block layout structure 100 is relatively small.

[0092] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A memory block layout structure for forming a memory block in a memory, characterized in that: include: a plurality of memory array layout structures arranged along a first direction and continuously disposed along a second direction, wherein adjacent memory array layout structures arranged along the first direction have the same position in the second direction; wherein each memory array layout structure is used to form a memory array in the memory block, and the first direction and the second direction are perpendicular to each other; The storage array layout structure is configured as a parallelogram area arranged based on a third direction and a fourth direction; wherein the angle α between the second direction and the fourth direction is less than 90°, and the angle 0 between the third direction and the fourth direction is less than β less than 90°; Each of the memory array layout structures is provided with a plurality of word lines and a plurality of bit lines, wherein one of the plurality of word lines and the plurality of bit lines is arranged at intervals in the third direction and extends in the fourth direction, and the other one of the word lines and the bit lines is arranged at intervals in the fourth direction and extends in the third direction; Also included between adjacent storage array layout structures arranged along the first direction: Multiple supplementary word line structures; Each of the supplementary word line structures is configured to connect a word line in the memory array layout structures on both sides and be coupled to a word line driver of the memory through a conductive node; Wherein, the conductive node is arranged on the supplementary word line structure.

2. The storage block layout structure according to claim 1, wherein: The supplementary word line structure is configured to connect word lines with the same position relationship in the memory array layout structures on both sides.

3. A memory block layout structure for forming a memory block in a memory, characterized in that: include: a plurality of memory array layout structure groups arranged along a first direction and continuously disposed along a second direction, wherein adjacent memory array layout structure groups arranged along the first direction have the same position in the second direction, and each memory array layout structure group includes N memory array layout structures continuously disposed along a third direction, where N ≥ 2; wherein each memory array layout structure is used to form a memory array in the memory block, and the first direction and the second direction are perpendicular to each other; The storage array layout structure is configured as a parallelogram area arranged based on the third direction and the fourth direction; wherein the angle α between the second direction and the fourth direction is less than 90°, and the angle 0 between the third direction and the fourth direction is less than β less than 90°; Each of the memory array layout structures is provided with a plurality of word lines and a plurality of bit lines, wherein one of the plurality of word lines and the plurality of bit lines is arranged at intervals in the third direction and extends in the fourth direction, and the other one of the word lines and the bit lines is arranged at intervals in the fourth direction and extends in the third direction; N memory array layout structures belonging to the same memory array layout structure group share a word line, and the word line is coupled to a word line driver of the memory through a conductive node; The conductive nodes are arranged on the word lines at any edge position of the memory array layout structure.

4. The storage block layout structure according to claim 3, wherein: include: The N=2, and the conductive node is disposed on the word line between two memory array layout structures in the same memory array layout structure group.

5. The storage block layout structure according to any one of claims 1 to 4, characterized in that: Each of the storage array layout structures includes a plurality of unit capacitor layout structures, and the plurality of unit capacitor layout structures are continuously arranged in the third direction and the fourth direction; the unit capacitor layout structure is configured as a parallelogram area arranged based on the third direction and the fourth direction, wherein the lengths of the unit capacitor layout structures arranged in the third direction and the fourth direction are the same.

6. The storage block layout structure according to any one of claims 1 to 4, characterized in that: An angle α between the second direction and the fourth direction is 0.

7. The storage block layout structure according to any one of claims 1 to 4, characterized in that: An included angle β between the third direction and the fourth direction is 60°.

8. A memory, characterized in that: Each storage block of the memory is arranged based on the storage block layout structure according to any one of claims 1 to 7.

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