Memory module, method of operating memory module, and memory system including memory module

Abstract

A memory module includes: a circuit board including a plurality of signal lines to which a command is applied; and a first memory device mounted on a first surface of the circuit board, connected to the plurality of signal lines, including a first mode register, and configured to: operate in a standard mode or a mirror mode based on a value set in the first mode register; a value corresponding to a mirroring mode is set in a first mode register based on a first command applied to a plurality of signal lines, in which at least one of a plurality of command / address bits in the first command is swapped with at least one of a plurality of command / address bits in a second command.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0121319 filed on September 12, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2024-0063088 filed on May 14, 2024, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0002] The present disclosure relates to a storage module, an operating method of the storage module, and a storage system including the storage module, and more particularly, to a storage module including a mirroring function, an operating method of the storage module, and a storage system including the storage module. Background Art

[0003] Memory devices are used to store data and are classified as either volatile memory devices or nonvolatile memory devices. Volatile memory devices are memory devices that lose the data stored therein when the power is turned off. Dynamic random access memory (DRAM) among volatile memory devices is used in various fields such as mobile systems, servers, and graphics devices.

[0004] DRAM can be used in a memory module that takes the form of a dual in-line memory module (DIMM) in which multiple chips are mounted on opposite surfaces of a circuit board. The DRAM chips mounted on the opposite surfaces can use command / address signals in common. In this case, a mirroring function can be implemented in the DRAM chip so that the DRAM chips mounted on the opposite surfaces operate in the same manner according to the command / address signals applied to the DRAM chips.

[0005] Generally, a DRAM chip may include a pin associated with a mirror function (hereinafter referred to as a "mirror pin"), and may operate in a standard mode or a mirror mode according to a signal applied to the mirror pin. A DRAM chip operating in the standard mode may use the values ​​of command / address signals applied to the DRAM chip without modification, and a DRAM chip operating in the mirror mode may swap and use the values ​​of command / address signals applied to the DRAM chip. Summary of the invention

[0006] The present disclosure aims to realize the mirror function without the need for mirror pins.

[0007] According to one aspect of the present disclosure, a storage module includes: a circuit board including a plurality of signal lines to which commands are applied; and a first storage device mounted on a first surface of the circuit board, connected to the plurality of signal lines, including a first mode register, and configured to: operate in a standard mode or a mirror mode based on a value set in the first mode register; and set a value corresponding to the mirror mode in the first mode register based on a first command applied to the plurality of signal lines, wherein at least one of a plurality of command / address bits in the first command is swapped with at least one of a plurality of command / address bits in a second command.

[0008] According to one aspect of the present disclosure, a storage system includes: a storage module including a first storage device mounted on a first surface of a circuit board; and a storage controller operatively connected to the storage module, wherein the first storage device includes a first mode register and is configured to operate in a standard mode or a mirror mode based on a value stored in the first mode register, wherein the circuit board includes a plurality of signal lines connected to the first storage device, wherein the storage controller is configured to apply a first command to the plurality of signal lines to set a value corresponding to the mirror mode in the first mode register, wherein the first command is a command to exchange at least one of a plurality of command / address bits with at least one of a plurality of command / address bits in a second command.

[0009] According to one aspect of the present disclosure, a method for a storage module is provided, the storage module including a first storage device mounted on one surface of a circuit board, the method including: operating the first storage device in a standard mode based on a default value set in a first mode register in the first storage device; setting a value corresponding to a mirror mode in the first mode register based on a first command applied to a plurality of signal lines connected to the first storage device; and operating the first storage device in the mirror mode based on the value corresponding to the mirror mode set in the first mode register, wherein the circuit board includes a plurality of signal lines, and wherein the first command is a command that exchanges at least one of a plurality of command / address bits with at least one of a plurality of command / address bits in a second command. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the present disclosure will become apparent by describing embodiments of the present disclosure with reference to the accompanying drawings.

[0011] Figure 1A A storage module according to an embodiment of the present disclosure is shown;

[0012] Figure 1B Shows Figure 1A An example of a storage module;

[0013] Figure 2AThe arrangement of pins of a memory device according to an embodiment of the present disclosure is shown;

[0014] Figure 2B The arrangement of pins of a memory device according to an embodiment of the present disclosure is shown;

[0015] Figure 3A shows a vertical cross-sectional view of a storage module according to an embodiment of the present disclosure;

[0016] Figure 3B shows the positional relationship between CA pins of a first storage device and a second storage device facing away from each other;

[0017] Figure 4 shows a vertical cross-sectional view of a storage module according to an embodiment of the present disclosure;

[0018] Figure 5 A first command according to an embodiment of the present disclosure is shown;

[0019] Figure 6 shows a vertical cross-sectional view of a storage module according to an embodiment of the present disclosure;

[0020] Figure 7 A memory device according to an embodiment of the present disclosure is shown;

[0021] Fig. 8A A command / address exchange circuit according to an embodiment of the present disclosure is shown;

[0022] Figure 8B Shows Fig. 8A An example of a unit command / address exchange circuit;

[0023] Figure 8C It shows Fig. 8A A diagram of an example of a unit command / address exchange circuit;

[0024] Fig. 9 shows a partial configuration of a memory device according to an embodiment of the present disclosure;

[0025] Fig. 10A Shown include Fig. 9 An example of a fuse circuit for a non-volatile storage area;

[0026] Fig. 10B An example of implementing a nonvolatile storage area by using anti-fuse cells of a fuse array is shown;

[0027] Fig.11 An operation method of a storage module according to an embodiment of the present disclosure is shown;

[0028] Fig.12 An operation method of a storage module according to an embodiment of the present disclosure is shown;

[0029] Fig.13 shows a partial configuration of a memory device according to an embodiment of the present disclosure;

[0030] Fig.14 A storage system according to an embodiment of the present disclosure is shown; and

[0031] Fig.15 The configuration of the storage module according to the embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0032] Hereinafter, one or more embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present disclosure pertains can easily implement the present disclosure.

[0033] The terms used in the present disclosure are only used to describe specific embodiments and are not intended to limit the scope of other embodiments. Unless otherwise clearly indicated in the context, the singular form includes plural indicators. The terms and words (including technical or scientific terms) used herein may have the same meaning as those generally understood by those skilled in the art. The terms generally defined in the dictionary may be interpreted as having the same or similar meaning as the contextual meaning of the relevant field. Unless otherwise defined, the terms should not be interpreted as ideal or too formal meanings. Even if a term is defined in the present disclosure, the term should not be interpreted as excluding embodiments of the present disclosure in some cases.

[0034] Before proceeding to the detailed description below, it may be advantageous to set forth the definitions of specific words and phrases used throughout this disclosure. The terms "include" and "comprises" and their derivatives refer to inclusion without limitation. The term "or" is an inclusive term, meaning "and / or". The phrase "associated with..." and its derivatives refer to including, being included, interconnected with..., containing, being contained within, being connected to or connected with..., being coupled to or coupled with..., being communicable with..., collaborating with..., interweaving, juxtaposing, approaching..., being bound to... or bound with..., having, having the attributes of..., having a relationship with... or a relationship with..., etc. The term "controller" (e.g., a storage controller) refers to any device, system, or part thereof that controls at least one operation. The functions associated with any particular controller may be centralized or distributed, whether local or remote. The phrase "at least one" when used with a list of items means that different combinations of one or more of the listed items may be used, and only one item in the list may be required. For example, "at least one of A, B, and C" includes any combination of A, B, C, A and B, A and C, B and C, A and B and C, and any variations thereof. As an additional example, the expression "at least one of a, b, or c" may mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof. Similarly, the term "set" means one or more. Thus, a set of items may be a single item, or a set of two or more items.

[0035] Figure 1A A storage module according to an embodiment of the present disclosure is shown, and Figure 1B It shows Figure 1A FIG. 1 is a diagram of an example of a storage module.

[0036] refer to Figure 1A and Figure 1B The storage module 1000 may include a circuit board 50, first storage devices 101a, 102a, ..., etc. mounted on a first surface 1000a of the circuit board 50, and second storage devices 101b, 102b, ..., etc. mounted on a second surface 1000b of the circuit board 50 facing away from the first surface 1000a.

[0037] The number of the first storage devices 101a, 102a, ..., etc., the number of the second storage devices 101b, 102b, ..., etc. and their arrangement can vary according to the standard or specification of the storage module 1000. According to an embodiment, the storage module 1000 can be various dual in-line memory modules (DIMMs) that comply with the Joint Electronic Device Engineering Council (JEDEC) standard. For example, the storage module 1000 can be a registered DIMM (RDIMM), a load reduction DIMM (LRDIMM), an unbuffered DIMM (UDIMM), a fully buffered DIMM (FB-DIMM) or a small form factor DIMM (SO-DIMM). However, this is provided only as an example, and the storage module 1000 can be a DIMM that does not comply with the JEDEC standard.

[0038] The first storage devices 101a, 102a, ..., etc. and the second storage devices 101b, 102b, ..., etc. may be mounted on the circuit board 50 to face away from each other. For example, the first storage device 101a and the second storage device 101b may be mounted on the circuit board 50 to face away from each other. In addition, the first storage device 102a and the second storage device 102b may be mounted on the circuit board 50 to face away from each other. As described above, each of the remaining first storage devices and the remaining second storage devices may be mounted on the circuit board 50 to face away from each other.

[0039] In some embodiments, the first storage device 101a, 102a, ..., etc. and the second storage device 101b, 102b, ..., etc. may include mirror information storage areas 101a_1, 102a_1, ..., etc., 101b_1, 102b_1, ..., etc., respectively. Each of the mirror information storage areas 101a_1, 102a_1, ..., etc., 101b_1, 102b_1, ..., etc. may store a value associated with a mirror function. For example, a first value corresponding to a standard mode or a second value corresponding to a mirror mode may be stored, set, or programmed in each of the mirror information storage areas 101a_1, 102a_1, ..., etc., 101b_1, 102b_1, ..., etc. To this end, each of the mirror information storage areas 101a_1, 102a_1, ..., etc., 101b_1, 102b_1, ..., etc. may include at least one of a mode register or a non-volatile memory.

[0040] Each of the first storage device 101a, 102a, ..., etc. and the second storage device 101b, 102b, ..., etc. can be operated in a standard mode or a mirror mode based on a value set in a corresponding one of the mirror information storage areas 101a_1, 102a_1, ..., etc., 101b_1, 102b_1, ..., etc. For example, when a second value is set in each mirror information storage area 101a_1, 102a_1, ..., etc. of the first storage device 101a, 102a, ..., etc., and a first value is set in each mirror information storage area 101b_1, 102b_1, ..., etc. of the second storage device 101b, 102b, ..., etc., the first storage device 101a, 102a, ..., etc. can be operated in the mirror mode, and the second storage device 101b, 102b, ..., etc. can be operated in the standard mode. However, the present disclosure is not limited thereto.

[0041] According to an embodiment, a default value may be set in each of the mirror information storage areas 101a_1, 102a_1, ..., etc., 101b_1, 102b_1, ..., etc. Here, a default value may be set in each of the mirror information storage areas 101a_1, 102a_1, ..., etc., 101b_1, 102b_1, ..., etc. The default value set in each of the mirror information storage areas 101a_1, 102a_1, ..., etc., 101b_1, 102b_1, ..., etc. may be maintained until a value different from the default value is set based on a first command to be described later.

[0042] In an embodiment, in the process of manufacturing the storage devices 101a, 102a, ..., etc., 101b, 102b, ..., etc., the default value may be determined in advance as one of the first value or the second value. Hereinafter, the first value is determined as the default value. Therefore, when the default value is set in each of the mirror information storage areas 101a_1, 102a_1, ..., etc., 101b_1, 102b_1, ..., etc., all the first storage devices 101a, 102a, ..., etc. and the second storage devices 101b, 102b, ..., etc. may be operated in the standard mode.

[0043] In some embodiments, the first storage devices 101a, 102a, ..., etc. and the second storage devices 101b, 102b, ..., etc. may use a command / address (CA) signal commonly applied through the circuit board 50. For example, the circuit board 50 may include a plurality of signal lines to which commands are applied, and each of the first storage devices 101a, 102a, ..., etc. and the second storage devices 101b, 102b, ..., etc. may be connected to the plurality of signal lines. Therefore, the first storage devices 101a, 102a, ..., etc. and the second storage devices 101b, 102b, ..., etc. may receive commands applied to the plurality of signal lines together and may operate based on the received commands.

[0044] According to an embodiment, in this case, the connection of the CA pins of the first storage device 101a, 102a, ..., etc. to the plurality of signal lines may be different from the connection of the CA pins of the second storage device 101b, 102b, ..., etc. to the plurality of signal lines. Therefore, the command applied to the plurality of signal lines may be received by the first storage device 101a, 102a, ..., etc. and the second storage device 101b, 102b, ..., etc. in different ways. This will be described below. In this case, since the first storage device 101a, 102a, ..., etc. and the second storage device 101b, 102b, ..., etc. operate identically according to the CA signal applied in common, the first storage device 101a, 102a, ..., etc. mounted on the first surface 1000a and the second storage device 101b, 102b, ..., etc. mounted on the second surface 1000b may be operated in different modes in association with the mirroring function.

[0045] In this regard, according to the first embodiment, when the second storage devices 101b, 102b, ..., etc. operate in the standard mode and the first storage devices 101a, 102a, ..., etc. operate in the mirror mode, the first storage devices 101a, 102a, ..., etc. and the second storage devices 101b, 102b, ..., etc. may operate identically according to the commonly applied CA signal. In addition, according to the second embodiment, when the first storage devices 101a, 102a, ..., etc. operate in the standard mode and the second storage devices 101b, 102b, ..., etc. operate in the mirror mode, the first storage devices 101a, 102a, ..., etc. and the second storage devices 101b, 102b, ..., etc. may operate identically according to the commonly applied CA signal.

[0046] Whether the first storage device 101a, 102a, ..., etc. or the second storage device 101b, 102b, ..., etc. operates in a mirror mode can be determined according to the connection relationship between the pins of the storage device and the signal line to which the CA signal is applied, which will be described later. Below, the case of the storage module 1000 corresponding to the first embodiment is described.

[0047] According to an embodiment, each of the first storage devices 101a, 102a, ..., etc. may set a second value in each of the mirror information storage areas 101a_1, 102a_1, ..., etc. For example, when the first storage devices 101a, 102a, ..., etc. and the second storage devices 101b, 102b, ..., etc. operate in a standard mode according to the default values ​​set in the mirror information storage areas 101a_1, 102a_1, ..., etc. and 101b_1, 102b_1, ..., etc., the storage controller 800 (refer to Fig.14 ) can apply the first command to the plurality of signal lines. Therefore, the first storage devices 101a, 102a, ..., etc. can respectively set the second value in the mirror information storage areas 101a_1, 102a_1, ..., etc. based on the first command applied to the plurality of signal lines. In this case, the value set in each of the mirror information storage areas 101a_1, 102a_1, ..., etc. of the first storage devices 101a, 102a, ..., etc. can be changed from the default value to the second value.

[0048] Here, the first command may be a command for setting a second value corresponding to the mirror mode in the mirror information storage areas 101a_1, 102a_1, ..., etc. of the first storage devices 101a, 102a, ..., etc. According to an embodiment, the first command may be a command that swaps at least some of the values ​​of the plurality of CA bits included in the second command for setting the second value corresponding to the mirror mode. For example, when the first command is a command that swaps at least some of the values ​​of the plurality of CA bits included in the second command, the first command / address bit of the first command may have the same value as the second command / address bit of the second command, and the second command / address bit of the first command may have the same value as the first command / address bit of the second command. In an embodiment, at least one of the plurality of command / address bits in the first command is swapped with at least one of the plurality of command / address bits in the second command.

[0049] In an embodiment, when the first command is applied to the plurality of signal lines, each of the first storage devices 101a, 102a, ..., etc. may receive a second command according to a connection relationship between the CA pin and the plurality of signal lines. Each of the first storage devices 101a, 102a, ..., etc. operating in the standard mode according to the default value may set a second value in the mirror information storage area 101a_1, 102a_1, ..., etc. based on the received second command.

[0050] When the second value is set in the mirror information storage area 101a_1, 102a_1, ..., etc. based on the first command, the first storage device 101a, 102a, ..., etc. can operate in the mirror mode. In this case, the second storage device 101b, 102b, ..., etc. can maintain the standard mode. Therefore, according to the first embodiment, the first storage device 101a, 102a, ..., etc. and the second storage device 101b, 102b, ..., etc. can operate identically according to the CA signal applied in common.

[0051] According to the above-mentioned embodiments of the present disclosure, even if the storage devices 101a, 102a, ..., etc. and 101b, 102b, ..., etc. do not have mirror pins, the mirror function can be implemented. That is, in order to transmit the second command to the first storage device 101a, 102a, ..., etc. currently operating in the standard mode and the first storage device 101a, 102a, ..., etc. that can be operated in the mirror mode among the second storage device 101b, 102b, ..., etc., the storage controller 800 can apply the first command to the plurality of signal lines. When the first command in which at least some values ​​of the plurality of CA bits included in the second command are exchanged is applied to the plurality of signal lines, the first storage device 101a, 102a, ..., etc. currently operating in the standard mode receives the second command through the plurality of signal lines, and the first storage device 101a, 102a, ..., etc. that receives the second command can set the second value corresponding to the mirror mode in the mirror information storage area 101a_1, 102a_1, ..., etc., and then can operate in the mirror mode.

[0052] In the above description, each of the first storage device 101a, 102a, ..., etc. and the second storage device 101b, 102b, ..., etc. can be a storage device based on DRAM or synchronous DRAM (SDRAM). In this case, according to an embodiment, each of the first storage device 101a, 102a, ..., etc. and the second storage device 101b, 102b, ..., etc. may include various types of storage elements, such as SDRAM storage elements, NAND flash memory elements, NOR flash memory elements, resistive RAM (RRAM) elements, ferroelectric RAM (FRAM) elements, phase change RAM (PRAM) elements, magnetoresistive RAM (MRAM) elements, or one-time programmable (OTP) storage elements. In addition, according to an embodiment, the types of the first storage device 101a, 102a, ..., etc. and the second storage device 101b, 102b, ..., etc. may be the same as each other or may be different from each other.

[0053] Figure 2A and Figure 2B An example arrangement of pins of a memory device according to an embodiment of the present disclosure is shown.

[0054] Figure 2A and Figure 2B An example of a pin arrangement of the memory device 10 is shown. Figure 2A and Figure 2B , the memory device 10 may include pins arranged in a matrix having 13 rows A, B, C, D, E, F, G, H, J, K, L, M, and N and 6 columns. In an embodiment, the six (6) columns may be divided into a first column group including the first to third columns and a second column group including the seventh to ninth columns. Unfilled fourth to sixth columns may exist between the first and second column groups.

[0055] The pins can be electrically populated with power / ground, command / address, clock signals, control signals, and data input / output (I / O) signals. For example, the pin MIR in the second column of the G row can indicate a mirror function, the pin CS_n in the third column of the H row can correspond to a chip select signal, the pin CA2 in the third column of the K row can correspond to the CA bit CA2, and the pin CA3 in the seventh column of the K row can correspond to the CA bit CA3.

[0056] When the MIR pin of the second column of the G row is connected to the power supply voltage VDDQ, the memory device 10 can operate in the mirror mode; when the MIR pin of the second column of the G row is connected to the ground voltage VSS, the memory device 10 can operate in the standard mode.

[0057] However, as described above, even without a separate pin for the mirror function, each of the memory devices 101a, 102a, ..., etc. and 101b, 102b, ..., etc. according to the embodiment of the present disclosure can implement the mirror function. Therefore, when the memory device 10 is implemented according to the embodiment of the present disclosure, the MIR pin is no longer necessary. In this case, the existing MIR pin can be used for any other purpose. For example, the integrity of the signal can be improved by filling the pin of the second column of the G row with an I / O signal, a power signal, or a ground signal. However, the present disclosure is not limited to this.

[0058] In some embodiments, the CA pin 11 corresponding to the CA bit may have a structure in which the even-numbered CA pins CA0, CA2, CA4, CA6, CA8, CA10, and CA12 are physically symmetrical with the odd-numbered CA pins CA1, CA3, CA5, CA7, CA9, CA11, and CA13. Embodiments of the present disclosure may also include the above structure. However, the present disclosure is not limited thereto.

[0059] Figure 3A and Figure 3B FIG. 4 shows the positional relationship of CA pins of memory devices facing away from each other according to an embodiment of the present disclosure. Figure 3A A vertical cross-sectional view of a memory module 1000 according to an embodiment of the present disclosure is shown. Figure 3B The positional relationship of the CA pins of the first storage device 101a and the second storage device 101b facing away from each other is shown.

[0060] For example, refer to Figure 3A and Figure 3B When the first storage device 101a and the second storage device 101b are observed along the X direction, the second storage device 101b may have Figure 3B The arrangement of the balls shown at the top, and the first storage device 101a may have Figure 3B The arrangement of the balls shown at the bottom.

[0061] In some embodiments, since the first storage device 101a and the second storage device 101b have the same pin arrangement and are mounted on the circuit board 50 in a manner of facing each other, when the first storage device 101a and the second storage device 101b are viewed along the X direction, the CA pin of the first storage device 101a and the CA pin of the second storage device 101b may have a left-right flipped position relationship. Figure 3B, the even CA pins CA0, CA2, CA4, CA6, CA8, CA10 and CA12 of the second storage device 101b can respectively face the odd CA pins CA1, CA3, CA5, CA7, CA9, CA11 and CA13 of the first storage device 101a; the odd CA pins CA1, CA3, CA5, CA7, CA9, CA11 and CA13 of the second storage device 101b can respectively face the even CA pins CA0, CA2, CA4, CA6, CA8, CA10 and CA12 of the first storage device 101a.

[0062] In this case, according to an embodiment, the CA pins facing each other may be electrically connected to each other through through holes formed in the circuit board 50. That is, the even-numbered CA pins CA0, CA2, CA4, CA6, CA8, CA10, and CA12 of the second storage device 101b are respectively connected to the odd-numbered CA pins CA1, CA3, CA5, CA7, CA9, CA11, and CA13 of the first storage device 101a; and the odd-numbered CA pins CA1, CA3, CA5, CA7, CA9, CA11, and CA13 of the second storage device 101b are respectively connected to the even-numbered CA pins CA0, CA2, CA4, CA6, CA8, CA10, and CA12 of the first storage device 101a.

[0063] In this case, the CA signal commonly applied through the circuit board 50 may be applied to the memory devices (the first memory device 101a and the second memory device 101b) through different CA pins of the two memory devices (the first memory device 101a and the second memory device 101b) facing away from each other. Therefore, one of the two memory devices (the first memory device 101a and the second memory device 101b) (facing away from each other) may be operated in a mirror mode so that the two memory devices (the first memory device 101a and the second memory device 101b) facing away from each other operate identically according to the CA signal commonly applied through the circuit board 50.

[0064] For example, the first storage device 101a may be operated in a mirror mode, and the second storage device 101b may be operated in a standard mode. In this case, when the CA0 to CA13 signals are commonly applied through the circuit board 50, the second storage device 101b may use the CA0 to CA13 signals applied to the CA0 to CA13 pins without modification. In some embodiments, the first storage device 101a may internally convert and use the CA signals applied to the CA1, CA3, CA5, CA7, CA9, CA11, and CA13 pins as CA0, CA2, CA4, CA6, CA8, CA10, and CA12 signals, and may internally convert and use the CA signals applied to the CA0, CA2, CA4, CA6, CA8, CA10, and CA12 pins as CA1, CA3, CA5, CA7, CA9, CA11, and CA13 signals. Therefore, the first storage device 101a and the second storage device 101b may operate identically according to the CA signals commonly applied through the circuit board 50.

[0065] The above description is made by taking the first storage device 101a and the second storage device 101b facing away from each other as an example, but the above description is equally applicable to the remaining first storage devices 102a, ..., etc. and the remaining second storage devices 102b, ..., etc. facing away from each other.

[0066] Figure 4 A vertical cross-sectional view of a memory module according to an embodiment of the present disclosure is shown. Figure 4 The storage module 1000-1 may be Figure 1A , Figure 1B and Figure 3A The embodiment of the storage module 1000 is shown in FIG. 1 , but the present disclosure is not limited thereto.

[0067] According to an embodiment, each of the first storage device 101a and the second storage device 101b may include a plurality of CA pins corresponding to the plurality of CA bits, respectively. For example, when the plurality of CA bits include 14 bits CA0 to CA13, each of the first storage device 101a and the second storage device 101b may include 14 CA pins CA0 to CA13. However, the present disclosure is not limited thereto.

[0068] exist Figure 4 In the example, multiple CA pins can be represented by two CA pins CA[x]_p and CA[x+1]_p. Figure 4, each of the first memory device 101a and the second memory device 101b may include a first CA pin CA[x]_p corresponding to the first CA bit CA[x] and a second CA pin CA[x+1]_p corresponding to the second CA bit CA[x+1]. In this case, "x" may have values ​​of 0, 2, 4, 6, 8, 10, and 12.

[0069] According to an embodiment, the first CA pin CA[x]_p of the second storage device 101b can be connected to the second CA pin CA[x+1]_p of the first storage device 101a through the first through hole 51-1 of the circuit board 50, and the second CA pin CA[x+1]_p of the second storage device 101b can be connected to the first CA pin CA[x]_p of the first storage device 101a through the second through hole 51-2 of the circuit board 50.

[0070] In an embodiment, the first through hole 51-1 and the second through hole 51-2 may be through holes penetrating opposite surfaces of the circuit board 50. In this case, the length between the CA pin of the first memory device 101a and the CA pin of the second memory device 101b connected to each other through the through holes 51-1 and 51-2 may be minimized. This may mean that the stub is reduced. Therefore, the signal integrity of the CA signal may be improved.

[0071] In some embodiments, the circuit board 50 may include a plurality of CA signal lines corresponding to the plurality of CA bits, respectively. A plurality of CA signals may be applied to the first storage device 101a and the second storage device 101b through the plurality of signal lines. Each CA signal may include the value of the corresponding CA bit. For example, when the plurality of CA bits constituting the command include 14 bits from CA0 to CA13, a CA0 signal including the value of the CA0 bit may be applied to the first storage device 101a and the second storage device 101b through the CA0 signal line. In addition, a CA1 signal including the value of the CA1 bit may be applied to the first storage device 101a and the second storage device 101b through the CA1 signal line. The above description will also apply to the remaining CA signals.

[0072] exist Figure 4 In FIG. 5 , a plurality of signal lines can be represented by two CA signal lines 53 - 1 and 53 - 2 . Figure 4 The circuit board 50 may include a first signal line 53-1 and a second signal line 53-2, a first CA signal CA[x]_s including a value of a first CA bit CA[x] is applied to the first signal line 53-1, and a second CA signal CA[x+1]_s including a value of a second CA bit CA[x+1] is applied to the second signal line 53-2.

[0073] In this case, according to an embodiment, the first signal line 53 - 1 may be connected to the first via 51 - 1 , and the second signal line 53 - 2 may be connected to the second via 51 - 2 .

[0074] In this way, the first CA signal CA[x]_s may be applied to the first CA pin CA[x]_p of the second storage device 101b and the second CA pin CA[x+1]_p of the first storage device 101a through the first signal line 53-1 and the first through hole 51-1, respectively. In addition, the second CA signal CA[x+1]_s may be applied to the second CA pin CA[x+1]_p of the second storage device 101b and the first CA pin CA[x]_p of the first storage device 101a through the second signal line 53-2 and the second through hole 51-2, respectively.

[0075] That is, the second memory device 101b can receive the value of the first CA bit CA[x] through the first CA pin CA[x]_p, and can receive the value of the second CA bit CA[x+1] through the second CA pin CA[x+1]_p. Conversely, the first memory device 101a can receive the value of the second CA bit CA[x+1] through the first CA pin CA[x]_p, and can receive the value of the first CA bit CA[x] through the second CA pin CA[x+1]_p.

[0076] In this case, in order to make the first storage device 101a and the second storage device 101b operate identically according to the commonly applied CA signal, the second storage device 101b may operate in the standard mode, and the first storage device 101a may operate in the mirror mode. That is, Figure 4 It can correspond to the first embodiment described above.

[0077] However, as described above, since the default values ​​set in the mirror information storage areas 101a_1 and 101b_1 of the first storage device 101a and the second storage device 101b correspond to the standard mode, in the initial state of the storage module 1000-1, the first storage device 101a and the second storage device 101b both operate in the standard mode. Therefore, it may be necessary to set a second value corresponding to the mirror mode in the mirror information storage area 101a_1 of the first storage device 101a so that the first storage device 101a operates in the mirror mode.

[0078] To this end, the first memory device 101a may set the second value in the mirror information storage area 101a_1 based on the first command. The first command may include a plurality of CA signals and may be applied from the external memory controller 800 to the CA signal lines 53-1 and 53-2.

[0079] According to an embodiment, the first command may be a command that swaps at least some values ​​of the plurality of CA bits included in the second command. For example, the second command may be a command that, when received by a memory device operating in standard mode, causes a second value to be set in a mirror information storage area of ​​the corresponding memory device.

[0080] In some embodiments, the second storage device 101b may receive the value of the first CA bit CA[x] through the first CA pin CA[x]_p, and may receive the value of the second CA bit CA[x+1] through the second CA pin CA[x+1]_p. Therefore, when the second command is applied to the CA signal lines 53-1 and 53-2, the second storage device 101b may receive the second command without modification. In this case, the second storage device 101b operating in the standard mode may set the second value in the mirror information storage area 101b_1 based on the received second command. Of course, according to the first embodiment, since the second storage device 101b may operate in the standard mode, the second command does not need to be actually applied to the second storage device 101b. As an example, a chip select signal may be used to select a storage device to which the second command is to be applied.

[0081] In contrast, the first storage device 101a may receive the value of the second CA bit CA[x+1] through the first CA pin CA[x]_p, and may receive the value of the first CA bit CA[x] through the second CA pin CA[x+1]_p. Therefore, when the second command is applied to the CA signal lines 53-1 and 53-2, the first storage device 101a may not receive the unmodified second command. In this case, the first storage device 101a operating in the standard mode may not set the second value in the mirror information storage area 101a_1 based on the second command applied to the CA signal lines 53-1 and 53-2.

[0082] Therefore, according to an embodiment of the present disclosure, in order to set a second value in the mirror information storage area 101a_1 of the first storage device 101a, a first command may be applied to the CA signal lines 53-1 and 53-2. In this case, the first command may be a command in which the values ​​of the first CA bit CA[x] and the second CA bit CA[x+1] of the second command are exchanged. In this case, the first CA bit CA[x] of the first command may have the same value as the second CA bit CA[x+1] of the second command, and the second CA bit CA[x+1] of the first command may have the same value as the first CA bit CA[x] of the second command. That is, when the second command is applied to the CA signal lines 53-1 and 53-2, the first storage device 101a may be able to receive the second command. Therefore, the first storage device 101a operating in the standard mode may be able to set the second value in the mirror information storage area 101a_1 based on the first command applied to the CA signal lines 53-1 and 53-2.

[0083] In some embodiments, since the first storage device 101a and the second storage device 101b are electrically connected to each other through the through holes 51-1 and 51-2, the first command can be applied to the second storage device 101b as well as the first storage device 101a. In this case, since the first command is a command for setting a second value in the mirror information storage areas 101a_1, 102a_1, ..., etc. of the first storage devices 101a, 102a, ..., etc., the first command applied to the second storage device 101b can be ignored.

[0084] For this purpose, the chip select signal can be used. Figure 4 , the first memory device 101a may include a chip selection pin CS1_p to which a first chip selection signal CS1_s is applied, and the second memory device 101b may include a chip selection pin CS0_p to which a second chip selection signal CS0_s is applied. Each of the first memory device 101a and the second memory device 101b may effectively receive or ignore the applied CA signal according to the value of the chip selection signal applied to the corresponding chip selection pin.

[0085] For example, when the chip selection signal applied to the corresponding chip selection pin has a low value, each of the first memory device 101a and the second memory device 101b can effectively receive the applied CA signal. In addition, when the chip selection signal applied to the corresponding chip selection pin has a high value, each of the first memory device 101a and the second memory device 101b can ignore the applied CA signal.

[0086] In this case, when the first command is applied to the CA signal lines 53-1 and 53-2, the first chip select signal CS1_s may have a low value and the second chip select signal CS0_s may have a high value. Therefore, the first command may be effectively applied only to the first memory device 101a.

[0087] In some embodiments, when the second value is set in the mirror information storage area 101a_1, based on the first command, the first storage device 101a can operate in the mirror mode. In this case, since the second storage device 101b maintains the standard mode, the first storage device 101a and the second storage device 101b can operate identically according to the CA signal applied in common.

[0088] For example, after the second value is set in the mirror information storage area 101a_1, a new command, such as a third command, may be applied to the CA signal lines 53-1 and 53-2. In this case, the second storage device 101b may receive the third command without modification. Therefore, the second storage device 101b operating in the standard mode may perform an operation corresponding to the third command while keeping the value of the CA bit included in the third command unchanged. In some embodiments, when the third command is applied to the CA signal lines 53-1 and 53-2, the first storage device 101a may receive a fourth command in which at least some of the CA bits included in the third command are swapped. However, since the first storage device 101a operates in the mirror mode, the first storage device 101a may perform an operation corresponding to the third command by swapping the values ​​of at least some of the CA bits included in the fourth command received thereby.

[0089] The above description is made by taking the first storage device 101a and the second storage device 101b as an example. The present disclosure is not limited thereto. The application described above is not limited to the first storage device 101a and the second storage device 101b. Figure 4 , the first storage device 102a and the second storage device 102b may also have the same structure and wiring as the first storage device 101a and the second storage device 101b. This may also be applied to the remaining first storage devices and the remaining second storage devices that are present in the storage module 1000-1 but not shown and face each other. Therefore, the remaining first storage devices 102a, ..., etc. may also operate in the same manner as the first storage device 101a, and the remaining second storage devices 102b, ..., etc. may also operate in the same manner as the second storage device 101b.

[0090] According to an embodiment, the operation of setting the second value in the mirror information storage areas 101a_1, 102a_1, ..., etc. of the first storage devices 101a, 102a, ..., etc. may be performed in an initial step of a module post-packaging repair process of the storage module 1000, but the present disclosure is not limited thereto.

[0091] Figure 5 The first command according to an embodiment of the present disclosure is shown. According to an embodiment, the command may include 14 CA bits from CA0 to CA13. In this case, the operation to be performed according to the command may be determined based on a command truth table defining the meaning of the CA bits.

[0092] For example, you can Figure 5 A command for setting a value (e.g., a second value) corresponding to the mirror mode in the mirror information storage areas 101a_1, 102a_1, ..., etc., 101b_1, 102b_1, ..., etc. is defined as the second command shown in FIG. 1 . Among them, bits CA0 to CA4 may indicate the kind of operation, bits CA5 to CA9 may indicate an address, and bits CA13 may indicate a value to be set in the mirror information storage areas 101a_1, 102a_1, ..., etc., 101b_1, 102b_1, ..., etc.

[0093] That is, according to the second command, a value "1" corresponding to the mirror mode may be set in the mirror information storage areas 101a_1, 102a_1, ..., etc., 101b_1, 102b_1, ..., etc. at address "10010". In the above embodiment, the default value corresponding to the standard mode may be "0".

[0094] Also refer to Figure 4 and Figure 5 , each of the second storage devices 101b, 102b, ..., etc. can receive the value of the first CA bit CA[x] through the first CA pin CA[x]_p, and can receive the value of the second CA bit CA[x+1] through the second CA pin CA[x+1]_p. Therefore, the second command "01101100101001" is applied to the CA signal lines 53-1 and 53-2, and the second storage devices 101b, 102b, ..., etc. operating in the standard mode can receive the second command "01101100101001" without modification, and therefore, the value "1" corresponding to the mirror mode can be set in the mirror information storage area 101b_1, 102b_1, ..., etc.

[0095] However, each of the first storage devices 101a, 102a, ..., etc. can receive the value of the second CA bit CA[x+1] through the first CA pin CA[x]_p, and can receive the value of the first CA bit CA[x] through the second CA pin CA[x+1]_p. Therefore, by applying the second command "01101100101001" to the CA signal lines 53-1, 53-2, the first storage devices 101a, 102a, ..., etc. operating in the standard mode may receive an erroneous command "10011100010110" different from the second command "01101100101001", and fail to set the value "1" corresponding to the mirror mode in the mirror information storage areas 101a_1, 102a_1, ..., etc.

[0096] Therefore, according to an embodiment of the present disclosure, a command (ie, a first command) in which at least some values ​​of a plurality of CA bits included in a second command are swapped may be applied to the first memory devices 101a, 102a, . . . , etc.

[0097] For example, refer to Figure 5 , the first command may be a command to exchange the value of the even CA bits CA0 / CA2 / CA4 / CA6 / CA8 / CA10 / CA12 of the second command with the value of the odd CA bits CA1 / CA3 / CA5 / CA7 / CA9 / CA11 / CA13 which are adjacent to the even CA bits CA0 / CA2 / CA4 / CA6 / CA8 / CA10 / CA12 and higher than the even CA bits CA0 / CA2 / CA4 / CA6 / CA8 / CA10 / CA12. In some embodiments, the first command "10011100010110" can be implemented by the following swapping of the CA bit values ​​of the second command: the value (0) of the CA0 bit is swapped with the value (1) of the CA1 bit, the value (1) of the CA2 bit is swapped with the value (0) of the CA3 bit, the value (1) of the CA4 bit is swapped with the value (1) of the CA5 bit, the value (0) of the CA6 bit is swapped with the value (0) of the CA7 bit, the value (1) of the CA8 bit is swapped with the value (0) of the CA9 bit, the value (1) of the CA10 bit is swapped with the value (0) of the CA11 bit, and the value (0) of the CA12 bit is swapped with the value (1) of the CA13 bit.

[0098] In this case, when the first command “10011100010110” is applied to the CA signal lines 53-1 and 53-2, the first storage devices 101a, 102a, ..., etc. can receive the same value as the CA0 to CA13 bits of the second command, i.e., “01101100101001”, and therefore, in the first storage devices 101a, 102a, ..., etc. operating in the standard mode, a value “1” corresponding to the mirror mode can be set in the mirror information storage areas 101a_1, 102a_1, ..., etc.

[0099] According to an embodiment, the first command may include a chip select bit CS1_n. In this case, the chip select bit CS1_n may have a low value. This may mean that the first command is effectively applied to the first memory device 101a, 102a, ..., etc. When the first command is applied to the first memory device 101a, 102a, ..., etc., a high value may be applied to the chip select pin of the second memory device 101b, 102b, ..., etc. Therefore, the first command applied to the second memory device 101b, 102b, ..., etc. may be ignored.

[0100] In some embodiments, Figure 5 , the case where the first command and the second command are "1-cycle commands" is shown as an example, but the present disclosure is not limited thereto. According to an embodiment, the first command and the second command may be implemented by using a 2-cycle command or a command having three or more cycles. For example, the first command and the second command may be implemented by using a mode register write (MRW) command, but the present disclosure is not limited thereto.

[0101] Figure 6 A vertical cross-sectional view of a memory module according to an embodiment of the present disclosure is shown. Figure 6 The storage module 1000-2 may be Figure 1A , Figure 1B and Figure 3A The embodiment of the storage module 1000 is shown in FIG. 1 , but the present disclosure is not limited thereto.

[0102] Figure 6 The storage module 1000-2 can be used with Figure 4 1 is the same as the memory module 1000-1 of FIG. 1 except that the first signal line 53-1 for applying the first CA signal CA[x]_s is connected to the second through hole 51-2 and the second signal line 53-2 for applying the second CA signal CA[x+1]_s is connected to the first through hole 51-1. Therefore, except for the description related to the above differences, reference is made to FIG. Figure 4 and Figure 5 The above description can be applied equally to Figure 6 The differences are described below.

[0103] refer to Figure 6 , the first CA signal CA[x]_s may be applied to the second CA pin CA[x+1]_p of the second storage device 101b and the first CA pin CA[x]_p of the first storage device 101a through the first signal line 53-1 and the second through hole 51-2, respectively. In addition, the second CA signal CA[x+1]_s may be applied to the first CA pin CA[x]_p of the second storage device 101b and the second CA pin CA[x+1]_p of the first storage device 101a, respectively, through the second signal line 53-2 and the first through hole 51-1.

[0104] That is, the first memory device 101a can receive the value of the first CA bit CA[x] through the first CA pin CA[x]_p, and can receive the value of the second CA bit CA[x+1] through the second CA pin CA[x+1]_p. Conversely, the second memory device 101b can receive the value of the second CA bit CA[x+1] through the first CA pin CA[x]_p, and can receive the value of the first CA bit CA[x] through the second CA pin CA[x+1]_p.

[0105] In this case, in order to make the first storage device 101a and the second storage device 101b operate identically according to the commonly applied CA signal, the first storage device 101a may operate in the standard mode, and the second storage device 101b may operate in the mirror mode. That is, Figure 6 It can correspond to the above-mentioned second embodiment.

[0106] In this case, in order to set a second value corresponding to the mirror mode in the mirror information storage area 101b_1 of the second storage device 101b operating in the standard mode based on the default value, the above-mentioned first command can be applied to the CA signal lines 53-1 and 53-2, and the second storage device 101b can receive the second command. That is, since the second value is set in the mirror information storage area 101b_1, the second storage device 101b can operate in the mirror mode. In some embodiments, since the first storage device 101a maintains the standard mode based on the default value, the first storage device 101a and the second storage device 101b can operate identically according to the CA signal applied in common.

[0107] Figure 7 A memory device according to an embodiment of the present disclosure is shown. Figure 7 The memory device 100 may correspond to one of the above-described memory devices 101a, 102a, . . . , etc. and 101b, 102b, . . . , etc., but the present disclosure is not limited thereto.

[0108] refer to Figure 7, the memory device 100 may include a control logic 410, an address register 420, a memory body control circuit 430, a row address multiplexer 440, a column address latch 450, a row decoder 460, a column decoder 470, a memory cell array 300, a sense amplifier unit 485, an input / output gating circuit 490, a data input / output buffer 520, an ECC engine 550 and a refresh control circuit 500.

[0109] The control logic 410 may control the operation of the memory device 100. For example, the control logic 410 may generate a control signal so that the memory device 100 performs a write operation or a read operation.

[0110] The control logic 410 may include a command decoder 411 that decodes a command CMD. For example, the command decoder 411 may decode a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc., and may generate a control signal corresponding to the command CMD.

[0111] The control logic 410 may include a mirror information storage area 412 that stores values ​​related to the mirror function. The mirror information storage area 412 may include a mode register and a non-volatile storage area. The mirror information storage area 412 may correspond to the above-mentioned mirror information storage areas 101a_1, 102a_1, ..., etc. and 101b_1, 102b_1, ..., etc., but the present disclosure is not limited thereto. Figure 7 An example is shown in which the mirror information storage area 412 is included in the control logic 410 , but the present disclosure is not limited thereto. For example, the mirror information storage area 412 may be placed outside the control logic 410 .

[0112] The memory cell array 300 may include a plurality of bank arrays 300_1 to 300_n. Each of the bank arrays 300_1 to 300_n may include a word line WL, a bit line BL, and a memory cell MC formed at a crossing of the word line WL and the bit line BL.

[0113] The row decoder 460 may include row decoders 460_1 to 460_n respectively connected to the memory arrays 300_1 to 300_n, the column decoder 470 may include column decoders 470_1 to 470_n respectively connected to the memory arrays 300_1 to 300_n, and the read amplifier unit 485 may include read amplifiers 4851 to 485n respectively connected to the memory arrays 300_1 to 300_n.

[0114] The bank arrays 300_1 to 300_n, the row decoders 460_1 to 460_n, the column decoders 470_1 to 470_n, and the sense amplifiers 4851 to 485n may constitute first to nth memory banks.

[0115] The address register 420 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 800 or a register clock driver (RCD) 1200 (refer to Fig.15 The address register 420 may provide the received bank address BANK_ADDR to the bank control circuit 430 , may provide the received row address ROW_ADDR to the row address multiplexer 440 , and may provide the received column address COL_ADDR to the column address latch 450 .

[0116] The address register 420 may include a command / address exchange circuit 421. The command / address exchange circuit 421 may exchange at least some values ​​of CA bits included in the received address ADDR based on the value set in the mirror information storage area 412.

[0117] For example, when a default value (e.g., "0") corresponding to the standard mode is set in the mirror information storage area 412, the command / address exchange circuit 421 may operate in the standard mode. In this case, the command / address exchange circuit 421 may maintain and output the received address ADDR without modification. In addition, when a second value (e.g., "1") corresponding to the mirror mode is set in the mirror information storage area 412, the command / address exchange circuit 421 may operate in the mirror mode. In this case, the command / address exchange circuit 421 may exchange and output at least some values ​​of the CA bits contained in the received address ADDR.

[0118] According to an embodiment, the command / address exchange circuit 421 may operate in the standard mode or the mirror mode based on the value set in the mode register of the mirror information storage area 412. Alternatively, according to an embodiment, the command / address exchange circuit 421 may operate in the standard mode or the mirror mode based on the value set in the non-volatile storage area of ​​the mirror information storage area 412.

[0119] Figure 7 An example is shown in which the command / address exchange circuit 421 is included in the address register 420 , but the present disclosure is not limited thereto. For example, the command / address exchange circuit 421 may be placed outside the address register 420 .

[0120] The bank control circuit 430 may generate a bank control signal in response to the bank address BANK_ADDR. Row decoders corresponding to the bank address BANK_ADDR among the row decoders 460_1 to 460_n and column decoders corresponding to the bank address BANK_ADDR among the column decoders 470_1 to 470_n may be activated in response to the bank control signal.

[0121] The row address multiplexer 440 may receive a row address ROW_ADDR from the address register 420 and may receive a refresh row address REF_ADDR from the refresh control circuit 500. The row address multiplexer 440 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 440 may be applied to each of the row decoders 460_1 to 460_n.

[0122] A row decoder activated by the bank control circuit 430 among the row decoders 460_1 to 460_n may decode a row address RA output from the row address multiplexer 440 and may activate a word line corresponding to the row address RA.

[0123] The column address latch 450 may receive the column address COL_ADDR from the address register 420 and may temporarily store the received column address COL_ADDR. In addition, in the burst mode, the column address latch 450 may gradually (or sequentially) increase the received column address COL_ADDR. The column address latch 450 may apply the temporarily stored column address COL_ADDR or the sequentially increased column address COL_ADDR to each of the column decoders 470_1 to 470_n.

[0124] A column decoder activated by the bank control circuit 430 among the column decoders 470_1 to 470 — n may activate a sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the input / output gating circuit 490 .

[0125] The input / output gating circuit 490 may include the following circuits and a circuit for gating input / output data: input data mask logic, a read data latch for storing data output from multiple memory arrays 300_1 to 300_n, and a write driver for writing data to the multiple memory arrays 300_1 to 300_n.

[0126] Data read from one bank array among the plurality of bank arrays 300_1 to 300 — n may be sensed by a sense amplifier corresponding to the one bank array and may be latched by a read data latch.

[0127] The data stored in the read data latch may be provided to the memory controller 800 through the data input / output buffer 520 after the ECC engine 550 performs ECC decoding on the stored data. Data to be written to one of the plurality of memory bank arrays 300_1 to 300_n may be provided to the data input / output buffer 520 from the memory controller 800.

[0128] The data DQ provided to the data input / output buffer 520 may be provided to the input / output gating circuit 490 after the ECC engine 550 performs ECC encoding on the data DQ.

[0129] In a normal mode write operation, the data input / output buffer 520 may provide a data signal DQ to the ECC engine 550. In a normal mode read operation, the data input / output buffer 520 may receive the data signal DQ from the ECC engine 550 and may provide the data signal DQ and a data strobe signal DQS to the memory controller 800.

[0130] Fig. 8A FIG. 4 shows a command / address exchange circuit 421 according to an embodiment of the present disclosure. Fig. 8A , the command / address exchange circuit 421 may include a plurality of unit command / address exchange circuits 421 - 1 to 421 - 13 .

[0131] Each of the plurality of unit command / address exchange circuits 421-1 to 421-13 may receive an even CA bit CA[x] and an odd CA bit CA[x+1] that is adjacent to the CA bit CA[x] and higher than the CA bit CA[x], and may maintain or exchange the value of the received CA bit based on the value "m" set in the mirror information storage area 412. Therefore, each of the plurality of unit command / address exchange circuits 421-1 to 421-13 may output internal CA bits ICA[x] and ICA[x+1]. In this case, "x" may have values ​​of 0, 2, 4, 6, 8, 10, and 12.

[0132] For example, when the value "m" set in the mirror information storage area 412 is the default value, the unit command / address exchange circuit 421-1 can operate in the standard mode and can output the internal CA bits ICA0 and ICA1 while maintaining the values ​​of the received CA bits CA0 and CA1.

[0133] In addition, when the value "m" set in the mirror information storage area 412 is the second value, the unit command / address exchange circuit 421-1 can operate in the mirror mode and can exchange the values ​​of the received CA bits CA0 and CA1. Therefore, the unit command / address exchange circuit 421-1 can output the exchanged CA bits CA0 and CA1 as internal CA bits ICA0 and ICA1. The above description can be applied to the remaining unit command / address exchange circuits 421-2 to 421-13 in the same manner.

[0134] Figure 8B and Figure 8C Shows Fig. 8A An example of a unit command / address exchange circuit. Figure 8B and Figure 8C The unit command / address exchange circuit 421 - 1 is shown as an example in FIG. 4 , but the remaining unit command / address exchange circuits 421 - 2 to 421 - 13 may be substantially the same as the unit command / address exchange circuit 421 - 1 .

[0135] Figure 8B The operation of the unit command / address exchange circuit 421-1 is shown when the value "m" set in the mirror information storage area 412 is at a high level "H." In this case, the high level "H" may refer to a value corresponding to the mirror mode.

[0136] refer to Figure 8B , the unit command / address exchange circuit 421 - 1 may include PMOS transistors 41 and 42 and NMOS transistors 43 and 44 .

[0137] The PMOS transistor 41 may include a first electrode connected to the first node N11 and receiving the value of the bit CA0, a gate electrode connected to the third node N13 and receiving the value "m" set in the mirror information storage area 412, and a second electrode connected to the fourth node N14 and outputting the internal CA bit ICA0. The PMOS transistor 42 may include a first electrode connected to the second node N12 and receiving the value of the bit CA1, a gate electrode connected to the third node N13 and receiving the value "m" set in the mirror information storage area 412, and a second electrode connected to the fifth node N15 and outputting the internal CA bit ICA1.

[0138] The NMOS transistor 43 may include a first electrode connected to the second node N12 and receiving the value of the bit CA1, a gate electrode connected to the third node N13 and receiving the value "m" set in the mirror information storage area 412, and a second electrode connected to the fourth node N14. The NMOS transistor 44 may include a first electrode connected to the first node N11 and receiving the value of the bit CA0, a gate electrode connected to the third node N13 and receiving the value "m" set in the mirror information storage area 412, and a second electrode connected to the fifth node N15.

[0139] When the value "m" set in the mirror information storage area 412 is a high level "H", the PMOS transistors 41 and 42 can be turned off, and the NMOS transistors 43 and 44 can be turned on. Therefore, the unit command / address exchange circuit 421-1 can output the value of the CA1 bit as the internal CA bit ICA0, and can output the value of the CA0 bit as the internal CA bit ICA1. That is, in this case, the memory device 100 can operate in the mirror mode.

[0140] Figure 8C The operation of the unit command / address exchange circuit 421-1 is shown when the value "m" set in the mirror information storage area 412 is at a low level "L." In this case, the low level "L" may refer to a value corresponding to the standard mode.

[0141] refer to Figure 8C , when the value "m" set in the mirror information storage area 412 is at a low level "L", the PMOS transistors 41 and 42 may be turned on, and the NMOS transistors 43 and 44 may be turned off. Therefore, the unit command / address exchange circuit 421-1 may output the value of the CA0 bit as the internal CA bit ICA0, and may output the value of the CA1 bit as the internal CA bit ICA1. That is, in this case, the memory device 100 may operate in the standard mode.

[0142] Fig. 9 A partial configuration of a memory device according to an embodiment of the present disclosure is shown. Fig. 9 The memory device 100A may correspond to one of the above-described memory devices 101a, 102a, . . . , etc. and 101b, 102b, . . . , etc., but the present disclosure is not limited thereto.

[0143] refer to Fig. 9 , the storage device 100A may include a mirror information storage area 412 and a command / address exchange circuit 421 .

[0144] The command / address exchange circuit 421 may exchange at least some values ​​of the applied CA bits based on the value set in the mode register 71. For example, when a default value corresponding to the standard mode is set in the mode register 71, the command / address exchange circuit 421 may maintain the value of the applied CA bits. Thus, the memory device 100A may operate in the standard mode. In some embodiments, when a second value corresponding to the mirror mode is set in the mode register 71, the command / address exchange circuit 421 may exchange at least some values ​​of the applied CA bits. Thus, the memory device 100A may operate in the mirror mode.

[0145] The mirror information storage area 412 may store values ​​related to the mirror function. The mirror information storage area 412 may include a mode register 71 and a non-volatile storage area (NVM) 72.

[0146] When the memory device 100A is powered on, the nonvolatile storage area 72 can store the value set in the mode register 71. Even if the power of the memory device 100A is turned off, the value stored in the nonvolatile storage area 72 can be maintained. To this end, for example, the nonvolatile storage area 72 can be implemented with one of an antifuse array, a mask read-only memory (MROM), and an OTP memory (e.g., an OTP programmable read-only memory (PROM)). However, this is only provided as an example. According to an embodiment, the nonvolatile storage area 72 can be implemented with one of a multi-time programmable (multi-time programming (MTP) voltage) memory, an electronic fuse array, a NAND flash memory, a NOR flash memory, a magnetic random access memory (MRAM), a spin torque transfer-MRAM (STT-MRAM), a resistive random access memory (ReRAM), and a phase change random access memory (PRAM).

[0147] For example, the default value may be stored in the nonvolatile storage area 72. The default value may be pre-stored in the nonvolatile storage area 72 during the process of manufacturing the memory device 100A. When the memory device 100A is powered on in a state where the default value is stored in the nonvolatile storage area 72, the default value may be set in the mode register 71. In this case, since the command / address exchange circuit 421 maintains the value of the applied CA bit, the memory device 100A may operate in the standard mode. That is, when the memory module 1000 / 1000-1 / 1000-2 is initially powered on, the memory device 100A installed in the memory module 1000 / 1000-1 / 1000-2 may operate in the standard mode.

[0148] In some embodiments, assuming Figure 4In the embodiment, when the memory device 100A is the first memory device 101a / 102a / etc., the memory device 100A operating in the standard mode may set a second value corresponding to the mirror mode in the mode register 71 based on the first command applied to the plurality of CA signal lines. In this case, since the command / address exchange circuit 421 exchanges at least some values ​​of the applied CA bits, the memory device 100A may operate in the mirror mode.

[0149] According to an embodiment, in response to setting the second value in the mode register 71, the memory device 100A may change the default value stored in the nonvolatile memory area 72 to the second value. Since the second value (rather than the default value) is stored in the nonvolatile memory area 72, when the memory device 100A is powered on later, the second value may be set in the mode register 71.

[0150] According to an embodiment, the nonvolatile storage area 72 may be implemented with an OTP memory. In this case, the initial state of the OTP memory may correspond to a default value. Therefore, when the memory device 100A is powered on, a default value may be set in the mode register 71, and the memory device 100A may operate in a standard mode.

[0151] Thereafter, when the first command is applied to the plurality of CA signal lines, the memory device 100A operating in the standard mode may set the second value in the mode register 71, and may then operate in the mirror mode. In response to setting the second value in the mode register 71, the memory device 100A may perform a programming operation on the OTP memory. The state in which the programming operation has been performed on the OTP memory may correspond to the second value. Therefore, the second value may be permanently stored in the OTP memory.

[0152] According to an embodiment, the operation of storing or programming the second value set in the mode register 71 in the non-volatile storage area 72 may be performed in a test mode register set (TMRS) mode. The TMRS mode may be a test mode for testing a memory module and / or a memory device. According to an embodiment, in order to enter the test mode, a command to enter the test mode may be provided from the memory controller 800 to the memory device 100A. The memory device 100A that receives the command to enter the test mode may enter the TMRS mode.

[0153] According to an embodiment, in order to prevent the storage device 100A from accidentally entering the TMRS mode, a security key (or protection key) may be received from the storage controller 800. The storage device 100A may enter the TMRS mode only when the security key is correctly received. For example, the security key may be defined as a setting value of one or more predetermined MRW commands. According to an embodiment, the security key may be received together with a command to enter the test mode. Alternatively, according to an embodiment, the security key may be received after receiving a command to enter the test mode.

[0154] Thereafter, when the memory device 100A enters the TMRS mode, the memory controller 800 may program the second value set in the mode register 71 of the memory device 100A in the nonvolatile memory area 72. In an embodiment, the operation of programming the second value set in the mode register 71 in the nonvolatile memory area 72 may be referred to as an OTP programming operation.

[0155] Fig. 10A and Fig. 10B shows the implementation of the fuse array Fig. 9 Example of a non-volatile storage area. Fig. 10A Shown include Fig. 9 An example of a fuse circuit 200 of the nonvolatile storage area 72 is shown. Fig. 10B An example is shown in which the nonvolatile storage area 72 is implemented by using an anti-fuse cell of a fuse array. Next, the fuse circuit 200 is implemented to be included in the control logic 410.

[0156] refer to Fig. 10A , the fuse circuit 200 may include a fuse controller 210 , a fuse column decoder 220 , a fuse row decoder 230 , a fuse sensing unit 240 , and a fuse array 250 .

[0157] The fuse controller 210 may be electrically connected to the fuse column decoder 220 and the fuse row decoder 230 , and may control all operations of the fuse circuit 200 .

[0158] The fuse column decoder 220 may select a column of fuse cells in the fuse array 250. The fuse row decoder 230 may select a row of fuse cells in the fuse array 250. The fuse sensing unit 240 may sense whether a fuse cell in the fuse array 250 is programmed.

[0159] The fuse array 250 may include a plurality of fuse box lines Fuse Box Line 1 to Fuse Box Line n. Each of the plurality of fuse box lines Fuse Box Line 1 to Fuse Box Line n may include a plurality of fuse cells.

[0160] In an embodiment, some of the plurality of fuse box lines Fuse Box Line 1 to Fuse Box Line n can be used for a repair operation. For example, in a post-packaging repair operation, the first fuse box line Fuse Box Line 1 can be used to program a fault address.

[0161] In an embodiment, some of the plurality of fuse box lines Fuse Box Line 1 to Fuse Box Line n may be used to store values ​​associated with the mirror function. That is, some of the plurality of fuse box lines Fuse Box Line 1 to Fuse Box Line n may be used as Fig. 9 The non-volatile storage area 72. For example, Fig. 10A As shown, the nth fuse box line Fuse Box Line n can be designated as an area including the nonvolatile storage area 72. In the OTP programming operation, the second value set in the mode register 71 can be programmed into the area corresponding to the nonvolatile storage area 72 in the nth fuse box line Fuse Box Line n.

[0162] refer to Fig. 10B , the nth fuse box line Fuse Box Line n including the nonvolatile storage area 72 may include a plurality of antifuses 251. Each of the antifuses 251 may have a unique column address and a unique row address. According to an embodiment, at least one of the plurality of antifuses 251 may be set to the nonvolatile storage area 72.

[0163] The anti-fuse 251 is a resistance element whose electrical characteristics are opposite to those of the fuse element. The anti-fuse 251 may have a high resistance value in an unprogrammed state and may have a low resistance value in a programmed state.

[0164] The antifuse 251 may be generally formed in a shape in which a dielectric is interposed between conductors. The programming operation of the antifuse 251 may be performed in the following manner: a high voltage is applied to the conductors at opposite ends of the antifuse 251 so that the dielectric between the conductors is broken down. As a result of the programming operation, the conductors at opposite ends of the antifuse 251 may be short-circuited, and therefore, the antifuse 251 may have a low resistance value.

[0165] For example, the anti-fuse 251 may be implemented with a depletion-type MOS transistor in which the source 4 is connected to the drain 5. In the initial state, since the first node 6 connected to the gate electrode 3 and the second node 7 commonly connected to the source 4 and the drain 5 are separated by a gate oxide layer, the resistance between the first node 6 and the second node 7 is quite large. This state may be defined as an unprogrammed state.

[0166] When a breakdown voltage is applied between the first node 6 and the second node 7, the gate oxide layer of the anti-fuse 251 may be broken down. When the gate oxide layer is broken down, the resistance between the first node 6 and the second node 7 decreases. This state may be defined as a programmed state.

[0167] As described above, according to the embodiment of the present disclosure, the nonvolatile storage area 72 can be implemented by using an antifuse. In an OTP programming operation, the second value set in the mode register 71 can be permanently programmed in the nonvolatile storage area 72 by breaking through the gate oxide layer of the antifuse.

[0168] In the above description, the fuse circuit 200 is included in the control logic 410. However, this is just an example, and the fuse circuit 200 may be implemented independently of the control logic 410.

[0169] Fig.11 The operation method of the storage module according to the embodiment of the present disclosure is shown. Fig.11 , the description given above will be omitted or simplified.

[0170] refer to Fig.11 , in operation S1110, the first and second memory devices 101a and 101b mounted in the memory module 1000 may operate in a standard mode.

[0171] In some embodiments, the first memory device 101a and the second memory device 101b may be mounted on opposite surfaces of the circuit board 50 to face each other, and may include a first mode register and a second mode register, respectively. In this case, each of the first memory device 101a and the second memory device 101b may operate in a standard mode or a mirror mode based on a value set in a corresponding mode register.

[0172] According to an embodiment, a default value corresponding to the standard mode may be set in the first mode register and the second mode register. Therefore, the first storage device 101a may operate in the standard mode based on the default value set in the first mode register, and the second storage device 101b may operate in the standard mode based on the default value set in the second mode register.

[0173] In operation S1120, the first storage device 101a may set a value corresponding to the mirror mode in the first mode register based on a first command applied to a plurality of signal lines connected to the first storage device 101a. In this case, the first command may be a command in which at least some values ​​of a plurality of command / address bits included in the second command are swapped. In addition, the second command may be a command for setting a value corresponding to the mirror mode in the second mode register. This has been described above, and therefore, additional description will be omitted to avoid redundancy.

[0174] In operation S1130 , the first memory device 101 a may operate in the mirroring mode based on a value corresponding to the mirroring mode set in the first mode register.

[0175] That is, CA pins of the first and second memory devices 101a and 101b mounted back to back may be electrically connected to each other through vias formed in the circuit board 50. Therefore, the CA signal may be commonly applied to the first and second memory devices 101a and 101b.

[0176] According to an embodiment, in order to use the CA signal applied together with the first storage device 101a and the second storage device 101b, the first storage device 101a can operate in the mirror mode when the second storage device 101b operates in the standard mode. To this end, a second value corresponding to the mirror mode can be set in the first mode register of the first storage device 101a.

[0177] However, since both the first storage device 101a and the second storage device 101b initially operate in the standard mode and the first storage device 101a to be operated in the mirror mode is operating in the standard mode, a command in a special format (ie, a first command) is required to set the second value in the first mode register.

[0178] When the first memory device 101a is set to operate in the mirror mode based on the first command applied to the plurality of signal lines, the first memory device 101a can operate in the mirror mode and the second memory device 101b can operate in the standard mode. Therefore, the first memory device 101a and the second memory device 101b can perform the same operation according to the CA signal applied in common.

[0179] According to an embodiment, after operation S1120, the first memory device 101a may change the default value stored in the nonvolatile memory area 72 to a value corresponding to the mirror mode and set in the first mode register. Fig. 9 , Fig. 10A and Fig. 10B This has been described, and thus, additional description will be omitted to avoid redundancy.

[0180] Fig.12 The operation method of the storage module according to the embodiment of the present disclosure is shown. Fig.12 , the description given above will be omitted or simplified.

[0181] refer to Fig.12 In operation S1210, the memory module 1000 may receive a command. For example, when operation S1130 is performed, the first memory device 101a may operate in the mirror mode, and the second memory device 101b may operate in the standard mode. In this state, a third command may be newly input into the memory module 1000.

[0182] In operation S1220, each of the first storage device 101a and the second storage device 101b may determine whether to operate in the mirror mode. For example, each of the first storage device 101a and the second storage device 101b may check the value set in the mirror information storage area (i.e., the mode register 71 and / or the non-volatile storage area 72) included therein, and may determine whether to operate in the mirror mode.

[0183] According to an embodiment, the second storage device 101b may receive the third command without modification. In this case, since the second storage device 101b operates in the standard mode, the second storage device 101b may maintain the value of the plurality of CA bits included in the third command in operation S1230. Therefore, in operation S1240, the second storage device 101b may perform an operation corresponding to the third command input to the storage module 1000.

[0184] According to an embodiment, the first storage device 101a may receive a fourth command in which the values ​​of the plurality of CA bits included in the third command are swapped. In this case, since the first storage device 101a operates in a mirroring mode, the first storage device 101a may swap the values ​​of the plurality of CA bits included in the fourth command thus received in operation S1250. Therefore, in operation S1260, the first storage device 101a may perform an operation corresponding to the third command thus received.

[0185] refer to Fig.11 and Fig.12 The description is made by taking the first storage device 101a and the second storage device 101b facing away from each other as an example, but the remaining first storage devices 102a, ..., etc. and the remaining second storage devices 102b, ..., etc. facing away from each other can also be operated in the same manner as described.

[0186] Fig.13 A partial configuration of a memory device according to an embodiment of the present disclosure is shown. Fig.13The memory device 100B may correspond to one of the above-described memory devices 101a, 102a, . . . , etc. and 101b, 102b, . . . , etc., but the present disclosure is not limited thereto.

[0187] refer to Fig.13 , the storage device 100B may include a mirror information storage area 412 and a command / address exchange circuit 421 . Fig.13 The memory device 100B is Fig. 9 The memory device 100A is the same as that of FIG. 1 except that the command / address exchange circuit 421 operates based on the value set in the nonvolatile storage area 72. Therefore, as long as there is no contradiction, reference Fig. 9 The description given can be applied equally to Fig.13 The memory device 100B is shown in FIG. 1 , except for the above-mentioned difference. The difference is described below.

[0188] The command / address exchange circuit 421 may exchange at least some of the values ​​of the applied CA bits based on the values ​​set in the nonvolatile storage area 72. For example, when a default value corresponding to the standard mode is set in the nonvolatile storage area 72, the command / address exchange circuit 421 may maintain the value of the applied CA bits. Thus, the storage device 100B may operate in the standard mode. In some embodiments, when a second value corresponding to the mirror mode is set in the nonvolatile storage area 72, the command / address exchange circuit 421 may exchange at least some of the values ​​of the applied CA bits. Thus, the storage device 100B may operate in the mirror mode. That is, Fig. 9 Unlike the memory device 100A, the memory device 100B may operate in the standard mode or the mirror mode based on the value set in the nonvolatile storage area 72 .

[0189] For example, the default value may be stored in the nonvolatile storage area 72. In an embodiment, the default value may be pre-stored in the nonvolatile storage area 72 during the manufacturing process of the storage device 100B. When the storage device 100B is powered on in a state where the default value is stored in the nonvolatile storage area 72, the command / address exchange circuit 421 may maintain the value of the applied CA bit, and the storage device 100B may operate in the standard mode. That is, when the storage module 1000 / 1000-1 / 1000-2 is initially powered on, the storage device 100B installed in the storage module 1000 / 1000-1 / 1000-2 may operate in the standard mode.

[0190] exist Figure 4In the embodiment, when the memory device 100B is the first memory device 101a / 102a / etc., the memory device 100B operating in the standard mode may set a second value corresponding to the mirror mode in the mode register 71 based on a first command applied to a plurality of signal lines.

[0191] In this case, since whether the memory device 100B operates in the mirror mode depends on the value set in the nonvolatile storage area 72, the memory device 100B does not operate in the mirror mode even if the second value is set in the mode register 71. That is, according to an embodiment of the present disclosure, after the second value is set in the mode register 71, the memory device 100B can operate in the mirror mode only when the second value is programmed in the nonvolatile storage area 72 according to the OTP programming operation.

[0192] As reference Fig. 9 As described above, the OTP programming operation process includes a process in which the memory device 100B receives a command to enter the test mode or an additional command such as a security key. In this case, in order to make the memory device 100B operating in the standard mode perform the OTP programming operation according to the additional command, the additional command may also be input to the memory device 100B in a state in which the value of the CA bit is swapped like the first command.

[0193] Therefore, according to an embodiment, the memory device 100B may receive a command in which the value of the CA bit is swapped until the second value set in the mode register 71 is programmed into the nonvolatile memory area 72. Therefore, when the second value is programmed in the nonvolatile memory area 72, the memory device 100B may operate in the mirror mode. The operations performed after programming the second value in the nonvolatile memory area 72 are similar to those in FIG. Fig. 9 The operations of the memory device 100A are the same as those of the memory device 100A, and therefore, additional description will be omitted to avoid redundancy.

[0194] Fig.14 A storage system according to an embodiment of the present disclosure is shown. Fig.14 , the storage system 1400 may include a storage module 1000 ′ and a storage controller 800 .

[0195] The storage module 1000' may be Figure 1A , Figure 1B , Figure 3A , Figure 4 and Figure 6The memory module 1000 / 1000-1 / 1000-2 shown in the embodiment of the present disclosure is not limited thereto. The memory module 1000' may include first memory devices 101a, 102a, ..., etc. and second memory devices 101b, 102b, ..., etc. mounted on opposite surfaces 1000a and 1000b of the circuit board to face each other, a serial presence detect (Serial Presence Detect, SPD) 1100 and an RCD 1200.

[0196] The first storage devices 101a, 102a, ..., etc. and the second storage devices 101b, 102b, ..., etc. may respectively include corresponding mirror information storage areas 101a_1, 102a_1, ..., etc., 101b_1, 102b_1, ..., etc. In this case, each mirror information storage area 101a_1, 102a_1, ..., etc., 101b_1, 102b_1, ..., etc. may include a mode register 71 and a non-volatile storage area 72.

[0197] In some embodiments, each of the first storage devices 101a, 102a, ..., etc. and the second storage devices 101b, 102b, ..., etc. may be operated in a standard mode or a mirror mode based on a value set in a corresponding one of the mirror information storage areas 101a_1, 102a_1, ..., etc., 101b_1, 102b_1, ..., etc. For example, each of the first storage devices 101a, 102a, ..., etc. and the second storage devices 101b, 102b, ..., etc. may be operated in a standard mode or a mirror mode based on a value set in a corresponding mode register 71. Alternatively, each of the first storage devices 101a, 102a, ..., etc. and the second storage devices 101b, 102b, ..., etc. may be operated in a standard mode or a mirror mode based on a value set in a corresponding non-volatile memory area 72.

[0198] In some embodiments, a default value corresponding to the standard mode may be set in the mirror information storage areas 101a_1, 102a_1, ..., etc., 101b_1, 102b_1, ..., etc. For example, the default value may be initially stored in the non-volatile storage area 72 of each of the mirror information storage areas 101a_1, 102a_1, ..., etc., 101b_1, 102b_1, ..., etc. Therefore, the default value may be set in the mode register 71 of each of the mirror information storage areas 101a_1, 102a_1, ..., etc., 101b_1, 102b_1, ..., etc. In this case, each of the first storage devices 101a, 102a, ..., etc. and the second storage devices 101b, 102b, ..., etc. may operate in the standard mode.

[0199] The SPD 1100 may include various information about the storage module 1000'. For example, the SPD 1100 may include initial information or device information (DI) of the storage module 1000'. In an embodiment, the SPD 1100 may include initial information or device information (DI) of the storage module 1000', such as module shape, module configuration, storage capacity, module type, and execution environment. The SPD 1100 may be implemented with an electrically erasable programmable read-only memory (EEPROM) device, but the present disclosure is not limited thereto.

[0200] For example, the SPD 1100 may communicate with the storage controller 800 via a serial bus. In addition, the SPD 1100 may communicate with the RCD 1200 via a serial bus. In an embodiment, the serial bus may include at least one of a 2-wire serial bus, such as an inter-integrated circuit (I2C), a system management bus (SMBus), a power management bus (PMBus), an intelligent platform management interface (IPMI), and a management component transport protocol (MCTP), but the present disclosure is not limited thereto.

[0201] The RCD 1200 may control the first storage devices 101a, 102a, ..., etc. and the second storage devices 101b, 102b, ..., etc. under the control of the memory controller 800. For example, the RCD 1200 may receive an address ADDR, a command CMD, and a clock signal CK from the memory controller 800. The RCD 1200 may transmit the received signals to the first storage devices 101a, 102a, ..., etc. and the second storage devices 101b, 102b, ..., etc. Therefore, the first storage devices 101a, 102a, ..., etc. and the second storage devices 101b, 102b, ..., etc. may write the received data through the data signal DQ and the data strobe signal DQS, or may output the stored data through the data signal DQ and the data strobe signal DQS.

[0202] The storage controller 800 may control the storage module 1000'. For example, the storage controller 800 may control the storage module 1000' according to a request of a processor supporting various applications such as server applications, personal computer (PC) applications, and mobile applications. For example, the storage controller 800 may be included in a host including a processor, and may control the storage module 1000' according to a request of the processor. According to an embodiment, the storage controller 800 may be included in various external devices such as a test device, an inspection device, and a packaging device for testing the storage module 1000'.

[0203] In order to control the memory module 1000', the memory controller 800 may transmit a command and / or an address to the memory module 1000'. In addition, the memory controller 800 may transmit data to the memory module 1000' or may receive data from the memory module 1000'.

[0204] When the storage system 1400 is started, the storage controller 800 may receive initial information and / or device information (DI) of the storage module 1000' from the SPD 1100, and may identify and control the storage module 1000' based on the received information. For example, the storage controller 800 may identify the types of the first storage devices 101a, 102a, ..., etc. and the second storage devices 101b, 102b, ..., etc. included in the storage module 1000' based on the information received from the SPD 1100.

[0205] Specifically, according to an embodiment, the memory controller 800 may identify a memory device to be used in the mirroring mode from among the first memory devices 101 a , 102 a , . . . , etc. and the second memory devices 101 b , 102 b , . . . , etc. based on information received from the SPD 1100 .

[0206] When the first storage device 101a, 102a, ..., etc. is identified as a storage device to be used in a mirror mode, the storage controller 800 may apply a first command to the storage module 1000' for setting a second value corresponding to the mirror mode in the mode register 71 of the first storage device 101a, 102a, ..., etc. In this case, the first command may be a command to exchange at least some values ​​of the plurality of CA bits included in the second command. Wherein, when a storage device operating in a standard mode receives a second command, the second command may be a command for setting a second value in a mirror information storage area of ​​the corresponding storage device. For example, the second command may be a command for setting a second value in the mode register 71 of each second storage device 101b, 102b, ..., etc.

[0207] According to an embodiment, the storage controller 800 may apply a first command to the storage module 1000' during a first operation performed after identifying a storage device to be used in the mirroring mode based on information received from the SPD 1100, but the present disclosure is not limited thereto. In some embodiments, the first command may be pre-defined for each storage module 1000' and may be pre-stored in the storage controller 800 or a storage device of a host including the storage controller 800, but the present disclosure is not limited thereto.

[0208] Therefore, when the first command is applied to the memory module 1000', a second value corresponding to the mirror mode may be set in the mode register 71 of each first memory device 101a, 102a, ..., etc. operating in the standard mode. Thereafter, the first memory devices 101a, 102a, ..., etc. may be used in the mirror mode.

[0209] Fig.15 FIG. 2 shows a configuration of a storage module according to an embodiment of the present disclosure. Fig.15 , the storage module 1000" may include a plurality of storage devices 101 to 140 disposed on opposite surfaces (ie, a first surface 1000a and a second surface 1000b). In addition, the storage module 1000" may include an SPD 1100 disposed on the center of the first surface 1000a and an RCD 1200 disposed on the center of the second surface 1000b.

[0210] A plurality of storage devices 101 to 120 disposed on the second surface 1000b of the storage module 1000″ may be included in the first level Rank0 and may be disposed on the left and right sides relative to the RCD 1200. In addition, a plurality of storage devices 121 to 140 disposed on the first surface 1000a of the storage module 1000″ may be included in the second level Rank1 and may be disposed on the left and right sides relative to the SPD 1100.

[0211] Each of the memory devices 101 to 140 may be Figure 7 The memory device 100 or Fig. 9 The memory device 100A of the present invention may include a mode register 71 and a non-volatile storage area 72. A default value corresponding to the standard mode may be stored in the non-volatile storage area 72 of each of the memory devices 101 to 140. Therefore, when the memory module 1000 is powered on, all the memory devices 101 to 140 may operate in the standard mode.

[0212] In this case, according to an embodiment, the configuration of the plurality of memory devices 101 to 140 may be similar to Figure 4That is, the plurality of memory devices 101 to 140 may have such a connection relationship that the memory devices 101 to 120 included in the first rank Rank0 receive the value of the CA bit without modification, and the memory devices 121 to 140 included in the second rank Rank1 receive the CA bit in a state where the value of the CA bit is swapped.

[0213] In this case, the memory devices 121 to 140 included in the second rank Rank1 may be used in the mirror mode, and the memory controller 800 may identify the memory devices 121 to 140 to be used in the mirror mode from among the plurality of memory devices 101 to 140 based on information stored in the SPD 1100 .

[0214] Therefore, the memory controller 800 may apply the first command to the memory module 1000". For example, the memory controller 800 may provide the first command to the RCD 1200, and the RCD 1200 may apply the first command received from the memory controller 800 to a plurality of signal lines included in the circuit board 50. Therefore, the memory devices 121 to 140 included in the second level Rank1 may operate in a mirror mode.

[0215] In this case, according to an embodiment, the memory devices 101 to 110 and 121 to 130 disposed on the left side of the memory module 1000” may communicate with the memory controller 800 through the first sub-channel Sub_Channel 1. In addition, the memory devices 111 to 120 and 131 to 140 disposed on the right side of the memory module 1000” may communicate with the memory controller 800 through the second sub-channel Sub_Channel 2. Therefore, the RCD 1200 may simultaneously apply the first command to the left memory devices 121 to 130 of the second rank Rank1 and the right memory devices 131 to 140 of the second rank Rank1 by using the first sub-channel Sub_Channel 1 and the second sub-channel Sub_Channel 2 independently of each other.

[0216] In some embodiments, the number and arrangement of components included in the memory module 1000 ″ (ie, the memory devices 101 to 140 , the SPD 1100 , and the RCD 1200 ) may be provided as examples and may be variously changed or modified according to the embodiments.

[0217] The above describes an embodiment in which the first value corresponding to the standard mode is used as the default value. However, the present disclosure is not limited thereto. According to an embodiment, a second value corresponding to the mirror mode can be used as the default value. In this case, within the initial time interval when the storage module 1000 is powered on, all first storage devices 101a, 102a, ..., etc. and second storage devices 101b, 102b, ..., etc. can operate in the mirror mode.

[0218] In this case, it is assumed that the storage module 1000-1 has Figure 4 In the structure shown, in order to enable the first storage devices 101a, 102a, ..., etc. and the second storage devices 101b, 102b, ..., etc. to perform the same operation according to the CA signal, the operation mode of the second storage devices 101b, 102b, ..., etc. can be changed from the mirror mode to the standard mode.

[0219] To this end, the memory controller 800 may apply the fourth command to the memory module 1000-1. In this case, the fourth command may be a command to set a value corresponding to the standard mode in the mirror information storage areas 101b_1, 102b_1, ..., etc. of the second memory devices 101b, 102b, ..., etc.

[0220] For example, Figure 5 The second command shown may be a command to set a value corresponding to the mirror mode in the mirror information storage areas 101b_1, 102b_1, ..., etc. of the second storage devices 101b, 102b, ..., etc.; in this case, the value corresponding to the mirror mode may be the value of the CA13 bit, i.e., "1". Figure 5 The command implemented by changing only the value of the CA13 bit to "0" in the second command is taken as an example of the fourth command. When the fourth command is applied to the storage module 1000-1, the values ​​corresponding to the standard mode can be set in the mirror information storage areas 101b_1, 102b_1, ..., etc. of the second storage devices 101b, 102b, ..., etc. The term "pin" used in the above description may be referred to as a "ball".

[0221] According to one or more embodiments of the present disclosure, the mirror function can be implemented without a mirror pin. For example, according to one or more embodiments of the present disclosure, the mirror function can be implemented without a mirror pin while maintaining a structure in which memory devices mounted on opposite surfaces of a circuit board facing each other share a CA signal through a through hole. Therefore, the existing pins used for the mirror function can be used as pins for any other purpose, such as an I / O pin or a ground pin. This can mean that the integrity of the signal is improved. According to one or more embodiments of the present disclosure, the mirror function can be implemented without a mirror pin.

[0222] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to one of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A storage module, comprising: a circuit board including a plurality of signal lines to which a command is applied; as well as A first memory device is mounted on a first surface of the circuit board, is connected to the plurality of signal lines, includes a first mode register, and is configured as follows: operating in standard mode or mirror mode based on the value set in the first mode register, setting a value corresponding to the mirror mode in the first mode register based on a first command applied to the plurality of signal lines, At least one of the plurality of command / address bits in the first command is exchanged with at least one of the plurality of command / address bits in the second command.

2. The storage module according to claim 1, wherein: The first storage device is further configured as: operating in the standard mode based on a default value set in the first mode register; and Based on the first command applied to the plurality of signal lines in the standard mode, a value corresponding to the mirror mode is set in the first mode register.

3. The storage module according to claim 2, wherein: The first storage device further includes a nonvolatile storage area configured to store a value set in the first mode register during a power-on operation, and The non-volatile storage area is configured to store the default value.

4. The storage module according to claim 3, wherein: When a value corresponding to the mirror mode is set in the first mode register based on the first command, the first storage device is further configured to change the default value stored in the nonvolatile storage area to a value corresponding to the mirror mode.

5. The storage module according to claim 1, wherein: When a third command is applied to the plurality of signal lines in the mirror mode, the first memory device is further configured to: receiving a fourth command in which at least one of the plurality of command / address bits is swapped with at least one of the plurality of command / address bits in the third command; and An operation corresponding to the third command is performed by swapping the at least one bit of the plurality of command / address bits in the fourth command with the at least one bit of the plurality of command / address bits in the third command.

6. The storage module according to claim 1, wherein: The first storage device further includes a plurality of pins corresponding to the plurality of command / address bits respectively, Wherein, the plurality of pins include: a first pin corresponding to a first command / address bit of the plurality of command / address bits; and a second pin, corresponding to a second command / address bit among the plurality of command / address bits, Wherein, the circuit board comprises: a first signal line corresponding to the first command / address bit; and A second signal line, corresponding to the second command / address bit, wherein the value of the first command / address bit is applied to the second pin of the first memory device via the first signal line, and The value of the second command / address bit is applied to the first pin of the first storage device through the second signal line.

7. The storage module according to claim 6, further comprising: a second storage device mounted on a second surface of the circuit board to face away from the first storage device and including a second mode register, The second storage device includes a plurality of pins corresponding to the plurality of command / address bits respectively. wherein the first pin of the second storage device is connected to the second pin of the first storage device through a first through hole of the circuit board, wherein the second pin of the second storage device is connected to the first pin of the first storage device through a second through hole of the circuit board, wherein the value of the first command / address bit is applied to the first pin of the second storage device through the first signal line and the first via, and The value of the second command / address bit is applied to the second pin of the second storage device through the second signal line and the second via.

8. The storage module according to claim 7, wherein: The first command is commonly applied to the first storage device and the second storage device, wherein the first memory device is configured to receive the first command based on a value of a first chip select signal, and The second storage device is configured to ignore the first command based on a value of a second chip select signal.

9. The storage module according to claim 6, wherein: The value of the first command / address bit of the first command is the same as the value of the second command / address bit of the second command, and The value of the second command / address bit of the first command is the same as the value of the first command / address bit of the second command.

10. The storage module according to claim 1, wherein: The first command is a command for exchanging values ​​of even command / address bits of the second command with values ​​of odd command / address bits of the second command that are adjacent to and higher than the even command / address bits.

11. The storage module according to claim 1, wherein: The first storage device further includes: a command / address swapping circuit configured to swap at least one of a plurality of command / address bits in an applied command based on a value set in the first mode register, wherein, when a default value corresponding to the standard mode is set in the first mode register, the command / address exchange circuit is further configured to maintain the at least one bit of the plurality of command / address bits in the applied command, and Wherein, when a value corresponding to the mirror mode is set in the first mode register, the command / address exchange circuit is further configured to exchange the at least one bit of the plurality of command / address bits in the applied command.

12. A storage system comprising: A memory module including a first memory device mounted on a first surface of a circuit board; as well as a storage controller operatively connected to the storage module, wherein the first memory device comprises a first mode register and is configured to operate in a standard mode or a mirror mode based on a value stored in the first mode register, wherein the circuit board includes a plurality of signal lines connected to the first storage device, wherein the storage controller is configured to apply a first command to the plurality of signal lines to set a value corresponding to the mirror mode in the first mode register, and The first command is a command for exchanging at least one bit among a plurality of command / address bits with at least one bit among a plurality of command / address bits in a second command.

13. The storage system according to claim 12, wherein: The first storage device is further configured as: operating in the standard mode based on a default value set in the first mode register; and Based on the first command applied to the plurality of signal lines in the standard mode, a value corresponding to the mirror mode is set in the first mode register.

14. The storage system according to claim 12, wherein: The memory controller is included in a test device of the memory module.

15. The storage system according to claim 12, wherein: The memory module further includes: a second memory device mounted on a second surface of the circuit board to face away from the first memory device; and a serial presence detection SPD including information about the memory module, The storage controller is configured to identify a storage device to be used in the mirroring mode from among the first storage device and the second storage device based on information received from the SPD.

16. The storage system according to claim 12, wherein: The first command is a command for exchanging values ​​of even command / address bits of the second command with values ​​of odd command / address bits of the second command that are adjacent to and higher than the even command / address bits.

17. A method for storing a module, the memory module comprising a first memory device mounted on one surface of a circuit board, the method comprising: operating the first storage device in a standard mode based on a default value set in a first mode register in the first storage device; setting a value corresponding to a mirror mode in the first mode register based on a first command applied to a plurality of signal lines connected to the first memory device; as well as operating the first memory device in the mirroring mode based on a value corresponding to the mirroring mode set in the first mode register, Wherein, the circuit board includes the plurality of signal lines, and The first command is a command for exchanging at least one bit among a plurality of command / address bits with at least one bit among a plurality of command / address bits in a second command.

18. The method according to claim 17, further comprising: storing, in a nonvolatile storage area, a value set in the first mode register during a power-on operation, and The default value is stored in the non-volatile storage area.

19. The method according to claim 18, further comprising: The default value stored in the nonvolatile storage area of ​​the first storage device is changed to a value corresponding to the mirroring mode set in the first mode register.

20. The method of claim 17, further comprising: applying a third command to the plurality of signal lines when the first memory device operates in the mirroring mode; receiving, at the first storage device, a fourth command in which at least one of the plurality of command / address bits is swapped with at least one of the plurality of command / address bits in the third command; as well as An operation corresponding to the third command is performed by swapping the at least one bit of the plurality of command / address bits in the fourth command with the at least one bit of the plurality of command / address bits in the third command.

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