Information transmission method, memory, control device and electronic equipment

Abstract

The invention provides an information transmission method, a memory, a control device and electronic equipment. The method comprises the following steps: receiving a first target instruction sent by the outside; and outputting first duty ratio data of the internal data clock signal through the first group of data ports based on the first target instruction, wherein the first duty ratio data at least continues in the first group of data ports until a first ending instruction sent by the outside is received.

Description

Technical Field

[0001] The present disclosure relates to the semiconductor field, and in particular to an information transmission method, a memory, a control device and an electronic device. Background Art

[0002] Taking the dynamic random access memory (DRAM) as an example, the system on chip (SoC) sends a register read instruction (MRR) to the memory, and then receives the strobe clock signal RDQS and the data signal DQ (output via the data port) returned by the memory, and uses the strobe clock signal RDQS to sample the data port of the memory to obtain the required data. At the same time, the aforementioned strobe clock signal RDQS is essentially generated according to the external data clock signal WCK0 received by the DRAM from the SoC.

[0003] During the initialization phase after power-on, the DRAM needs to first adjust the duty cycle of the external data clock signal WCK0 sent by the SoC so that the duty cycle of the data clock signal (also referred to as the internal data clock signal WCK1) received by the memory meets the requirements. Summary of the invention

[0004] The present disclosure provides an information transmission method, a memory, a control device and an electronic device.

[0005] The technical solution of the present disclosure is achieved as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides an information transmission method, which is applied to a memory, and the method includes:

[0007] receiving a first target instruction sent externally;

[0008] Based on the first target instruction, the first duty cycle data of the internal data clock signal is output through the first group of data ports, and the first duty cycle data continues in the first group of data ports at least until a first end instruction sent externally is received.

[0009] In some embodiments, before receiving the first target instruction sent externally, the method further includes:

[0010] Receive the duty cycle start detection instruction sent externally;

[0011] Based on the duty cycle start detection instruction, a duty cycle detection is performed on the internal data clock signal to generate the first duty cycle data.

[0012] In some embodiments, the method further comprises:

[0013] Control the first group of data ports to be initially in a high-impedance state; receive the first target instruction sent from the outside; take the receipt of the first target instruction as the timing starting point, and after an interval of a first preset time, use the first group of data ports to output the first duty cycle data, and the first duty cycle data continues to exist in the first group of data ports; take the receipt of the first end instruction as the timing starting point, and after an interval of a second preset time, control the first group of data ports to restore to a high-impedance state.

[0014] In some embodiments, the method further comprises:

[0015] Based on the first target instruction, another duty cycle detection is performed on the internal data clock signal to generate second duty cycle data; a second target instruction sent externally is received; based on the second target instruction, the second duty cycle data is output through a second group of data ports, and the second duty cycle data continues in the second group of data ports at least until a second end instruction sent externally is received.

[0016] In some embodiments, the method further comprises:

[0017] Control the second group of data ports to be initially in a high-impedance state; receive the second target instruction sent externally; take the receipt of the second target instruction as the timing starting point, and after an interval of a third preset time, use the second group of data ports to output the second duty cycle data, and the second duty cycle data continues to exist in the second group of data ports; wherein the second target instruction is later than the first target instruction; take the receipt of the second end instruction as the timing starting point, and after an interval of a fourth preset time, control the second group of data ports to resume the high-impedance state.

[0018] In some embodiments, the first target instruction is a duty cycle reversal detection instruction; the second target instruction is a duty cycle reversal detection output instruction; the first end instruction and the second end instruction are the same duty cycle detection end instruction.

[0019] In a second aspect, an embodiment of the present disclosure provides an information transmission method, which is applied to a control device, wherein the control device is connected to a memory, and the information transmission method includes:

[0020] In the duty cycle adjustment mode, a first target instruction is sent to the memory; after sending the first target instruction, a first group of data ports of the memory are sampled using an internal clock signal to obtain first duty cycle data; wherein the internal clock signal refers to a clock signal generated inside the control device; and a first end instruction is sent to the memory.

[0021] In some embodiments, before sending the first target instruction to the memory, the method further includes:

[0022] A duty cycle start detection instruction is sent to the memory, wherein the duty cycle start detection instruction instructs the memory to perform a duty cycle detection on an internal data clock signal to generate the first duty cycle data.

[0023] In some embodiments, the step of sampling the first group of data ports of the memory using the internal clock signal to obtain the first duty cycle data includes:

[0024] A first target instruction is sent to the memory, and the sending of the first target instruction is used as a timing starting point. After a fifth preset time interval, the first group of data ports of the memory are sampled using the internal clock signal to obtain first duty cycle data.

[0025] In some embodiments, the first target instruction further instructs the memory to perform another duty cycle detection on the internal data clock signal to generate second duty cycle data; after sending the first target instruction to the memory, the method further includes:

[0026] Sending a second target instruction to the memory; after sending the second target instruction, sampling a second group of data ports of the memory using the internal clock signal to obtain second duty cycle data; sending a second end instruction to the memory.

[0027] In some embodiments, the using the internal clock signal to sample the second group of data ports of the memory to obtain second duty cycle data includes:

[0028] A second target instruction is sent to the memory, and the sending of the second target instruction is used as a timing starting point. After a sixth preset time interval, the second group of data ports of the memory are sampled using the internal clock signal to obtain second duty cycle data.

[0029] In some embodiments, the first target instruction is a duty cycle reversal detection instruction; the second target instruction is a duty cycle reversal detection output instruction; the first end instruction and the second end instruction are the same duty cycle detection end instruction.

[0030] In some embodiments, the method further includes: in a non-duty cycle adjustment mode, receiving a gate clock signal sent by the memory; and performing signal sampling on a data port of the memory based on the gate clock signal.

[0031] In a third aspect, an embodiment of the present disclosure provides a memory, the memory comprising:

[0032] A duty cycle detection circuit is configured to perform a duty cycle detection on an internal data clock signal to generate first duty cycle data; a transmission circuit is respectively connected to the duty cycle detection circuit and a first group of data ports of the memory, and is configured to receive a first target instruction sent externally, receive the first duty cycle data based on the first target instruction, and transmit the first duty cycle data to the first group of data ports; wherein the first duty cycle data persists in the first group of data ports at least until the memory receives a first end instruction sent externally.

[0033] In some embodiments, the duty cycle detection circuit is specifically configured to receive an externally sent duty cycle start detection instruction; based on the duty cycle start detection instruction, perform a duty cycle detection on the internal data clock signal to generate the first duty cycle data; the first group of data ports are initially in a high-impedance state; the transmission circuit is specifically configured to receive an externally sent first target instruction, take the receipt of the first target instruction as the timing starting point, and after an interval of a first preset time length, transmit the first duty cycle data to the first group of data ports, and the first duty cycle data continues to exist in the first group of data ports; and, receive the first end instruction sent externally, take the receipt of the first end instruction as the timing starting point, and after an interval of a second preset time length, control the first group of data ports to restore to a high-impedance state.

[0034] In some embodiments, the duty cycle detection circuit is further configured to receive the first target instruction, and based on the first target instruction, perform another duty cycle detection on the internal data clock signal to generate second duty cycle data; the transmission circuit is further configured to receive a second target instruction sent externally, and based on the second target instruction, receive the second duty cycle data, and transmit the second duty cycle data to the second group of data ports; wherein the second duty cycle data persists in the second group of data ports at least until the memory receives a second end instruction sent externally.

[0035] In some embodiments, the second group of data ports is initially in a high-impedance state; the transmission circuit is specifically configured to receive a second target instruction sent externally, take the receipt of the second target instruction as the timing starting point, and after an interval of a third preset time, transmit the second duty cycle data to the second group of data ports, and the second duty cycle data continues to exist in the second group of data ports; wherein the second target instruction is later than the first target instruction; and, receive the second end instruction sent externally, take the receipt of the second end instruction as the timing starting point, and after an interval of a fourth preset time, control the second group of data ports to return to a high-impedance state.

[0036] In some embodiments, the duty cycle detection circuit includes a control circuit and a detection circuit; the detection circuit is configured to perform duty cycle detection on the clock signal at its first input terminal and the clock signal at its second input terminal; the control circuit is configured to receive the internal data clock signal and its complementary signal; based on the received duty cycle start detection instruction, the internal data clock signal is output to the first input terminal of the detection circuit and the complementary signal of the internal data clock signal is output to the second input terminal of the detection circuit, so that the detection circuit outputs the first duty cycle data; or, based on the received first target instruction, the internal data clock signal is output to the second input terminal of the detection circuit and the complementary signal of the internal data clock signal is output to the first input terminal of the detection circuit, so that the detection circuit outputs the second duty cycle data.

[0037] In some embodiments, the first target instruction is a duty cycle reversal detection instruction; the second target instruction is a duty cycle reversal detection output instruction; the first end instruction and the second end instruction are the same duty cycle detection end instruction.

[0038] In a fourth aspect, an embodiment of the present disclosure provides a control device connected to a memory, the control device comprising:

[0039] An instruction generating circuit is configured to generate a first target instruction in a duty cycle adjustment mode and send the first target instruction to the memory; a clock circuit is configured to generate an internal clock signal; a selection circuit is connected to the clock circuit and the memory and configured to receive a duty cycle detection enable signal, the internal clock signal and a selection clock signal sent by the memory; when the duty cycle detection enable signal indicates that the control device is in the duty cycle adjustment mode, the internal clock signal is output as a sampling clock signal; a sampling circuit is connected to the selection circuit and a data port of the memory and configured to sample signals of a first group of data ports using the sampling clock signal after sending the first target instruction to obtain first duty cycle data.

[0040] In some embodiments, the sampling circuit is specifically configured to use sending the first target instruction as a timing starting point, and after a fifth preset time interval, use the sampling clock signal to sample signals on the first group of data ports of the memory to obtain first duty cycle data.

[0041] In some embodiments, the instruction generating circuit is further configured to generate a second target instruction after sending the first target instruction, and send the second target instruction to the memory; the sampling circuit is further configured to use the sending of the second target instruction as the timing starting point, and after an interval of a sixth preset time length, use the internal clock signal to sample signals on the second group of data ports of the memory to obtain second duty cycle data.

[0042] In some embodiments, the first target instruction is a duty cycle reversal detection instruction; and the second target instruction is a duty cycle reversal detection output instruction.

[0043] In some embodiments, the selection circuit is further configured to output the selection clock signal as a sampling clock signal when the duty cycle detection enable signal indicates that the control device is not in a duty cycle adjustment mode.

[0044] In a fifth aspect, an embodiment of the present disclosure provides an electronic device, which at least includes the memory as described in the third aspect and the control device as described in the fourth aspect.

[0045] The embodiments of the present disclosure provide an information transmission method, a memory, a control device and an electronic device, which output the duty cycle detection result of the internal data clock signal (for example, the first duty cycle data) through the corresponding data port and maintain it in the corresponding data port, without the need to additionally store it in a mode register and then read it out through an MRR instruction, thereby saving the number of instructions and simplifying the interaction process; at the same time, because the first duty cycle data will be maintained in the data port for a considerable period of time, there is no need to provide a selection clock signal, thereby avoiding the problem of the control device being unable to sample the detection result due to the distortion of the selection clock signal, thereby ensuring the correctness of the duty cycle detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 A signal timing diagram for duty cycle detection

[0047] Figure 2 This is a schematic diagram of the operation timing of the MRR instruction;

[0048] Figure 3 It is a schematic diagram of the local structure of the memory;

[0049] Figure 4 A waveform diagram of a gate clock signal;

[0050] Figure 5 A schematic diagram of a method for transmitting information provided by the present disclosure Figure 1 ;

[0051] Figure 6A schematic diagram of a method for transmitting information provided by the present disclosure Figure 2 ;

[0052] Figure 7 A schematic diagram of a method for transmitting information provided by the present disclosure Figure 3 ;

[0053] Figure 8 A signal timing diagram for duty cycle detection provided by an embodiment of the present disclosure;

[0054] Fig. 9 A schematic diagram of a memory structure provided in an embodiment of the present disclosure Figure 1 ;

[0055] Fig.10 A schematic diagram of a memory structure provided in an embodiment of the present disclosure Figure 2 ;

[0056] Fig.11 A schematic diagram of a working scenario of a memory provided by an embodiment of the present disclosure;

[0057] Fig.12 Another information transmission method provided by the present invention is shown in FIG. Figure 1 ;

[0058] Fig.13 Another information transmission method provided by the present invention is shown in FIG. Figure 2 ;

[0059] Fig.14 A schematic diagram of the structure of a control device provided in an embodiment of the present disclosure;

[0060] Fig.15 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0061] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant application, rather than to limit the application. It should also be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0063] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0064] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0065] Dynamic Random Access Memory (DRAM);

[0066] Synchronous Dynamic Random Access Memory (SDRAM);

[0067] Double Data Rate SDRAM (DDR);

[0068] Low Power DDR (LPDDR);

[0069] Sixth generation LPDDR (LPDDR);

[0070] MRR (Mode Register Read): mode register read instruction;

[0071] MRW (Mode Register Write): mode register read instruction;

[0072] Mbps (Million bits per second): megabits per second;

[0073] NMOS (N-Metal-Oxide-Semiconductor): N-channel field effect transistor;

[0074] PMOS (P-Metal-Oxide-Semiconductor): P-channel field effect transistor.

[0075] For the memory (taking LPDDR6 as an example), it needs to receive the external data clock signal WCK0 from the SoC to generate the internal data clock signal WCK1, and use the internal data clock signal WCK1 to generate the strobe data signal RDQS. During the operation of the DRAM, it is necessary to output the data signal DQ at its own data port and synchronously output the strobe data signal RDQS, so that the SoC can use the received strobe data signal RDQS to sample the DRAM data port and obtain the required data.

[0076] At the same time, during the initialization phase of the DRAM, the duty cycle of the received internal data clock signal WCK1 needs to be adjusted to ensure the quality of subsequent data output; after the DRAM adjusts the internal data clock signal WCK1 once, the DRAM also needs to detect the duty cycle of the adjusted internal data clock signal WCK1 and feed it back to the SoC so that the SoC can determine whether the duty cycle adjustment is completed. Figure 1 , which shows a signal timing diagram for duty cycle detection. Figure 1 In the figure, Tc0, Tc1, ... are used to identify different clock cycles, CK_c and CK_t are a pair of differential clock signals, CMD indicates an operation instruction, DQ is an output signal of the data port of the DRAM, and the aforementioned internal data clock signal WCK1 may appear as a single signal or a pair of differential clock signals WCK_c and WCK_t at different circuit locations.

[0077] like Figure 1 As shown, the specific process of the duty cycle detection is as follows:

[0078] (1) SoC sends a duty cycle start detection instruction (MRW-DCM start) to DRAM, and DRAM performs a duty cycle detection on the internal data clock signal WCK1 to obtain the first duty cycle data; here, the first duty cycle data is not the specific value of the duty cycle of the external data clock signal WCK0, but the comparison result of the duty cycle of the external data clock signal WCK0 and 50%;

[0079] (2) At a certain interval (tDCMM), the SoC sends a duty cycle flip detection instruction (MRW-DCM Flip1) to the DRAM, and the DRAM stores the first duty cycle data in a mode register MR; at the same time, the DRAM performs another duty cycle detection on the internal data clock signal WCK1 to obtain the second duty cycle data; here, the second duty cycle data is also the comparison result of the duty cycle of the external data clock signal WCK0 and 50%;

[0080] (3) After a certain time interval (tDCMM), the SoC sends a duty cycle flip detection output instruction (MRW-DCMFlip 0) to the DRAM, and the DRAM stores the second duty cycle data in another mode register MR;

[0081] (4) After a certain period of time (tDCMM), the SoC sends a duty cycle detection end instruction (MRW-DCMstop) to the DRAM;

[0082] (5) At a certain time interval (tMRD), the SoC sends a register read instruction (MRR) to the DRAM to obtain the first duty cycle data and the second duty cycle data.

[0083] In DRAM, the MRR instruction and the normal read instruction use exactly the same operation timing. Figure 2 , which shows the operation timing diagram of the MRR instruction. Figure 2 In the example, COMMAND indicates an operation instruction, DMI is a data mask inversion signal, which is also output through a data port; the selection clock signal RDQS is a clock signal output by the memory to the electronic device, which may appear as a single signal or a pair of differential clock signals RDQS_c and RDQS_t in different circuit positions. Its essence is based on the internal data clock signal WCK1 ( Figure 2 WCK_t and WCK_c) in .

[0084] like Figure 2 As shown, after the DRAM receives the MRR instruction sent by the SoC, it generates a data signal DQ carrying information at its own data port, and uses the DRAM internal data clock signals WCK_c and WCK_t to generate effective strobe clock signals RDQS_c and RDQS_t. During the execution of the MRR instruction, the DRAM returns the data signal DQ carrying information and the effective strobe clock signal RDQS to the SoC, and then the SoC uses the strobe clock signal RDQS to sample the data signal DQ to obtain the required information. In addition, Figure 2 This is the standard timing specified by the Joint Electronic Device Engineering Council (JEDEC) standard, in which the meaning of each signal, the principles of related changes, and some abbreviations not mentioned can be understood by referring to the industry standard document JEDEC, and are irrelevant to the technical solution of the embodiments of the present disclosure, and will not affect the technical personnel's understanding of the embodiments of the present disclosure, and therefore will not be explained.

[0085] See also Figure 3 , which shows a schematic diagram of a partial structure of a memory. Figure 3As shown, in the memory, the receiver is used to receive the external data clock signal WCK0 from the outside, the adjustment module adjusts the duty cycle of the received data clock signal (i.e., the internal data clock signal WCK1), and the detection module is used to detect the duty cycle parameters (first duty cycle data and second duty cycle data) of the internal data clock signal WCK1 and store them in the mode register. At the same time, during the process of the memory adjusting the duty cycle, the SoC sends an MRR instruction to read the duty cycle parameters in the mode register to determine the next operation. In an example case, as Figure 3 As shown, the duty cycle of the external data clock signal WCK0 inputted from the outside is the upper limit of 57% specified by JEDEC. In the initial step of duty cycle adjustment, the adjustment module increases the duty cycle of the external data clock signal WCK0 by 7 units (the upper limit specified by JEDEC, and each unit is 5 picoseconds), that is, by 35 picoseconds, which is equivalent to increasing the duty cycle by 15% at a speed of 8533Mbps. At this time, the duty cycle of the internal data clock signal WCK1 in the memory will be as high as 72%, and the duty cycle of the selection clock signal RDQS generated by it will also be as high as 72%. At this time, see Figure 4 , which shows a waveform diagram of a gate clock signal. Figure 4 As shown in the figure, the strobe clock signal RDQS with a duty cycle of up to 72% is attenuated during transmission through the circuit module, and is severely distorted when it reaches the SoC receiving end, making it difficult for the SoC to correctly identify it, that is, the MRR instruction may obtain incorrect data, which ultimately leads to duty cycle adjustment failure. If the memory speed is higher, this problem will be more serious.

[0086] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0087] In one embodiment of the present disclosure, an information transmission method is provided, which can be applied to memories, such as DRAM, SDRAM, double-rate DRAM, low-power double-rate DRAM, etc., and is particularly suitable for LPDDR6.

[0088] The information transmission method is specifically applied to the process in which the memory adjusts the duty cycle of the internal data clock signal WCK1. In short, the SoC generates an external data clock signal WCK0 and transmits the external data clock signal WCK0 to the memory. The memory generates an internal data clock signal WCK1 according to the received external data clock signal WCK0 and adjusts the duty cycle of the internal data clock signal WCK1. After each duty cycle adjustment, the memory needs to obtain the duty cycle information of the internal data clock signal WCK1 and inform the SoC of the duty cycle information for the next step.

[0089] See also Figure 5, which shows a schematic diagram of the process of an information transmission method provided by an embodiment of the present disclosure Figure 1 .like Figure 5 As shown, the method includes:

[0090] S111: Receive a first target instruction sent from outside.

[0091] It should be noted that “external” may be SoC. Exemplarily, the first target instruction may be a duty cycle start detection instruction MRW-DCM start, a duty cycle flip detection instruction MRW-DCM Flip 1, or an additionally defined new instruction.

[0092] S112: Outputting first duty cycle data of the internal data clock signal through a first group of data ports based on a first target instruction, and the first duty cycle data continues in the first group of data ports at least until a first end instruction sent externally is received.

[0093] It should be noted that the first duty cycle data indicates the duty cycle information of the internal data clock signal, specifically the comparison result of the internal data clock signal with 50%. The first end instruction may have multiple possibilities, for example: duty cycle flip detection output instruction MRW-DCM Flip0, duty cycle detection end instruction MRW-DCM stop, (next) duty cycle adjustment instruction, (next) duty cycle start detection instruction MRW-DCM start, (next) duty cycle flip detection instruction MRW-DCMFlip 1, or it may also be an additionally introduced new instruction.

[0094] Here, the memory includes a plurality of data ports for transmitting data signals DQ, and the first group of data ports refers to one or more data ports of the memory. Meanwhile, the number of data ports included in the first group of data ports is the same as the number of bits of the first duty cycle data.

[0095] Thus, in the disclosed embodiment, there is no need to wait for the SoC to issue a special MRR instruction. After receiving the first target instruction, the memory directly transmits the first duty cycle data obtained by detection to the first group of data ports, and the first duty cycle data will be maintained at the first group of data ports for a certain period of time. Therefore, as long as the SoC samples the first group of data ports at any time point within this time period, the correct first duty cycle data can be obtained, thereby avoiding duty cycle adjustment failure, reducing the number of interactive instructions, and saving power consumption.

[0096] In some embodiments, see Figure 6 , before step S111, the method further includes:

[0097] S101: receiving a duty cycle detection start instruction sent externally.

[0098] S102: Based on the duty cycle start detection instruction, perform a duty cycle detection on the internal data clock signal to generate first duty cycle data.

[0099] Here, the duty cycle start detection instruction MRW-DCM start refers to an instruction sent by the SoC to the memory for instructing the memory to detect the duty cycle of the internal data clock signal.

[0100] In some embodiments, after step S111, the method further includes:

[0101] S121: Based on the first target instruction, another duty cycle detection is performed on the internal data clock signal to generate second duty cycle data.

[0102] That is, the first target instruction has two functions: (1) instructing the memory to output the first duty cycle data; (2) instructing the memory to flip the internal data clock signal and perform another duty cycle detection, thereby balancing the mismatch problem of the measurement circuit. For details, please refer to the subsequent description.

[0103] S122: receiving a second target instruction sent externally; based on the second target instruction, outputting the second duty cycle data through the second group of data ports, and the second duty cycle data continues in the second group of data ports at least until a second end instruction sent externally is received.

[0104] It should be noted that the second target instruction may be the aforementioned duty cycle flip detection output instruction MRW-DCMFlip0 or an additionally defined new instruction.

[0105] The second end instruction also has multiple possibilities, for example: duty cycle detection end instruction MRW-DCM stop, (next) duty cycle adjustment instruction, (next) duty cycle start detection instruction MRW-DCM start, (next) duty cycle flip detection instruction MRW-DCM Flip1, (next) duty cycle flip detection output instruction MRW-DCM Flip0, or a new instruction can also be introduced.

[0106] Here, the second group of data ports also refers to one or more data ports of the memory, and there are no duplicate data ports in the second group of data ports and the first group of data ports. Meanwhile, the number of data ports included in the second group of data ports is the same as the number of bits of the second duty cycle data.

[0107] In this way, in the embodiment of the present disclosure, there is no need to wait for the SoC to issue a special MRR instruction. After receiving the second target instruction, the memory directly transmits the second duty cycle data obtained by detection to the second group of data ports, and the second duty cycle data will be maintained at the second group of data ports for a certain period of time. Therefore, as long as the SoC samples the second group of data ports at any time point within this time period, the correct second duty cycle data can be obtained to avoid duty cycle adjustment failure.

[0108] In some embodiments, the method further comprises:

[0109] Receive an external data clock signal WCK0 sent from the outside (SoC); and generate an internal data clock signal WCK1 based on the external data clock signal WCK0.

[0110] In a specific scenario, there is only one internal data clock signal WCK1 in the memory (which can be expressed as a single signal or a pair of differential signals WCK_t and WCK_c in different circuit locations), and all data signals DQ share this internal data clock signal WCK1. At this time, the external data clock signal WCK0 sent by the SoC is also a signal, which can be a single-ended signal or a pair of differential signals.

[0111] Correspondingly, the memory also includes a detection circuit, the detection circuit has a first input terminal (S1) and a second input terminal (S2), and the first input terminal (S1) and the second input terminal (S2) respectively receive a clock signal, and the clock signal of the first input terminal (S1) and the clock signal of the second input terminal (S2) are complementary. The detection circuit can be composed of devices such as comparators, NMOS, PMOS, etc.; depending on the connection relationship of the devices, the detailed functions of the detection circuit may be slightly different. Exemplarily, the detection circuit can detect whether the duty cycle of the clock signal of the first input terminal (S1) is greater than the duty cycle of the clock signal of the second input terminal (S2). Exemplarily, for the detection circuit, if the duty cycle of the clock signal at the first input terminal is greater than the duty cycle of the clock signal at the second input terminal, a high-level signal is output. Since the clock signals at the first input terminal and the second input terminal are complementary, it also represents that the duty cycle of the clock signal at the first input terminal is greater than 50%; similarly, if the duty cycle of the clock signal at the first input terminal is less than the duty cycle of the clock signal at the second input terminal, a low-level signal is output. Since the clock signals at the first input terminal and the second input terminal are complementary, it also represents that the duty cycle of the low-bit data clock signal is less than 50%.

[0112] Therefore, step S102 specifically includes:

[0113] Transmitting an internal data clock signal to a first input terminal (S1) of a detection circuit, transmitting a complementary signal of the internal data clock signal to a second input terminal (S2) of the detection circuit, and acquiring first duty cycle data from an output terminal of the detection circuit;

[0114] Step S121 specifically includes:

[0115] The internal data clock signal is transmitted to the second input terminal (S2) of the detection circuit, the complementary signal of the internal data clock signal is transmitted to the first input terminal (S1) of the detection circuit, and the second duty cycle data is obtained from the output terminal of the detection circuit.

[0116] In this way, through the duty cycle detection with two input terminal signal swaps, the mismatch and error problems on the detection circuit itself can be offset, so that the result of the duty cycle detection is more accurate.

[0117] In a specific embodiment, the detection circuit has one output terminal (Q). At this time, under ideal conditions, the first duty cycle data and the second duty cycle data are complementary. However, due to the mismatch problem of the first detection circuit / the second detection circuit itself, the first duty cycle data and the second duty cycle data may not be completely complementary.

[0118] In another specific embodiment, the detection circuit has two output terminals: a positive phase output terminal (Q) and a negative phase output terminal (Q / ), and the first duty cycle data is output from the positive phase output terminal (Q), and the second duty cycle data is output from the negative phase output terminal (Q / ). At this time, ideally, the first duty cycle data and the second duty cycle data are the same, but due to the mismatch problem of the detection circuit itself, the first duty cycle data and the second duty cycle data may not be completely the same.

[0119] At the same time, in this scenario, the first duty cycle data and the second duty cycle data each include only 1 bit of data, for example, the first duty cycle data = 1, indicating that the duty cycle of the internal data clock signal WCK_t is greater than 50%, the first duty cycle data = 0, indicating that the duty cycle of the internal data clock signal WCK_t is less than 50%; the second duty cycle data = 1, indicating that the duty cycle of the complementary signal WCK_c of the internal data clock signal is less than 50%, the second duty cycle data = 0, indicating that the duty cycle of the complementary signal WCK_c of the internal data clock signal is greater than 50%. Of course, the above is only an example, and the meaning of the values ​​of the first duty cycle data and the second duty cycle data can be defined according to the actual application scenario. Accordingly, the first group of data ports includes one data port, and the second group of data ports includes another data port.

[0120] In a specific example, the following combination Figure 7 The working process of the first group of data ports and the second group of data ports is described as follows:

[0121] S201: Control the first group of data ports and the second group of data ports to be initially in a high impedance state.

[0122] S202: Receive a first target instruction sent from the outside; take the receipt of the first target instruction as the timing starting point, and after an interval of a first preset time, use the first group of data ports to output first duty cycle data, and the first duty cycle data continues to exist on the first group of data ports.

[0123] S203: receiving a second target instruction sent externally; taking the receipt of the second target instruction as the timing starting point, after an interval of a third preset time, using the second group of data ports to output second duty cycle data, and the second duty cycle data continues to exist in the second group of data ports; wherein the second target instruction is later than the first target instruction.

[0124] S204: Taking the receipt of the first end instruction as the timing start point, after a second preset time interval, control the first group of data ports to return to a high impedance state.

[0125] S205: Taking the receipt of the second end instruction as the timing start point, after a fourth preset time period, control the second group of data ports to return to a high impedance state.

[0126] Here, the first preset duration and the third preset duration may be the same or different, the second preset duration and the fourth preset duration may be the same or different, the first preset duration and the second preset duration may be the same or different, and the third preset duration and the fourth preset duration may be the same or different. The execution order of the above steps is only an example. In actual scenarios, different steps are not necessarily executed in the above order, and may be intertwined or executed simultaneously.

[0127] In a specific embodiment, the first target instruction is a duty cycle flip detection instruction MRW-DCM Flip 1; the second target instruction is a duty cycle flip detection output instruction MRW-DCM Flip 0; the first end instruction and the second end instruction are the same duty cycle detection end instruction MRW-DCM stop, the first preset time length, the second preset time length, the third preset time length and the fourth preset time length are the same and are expressed as tDCMO, the first group of data ports are expressed as DQ2, and the second group of data ports are expressed as DQ3. Please refer to Figure 8 , which shows a signal timing diagram provided by an embodiment of the present disclosure. Figure 8 As shown:

[0128] (1) The initial state of DQ2 and DQ3 is high-impedance state High-Z, that is, no valid signal is transmitted on them;

[0129] (2) After the memory receives MRW-DCM start, the internal data clock signal WCK1 is subjected to duty cycle detection, assuming that the first duty cycle data obtained is 1;

[0130] (3) After the memory receives MRW-DCM Flip1, after tDCMO (for example, 2us) has passed since the MRW-DCM Flip 1 was received, DQ2 continues to output a high-level signal (i.e., the first duty cycle data); at the same time, MRW-DCM Flip1 also instructs to perform duty cycle detection on WCK1 again, assuming that the obtained second duty cycle data is also 1;

[0131] (4) After the memory receives MRW-DCM Flip0, DQ3 outputs a high-level signal (i.e., the second duty cycle data) after tDCMO (e.g., 2 us) has passed since the MRW-DCM Flip0 was received;

[0132] (4) After the memory receives the duty cycle detection end instruction (MRW-DCM stop), after an interval of tDCMO, DQ2 and DQ3 return to the high-impedance state High-Z, thereby completing the measurement and output of the duty cycle data.

[0133] For the convenience of explanation, the moment when the MRW-DCM Flip 1 instruction is received is recorded as TA, the moment when the MRW-DCMFlip0 instruction is received is recorded as TB, and the moment when the MRW-DCM stop instruction is received is recorded as TC. Then, in the time period of (TA+tDCMO)~(TC+tDCMO), DQ2 continuously outputs the first duty cycle data; in the time period of (TB+tDCMO)~(TC+tDCMO), DQ3 continuously outputs the second duty cycle data. In this way, since the first duty cycle data and the second duty cycle data are each continuously output for a long time, the SoC can use its own internal clock signal for sampling, so the memory does not need to output RDQS, that is, the RDQS port clock is in the high-impedance state High-Z.

[0134] In addition, the specific positions of the first group of data ports and the second group of data ports are not limited. For an 8-bit memory, the first group of data ports and the second group of data ports can be any two data ports from DQ0 to DQ7; for a 16-bit memory, the first group of data ports and the second group of data ports can be any two data ports from DQ0 to DQ15; and are not limited to DQ2 to DQ5 in the above scenario.

[0135] In some embodiments, the method further comprises:

[0136] Receiving a duty cycle adjustment instruction sent externally, and adjusting the duty cycle of the internal data clock signal based on the duty cycle adjustment instruction;

[0137] Receiving a duty cycle start detection instruction, a duty cycle flip detection instruction, a duty cycle flip detection output instruction, and a duty cycle detection end instruction in sequence;

[0138] Continue to receive the next duty cycle adjustment instruction, the next duty cycle start detection instruction, the next duty cycle flip detection instruction, the next duty cycle flip detection output instruction and the next duty cycle detection end instruction sent from the outside until the duty cycle adjustment of the internal data clock signal is completed. Here, the duty cycle adjustment instruction is an instruction issued by the SoC to instruct the memory to adjust the duty cycle of the low-order data clock signal and / or the high-order data clock signal.

[0139] It should be noted that the SoC will confirm whether the duty cycle of the low-order data clock signal of the memory has been adjusted based on multiple consecutive first duty cycle data. After the adjustment is completed, the SoC will no longer issue the corresponding duty cycle adjustment instruction. Similarly, the SoC will confirm whether the duty cycle of the high-order data clock signal has been adjusted based on multiple consecutive second duty cycle data received. After the adjustment is completed, the SoC will no longer issue the corresponding duty cycle adjustment instruction.

[0140] In another specific scenario, for a higher-speed memory, the synchronously output data signal DQ has a larger number of bits, which can generally be divided into a high-order data signal DQH and a low-order data signal DQL; accordingly, the internal data clock signal WCK1 includes two independent clock signals, namely, a low-order data clock signal LWCK (which can be expressed as a single signal or a pair of differential signals LWCK_t and LWCK_c at different circuit positions) and a high-order data clock signal (which can be expressed as a single signal or a pair of differential signals HWCK_t and HWCK_c at different circuit positions), all low-order data signals share the low-order data clock signal LWCK, and all high-order data signals share the high-order data clock signal HWCK.

[0141] For example, for a 16-bit memory, it can synchronously output 16-bit data signals DQ[15:0], where DQ[7:0] are all low-order data signals and need to be generated based on the low-order data clock signal LWCK; DQ[15:8] are all high-order data signals and need to be generated based on the high-order data clock signal HWCK.

[0142] Accordingly, the method further includes:

[0143] Receive a low-order external data clock signal (specifically, it can be a single-ended signal or a pair of differential signals) and a high-order external data clock signal (specifically, it can be a single-ended signal or a pair of differential signals) sent from the outside (SoC); generate a low-order data clock signal LWCK based on the low-order external data clock signal; generate a high-order data clock signal HWCK based on the high-order external data clock signal.

[0144] At this time, the first duty cycle data includes a first low-order duty value and a first high-order duty value, the first low-order duty value is used to indicate the duty cycle of the low-order data clock signal, and the first high-order duty value is used to indicate the duty cycle of the high-order data clock signal.

[0145] The memory further includes a first detection circuit and a second detection circuit. The aforementioned step S102 may specifically include:

[0146] A low-order data clock signal (e.g., LWCK_t) is transmitted to a first input terminal (S1) of a first detection circuit, a complementary signal of the low-order data clock signal (e.g., LWCK_c) is transmitted to a second input terminal (S2) of the first detection circuit, and a first low-order duty value is obtained from an output terminal of the first detection circuit; and a high-order data clock signal (e.g., HWCK_t) is transmitted to a first input terminal (S1) of a second detection circuit, a complementary signal of the high-order data clock signal (e.g., HWCK_c) is transmitted to a second input terminal (S2) of the second detection circuit, and a first high-order duty value is obtained from an output terminal of the second detection circuit.

[0147] It should be noted that the first detection circuit, the second detection circuit and the aforementioned detection circuit have the same principle.

[0148] Meanwhile, since the first duty cycle data and the second duty cycle data each include a 2-bit signal, the first group of data ports and the second group of data ports each need to include 2 data ports.

[0149] In summary, the embodiments of the present disclosure provide a signal transmission method applied to a memory, which, after performing duty cycle detection on an internal data clock signal, outputs the detection result through a corresponding data port based on a first target instruction subsequently received, and maintains it in the corresponding data port, without the need for additional storage in a mode register and then reading it out through an MRR instruction, thereby saving the number of instructions and simplifying the interaction process; at the same time, since the detection result will be maintained in the data port for a considerable period of time, there is no need to provide a selection clock signal, thereby avoiding the problem of the control device being unable to sample the detection result due to distortion of the selection clock signal, thereby ensuring the correctness of the duty cycle detection.

[0150] In another embodiment of the present disclosure, to implement the above-mentioned signal transmission method, see Fig. 9, which shows a schematic diagram of the structure of a memory 30 provided by an embodiment of the present disclosure. Fig. 9 As shown, the memory 30 includes:

[0151] The duty cycle detection circuit 31 is configured to perform a duty cycle detection on the internal data clock signal WCK1 to generate first duty cycle data;

[0152] The transmission circuit 32 is connected to the duty cycle detection circuit 31 and the first group of data ports 331 of the memory 30, respectively, and is configured to receive a first target instruction sent from the outside, receive first duty cycle data based on the first target instruction, and transmit the first duty cycle data to the first group of data ports 331. The first duty cycle data is maintained in the first group of data ports 331 at least until the memory 30 receives a first end instruction sent from the outside.

[0153] It should be noted that in Fig. 9 In the figure, the transmission circuit 32 is only a simple illustration, but in fact the transmission circuit 32 may include a variety of circuit devices such as a signal selector, a driver, a three-state output gate, etc., and may also combine certain lines by multiplexing to simplify the circuit structure.

[0154] In some embodiments, the duty cycle detection circuit 31 is specifically configured to receive a duty cycle start detection instruction sent externally, perform a duty cycle detection on the internal data clock signal WCK1 based on the duty cycle start detection instruction, and generate first duty cycle data.

[0155] In some embodiments, the first group of data ports 331 are initially in a high impedance state;

[0156] The transmission circuit 32 is specifically configured to receive a first target instruction sent from the outside, take the receipt of the first target instruction as the timing starting point, and after a first preset time interval, transmit the first duty cycle data to the first group of data ports 331, and the first duty cycle data continues to exist in the first group of data ports; and receive a first end instruction sent from the outside, take the receipt of the first end instruction as the timing starting point, and after a second preset time interval, control the first group of data ports 331 to restore the high impedance state. In some embodiments, Fig. 9 As shown, the duty cycle detection circuit 31 is further configured to receive a first target instruction, and based on the first target instruction, perform another duty cycle detection on the internal data clock signal to generate second duty cycle data;

[0157] The transmission circuit 32 is also configured to receive a second target instruction sent externally, receive second duty cycle data based on the second target instruction, and transmit the second duty cycle data to the second group of data ports 332; wherein the second duty cycle data persists in the second group of data ports 332 at least until the memory 30 receives a second end instruction sent externally.

[0158] Specifically, the second group of data ports 332 are initially in a high impedance state;

[0159] The transmission circuit 32 is specifically configured to receive a second target instruction sent from the outside, take the receipt of the second target instruction as the timing starting point, and after an interval of a third preset time, transmit the second duty cycle data to the second group of data ports 332, and the second duty cycle data continues to exist in the second group of data ports; wherein the second target instruction is later than the first target instruction; and, receive a second end instruction sent from the outside, take the receipt of the second end instruction as the timing starting point, and after an interval of a fourth preset time, control the second group of data ports 332 to restore to a high-impedance state.

[0160] In some embodiments, the memory 30 further includes: a clock processing circuit configured to receive an external data clock signal WCK0 sent from the outside, and generate an internal data clock signal WCK1 based on the external data clock signal WCK0 .

[0161] In a specific possibility, there is only one internal data clock signal WCK1 in the memory (which can be expressed as a single signal or a pair of differential signals WCK_t and WCK_c in different circuit positions), and all data signals DQ share this internal data clock signal WCK1. At this time, the external data clock signal WCK0 sent by the SoC is also a signal, which can be a single-ended signal or a pair of differential signals.

[0162] At this time, if Fig.10 As shown, the duty cycle detection circuit 31 includes a control circuit 311 and a detection circuit 312;

[0163] The detection circuit 311 is configured to perform duty cycle detection on the clock signal at its first input terminal and the clock signal at its second input terminal;

[0164] The control circuit 312 is configured to receive the internal data clock signal and its complementary signal; based on the received duty cycle start detection instruction, the internal data clock signal WCK_t is output to the first input terminal (S1) of the detection circuit 312 and the complementary signal WCK_c of the internal data clock signal is output to the second input terminal (S2) of the detection circuit 312, so that the detection circuit 312 outputs the first duty cycle data; or,

[0165] Based on the received first target instruction, the internal data clock signal WCK_t is output to the second input terminal (S2) of the detection circuit 312 and the complementary signal WCK_c of the internal data clock signal is output to the first input terminal (S1) of the detection circuit 312, so that the detection circuit 312 outputs the second duty cycle data.

[0166] Exemplarily, the control circuit 311 specifically includes a preprocessing circuit and two two-to-one data selectors. The preprocessing circuit outputs four selection signals, Sel1 and Sel1B, according to whether a duty cycle start detection instruction and a duty cycle flip detection instruction are received. The levels of Sel1 and Sel1B are complementary. For the first data selector, its two input ends receive WCK_c and WCK_t respectively, the selection end receives Sel1, and the output end is connected to the first input end (S1) of the detection circuit 312. For the second data selector, its two input ends receive WCK_c and WCK_t respectively, the selection end receives Sel1B, and the output end is connected to the second input end (S2) of the detection circuit 312.

[0167] See also Fig.11 In (a), after the SoC issues a duty cycle start detection instruction, Sel1=1, Sel1B=0, for the detection circuit 312, its first input terminal (S1) receives WCK_t, its second input terminal (S2) receives WCK_c, and its positive phase output terminal (Q) outputs the first duty cycle data to the data port DQ2;

[0168] See also Fig.11 In (b), after the SoC issues the first target instruction, Sel1=0, Sel1B=1, for the detection circuit 312, its first input terminal (S1) receives WCK_c, its second input terminal (S2) receives WCK_t, and its inverting output terminal ( / Q) outputs the second duty cycle data to the data port DQ3.

[0169] In a specific embodiment, the first target instruction is a duty cycle reversal detection instruction; the second target instruction is a duty cycle reversal detection output instruction; the first end instruction and the second end instruction are the same duty cycle detection end instruction.

[0170] In another working scenario, the internal data clock signal WCK1 includes a low data clock signal LWCK and a high data clock signal HWCK; that is, the memory 30 receives the external data clock signal WCK0 from the SoC, and then generates a low data clock signal LWCK and a high data clock signal HWCK.

[0171] Correspondingly, the first duty cycle data includes a first low duty value and a first high duty value; the second duty cycle data includes a second low duty value and a second high duty value.

[0172] Correspondingly, the duty cycle detection circuit 31 includes a control circuit 311, a first detection circuit and a second detection circuit. The functions of the first detection circuit and the second detection circuit are the same, namely: the first detection circuit is configured to perform duty cycle detection on the clock signal at its first input terminal and the clock signal at its second input terminal; the second detection circuit is configured to perform duty cycle detection on the clock signal at its first input terminal and the clock signal at its second input terminal.

[0173] The control circuit 311 is configured to receive the low-order data clock signal and its complementary signal (see Fig.10 LWCK_c / LWCK_t in), high-order data clock signal and its complementary signal (please refer to Fig.10 ; based on the received duty cycle start detection instruction, output the low-order data clock signal LWCK_t to the first input terminal (S1) of the first detection circuit and output the complementary signal LWCK_c of the low-order data clock signal to the second input terminal (S2) of the first detection circuit, so that the first detection circuit outputs a first low-order duty value; and, output the high-order data clock signal HWCK_t to the first input terminal (S1) of the second detection circuit and output the complementary signal HWCK_c of the high-order data clock signal to the second input terminal (S2) of the second detection circuit, so that the second detection circuit outputs a first high-order duty value;

[0174] The control circuit 311 is also configured to output the low-order data clock signal LWCK_t to the second input terminal (S2) of the first detection circuit and the complementary signal LWCK_c of the low-order data clock signal to the first input terminal (S1) of the first detection circuit based on the received duty cycle flip detection instruction, so that the first detection circuit outputs a second low-order duty value; and output the high-order data clock signal HWCK_t to the second input terminal (S2) of the second detection circuit and the complementary signal HWCK_c of the high-order data clock signal to the first input terminal (S1) of the second detection circuit, so that the second detection circuit outputs a second high-order duty value.

[0175] In summary, the embodiments of the present disclosure provide a memory which, after performing duty cycle detection on an internal data clock signal, outputs the detection result through a corresponding data port based on a first target instruction subsequently received, and maintains the result in the corresponding data port, without the need for additional storage in a mode register and then reading it out through an MRR instruction, thereby saving the number of instructions and simplifying the interaction process; at the same time, since the detection result will be maintained in the data port for a considerable period of time, there is no need to provide a selection clock signal, thereby avoiding the problem of the control device being unable to sample the detection result due to distortion of the selection clock signal, thereby ensuring the correctness of the duty cycle detection.

[0176] In yet another embodiment, see Fig.12, which shows a schematic diagram of the process of another information transmission method provided by an embodiment of the present disclosure Figure 1 The information transmission method may be applied to a control device (which may be referred to as a SoC) which is connected to the aforementioned memory.

[0177] The information transmission method is specifically applied to the process of the memory adjusting the duty cycle of the internal data clock signal. In simple terms, the SoC generates an external data clock signal WCK0 and transmits the external data clock signal WCK0 to the memory. The memory generates an internal data clock signal WCK1 according to the received external data clock signal WCK0 and adjusts the duty cycle of the internal data clock signal WCK1. After each duty cycle adjustment of the memory, the SoC needs to know the duty cycle information of the adjusted internal data clock signal WCK1 in the memory.

[0178] like Fig.12 As shown, the information transmission method includes:

[0179] S411: In the duty cycle adjustment mode, sending a first target instruction to the memory.

[0180] It should be noted that, for step S401, "in the duty cycle adjustment mode" can be regarded as a usage scenario rather than a limiting feature. That is, when the SoC generates and sends a duty cycle start detection instruction to the memory, the SoC can be regarded as being in the duty cycle adjustment mode, and it is not necessary for the SoC to enter the duty cycle adjustment mode through a physical behavior and then send the duty cycle start detection instruction to the memory.

[0181] S412: After sending the first target instruction, use the internal clock signal to perform signal sampling on the first group of data ports of the memory to obtain first duty cycle data.

[0182] It should be noted that the internal clock signal refers to a clock signal generated inside the control device via an oscillator or a similar module, which will be hereinafter represented as CLKIn.

[0183] S413: Send a first end instruction to the memory.

[0184] In some embodiments, Fig.13 As shown, before step S411, the method further includes:

[0185] S401: Send a duty cycle start detection instruction to the memory; wherein the duty cycle start detection instruction instructs the memory to perform a duty cycle detection on an internal data clock signal to generate first duty cycle data.

[0186] In this way, after the SoC sends the duty cycle start detection instruction to the memory, as mentioned above, the memory will transmit the first duty cycle data on the first group of data ports and maintain it for a period of time. Correspondingly, the SoC can use its own internal clock signal CLKIn to sample the first group of data ports of the memory to obtain the correct first duty cycle data.

[0187] In some embodiments, the first target instruction further instructs the memory to perform another duty cycle detection on the internal data clock signal to generate second duty cycle data. Fig.13 As shown, after step S412, the method further includes:

[0188] S421: Sending a second target instruction to the memory;

[0189] S422: After sending the second target instruction, use the internal clock signal to perform signal sampling on the second group of data ports of the memory to obtain second duty cycle data;

[0190] S423: Send a second end instruction to the memory.

[0191] In some embodiments, step S412 specifically includes: sending a first target instruction to the memory, taking the sending of the first target instruction as the timing starting point, and after an interval of a fifth preset time, using the internal clock signal to sample the first group of data ports of the memory to obtain first duty cycle data.

[0192] Similarly, step S422 specifically includes: sending a second target instruction to the memory, taking the sending of the second target instruction as the timing starting point, and after an interval of a sixth preset time length, using the internal clock signal to sample the second group of data ports of the memory to obtain second duty cycle data.

[0193] It should be noted that the fifth preset time length is at least greater than the first preset time length, and the sixth preset time length is at least greater than the third preset time length.

[0194] In a specific embodiment, the first target instruction is a duty cycle reversal detection instruction; the second target instruction is a duty cycle reversal detection output instruction; the first end instruction and the second end instruction are the same duty cycle detection end instruction.

[0195] In particular, if the first end instruction and the second end instruction are the same duty cycle detection end instruction, the method further includes: sending the duty cycle detection end instruction to the memory, so as to simultaneously send the first end instruction to the memory and send the second end instruction to the memory. That is, step S413 and step S423 are completed simultaneously through one action.

[0196] That is to say, the SoC only needs to send one duty cycle detection end instruction to the memory, and it can be regarded as the SoC sending the first end instruction and the second end instruction at the same time.

[0197] In some embodiments, the method further comprises:

[0198] Sending an external data clock signal WCK0 to the memory so that the memory generates an internal data clock signal WCK1 based on the external data clock signal WCK0;

[0199] The first duty cycle data indicates a result of the memory performing a duty cycle detection on the internal data clock signal, and the second duty cycle data indicates a result of the memory performing another duty cycle detection on the internal data clock signal.

[0200] In one scenario, there is only one internal data clock signal WCK1 in the memory (which can be expressed as a single signal or a pair of differential signals WCK_t and WCK_c in different circuit positions), and all data signals DQ share this internal data clock signal WCK1. At this time, the first duty cycle data and the second duty cycle data each include a 1-bit signal, and the first group of data ports and the second group of data ports each include 1 data port.

[0201] In another scenario, for a memory with a higher speed, the synchronously output data signal DQ has a larger number of bits, which can generally be divided into a high-order data signal DQH and a low-order data signal DQL; accordingly, the internal data clock signal WCK1 includes two independent clock signals, namely, a low-order data clock signal LWCK (which can be expressed as a single signal or a pair of differential signals LWCK_t and LWCK_c at different circuit positions) and a high-order data clock signal (which can be expressed as a single signal or a pair of differential signals HWCK_t and HWCK_c at different circuit positions), all low-order data signals share the low-order data clock signal LWCK, and all high-order data signals share the high-order data clock signal HWCK. At this time, the first duty cycle data and the second duty cycle data each include a 2-bit signal, and the first group of data ports and the second group of data ports each include 2 data ports.

[0202] In some embodiments, the method further comprises:

[0203] Based on the first duty cycle data and the second duty cycle data, determining whether the memory has completed the duty cycle adjustment of the internal data clock signal;

[0204] When the duty cycle of the internal data clock signal has not been adjusted, a duty cycle adjustment instruction is sent to the memory to instruct the memory to continue adjusting the duty cycle of the internal data clock signal;

[0205] Send the next duty cycle start detection instruction, the next duty cycle flip detection instruction, the next duty cycle flip detection output instruction and the next duty cycle detection end instruction to the memory.

[0206] Exemplarily, the process of duty cycle adjustment is as follows: when the SoC sends a duty cycle adjustment instruction to the memory, the memory increases / decreases the duty cycle of the WCK by a preset step size by increasing / decreasing the duty cycle adjustment code (the increase or decrease may be carried by the duty cycle adjustment instruction, or the duty cycle adjustment instruction may not be carried but is pre-designed by the memory); after each adjustment of the duty cycle adjustment code, the SoC will continue to send a duty cycle start detection instruction, a duty cycle flip detection instruction, a duty cycle flip detection output instruction and a duty cycle detection end instruction, thereby completing an adjustment cycle.

[0207] Please refer to Table 1, which provides an example adjustment scenario, as shown in Table 1. Specifically, when the duty cycle adjustment code = -1 gear, the first duty cycle data is flipped, and when the duty cycle adjustment code = +3 gear, the second duty cycle data is flipped, then the +1 gear (the middle value of -1 to +3) of the duty cycle adjustment code can be considered as the final value. At this time, after the duty cycle adjustment is completed, the SoC will also inform the memory of the final value of the duty cycle adjustment code so that the memory can lock the duty cycle adjustment code to the +1 gear.

[0208] In the above scenario, when the duty cycle adjustment code changes to the adjustment period corresponding to the +3 gear position, it can be considered that the adjustment of the low-order data clock signal LWCK is completed.

[0209] Table 1

[0210]

[0211]

[0212] In some embodiments, the method further comprises:

[0213] In the non-duty cycle adjustment mode, a strobe clock signal RDQS sent by the memory is received; and a signal sampling is performed on a data port of the memory based on the strobe clock signal RDQS.

[0214] It should be understood that after the duty cycle adjustment is completed and the normal working process begins, the memory needs to provide the selection clock signal RDQS while transmitting the data signal (with a faster transmission speed) through its own data port, and the SoC needs to use the received selection clock signal RDQS to sample the data port of the memory, so as to ensure the synchronization of sampling to obtain the correct data signal. However, during the duty cycle adjustment process, the data signal carrying the duty cycle data will last for a long time on the corresponding data port, so the SoC can use its own internal clock signal CLKIn for sampling without worrying about the sampling synchronization problem; at the same time, the memory does not need to send the selection clock signal RDQS (or send it but the SoC does not use it) during this process, so there is no need to worry about the distortion of the selection clock signal RDQS due to the duty cycle not being adjusted well.

[0215] The disclosed embodiment provides a signal transmission method applied to a control device. After a duty cycle start detection instruction / duty cycle flip detection instruction is sent to a memory, the data port of the memory is sampled using an internal clock signal CLKIn to obtain a duty cycle detection result. There is no need to use a selection clock signal RDQS provided by the memory for sampling, thereby avoiding the problem that the control device cannot sample the detection result due to distortion of the selection clock signal RDQS. This ensures the correctness of the duty cycle detection, saves the number of instructions, and simplifies the interaction process.

[0216] In yet another embodiment of the present disclosure, to implement the above-mentioned signal transmission method, see Fig.14 , which shows a schematic diagram of the structure of a control device 50 provided in an embodiment of the present disclosure. The control device 50 is connected to the memory 30, such as Fig.14 As shown, the control device 50 includes:

[0217] The instruction generating circuit 51 is configured to generate a first target instruction in the duty cycle adjustment mode, and send the first target instruction to the memory 30;

[0218] A clock circuit 52 configured to generate an internal clock signal CLKIn;

[0219] The selection circuit 53 is connected to the clock circuit 52 and the memory 30, and is configured to receive the duty cycle detection enable signal DCAEn, the internal clock signal CLKIn and the selection clock signal RDQS sent by the memory 30; when the duty cycle detection enable signal DCAEn indicates that the control device 50 is in the duty cycle adjustment mode, the internal clock signal CLKIn is output as the sampling clock signal SamCLK;

[0220] The sampling circuit 54 is connected to the selection circuit 53 and the data port of the memory 30, and is configured to use the sampling clock signal SamCLK to sample the first group of data ports ( Fig.14 The signals thereon are collectively referred to as DQ) and signal sampling is performed to obtain the first duty cycle data.

[0221] It should be noted that the clock circuit 52 can be implemented by various types of oscillators, the selection circuit 53 can be implemented by a two-to-one data selector, the sampling circuit 54 can be implemented by a D-type flip-flop, and the instruction generation circuit 51 can be implemented by a variety of logic devices.

[0222] It should also be noted that the first duty cycle data indicates the duty cycle of the internal data clock signal in the memory. In some embodiments, the clock circuit 52 is further configured to generate an external data clock signal WCK0; wherein the external data clock signal WCK0 is transmitted to the memory 30 to generate the internal data clock signal WCK1.

[0223] In some embodiments, the instruction generating circuit 51 is also configured to generate a duty cycle detection start instruction in the duty cycle adjustment mode, and send the duty cycle detection start instruction to the memory 30; the duty cycle detection start instruction instructs the memory to perform a duty cycle detection on the internal data clock signal to obtain the aforementioned first duty cycle data.

[0224] In some embodiments, Fig.14 As shown, the sampling circuit 54 is also configured to use the sending of the first target instruction as the timing starting point, and after an interval of the fifth preset time, use the sampling clock signal (actually the internal clock signal CLKIn) to sample the signals of the first group of data ports of the memory to obtain the first duty cycle data.

[0225] In some embodiments, the instruction generation circuit 51 is further configured to generate a second target instruction after sending the first target instruction, and send the second target instruction to the memory;

[0226] The sampling circuit 54 is further configured to use the sending of the second target instruction as the timing starting point, and after a sixth preset time interval, use the sampling clock signal (actually the internal clock signal CLKIn) to sample the second group of data ports of the memory to obtain second duty cycle data.

[0227] Exemplarily, the first target instruction is a duty cycle reversal detection instruction; the second target instruction is a duty cycle reversal detection output instruction.

[0228] In some embodiments, the instruction generation circuit 51 is further configured to generate a first end instruction and send the first end instruction to the memory 30 ; and to generate a second end instruction and send the second end instruction to the memory 30 .

[0229] Exemplarily, the first end instruction and the second end instruction may be the same duty cycle end detection instruction.

[0230] In some embodiments, the selection circuit 53 is further configured to output the strobe clock signal RDQS as the sampling clock signal SamCLK when the duty cycle detection enable signal DCA En indicates that the control device 50 is not in the duty cycle adjustment mode.

[0231] In this way, in the non-duty cycle adjustment mode, the sampling circuit 54 actually uses the selection clock signal RDQS to sample the signal on the data port of the memory; however, in the duty cycle adjustment mode, the sampling circuit 54 actually uses the internal clock signal CLKIn to sample the signal on the data port of the memory, avoiding the problem of sampling errors caused by the distortion of the selection clock signal RDQS.

[0232] In yet another embodiment of the present disclosure, see Fig.15 , which shows a schematic diagram of the structure of an electronic device 60 provided by an embodiment of the present disclosure. Fig.15 As shown, the electronic device 60 at least includes the aforementioned memory 30 and the aforementioned control device 50 .

[0233] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure. It should be noted that in the present disclosure, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such a process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes one..." does not exclude the presence of other identical elements in the process, method, article or device including the element. The above serial numbers of the embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An information transmission method, characterized in that: Applied to a memory, the method comprises: receiving a first target instruction sent externally; Based on the first target instruction, the first duty cycle data of the internal data clock signal is output through the first group of data ports, and the first duty cycle data continues in the first group of data ports at least until a first end instruction sent externally is received.

2. The information transmission method according to claim 1, characterized in that: Before receiving the first target instruction sent externally, the method further includes: Receive the duty cycle start detection instruction sent externally; Based on the duty cycle start detection instruction, a duty cycle detection is performed on the internal data clock signal to generate the first duty cycle data.

3. The information transmission method according to claim 1, characterized in that: The method further comprises: Controlling the first group of data ports to be initially in a high impedance state; Receive the first target instruction sent from the outside; take the receipt of the first target instruction as the timing starting point, and after a first preset time interval, use the first group of data ports to output the first duty cycle data, and the first duty cycle data continues to exist on the first group of data ports; The receipt of the first end instruction is taken as a timing start point, and after a second preset time interval, the first group of data ports is controlled to return to a high-impedance state.

4. The information transmission method according to claim 1, characterized in that: The method further comprises: Based on the first target instruction, another duty cycle detection is performed on the internal data clock signal to generate second duty cycle data; Receive a second target instruction sent externally; based on the second target instruction, output the second duty cycle data through a second group of data ports, and the second duty cycle data continues in the second group of data ports at least until a second end instruction sent externally is received.

5. The information transmission method according to claim 4, characterized in that: The method further comprises: Controlling the second group of data ports to be initially in a high impedance state; Receive the second target instruction sent from the outside; take the receipt of the second target instruction as the timing starting point, and after a third preset time interval, use the second group of data ports to output the second duty cycle data, and the second duty cycle data continues to exist in the second group of data ports; wherein the second target instruction is later than the first target instruction; The receipt of the second end instruction is used as a timing start point, and after a fourth preset time period, the second group of data ports is controlled to return to a high-impedance state.

6. The information transmission method according to any one of claims 4 to 5, characterized in that: The first target instruction is a duty cycle reversal detection instruction; the second target instruction is a duty cycle reversal detection output instruction; the first end instruction and the second end instruction are the same duty cycle detection end instruction.

7. An information transmission method, characterized in that: Applied to a control device, the control device is connected to a memory, and the information transmission method includes: In a duty cycle adjustment mode, sending a first target instruction to the memory; After sending the first target instruction, sampling the first group of data ports of the memory using an internal clock signal to obtain first duty cycle data; wherein the internal clock signal refers to a clock signal generated inside the control device; A first end instruction is sent to the memory.

8. The information transmission method according to claim 7, characterized in that: Before sending the first target instruction to the memory, the method further includes: Sending a duty cycle start detection instruction to the memory; The duty cycle start detection instruction instructs the memory to perform a duty cycle detection on the internal data clock signal to generate the first duty cycle data.

9. The information transmission method according to claim 7, characterized in that: The method of sampling the first group of data ports of the memory using the internal clock signal to obtain first duty cycle data includes: A first target instruction is sent to the memory, and the sending of the first target instruction is used as a timing starting point. After a fifth preset time interval, the first group of data ports of the memory are sampled using the internal clock signal to obtain first duty cycle data.

10. The information transmission method according to claim 8, characterized in that: The first target instruction further instructs the memory to perform another duty cycle detection on the internal data clock signal to generate second duty cycle data; After sending the first target instruction to the memory, the method further includes: sending a second target instruction to the memory; After sending the second target instruction, sampling the second group of data ports of the memory using the internal clock signal to obtain second duty cycle data; A second end instruction is sent to the memory.

11. The information transmission method according to claim 10, characterized in that: The method of sampling the second group of data ports of the memory using the internal clock signal to obtain second duty cycle data includes: A second target instruction is sent to the memory, and the sending of the second target instruction is used as a timing starting point. After a sixth preset time interval, the second group of data ports of the memory are sampled using the internal clock signal to obtain second duty cycle data.

12. The information transmission method according to claim 11, characterized in that: The first target instruction is a duty cycle reversal detection instruction; the second target instruction is a duty cycle reversal detection output instruction; the first end instruction and the second end instruction are the same duty cycle detection end instruction.

13. The information transmission method according to any one of claims 7 to 12, characterized in that: The method further comprises: In a non-duty cycle adjustment mode, receiving a gate clock signal sent by the memory; A signal is sampled on a data port of the memory based on the selection clock signal.

14. A memory, characterized in that: The memory comprises: A duty cycle detection circuit is configured to perform a duty cycle detection on an internal data clock signal to generate first duty cycle data; a transmission circuit, connected to the duty cycle detection circuit and the first group of data ports of the memory respectively, configured to receive a first target instruction sent from the outside, receive the first duty cycle data based on the first target instruction, and transmit the first duty cycle data to the first group of data ports; The first duty cycle data persists in the first group of data ports at least until the memory receives a first end instruction sent externally.

15. The memory according to claim 14, characterized in that: The duty cycle detection circuit is specifically configured to receive a duty cycle start detection instruction sent from the outside; based on the duty cycle start detection instruction, perform a duty cycle detection on the internal data clock signal to generate the first duty cycle data; The first group of data ports is initially in a high impedance state; The transmission circuit is specifically configured to receive a first target instruction sent from the outside, take the receipt of the first target instruction as the timing starting point, and after a first preset time interval, transmit the first duty cycle data to the first group of data ports, and the first duty cycle data continues to exist in the first group of data ports; And, receiving the first end instruction sent from the outside, taking the receipt of the first end instruction as the timing starting point, and after an interval of a second preset time, controlling the first group of data ports to restore to a high-impedance state.

16. The memory according to claim 14, characterized in that: The duty cycle detection circuit is further configured to receive the first target instruction, and based on the first target instruction, perform another duty cycle detection on the internal data clock signal to generate second duty cycle data; The transmission circuit is further configured to receive a second target instruction sent from the outside, receive the second duty cycle data based on the second target instruction, and transmit the second duty cycle data to the second group of data ports; The second duty cycle data lasts in the second group of data ports at least until the memory receives a second end instruction sent externally.

17. The memory according to claim 16, characterized in that: The second group of data ports is initially in a high impedance state; The transmission circuit is specifically configured to receive a second target instruction sent from the outside, take the receipt of the second target instruction as the timing starting point, and after a third preset time interval, transmit the second duty cycle data to the second group of data ports, and the second duty cycle data continues to exist in the second group of data ports; wherein the second target instruction is later than the first target instruction; as well as, The second end instruction sent from the outside is received, and the receiving of the second end instruction is used as a timing starting point. After a fourth preset time interval, the second group of data ports is controlled to return to a high-impedance state.

18. The memory according to claim 17, characterized in that: The duty cycle detection circuit includes a control circuit and a detection circuit; The detection circuit is configured to perform duty cycle detection on the clock signal at its first input terminal and the clock signal at its second input terminal; the control circuit is configured to receive the internal data clock signal and its complementary signal; based on the received duty cycle start detection instruction, the internal data clock signal is output to the first input terminal of the detection circuit and the complementary signal of the internal data clock signal is output to the second input terminal of the detection circuit, so that the detection circuit outputs the first duty cycle data; or, Based on the first target instruction received, the internal data clock signal is output to the second input terminal of the detection circuit and the complementary signal of the internal data clock signal is output to the first input terminal of the detection circuit, so that the detection circuit outputs the second duty cycle data, so that the detection circuit outputs the second duty cycle data.

19. The memory according to claim 17 or 18, characterized in that: The first target instruction is a duty cycle reversal detection instruction; the second target instruction is a duty cycle reversal detection output instruction; the first end instruction and the second end instruction are the same duty cycle detection end instruction.

20. A control device, characterized in that: Connected to the memory, the control device comprises: An instruction generating circuit is configured to generate a first target instruction in a duty cycle adjustment mode, and send the first target instruction to the memory; a clock circuit configured to generate an internal clock signal; a selection circuit connected to the clock circuit and the memory, and configured to receive a duty cycle detection enable signal, the internal clock signal, and a gated clock signal sent by the memory; and output the internal clock signal as a sampling clock signal when the duty cycle detection enable signal indicates that the control device is in a duty cycle adjustment mode; The sampling circuit is connected to the selection circuit and the data port of the memory, and is configured to perform signal sampling on the first group of data ports using the sampling clock signal after sending the first target instruction to obtain first duty cycle data.

21. The control device according to claim 20, characterized in that: The sampling circuit is specifically configured to use the sending of the first target instruction as a timing starting point, and after an interval of a fifth preset time, use the sampling clock signal to sample signals on the first group of data ports of the memory to obtain first duty cycle data.

22. The control device according to claim 20, characterized in that: The instruction generation circuit is further configured to generate a second target instruction after sending the first target instruction, and send the second target instruction to the memory; The sampling circuit is further configured to use the sending of the second target instruction as a timing starting point, and after a sixth preset time interval, use the internal clock signal to perform signal sampling on the second group of data ports of the memory to obtain second duty cycle data.

23. The control device according to claim 22, characterized in that: The first target instruction is a duty cycle reversal detection instruction; the second target instruction is a duty cycle reversal detection output instruction.

24. The control device according to any one of claims 20 to 23, characterized in that: The selection circuit is further configured to output the gated clock signal as a sampling clock signal when the duty cycle detection enable signal indicates that the control device is not in a duty cycle adjustment mode.

25. An electronic device, characterized in that: The electronic device comprises the memory according to any one of claims 14 to 19 and the control device according to any one of claims 20 to 24.

Images