Memory device, operating method thereof, memory system, and storage medium

Abstract

The embodiment of the invention provides a memory device and an operation method thereof, a memory system and a storage medium. The memory device comprises a memory cell array and a peripheral circuit. The memory cell array comprises a plurality of memory blocks; each storage block comprises a plurality of storage units and a plurality of word lines; the peripheral circuit is configured to apply a first pass voltage on the first word line, a second pass voltage on the second word line, and a third pass voltage on the third word line when a first read operation is performed on a memory cell coupled to a selected word line; the first word lines are at least one word line which is physically located above and below the selected word line respectively; the second word line and the third word line are both word lines which are physically located on the side, away from the selected word line, of the first word line, the storage unit coupled to the second word line is a programmed storage unit, and the storage unit coupled to the third word line is an unprogrammed storage unit; the first passing voltage, the second passing voltage and the third passing voltage are different.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a memory device and an operating method thereof, a memory system, and a storage medium. Background Art

[0002] Non-volatile memory devices with low power consumption, light weight and good performance, such as 3D NAND memory, have been widely used in electronic products. However, in the related art, there are still many problems to be solved when performing a read operation on the memory device. Summary of the invention

[0003] In order to solve one or more of the existing technical problems, the embodiments of the present disclosure provide a memory device and an operation method thereof, a memory system, and a storage medium. The embodiments of the present disclosure provide a memory device, comprising: a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array comprises a plurality of memory blocks; each of the memory blocks comprises a plurality of memory cells and a plurality of word lines coupled to the plurality of memory cells.

[0004] The peripheral circuit is configured as follows: when performing a first read operation on a memory cell coupled to a selected word line, a first pass voltage is applied to a first word line, a second pass voltage is applied to a second word line, and a third pass voltage is applied to a third word line; the first word line is at least one word line physically located above and below the selected word line; the second word line and the third word line are both word lines physically located on a side of the first word line away from the selected word line, the memory cell coupled to the second word line is a programmed memory cell, and the memory cell coupled to the third word line is an unprogrammed memory cell; the first pass voltage, the second pass voltage, and the third pass voltage are all different.

[0005] In some embodiments, the first pass voltage is greater than the second pass voltage; and the second pass voltage is greater than the third pass voltage.

[0006] In some embodiments, the peripheral circuit is further configured to: perform storage status detection on a selected storage block; the storage status detection result includes a full storage block and an incomplete storage block; perform the first read operation on the storage cell coupled to the selected word line in the incomplete storage block; and perform the second read operation on the storage cell coupled to the selected word line in the full storage block.

[0007] In some embodiments, the peripheral circuit is further configured to: apply the first pass voltage to the fourth word line and apply the second pass voltage to the fifth word line when performing the second read operation on the memory cell coupled to the selected word line in the full memory block; the fourth word line is at least one word line physically located above and below the selected word line; the fifth word line is all word lines physically located on the side of the fourth word line away from the selected word line.

[0008] In some embodiments, the peripheral circuit is further configured to: increase the read count by a first count value after executing the first read operation once; increase the read count by a second count value after executing the second read operation once; and the first count value is smaller than the second count value.

[0009] In some embodiments, when the first word line and the third word line are the same word line, the first pass voltage is applied to the same word line.

[0010] In some embodiments, a dummy word line is provided between at least any two of the first word line, the second word line, and the third word line; and the peripheral circuit is further configured to apply the second pass voltage to the dummy word line when performing the first read operation.

[0011] In some embodiments, the peripheral circuit is further configured to: apply a read voltage to the selected word line during the execution of the first read operation; wherein the memory cell coupled to the selected word line is a programmed memory cell.

[0012] In some embodiments, the memory device comprises a three-dimensional NAND-type memory.

[0013] An embodiment of the present disclosure further provides a memory system, comprising: one or more memory devices as described in the above embodiments of the present disclosure; and a memory controller coupled to the memory device for controlling the memory device.

[0014] The present disclosure also provides an operation method of a memory device, the operation method comprising: when performing a first read operation on a memory cell coupled to a selected word line, applying a first pass voltage to a first word line, applying a second pass voltage to a second word line, and applying a third pass voltage to a third word line; the first word line is at least one word line physically located above and below the selected word line; the second word line and the third word line are both word lines physically located on a side of the first word line away from the selected word line, the memory cell coupled to the second word line is a programmed memory cell, and the memory cell coupled to the third word line is an unprogrammed memory cell; the first pass voltage, the second pass voltage, and the third pass voltage are all different;

[0015] The memory device includes a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array includes a plurality of memory blocks; each of the memory blocks includes a plurality of memory cells and a plurality of word lines coupled to the plurality of memory cells.

[0016] In some embodiments, the first pass voltage is greater than the second pass voltage; and the second pass voltage is greater than the third pass voltage.

[0017] In some embodiments, the operating method also includes: performing storage status detection on a selected storage block; the storage status detection result includes a full storage block and an incomplete storage block; performing the first read operation on a storage cell coupled to a selected word line in the incomplete storage block; and performing a second read operation on a storage cell coupled to a selected word line in the full storage block.

[0018] In some embodiments, the operating method also includes: when performing the second read operation on the storage cell coupled to the selected word line in the full storage block, applying the first pass voltage on the fourth word line and applying the second pass voltage on the fifth word line; the fourth word line is at least one word line physically located above and below the selected word line; the fifth word line is all word lines physically located on the side of the fourth word line away from the selected word line.

[0019] In some embodiments, the operation method further includes: after executing the first read operation once, increasing the read count by a first count value; after executing the second read operation once, increasing the read count by a second count value; the first count value is less than the second count value.

[0020] In some embodiments, when the first word line and the third word line are the same word line, the first pass voltage is applied to the same word line.

[0021] In some embodiments, a dummy word line is provided between at least any two of the first word line, the second word line, and the third word line; and the operation method further comprises: applying the second pass voltage to the dummy word line when performing the first read operation.

[0022] In some embodiments, the operation method further includes: applying a read voltage to the selected word line during the execution of the first read operation; wherein the memory cell coupled to the selected word line is a programmed memory cell.

[0023] The embodiments of the present disclosure further provide a storage medium having executable instructions stored thereon. When the executable instructions are executed by a memory controller, the steps of the method described in the above embodiments of the present disclosure can be implemented.

[0024] The embodiment of the present disclosure provides a memory device and an operation method thereof, a memory system, and a storage medium. The memory device includes: a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array includes a plurality of memory blocks; each of the memory blocks includes a plurality of memory cells and a plurality of word lines coupled to the plurality of memory cells; the peripheral circuit is configured to: when performing a first read operation on a memory cell coupled to a selected word line, apply a first pass voltage to a first word line, apply a second pass voltage to a second word line, and apply a third pass voltage to a third word line; the first word line is at least one word line physically located above and below the selected word line; the second word line and the third word line are both word lines physically located on the side of the first word line away from the selected word line, the memory cell coupled to the second word line is a programmed memory cell, and the memory cell coupled to the third word line is an unprogrammed memory cell; the first pass voltage, the second pass voltage, and the third pass voltage are all different. In the embodiment of the present disclosure, when performing the first read operation, the first pass voltage is applied to the first word line adjacent to the selected word line to reduce the coupling effect of the read voltage on the adjacent word line. At the same time, applying the third turn-on voltage to the third word line coupled to the unprogrammed memory cell can reduce the read disturbance caused by the first read operation to the unprogrammed memory cell, thereby improving the read performance and reliability of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0026] Figure 2a A schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0027] Figure 2bA schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure;

[0028] Figure 3a A schematic diagram of the distribution of storage cells of a three-dimensional NAND memory according to an embodiment of the present disclosure;

[0029] Figure 3b A schematic diagram of an exemplary memory including a peripheral circuit according to an embodiment of the present disclosure;

[0030] Figure 4 A cross-sectional schematic diagram of a memory cell array including a NAND memory string according to an embodiment of the present disclosure;

[0031] Figure 5 A schematic diagram of an exemplary memory device including a memory cell array and a peripheral circuit according to an embodiment of the present disclosure;

[0032] Figure 6a A schematic diagram of a storage string in a full storage block provided by an embodiment of the present disclosure;

[0033] Figure 6b A schematic diagram of a storage string in an unfilled storage block provided by an embodiment of the present disclosure;

[0034] Figure 6c A schematic diagram of a storage string in another unfilled storage block provided by an embodiment of the present disclosure;

[0035] Figure 7 A schematic diagram of a flow chart of a method for performing a first read operation on an incomplete storage block provided by an embodiment of the present disclosure;

[0036] Figure 8 A schematic diagram of a storage string in another unfilled storage block provided by an embodiment of the present disclosure;

[0037] Figure 9a A schematic diagram of a voltage application condition when a first read operation is performed on an incomplete storage block provided by an embodiment of the present disclosure;

[0038] Figure 9b A schematic diagram of voltage application when a second read operation is performed on a fully written storage block provided by an embodiment of the present disclosure;

[0039] Fig.10 A schematic diagram of a read operation implementation flow of a memory device provided in an embodiment of the present disclosure.

[0040] In the above drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0041] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0042] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0043] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0044] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0045] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0046] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0047] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure.

[0048] The memory device in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND memory. For ease of understanding, the three-dimensional NAND memory is taken as an example for description.

[0049] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1As shown in , system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0050] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment solid state drive (SSD) or embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0051] The memory controller 106 may be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., a host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI Express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer mini interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.

[0052] The memory controller 106 and the one or more memory devices 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products. Figure 2a In one example shown in , the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in the embodiment. Figure 2b In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0053] Figure 3a A schematic diagram of the structure of a storage cell array of a three-dimensional NAND memory is given as an example. Figure 3a As shown, the memory cell array of the three-dimensional NAND memory is composed of several parallel and staggered rows of memory cell rows parallel to the gate isolation structure, every two rows of memory cell rows are separated by the gate isolation structure and the upper selection gate isolation structure, and each memory cell row includes a plurality of memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure, the first gate isolation structure divides the memory cell array into a plurality of memory blocks (Blocks), the plurality of second gate isolation structures may divide the memory blocks into a plurality of finger storage areas (Fingers), and the upper selection gate isolation structure disposed in the middle of each finger storage area may divide the finger storage area into two parts, thereby dividing the finger storage area into two memory slices. Figure 3a A storage block shown in FIG. 1 includes 6 storage slices. In actual applications, the number of storage slices in a storage block is not limited thereto.

[0054] In some embodiments, each memory block may be coupled to a plurality of word lines, and a plurality of memory cells coupled to each individually controlled word line constitute a page. For example, Figure 3a All memory cells in each memory slice are coupled to form a page.

[0055] It should be noted that Figure 3a The number of memory cell rows between the gate isolation structure and the upper selection gate isolation structure given in the disclosure is only an exemplary demonstration and is not used to limit the number of memory cell rows contained in a finger storage area of ​​the three-dimensional NAND memory in the present disclosure. In actual applications, the number of memory cell rows contained in a finger storage area can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0056] Figure 3b 1 is a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to some aspects of the present disclosure. The memory device 300 may be Figure 1 300 is an example of a memory device 104 in FIG. The memory device 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 is taken as an example of a three-dimensional NAND-type memory cell array, wherein the memory cell 306 is a NAND-type memory cell, and the memory cell 306 is provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons captured in the region of the memory cell 306. Each memory cell 306 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0057] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible storage states and can therefore store one bit of data. For example, the first storage state "0" may correspond to a first voltage range, and the second storage state "1" may correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-bit memory cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell (also referred to as a two-bit memory cell, Double-Level Cell), three bits per cell (also referred to as a three-bit memory cell (TLC, Trinary-Level Cell)), four bits per cell (also referred to as a four-bit memory cell (QLC, Quad-Level Cell)), five bits per cell (also referred to as a five-bit memory cell (PLC, Penta-level cell)), or more than five bits per cell. Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLCs can be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell, a fourth nominal storage value can be used for the erased state.

[0058] like Figure 3bAs shown in , each memory string 308 may include a lower selection transistor 310 (also known as a source selection transistor BSG, which includes a source selection gate) at its source terminal and an upper selection transistor 312 (also known as a drain selection transistor TSG, which includes a drain selection gate) at its drain terminal. The source selection transistor BSG310 and the drain selection transistor TSG312 can be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled through the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each storage string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of a transistor having TSG312) or a deselection voltage (e.g., 0 V) ​​to a corresponding TSG312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of a transistor having BSG310) or a deselection voltage (e.g., 0 V) ​​to a corresponding BSG310 via one or more BSG lines 315.

[0059] like Figure 3b As shown in , the memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, that is, all memory cells 306 on the same memory block 304 are erased at the same time. In order to erase the memory cells 306 in a selected memory block 304, the source lines 314 coupled to the selected memory block 304 and the unselected memory blocks 304 in the same plane as the selected memory block 304 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at a half-memory block level, at a quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by the read and program operations. In some embodiments, in combination with the previous Figure 3a, multiple memory cells are isolated by an upper selection gate isolation structure and a gate isolation structure, and multiple memory cells between the upper selection gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, and each memory cell row is parallel to the gate isolation structure and the upper selection gate isolation structure. Among them, the memory cells in the memory slice sharing the same word line form a physical page 320, and each physical page 320 can be mapped to at least one logical page according to the storage mode of the corresponding memory cell 306 (for example, SLC or MLC as mentioned above), and the logical page can constitute the basic data unit of the programming operation and the reading operation.

[0060] refer to Figure 3a , Figure 3b Each memory cell 306 in the plurality of memory cells is coupled to a corresponding word line 318, and each memory string 308 is coupled to a corresponding bit line 316 via a corresponding selection transistor (such as the top selection transistor (TSG) 312).

[0061] Figure 4 FIG. 3 is a cross-sectional schematic diagram of an exemplary memory cell array 301 including a memory string 308 using NAND as an example according to some aspects of the present disclosure. Figure 4 As shown, the NAND memory cell array 301 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 that are alternately stacked in sequence, and a channel structure that vertically penetrates the gate layers 411 and the insulating layers 412, wherein the channel structure is coupled with each gate layer to form a memory cell, and the channel structure is coupled with a plurality of gate layers in the stacked structure 410 to form a memory string 308. The gate layers 411 and the insulating layers 412 may be alternately stacked, and two adjacent gate layers 411 are separated by a layer of insulating layer 412.

[0062] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0063] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0064] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0065] Return to reference Figure 3b , the peripheral circuit 302 may be coupled to the memory cell array 301 through the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each target memory cell 306 via the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, it may also include Figure 5 Additional peripheral circuits not shown.

[0066] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic 512. In one example, the page buffer / sense amplifier 504 can store the program data (write data) to be programmed into the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing the data bit stored in the memory cell 306, and amplify the small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512, and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0067] The row decoder / word line driver 508 may be configured to be controlled by the control logic 512 and select / deselect the memory block 304 of the memory cell array 301 and select / deselect the word line 318 of the memory block 304. The row decoder / word line driver 508 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 may also select / deselect and drive the BSG line 315 and the TSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cell 306 coupled to the (one or more) selected word lines 318. The voltage generator 510 may be configured to be controlled by the control logic 512 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 301.

[0068] The control logic 512 may be coupled to each of the other parts in the peripheral circuits described above, and is configured to control the operation of each of the other parts in the peripheral circuits. The register 514 may be coupled to the control logic 512, and includes a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 516 may be coupled to the control logic 512, and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, and to buffer status information received from the control logic 512 and relay them to the host. The interface 516 may also be coupled to the column decoder / bit line driver 506 via the data bus 518, and act as a data I / O interface and a data buffer to buffer data and relay them to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0069] In practical applications, a 3D NAND memory may include at least one memory cell array, and the memory cell array may include a plurality of memory cell layers stacked in a vertical direction, each memory cell layer including a plurality of memory cells, and a plurality of memory cells in each memory cell layer may be coupled to a word line; wherein the plurality of memory cell layers may be divided into a plurality of memory blocks. With the development of 3D NAND memory, the number of memory cell layers increases, and the size of a single memory block increases, resulting in the frequent occurrence of memory blocks that are not fully written (Open block). However, when performing a read operation on an unfull memory block, a variety of problems that affect the read performance may occur. For example, with the increase in the number of stacked layers and the miniaturization of device size, the distance between memory cell layers becomes smaller and smaller. When a read voltage is applied to a selected word line, a coupling effect is easily generated between the selected word line and the adjacent word line, and the closer the distance between the selected word line and the adjacent word line, the more serious the coupling effect. For example, when a read voltage is applied to a selected word line, read interference is generated on unselected word lines, especially on unprogrammed memory cells coupled to the unselected word lines, thereby affecting subsequent use of the unprogrammed memory cells.

[0070] Based on one or more of the above problems, embodiments of the present disclosure provide a memory device and an operating method thereof, wherein the memory device includes a peripheral circuit and a memory cell array coupled to the peripheral circuit.

[0071] The peripheral circuit may include any suitable digital, analog and / or mixed signal circuit configured to facilitate the memory to implement various operations such as read operation, write operation, erase operation, etc. For example, the peripheral circuit may include control logic (such as control circuit or controller), data buffer, decoder (decoder may also be called decoder), driver and read-write circuit, etc. When the control logic receives the read-write operation command and address data, under the action of the control logic, the decoder may apply the corresponding voltage obtained from the driver to the corresponding bit line and word line based on the decoded address to realize data reading and writing, and perform data exchange with the outside through the data buffer.

[0072] The memory cell array may include a plurality of memory blocks, each memory block may include a plurality of memory strings, each memory string may include a plurality of memory cells stacked in a vertical direction, the topmost memory cell (upper selection transistor TSG) of each memory string is coupled to an upper selection line SSL, the bottommost memory cell (lower selection transistor BSG) of each memory string is coupled to a ground selection line GSL, and a plurality of memory cells located between the topmost memory cell and the bottommost memory cell are coupled to a plurality of word lines (WL). Here, the plurality of word lines may include a dummy word line (DWL), a selected word line (Select Word Line, i.e., Sel.WL), an unselected word line (Unselect Word Line, i.e., Unsel.WL), etc.

[0073] It should be noted that, for the programming process of 3D NAND type memory, the general programming sequence is to start programming from the memory cell closest to the lower selection transistor BSG of the storage string, and end from bottom to top to the memory cell closest to the upper selection transistor TSG. This programming sequence can be called the typical sequential programming (Normal Program Sequence) or the forward programming sequence. In some other embodiments, the programming sequence is to start programming from the memory cell closest to the upper selection transistor TSG of the storage string, and end from top to bottom to the memory cell closest to the lower selection transistor BSG. This programming sequence can be called reverse programming. In some embodiments, due to the different amounts of data to be programmed, the storage states of the storage blocks in the memory cell array are different. For example, some memory blocks in the memory cell array may be full, while some memory blocks may not be full. For example, Figure 6a A schematic diagram of a storage string in a full storage block is shown; Figure 6b and Figure 6c Schematic diagrams of a storage string in an unfilled storage block are shown respectively (wherein, Figure 6b The programming order of the memory string shown is reverse programming. Figure 6cThe programming order of the storage strings shown is sequential programming, which is explained in detail below and will not be repeated here).

[0074] After programming a memory block, it can be read.

[0075] It should be noted that, based on the different storage states of the above-mentioned storage blocks (full or not full), the problems that may arise during the reading process are also different; based on this, before performing a read operation on the storage block, the operating method of the memory device includes: performing a storage state detection on the selected storage block; the storage state detection result includes a full storage block and an not full storage block; performing the first read operation on the storage cell coupled to the selected word line in the not full storage block; performing the second read operation on the storage cell coupled to the selected word line in the full storage block.

[0076] refer to Figure 6a , Figure 6b , Figure 6c According to the detection results, the storage blocks can be divided into full storage blocks (refer to Figure 6a ) and partially filled memory blocks (refer to Figure 6b , Figure 6c ). When performing a read operation, a first read operation is performed on a memory cell coupled to a selected word line in an unfilled memory block, and a second read operation is performed on a memory cell coupled to a selected word line in a filled memory block. It should be noted that, Figure 6b The memory string shown is programmed in reverse order, and the unprogrammed memory cell (coupled to the third word line 606) on the memory string is adjacent to the lower selection transistor BSG (such as 607a); Figure 6c The memory string shown is sequentially programmed, and the unprogrammed memory cell on the memory string (coupled to the third word line 606) is adjacent to the upper selection transistor TSG (such as 601a); in other embodiments, according to the selection of the programming sequence, the unprogrammed memory cell on the memory string can also be located in the middle of the memory string, that is, the upper and lower sides of the unprogrammed memory cell are both programmed memory cells (not shown in the drawings). For ease of understanding, here and below, one of the memory strings of the unfilled memory block is represented by Figure 6b The storage string shown is used as an example for explanation.

[0077] Combine the following Figure 6a , Figure 6b , Figure 7 , Figure 8 , details of performing a first read operation on memory cells coupled to a selected word line of an unfull memory block, and performing a second read operation on memory cells coupled to a selected word line of a full memory block are explained.

[0078] refer to Figure 6a , Figure 7 , Figure 7 A schematic flow chart of a method for performing a first read operation on a memory cell coupled to a selected word line of an unfilled memory block provided by an embodiment of the present disclosure is shown in FIG. Figure 7 As shown, the method for performing the first reading operation includes the following steps:

[0079] Step S701: When performing a first read operation on a memory cell coupled to a selected word line, a first pass voltage is applied to the first word line, a second pass voltage is applied to the second word line, and a third pass voltage is applied to the third word line; the first word line is at least one word line physically located above and below the selected word line; the second word line and the third word line are both word lines physically located on a side of the first word line away from the selected word line, the memory cell coupled to the second word line is a programmed memory cell, and the memory cell coupled to the third word line is an unprogrammed memory cell; the first pass voltage, the second pass voltage, and the third pass voltage are all different.

[0080] It should be noted that the first word line, the second word line and the third word line are all non-selected word lines; wherein the first word line is a non-selected word line adjacent to the selected word line, and may include one word line, two word lines, three word lines, etc., each physically located above and below the selected word line. For ease of understanding, here and below, only the first word line including one word line, each physically located above and below the selected word line, is used as an example for explanation; Figure 6a , that is, the first word line 604 is a non-selected word line adjacent to the upper and lower sides of the selected word line 605. Compared with the first word line, the second word line and the third word line are physically located farther away from the selected word line; here, the memory cell coupled to the second word line is a programmed memory cell, and the memory cell coupled to the third word line is an unprogrammed memory cell. It should be noted that due to the different programming sequences of the memory strings (sequential programming and / or reverse programming), the relative positions of the second word line and the third word line on the memory string are different. For example, reverse programming is taken as an example here, refer to Figure 6b , the second word line 603 is located between the third word line 606 and the first word line 604, that is, the third word line 606 is physically located on the side of the second word line 603 away from the first word line 604, that is, the distance between the third word line 606 and the selected word line 605 is greater than the distance between the second word line 603 and the selected word line 605. In addition, it should be noted that the following description of the number of first word lines and the relative position relationship between the second word line and the third word line is only used to describe the present disclosure, and is not used to limit the scope of the present disclosure.

[0081] Exemplary, reference Figure 6b , Figure 7 , Figure 9aIn step S701, when performing the first read operation, a read voltage Vread is applied to the selected word line 605 (in order to distinguish it from the read voltage in the second read operation, the read voltage here is named the first read voltage Vread1), a first pass voltage Vpass1 is applied to the first word line 604 adjacent to the selected word line 605, a second pass voltage Vpass2 is applied to the second word line 603, and a third pass voltage Vpass3 is applied to the third word line 606, wherein the first pass voltage Vpass1, the second pass voltage Vpass2, and the third pass voltage Vpass3 are all different based on the different distances between the first word line, the second word line, and the third word line and the selected word line.

[0082] In some embodiments, reference Figure 6b , the distances between the first word line, the second word line, and the third word line and the selected word line gradually increase, and the first pass voltage Vpass1 applied to the first word line 604, the second pass voltage Vpass2 applied to the second word line 603, and the third pass voltage Vpass3 applied to the third word line 606 gradually decrease in sequence; illustratively, the first pass voltage Vpass1 is greater than the second pass voltage Vpass2, that is, Vpass1>Vpass2; the second pass voltage Vpass2 is greater than the third pass voltage Vpass3, that is, Vpass2>Vpass3.

[0083] In this way, the first pass voltage Vpass1 is applied to the first word line 604 adjacent to the selected word line 605, which can reduce the voltage difference between the selected word line 605 and the first word line 604, thereby reducing the coupling effect between the selected word line 605 and the first word line 604. In addition, it should be understood that when performing the first read operation, a voltage of 0V is applied to the channel, and the first read voltage Vread1 is applied to the selected word line 605. At this time, an electric field is formed between the memory cells coupled to the non-selected word lines (the second word line 603 and the third word line 606) and the channel, which is easy to cause read interference; based on this, the second pass voltage Vpass2 is applied to the second word line 603 coupled to the programmed memory cell, and the third pass voltage Vpass3 is applied to the third word line 606 coupled to the unprogrammed memory cell, which reduces the read interference (weak programming) generated by the read voltage on the programmed memory cell and the unprogrammed memory cell; in this way, the read performance and reliability of the memory device can be improved. In addition, based on the different distances between the non-selected word lines (first word line, second word line, third word line) and the selected word line, applying different pass voltages on the non-selected word lines can more accurately solve the problem of superposition of read interference and coupling effect in the read operation.

[0084] It should be noted that the memory cells coupled to the selected word line in the embodiment of the present disclosure are all programmed memory cells. Among them, in the unfilled memory block, when the memory cells coupled to the selected word line are the last group (layer) of memory cells in the programmed memory cells, a first word line adjacent to the selected word line overlaps with a third word line coupled to the unprogrammed memory cells, that is, the selected word line is adjacent to the third word line. In this case, when performing the first read operation, a first pass voltage is applied to the same word line where the first word line overlaps with the third word line.

[0085] Exemplary, reference Figure 8 , the selected word line 605 is the word line coupled to the last group (layer) of memory cells in the programmed memory cells, and a first word line 604 and a third word line 606 adjacent to the selected word line 605 overlap, that is, the two are the same word line. In this case, when performing the first read operation, the first pass voltage Vpass1 is applied to the overlapping word line. Here, the first pass voltage Vpass1 is greater than the third pass voltage Vpass3, that is, Vpass1>Vpass3. In this way, on the one hand, the coupling effect caused by the first read voltage to the adjacent word line (such as the first word line) can be reduced, and on the other hand, the read interference caused by the first read voltage to the unprogrammed memory cell (coupled to the third word line) can also be reduced.

[0086] In some embodiments, a dummy unit is further provided in the storage block, and the dummy unit is coupled to a dummy word line; the physical position of the dummy unit in the storage block can be selected and set according to actual conditions; in other words, the relative position of the dummy word line to the first word line, the second word line, and the third word line is different based on the position of the dummy unit in the storage block; that is, a dummy word line can be set between at least any two word lines among the first word line, the second word line, and the third word line. In the embodiment of the present disclosure, when performing the first read operation, a second pass voltage is applied to the dummy word line. Exemplarily, reference Figure 6b , the dummy unit is coupled to the dummy word line 602, where the dummy word line 602 is located between the second word line 603 and the upper selection transistor (such as 601a). When performing the first read operation, a second pass voltage Vpass2 is applied to the dummy word line 602 to reduce the coupling effect between the dummy word line 602 and its adjacent word line (such as the second word line 603).

[0087] Combine the following Figure 6a , Figure 9b The case where the second read operation is performed on a full storage block is described.

[0088] In some embodiments, the operating method also includes: when performing a second read operation on a memory cell coupled to a selected word line in a fully written memory block, applying a first pass voltage on a fourth word line and applying a second pass voltage on a fifth word line; the fourth word line is at least one word line physically located above and below the selected word line; the fifth word line is all word lines physically located on the side of the fourth word line away from the selected word line.

[0089] refer to Figure 6a , the fourth word line and the fifth word line are both non-selected word lines, and the fourth word line may include one word line, two word lines, three word lines, etc., each physically located above and below the selected word line. Taking the fourth word line as one word line physically located above and below the selected word line as an example, the fifth word line is all word lines physically located on the side of the fourth word line away from the selected word line. All word lines here refer to all non-selected word lines except the selection lines coupled to the upper selection transistor and the lower selection transistor, and the fourth word line, such as the non-selected word lines coupled to the programmed storage cells, the dummy word lines coupled to the dummy cells ( Figure 6a It should be understood that the physical position of the fifth word line is farther from the selected word line than the fourth word line; for example, referring to Figure 6a , the fourth word line 609 is located between the selected word line 608 and the fifth word line 610. In addition, it should be noted that the following description of the number of fourth word lines is only used to illustrate the present disclosure and is not used to limit the scope of the present disclosure. It should be understood that, in the full memory block, except for the dummy word line, the memory cells coupled to the selected word line, the fourth word line, and the fifth word line are all programmed memory cells.

[0090] Exemplary, reference Figure 6a , when performing the second read operation, a second read voltage Vread2 is applied to the selected word line 608, a first pass voltage Vpass1 is applied to the fourth word line 609, and a second pass voltage Vpass2 is applied to the fifth word line 610; here, the first pass voltage Vpass1 is greater than the second pass voltage Vpass2, that is, Vpass1>Vpass2. In the embodiment of the present disclosure, when performing the second read operation, when the first pass voltage is applied to the non-selected word line (such as the fourth word line) adjacent to the selected word line, the coupling effect between the selected word line and the adjacent word line (such as the fourth word line) can be reduced. Applying the second pass voltage to the fifth word line can reduce the read interference caused by the second read voltage to the fifth word line.

[0091] It should be noted that the second read voltage Vread2 may be the same as or different from the first read voltage Vread1 .

[0092] As mentioned above, the memory block further includes an upper selection transistor TSG and a lower selection transistor BSG, and the number of the upper selection transistor TSG and the lower selection transistor BSG can be set arbitrarily. Figure 6a , Figure 6b , the upper selection transistor TSG includes a selected upper selection transistor 601b and an unselected upper selection transistor 601a; and the lower selection transistor BSG includes a selected lower selection transistor 607a and an unselected lower selection transistor 607b.

[0093] refer to Figure 6b , Figure 9a When performing the first read operation, the first selection voltage Vtsg is applied to the selected upper selection transistor 601b, and the second selection voltage Vss is applied to the unselected upper selection transistor 601a. ​​The third selection voltage Vbsg is applied to the selected lower selection transistor 607a, and the fourth selection voltage Vss is applied to the unselected lower selection transistor 607b; here, the fourth selection voltage is the same as the second selection voltage.

[0094] refer to Figure 6a , Figure 9b When performing the second read operation, the first selection voltage Vtsg is applied to the selected upper selection transistor 601b, and the second selection voltage Vss is applied to the unselected upper selection transistor 601a. ​​The third selection voltage Vbsg is applied to the selected lower selection transistor 607a, and the fourth selection voltage Vss is applied to the unselected lower selection transistor 607b; here, the fourth selection voltage is the same as the second selection voltage.

[0095] In some embodiments, the memory device further comprises a plurality of bit lines, wherein when performing a read operation, the plurality of bit lines can be further divided into selected bit lines and unselected bit lines. Figure 9a , Figure 9b When performing the first read operation or the second read operation, the bit line voltage Vdd is applied to the selected bit line 611, and the inhibit voltage ( Figure 9a , Figure 9b not shown).

[0096] In some specific embodiments, the memory device further includes a counter; the counter is used to count the number of times the storage unit performs a read operation, and the counter accumulates the number of reads; when the count value of the counter reaches a certain threshold (such as a preset threshold), a read scan of the corresponding storage block is triggered, that is, a reliability test is performed on the corresponding storage block; at this time, the operation method further includes: testing / checking the reliability of the storage block; and after each test, the count value of the counter is cleared. However, when the number of read operations often reaches the preset threshold, the frequency (or number of times) of the reliability test (i.e., the read scan) of the storage block increases; wherein, the more times the test is performed, the greater the impact on the read performance of the memory device.

[0097] It should be understood that each time a read operation is performed on a storage unit of a storage block, the wear of the storage block increases once. When a read operation is performed on a storage block that is not full using the method for performing the first read operation in the above embodiment of the present disclosure, the wear of the corresponding storage block is improved. Based on this, in some embodiments of the present disclosure, different counting methods are used for different storage blocks.

[0098] In some embodiments, the operation method further includes: after performing a first read operation, increasing the read count by a first count value; after performing a second read operation, increasing the read count by a second count value; the first count value is smaller than the second count value.

[0099] Exemplarily, the first count value is 0.7, that is, after executing the first read operation once, the count value of the counter increases by 0.7; the first count value can also be selected and set according to actual conditions, such as 0.6, 0.8, etc. The second count value is 1, that is, after executing the second read operation once, the count value of the counter increases by 1. In other embodiments, for a full storage block and an incomplete storage block, the count value of the corresponding counter can be increased by 1 when a read operation is performed once. In this way, in the above-mentioned embodiment of the present disclosure, when the first read operation is performed on an incomplete storage block, the count value of its corresponding counter is set to be less than 1, the frequency of triggering a read scan (read scan) can be reduced, and the number of times the read scan (read scan) is triggered can be reduced, thereby reducing the number of detections of the corresponding storage block, thereby improving the reading performance and service life of the incomplete storage block.

[0100] Based on this, in the embodiment of the present disclosure, when performing the first read operation, the coupling effect between the selected word line and its adjacent word line is reduced by applying the first pass voltage to the non-selected word line (such as the first word line) adjacent to the selected word line. At the same time, applying the third conduction voltage to the non-selected word line (such as the third word line) coupled to the unprogrammed memory cell can reduce the read interference caused by the first read operation to the unprogrammed memory cell, thereby improving the read performance and reliability of the memory device. In addition, in the embodiment of the present disclosure, the count value of the counter after each execution of the first read operation is set to be less than the count value of the counter after each execution of the second read operation. In this way, the frequency of the count value of the corresponding counter reaching the preset threshold when counting the number of times of the first read operation can be reduced, and the number of times of triggering the read scan (read scan) can be reduced, thereby improving the read performance and service life of the unfilled storage block.

[0101] For ease of understanding, the following Fig.10 The present disclosure is further described in detail. Fig.10 The following is a flowchart of a read operation implementation of a memory device provided by an embodiment of the present disclosure. Fig.10 As shown, after receiving the read instruction, step S1001 is executed and the read operation starts.

[0102] Step S1002 is executed, a determination module in the memory device, such as a determiner, determines the storage state of the currently selected storage block; and determines whether the storage state of the selected storage block is not full according to the detection result.

[0103] When the storage state of the selected storage block is not full, step S1003 is executed to perform a first read operation on the selected storage block; and after each execution of the first read operation, the count value of the counter increases by a first count value, such as 0.7.

[0104] When the storage state of the selected storage block is the full state, step S1004 is executed to perform a second read operation on the selected storage block; and after each execution of the second read operation, the count value of the counter is increased by a second count value, such as 1.

[0105] After the first reading operation or the second reading operation is completed, step S1005 is executed and the reading operation ends.

[0106] Based on the operation method of the above-mentioned memory device, an embodiment of the present disclosure also provides a memory device, wherein the memory device includes: a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array includes multiple memory blocks; each memory block includes multiple memory cells and multiple word lines coupled to the multiple memory cells; the peripheral circuit is configured to: when performing a first read operation on the memory cell coupled to the selected word line, apply a first pass voltage to the first word line, apply a second pass voltage to the second word line, and apply a third pass voltage to the third word line; the first word line is at least one word line physically located above and below the selected word line; the second word line and the third word line are both word lines physically located on the side of the first word line away from the selected word line, the memory cell coupled to the second word line is a programmed memory cell, and the memory cell coupled to the third word line is an unprogrammed memory cell; the first pass voltage, the second pass voltage and the third pass voltage are all different.

[0107] In some embodiments, the first pass voltage is greater than the second pass voltage; and the second pass voltage is greater than the third pass voltage.

[0108] In some embodiments, the peripheral circuit is further configured to: perform storage status detection on a selected storage block; the storage status detection result includes a full storage block and an incomplete storage block; perform a first read operation on a storage cell coupled to a selected word line in the incomplete storage block; and perform a second read operation on a storage cell coupled to a selected word line in the full storage block.

[0109] In some embodiments, the peripheral circuit is further configured to: apply a first pass voltage to a fourth word line and a second pass voltage to a fifth word line when performing a second read operation on a memory cell coupled to a selected word line in a fully written memory block; the fourth word line is at least one word line physically located above and below the selected word line; the fifth word line is all word lines physically located on the side of the first word line away from the selected word line.

[0110] In some embodiments, the peripheral circuit is further configured to: after executing a first read operation, increase the read count by a first count value; after executing a second read operation, increase the read count by a second count value; the first count value is smaller than the second count value.

[0111] In some embodiments, when the first word line and the third word line are the same word line, the first pass voltage is applied to the same word line.

[0112] In some embodiments, a dummy word line is provided between at least any two of the first word line, the second word line, and the third word line; and the peripheral circuit is further configured to apply a second pass voltage to the dummy word line when performing the first read operation.

[0113] In some embodiments, the peripheral circuit is further configured to: apply a read voltage to a selected word line during the execution of the first read operation; wherein the memory cell coupled to the selected word line is a programmed memory cell.

[0114] In some embodiments, the memory device comprises a three-dimensional NAND-type memory.

[0115] Based on the above-mentioned memory device and its operation method, the embodiment of the present disclosure also provides a memory system, including: one or more memory devices as described in the above-mentioned embodiments of the present disclosure; and a memory controller coupled to the memory device for controlling the memory device.

[0116] The embodiments of the present disclosure further provide a storage medium, wherein executable instructions are stored on the storage medium. When the executable instructions are executed by a peripheral circuit, the steps of the method described in the above embodiments of the present disclosure can be implemented.

[0117] In some specific embodiments, the storage medium can be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface storage, an optical disk, or a compact disc read-only memory (CD-ROM); it can also be various devices including one or any combination of the above-mentioned memory devices.

[0118] In some embodiments, executable instructions may be in the form of a program, software, software module, script or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine or other unit suitable for use in a computing environment.

[0119] As an example, executable instructions may, but need not, correspond to a file in a file system, may be stored as part of a file that stores other programs or data, such as in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or code portions).

[0120] It should be noted that: "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. In addition, the technical solutions recorded in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0121] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

Claims

1. A memory device, characterized in that: include: A memory cell array and a peripheral circuit coupled to the memory cell array; The memory cell array includes a plurality of memory blocks; each of the memory blocks includes a plurality of memory cells and a plurality of word lines coupled to the plurality of memory cells; The peripheral circuit is configured as: When performing a first read operation on a memory cell coupled to a selected word line, a first pass voltage is applied to a first word line, a second pass voltage is applied to a second word line, and a third pass voltage is applied to a third word line; the first word line is at least one word line physically located above and below the selected word line; The second word line and the third word line are both word lines physically located at a side of the first word line away from the selected word line, the memory cells coupled to the second word line are programmed memory cells, and the memory cells coupled to the third word line are unprogrammed memory cells; The first pass voltage, the second pass voltage, and the third pass voltage are all different.

2. The memory device according to claim 1, wherein: The first pass voltage is greater than the second pass voltage; the second pass voltage is greater than the third pass voltage.

3. The memory device according to claim 2, wherein: The peripheral circuit is further configured as: Performing a storage status detection on the selected storage block; the storage status detection result includes a full storage block and an incomplete storage block; performing the first read operation on the memory cells coupled to the selected word line in the unfilled memory block; A second read operation is performed on memory cells coupled to the selected word line in the fully written memory block.

4. The memory device according to claim 3, wherein: The peripheral circuit is further configured as: When the second read operation is performed on the memory cells coupled to the selected word line in the fully written memory block, the first pass voltage is applied to the fourth word line, and the second pass voltage is applied to the fifth word line; the fourth word line is at least one word line physically located above and below the selected word line; the fifth word line is all word lines physically located on the side of the fourth word line away from the selected word line.

5. The memory device according to claim 4, wherein: The peripheral circuit is further configured as: After executing the first read operation once, the read count is increased by a first count value; after executing the second read operation once, the read count is increased by a second count value; the first count value is smaller than the second count value.

6. The memory device according to claim 1, wherein: When the first word line and the third word line are the same word line, the first pass voltage is applied to the same word line.

7. The memory device according to claim 1, wherein: A dummy word line is provided between at least any two of the first word line, the second word line, and the third word line; The peripheral circuit is further configured as: When performing the first read operation, the second pass voltage is applied to the dummy word line.

8. The memory device according to claim 1, wherein: The peripheral circuit is further configured as: During the execution of the first read operation, applying a read voltage on the selected word line; The memory cells coupled to the selected word line are programmed memory cells.

9. The memory device according to claim 1, wherein: The memory device comprises a three-dimensional NAND type memory.

10. A memory system, characterized in that: include: One or more memory devices as claimed in any one of claims 1 to 9; as well as The memory controller is coupled to the memory device and is used to control the memory device.

11. A method for operating a memory device, characterized in that: The operation method comprises: When performing a first read operation on a memory cell coupled to a selected word line, a first pass voltage is applied to the first word line, a second pass voltage is applied to the second word line, and a third pass voltage is applied to the third word line; the first word line is at least one word line physically located above and below the selected word line; the second word line and the third word line are both word lines physically located on a side of the first word line away from the selected word line, the memory cell coupled to the second word line is a programmed memory cell, and the memory cell coupled to the third word line is an unprogrammed memory cell; the first pass voltage, the second pass voltage, and the third pass voltage are all different; The memory device includes a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array includes a plurality of memory blocks; each of the memory blocks includes a plurality of memory cells and a plurality of word lines coupled to the plurality of memory cells.

12. The operating method according to claim 11, characterized in that: The first pass voltage is greater than the second pass voltage; the second pass voltage is greater than the third pass voltage.

13. The operating method according to claim 12, characterized in that: The operation method also includes: Performing a storage status detection on the selected storage block; the storage status detection result includes a full storage block and an incomplete storage block; performing the first read operation on the memory cells coupled to the selected word line in the unfilled memory block; A second read operation is performed on memory cells coupled to the selected word line in the fully written memory block.

14. The operating method according to claim 13, characterized in that: The operation method also includes: When the second read operation is performed on the memory cells coupled to the selected word line in the fully written memory block, the first pass voltage is applied to the fourth word line, and the second pass voltage is applied to the fifth word line; the fourth word line is at least one word line physically located above and below the selected word line; the fifth word line is all word lines physically located on the side of the fourth word line away from the selected word line.

15. The operating method according to claim 14, characterized in that: The operation method also includes: After executing the first read operation once, the read count is increased by a first count value; after executing the second read operation once, the read count is increased by a second count value; the first count value is smaller than the second count value.

16. The operating method according to claim 11, characterized in that: When the first word line and the third word line are the same word line, the first pass voltage is applied to the same word line.

17. The operating method according to claim 11, characterized in that: A dummy word line is provided between at least any two of the first word line, the second word line, and the third word line; The operation method also includes: When performing the first read operation, the second pass voltage is applied to the dummy word line.

18. The operating method according to claim 11, characterized in that: The operation method also includes: During the execution of the first read operation, applying a read voltage on the selected word line; The memory cells coupled to the selected word line are programmed memory cells.

19. A storage medium, characterized in that: The storage medium stores executable instructions, and when the executable instructions are executed by the memory controller, the steps of the method as claimed in any one of claims 11 to 18 can be implemented.

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