Multi-channel cranial meridian electrical stimulation circuit

Abstract

The multi-channel cranial meridian electrical stimulation circuit comprises a main control module, a driving module, a current detection module and a multi-path current detection and selection module, wherein the main control module is connected with the driving module, the driving module is connected with the current detection module, and the current detection module is connected with the multipath current detection selection module; the multipath current detection and selection module realizes selection of current paths flowing through resistors R7 and R22 by switching the state of an EN pin, and the multipath current detection and selection module comprises a first multipath current detection and selection circuit and a third multipath current detection and selection circuit; a pin 3 of the first multi-path current detection and selection circuit controls conduction between the pin 1 and the pin 2 and is connected to a pin 52 of the main control module, and a pin 3 of the third multi-path current detection and selection circuit controls conduction between the pin 1 and the pin 2 and is connected to a pin 59 of the main control module.

Description

Technical Field

[0001] The present application relates to the field of electrical stimulation medical devices, and specifically to a multi-channel cranial electrical stimulation circuit. Background Art

[0002] At present, transcranial electrical stimulation (TES) is a non-invasive neuromodulation technology that mainly stimulates specific brain areas by passing weak currents through electrodes on the scalp to produce membrane polarization effects, achieve synaptic plasticity regulation, and then regulate the neural activity and excitability of the cerebral cortex. TES has broad application prospects in the fields of research and treatment, and has gradually become an important means of treating mental illness and improving cognitive abilities. However, existing TES devices generally have technical and functional limitations. Specifically, existing TES devices generally face the problem of a single current output channel. Most devices can only provide a fixed current channel during the stimulation process, and the current parameters are preset before the stimulation is started. This single-channel design lacks flexibility, making it impossible for the device to adjust according to the patient's real-time status and feedback, limiting the treatment effect.

[0003] In addition, existing TES devices tend to meet different treatment needs in the form of independent single-category products. These devices usually have fixed electrical stimulation programs built in. Although they provide simple parameter adjustment functions, they cannot achieve more personalized treatment plans. In short, existing TES devices generally have the defects of low accuracy and poor feedback, which greatly affects the therapeutic effect of transcranial electrical stimulation.

[0004] Therefore, how to achieve effective multi-channel implementation of transcranial electrical stimulation, realize personalized diagnosis and treatment, and improve the accuracy of electrical stimulation is an urgent problem to be solved in the field of electrical stimulation medical devices. Summary of the invention

[0005] In order to solve or at least address the problems raised in the above background technology, the present application provides a multi-channel cranial electrical stimulation circuit.

[0006] To achieve the above objectives, this application provides the following technical solutions:

[0007] A multi-channel cranial electrical stimulation circuit, comprising: a main control module, a driving module, a current detection module, and a multi-channel current detection selection module;

[0008] Wherein, the main control module is connected to the driving module, the driving module is connected to the current detection module, and the current detection module is connected to the multi-channel current detection selection module;

[0009] A current detection module, wherein the current detection circuit includes a first current detection circuit and a second current detection circuit, wherein the first current detection circuit includes a current detection chip U2 and a resistor R7, wherein the pin 5 of the current detection chip U2 is connected to the pin 16 of the main control chip U1, wherein one end of the resistor R7 is connected to the pin 1 of the current detection chip U2, and the other end is connected to the pin 8 of the current detection chip U2 and forms a resistor voltage divider circuit with the pin 7 of the current detection chip U2 connected to the power module VDD, and the current is detected by measuring the voltage drop across the resistor R7, wherein the second current detection circuit includes a current detection chip U3 and a resistor R22, wherein the pin 5 of the current detection chip U3 is connected to the pin 17 of the main control chip U1, wherein one end of the resistor R22 is connected to the pin 1 of the current detection chip U3, and the other end is connected to the pin 8 of the current detection chip U3 and forms a resistor voltage divider circuit with the pin 7 of the current detection chip U3 connected to the power module VDD, and the current is detected by measuring the voltage drop across the resistor R22;

[0010] A multi-channel current detection selection module, wherein the multi-channel current detection selection module selects the current path flowing through the resistors R7 and R22 by switching the state of the EN pin, wherein the multi-channel current detection selection module includes a first multi-channel current detection selection circuit and a third multi-channel current detection selection circuit; pin 3 of the first multi-channel current detection selection circuit controls conduction between pin 1 and pin 2, and is connected to pin 52 of the main control module, and pin 3 of the third multi-channel current detection selection circuit controls conduction between pin 1 and pin 2, and is connected to pin 59 of the main control module.

[0011] As a further solution of the present application, the main control module includes a main control chip U1 and a crystal oscillator circuit, wherein the crystal oscillator circuit is connected to pins 12 and 13 of the main control chip U1, and pins 11, 19, 21, 22, 28, 50, 75 and 100 of the main control chip U1 are connected to the power supply module VDD; the crystal oscillator circuit includes a resistor R1, a resistor R3, a capacitor C1, a capacitor C3 and a crystal oscillator Y1, and pin 12 of the main control chip U1 is simultaneously connected to one end of the resistor R3, the end of the capacitor C1 and the end of the capacitor C2. One end of the resistor R3, one end of the capacitor C1 and one end of the crystal oscillator Y1 are connected to each other to form a path, and the other end of the capacitor C1 is grounded; the pin 13 of the main control chip U1 is connected to the resistor R1, and the resistor R1 is simultaneously connected to the other end of the resistor R3, one end of the capacitor C3 and the other end of the crystal oscillator Y1, the other end of the resistor R3, one end of the capacitor C3 and the other end of the crystal oscillator Y1 are connected to each other to form a path, and the other end of the capacitor C3 is grounded; the crystal oscillator Y1 is grounded.

[0012] As a further solution of the present application, the main control module also includes a reset circuit, which includes a resistor R4, a capacitor C4 and a reset button RST1, wherein one end of the resistor R4 is connected to the power module VDD, and the other end is connected to the capacitor C4; one end of the capacitor C4 away from the resistor R4 is grounded, and the reset button RST1 forms a parallel circuit with the capacitor C4, one end of the reset button RST1 is simultaneously connected to the capacitor C4 and the resistor R4, and the other end is simultaneously connected to the capacitor C4 and the ground end.

[0013] As a further solution of the present application, the main control module also includes a debugging serial port, which includes a first debugging serial port and a second debugging serial port. The first debugging serial port includes a debugging element J5, a resistor R5 and a resistor R6. Pin 1 of the debugging element J5 is simultaneously connected to one end of the resistor R6 and pin 26 of the main control chip U1, and the other end of the resistor R6 is connected to the power module VDD. Pin 2 of the debugging element J5 is grounded, and pin 3 of the debugging element J5 is simultaneously connected to one end of the resistor R5 and pin 25 of the main control chip U1, and the other end of the resistor R5 is connected to the power module VDD; the second debugging serial port includes a debugging element J6, a resistor R20 and a resistor R21. Pin 1 of the debugging element J6 is simultaneously connected to one end of the resistor R20 and pin 63 of the main control chip U1, and the other end of the resistor R20 is connected to the power module VDD. Pin 2 of the debugging element J6 is simultaneously connected to one end of the resistor R21 and pin 64 of the main control chip U1, and the other end of the resistor R21 is connected to the power module VDD. Pins 3 to 6 of the debugging element J6 are grounded.

[0014] As a further solution of the present application, the driving module includes a first signal amplifying circuit, a second signal amplifying circuit, a third signal amplifying circuit, and a fourth signal amplifying circuit, wherein the first signal amplifying circuit is connected to pin 29 of the main control chip U1, and receives a voltage signal DA1 from the main control chip U1; the second signal amplifying circuit is connected to pin 30 of the main control chip U1, and receives a voltage signal DA2 from the main control chip U1; the third signal amplifying circuit is connected to pin 33 of the main control chip U1, and receives a voltage signal DA3 from the main control chip U1; the fourth signal amplifying circuit is connected to pin 34 of the main control chip U1, and receives a voltage signal DA4 from the main control chip U1.

[0015] As a further solution of the present application, the first signal amplification circuit includes a resistor R8, a resistor R9, a resistor R16, a capacitor C6, an inductor L1 and a first operational amplifier; one end of the resistor R16 is connected to the pin 29 of the main control chip U1, and the other end is connected to the pin 3 of the first operational amplifier to receive the voltage signal DA1 from the main control chip U1, one end of the resistor R8 is grounded, and the other end is simultaneously connected to one end of the resistor R9 and the pin 2 of the first operational amplifier, the other end of the resistor R9 is connected to the output pin 6 of the first operational amplifier, and one end of the inductor L1 is connected to the power module VDD The second signal amplifying circuit includes a resistor R10, a resistor R11, a resistor R17, a capacitor C7, an inductor L2 and a second operational amplifier; one end of the resistor R17 is connected to the pin 30 of the main control chip U1, and the other end is connected to the pin 3 of the second operational amplifier to receive the voltage signal DA2 from the main control chip U1; one end of the resistor R10 is grounded, and the other end is connected to one end of the resistor R11 and the pin 7 of the second operational amplifier; the other end of the capacitor C6 is grounded, and the pin 4 of the first operational amplifier is grounded; the second signal amplifying circuit includes a resistor R10, a resistor R11, a resistor R17, a capacitor C7, an inductor L2 and a second operational amplifier; one end of the resistor R17 is connected to the pin 30 of the main control chip U1, and the other end is connected to the pin 3 of the second operational amplifier to receive the voltage signal DA2 from the main control chip U1; one end of the resistor R10 is grounded, and the other end is connected to one end of the resistor R11 and the pin 7 of the second operational amplifier Pin 2, the other end of the resistor R11 is connected to the output pin 6 of the second operational amplifier, one end of the inductor L2 is connected to the power module VDD, and the other end is connected to one end of the capacitor C7 and the pin 7 of the second operational amplifier, the other end of the capacitor C7 is grounded, and the pin 4 of the second operational amplifier is grounded; the third signal amplification circuit includes a resistor R12, a resistor R13, a resistor R18, a capacitor C9, an inductor L3 and a third operational amplifier; one end of the resistor R18 is connected to the pin 33 of the main control chip U1, and the other end is connected to the pin 3 of the third operational amplifier to receive the signal from the main control chip U1. The voltage signal DA3 of the chip U1, one end of the resistor R12 is grounded, and the other end is connected to one end of the resistor R13 and the pin 2 of the third operational amplifier, the other end of the resistor R13 is connected to the output pin 6 of the third operational amplifier, one end of the inductor L3 is connected to the power module VDD, and the other end is connected to one end of the capacitor C9 and the pin 7 of the third operational amplifier, the other end of the capacitor C9 is grounded, and the pin 4 of the third operational amplifier is grounded; the fourth signal amplification circuit includes a resistor R14, a resistor R15, a resistor R19, a capacitor C10, an inductor L4 and a fourth operational amplifier;One end of the resistor R19 is connected to the pin 34 of the main control chip U1, and the other end is connected to the pin 3 of the fourth operational amplifier to receive the voltage signal DA4 from the main control chip U1. One end of the resistor R14 is grounded, and the other end is simultaneously connected to one end of the resistor R15 and the pin 2 of the fourth operational amplifier. The other end of the resistor R15 is connected to the output pin 6 of the fourth operational amplifier. One end of the inductor L4 is connected to the power module VDD, and the other end is simultaneously connected to one end of the capacitor C10 and the pin 7 of the fourth operational amplifier. The other end of the capacitor C10 is grounded, and the pin 4 of the fourth operational amplifier is grounded. The fourth signal amplification circuit is connected to the pin 34 of the main control chip U1 to receive the voltage signal DA4 from the main control chip U1. ;

[0016] As a further solution of the present application, the first current detection circuit includes a current detection chip U2, a resistor R7 and a capacitor C8, one end of the resistor R7 connected to the current detection chip U2 is also connected to the output pin 6 of the second signal amplifier; the pin 6 of the current detection chip U2 is simultaneously connected to the power module VDD and one end of the capacitor C8, the end of the capacitor C8 connected to the VS pin 6 is connected to the power module VDD, and the other end is grounded, the pin 7 of the current detection chip U2 is connected to the grounded end of the capacitor C8 to form a resistor voltage divider circuit, the pin 5 of the current detection chip U2 is connected to the pin 16 of the main control chip U1, one end of the resistor R7 is connected to the pin 1 of the current detection chip U2, and the other end is connected to the pin 8 of the current detection chip U2 and forms a resistor voltage divider circuit with the pin 7 of the current detection chip U2 connected to the power module VDD, and the current is detected by measuring the voltage drop on the resistor R7; the second current detection circuit The circuit includes a current detection chip U3, a resistor R22 and a capacitor C11, wherein one end of the resistor R22 connected to the current detection chip U3 is also connected to the output pin 6 of the fourth signal amplifier; the VS pin 6 of the current detection chip U3 is simultaneously connected to the power module VDD and one end of the capacitor C22, the end of the capacitor C22 connected to the pin 6 is connected to the power module VDD, and the other end is grounded, the pin 7 of the current detection chip U3 is connected to the grounded end of the capacitor C22 to form a resistor voltage divider circuit, which is used for the current detection chip U3 to test the current flowing through the resistor R22, the pin 5 of the current detection chip U3 is connected to the pin 17 of the main control chip U1, one end of the resistor R22 is connected to the pin 1 of the current detection chip U3, and the other end is connected to the pin 8 of the current detection chip U3 and forms a resistor voltage divider circuit with the pin 7 of the current detection chip U3 connected to the power module VDD, and the current is detected by measuring the voltage drop on the resistor R22.

[0017] As a further solution of the present application, the first multi-channel current detection selection module includes a multi-channel current detection selection chip U4, a capacitor C12 and a capacitor C13, pins 4 and 5 of the multi-channel current detection selection chip U4 are connected and grounded, pin 12 is simultaneously connected to the power module VDD and one end of the capacitor C12, the other end of the capacitor C12 is grounded, pin 13 is simultaneously connected to the power module VDD and one end of the capacitor C13, the other end of the capacitor C13 is grounded, pin 2, pin 7, pin 10 and pin 15 of the multi-channel current detection selection chip U4 are connected to one end of the resistor R7, pin 14 of the multi-channel current detection selection chip U3 is connected to pin 51 of the main control chip U1, pin 3 is connected to pin 52 of the main control chip U1, pin 6 is connected to pin 55 of the main control chip U1, and pin 11 is connected to pin 56 of the main control chip U1.

[0018] As a further solution of the present application, the multi-channel current detection selection module also includes a second multi-channel current detection selection circuit, the second multi-channel current detection selection module includes a multi-channel current detection selection chip U5, a capacitor C14 and a capacitor C15, pins 4 and 5 of the multi-channel current detection selection chip U3 are connected and grounded, pin 12 is simultaneously connected to the power module VDD and one end of the capacitor C14, the other end of the capacitor C14 is grounded, pin 13 is simultaneously connected to the power module VDD and one end of the capacitor C15, the other end of the capacitor C15 is grounded, pin 2 of the multi-channel current detection selection chip U5 is connected to one end of the resistor R7, pin 3 of the multi-channel current detection selection chip U5 is connected to pin 57 of the main control chip U1, pin 7 of the multi-channel current detection selection chip U5 is connected to one end of the resistor R22, and pin 6 of the multi-channel current detection selection chip U5 is connected to pin 57 of the main control chip U1.

[0019] As a further solution of the present application, the third multi-channel current detection selection module includes a multi-channel current detection selection chip U6, a capacitor C16 and a capacitor C17, pins 4 and 5 of the multi-channel current detection selection chip U6 are connected and grounded, pin 12 is simultaneously connected to the power module VDD and one end of the capacitor C16, the other end of the capacitor C16 is grounded, pin 13 is simultaneously connected to the power module VDD and one end of the capacitor C17, the other end of the capacitor C17 is grounded, pin 2, pin 7, pin 10 and pin 15 of the multi-channel current detection selection chip U6 are connected to one end of the resistor R22, pin 14 of the multi-channel current detection selection chip U6 is connected to pin 58 of the main control chip U1, pin 3 is connected to pin 59 of the main control chip U1, pin 6 is connected to pin 60 of the main control chip U1, and pin 11 is connected to pin 61 of the main control chip U1.

[0020] Compared with the prior art, this application has the following beneficial effects:

[0021] 1. In the scheme of the present application, multiple independent current output channels are realized through a cleverly designed multi-channel circuit. This design not only enables the device to electrically stimulate different brain areas simultaneously or separately, but also greatly improves the flexibility and pertinence of the treatment. The electrical stimulation parameters of each channel can be flexibly adjusted according to the patient's specific condition and real-time feedback, so as to formulate a more personalized treatment plan. And a multi-channel current detection selection module is set on the basis of the multi-channel circuit, so that the present application can realize the intelligent selection of current paths flowing through different resistors, so that the device can automatically adjust the current path and parameters according to real-time current feedback data to optimize the treatment effect, realize personalized diagnosis and treatment, and improve the accuracy of electrical stimulation.

[0022] 2. The present application can accurately detect the current flowing through each channel through the first current detection circuit and the second current detection circuit in the current detection module, thereby ensuring the safety and effectiveness of electrical stimulation. This design not only helps to adjust the electrical stimulation parameters in a timely manner, but also can issue an alarm in time when the current is abnormal, and cooperates with the reset circuit and crystal oscillator circuit of the present application to improve the stability and safety performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A circuit diagram of a main control chip U1 of a multi-channel cranial electrical stimulation circuit provided in an embodiment of the present application.

[0024] Figure 2 A circuit diagram of a reset circuit for a multi-channel cranial electrical stimulation circuit provided in an embodiment of the present application.

[0025] Figure 3 A circuit diagram of a first debugging serial port of a multi-channel cranial electrical stimulation circuit provided in an embodiment of the present application.

[0026] Figure 4 A circuit diagram of a second debugging serial port of a multi-channel cranial electrical stimulation circuit provided in an embodiment of the present application.

[0027] Figure 5 A circuit diagram of a driving module of a multi-channel cranial electrical stimulation circuit provided in an embodiment of the present application.

[0028] Figure 6 A circuit diagram of a first current detection circuit of a multi-channel cranial electrical stimulation circuit provided in an embodiment of the present application.

[0029] Figure 7 A circuit diagram of a second current detection circuit of a multi-channel cranial electrical stimulation circuit provided in an embodiment of the present application.

[0030] Figure 8 A circuit diagram of a first multi-channel current detection selection circuit of a multi-channel cranial electrical stimulation circuit provided in an embodiment of the present application.

[0031] Fig. 9 A circuit diagram of a second multi-channel current detection selection circuit of a multi-channel cranial electrical stimulation circuit provided in an embodiment of the present application.

[0032] Fig.10 A circuit diagram of a third multi-channel current detection selection circuit of a multi-channel cranial electrical stimulation circuit provided in an embodiment of the present application.

[0033] Fig.11 A circuit diagram of a signal output terminal of a multi-channel cranial electrical stimulation circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] The technical solution of this patent is further described in detail below in conjunction with specific implementation methods.

[0035] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0036] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application; the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance; in addition, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be a connection between the two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0037] The inventors of the present application have discovered that existing TES devices generally face the problem of a single current output channel. Most devices can only provide a fixed current channel during the stimulation process, and the current parameters are preset before the stimulation is started. This single-channel design lacks flexibility, making it impossible for the device to adjust according to the patient's real-time status and feedback, limiting the treatment effect. In addition, existing TES devices also tend to meet different treatment needs in the form of independent single-category products. These devices usually have built-in fixed electrical stimulation programs. Although they provide simple parameter adjustment functions, they cannot achieve more personalized treatment plans. In short, existing TES devices generally have the defects of low precision and poor feedback, which greatly affect the therapeutic effect of transcranial electrical stimulation.

[0038] In view of this, the present application provides a multi-channel cranial electrical stimulation circuit, including: a main control module, a driving module, a current detection module, and a multi-channel current detection selection module;

[0039] Wherein, the main control module is connected to the driving module, the driving module is connected to the current detection module, and the current detection module is connected to the multi-channel current detection selection module;

[0040] A current detection module, wherein the current detection circuit includes a first current detection circuit and a second current detection circuit, wherein the first current detection circuit includes a current detection chip U2 and a resistor R7, wherein the pin 5 of the current detection chip U2 is connected to the pin 16 of the main control chip U1, wherein one end of the resistor R7 is connected to the pin 1 of the current detection chip U2, and the other end is connected to the pin 8 of the current detection chip U2 and forms a resistor voltage divider circuit with the pin 7 of the current detection chip U2 connected to the power module VDD, and the current is detected by measuring the voltage drop across the resistor R7, wherein the second current detection circuit includes a current detection chip U3 and a resistor R22, wherein the pin 5 of the current detection chip U3 is connected to the pin 17 of the main control chip U1, wherein one end of the resistor R22 is connected to the pin 1 of the current detection chip U3, and the other end is connected to the pin 8 of the current detection chip U3 and forms a resistor voltage divider circuit with the pin 7 of the current detection chip U3 connected to the power module VDD, and the current is detected by measuring the voltage drop across the resistor R22;

[0041] A multi-channel current detection selection module, wherein the multi-channel current detection selection module selects the current path flowing through the resistors R7 and R22 by switching the state of the EN pin, wherein the multi-channel current detection selection module includes a first multi-channel current detection selection circuit and a third multi-channel current detection selection circuit; pin 3 of the first multi-channel current detection selection circuit controls conduction between pin 1 and pin 2, and is connected to pin 52 of the main control module, and pin 3 of the third multi-channel current detection selection circuit controls conduction between pin 1 and pin 2, and is connected to pin 59 of the main control module.

[0042] See also Figure 1-4 , Figure 1 A circuit diagram of a main control chip U1 of a multi-channel cranial electrical stimulation circuit provided in an embodiment of the present application. Figure 2 A circuit diagram of a reset circuit for a multi-channel cranial electrical stimulation circuit provided in an embodiment of the present application. Figure 3 A circuit diagram of a first debugging serial port of a multi-channel cranial electrical stimulation circuit provided in an embodiment of the present application. Figure 4 A circuit diagram of a second debugging serial port of a multi-channel cranial electrical stimulation circuit provided in an embodiment of the present application.

[0043] In order to achieve overall control of the device, realize the electrical connection of various components, and improve the overall stability of the device, in this embodiment, the main control module includes a main control chip U1 and a crystal oscillator circuit, wherein the crystal oscillator circuit is connected to pins 12 and 13 of the main control chip U1, and pins 11, 19, 21, 22, 28, 50, 75 and 100 of the main control chip U1 are connected to the power module VDD; the crystal oscillator circuit includes a resistor R1, a resistor R3, a capacitor C1, a capacitor C3 and a crystal oscillator Y1, and pin 12 of the main control chip U1 is simultaneously connected to Connected to one end of the resistor R3, one end of the capacitor C1 and one end of the crystal oscillator Y1, one end of the resistor R3, one end of the capacitor C1 and one end of the crystal oscillator Y1 are connected to each other to form a path, and the other end of the capacitor C1 is grounded; the pin 13 of the main control chip U1 is connected to the resistor R1, and the resistor R1 is simultaneously connected to the other end of the resistor R3, one end of the capacitor C3 and the other end of the crystal oscillator Y1, the other end of the resistor R3, one end of the capacitor C3 and the other end of the crystal oscillator Y1 are connected to each other to form a path, and the other end of the capacitor C3 is grounded; the crystal oscillator Y1 is grounded. The crystal oscillator circuit is used to provide a stable clock signal for the main control chip to ensure the stable operation of the entire circuit system.

[0044] In order to restore the device to its initial state and improve the reliability of the device when an abnormality occurs in the device or a restart is required, in this embodiment, the main control module also includes a reset circuit, and the reset circuit includes a resistor R4, a capacitor C4 and a reset button RST1, wherein one end of the resistor R4 is connected to the power module VDD, and the other end is connected to the capacitor C4; the end of the capacitor C4 away from the resistor R4 is grounded, and the reset button RST1 forms a parallel circuit with the capacitor C4, one end of the reset button RST1 is simultaneously connected to the capacitor C4 and the resistor R4, and the other end is simultaneously connected to the capacitor C4 and the ground end.

[0045] In order to facilitate the user to debug and maintain the equipment, in this embodiment, the main control module also includes a debugging serial port, the debugging serial port includes a first debugging serial port and a second debugging serial port, the first debugging serial port includes a debugging element J5, a resistor R5 and a resistor R6, the pin 1 of the debugging element J5 is simultaneously connected to one end of the resistor R6 and the pin 26 of the main control chip U1, the other end of the resistor R6 is connected to the power module VDD, the pin 2 of the debugging element J5 is grounded, and the pin 3 of the debugging element J5 is simultaneously connected to one end of the resistor R5 and the main control chip U 1, and the other end of the resistor R5 is connected to the power module VDD; the second debugging serial port includes a debugging element J6, a resistor R20 and a resistor R21, pin 1 of the debugging element J6 is simultaneously connected to one end of the resistor R20 and pin 63 of the main control chip U1, the other end of the resistor R20 is connected to the power module VDD, pin 2 of the debugging element J6 is simultaneously connected to one end of the resistor R21 and pin 64 of the main control chip U1, the other end of the resistor R21 is connected to the power module VDD, and pins 3 to 6 of the debugging element J6 are grounded.

[0046] See also Figure 5 , Figure 5 A circuit diagram of a driving module of a multi-channel cranial electrical stimulation circuit provided in an embodiment of the present application. In order to receive a voltage signal from a main control module and amplify the signal so that the driving circuit generates sufficient current for electrical stimulation treatment, in this embodiment, the driving module includes a first signal amplification circuit, a second signal amplification circuit, a third signal amplification circuit, and a fourth signal amplification circuit, wherein the first signal amplification circuit is connected to pin 29 of the main control chip U1, and receives a voltage signal DA1 from the main control chip U1; the second signal amplification circuit is connected to pin 30 of the main control chip U1, and receives a voltage signal DA2 from the main control chip U1; the third signal amplification circuit is connected to pin 33 of the main control chip U1, and receives a voltage signal DA3 from the main control chip U1; the fourth signal amplification circuit is connected to pin 34 of the main control chip U1, and receives a voltage signal DA4 from the main control chip U1.

[0047] In order to enable the driving module to further realize the technical function, multiple independent signal amplification circuits are used to ensure that the multi-channel circuit can work simultaneously or independently. In this embodiment, the first signal amplification circuit includes a resistor R8, a resistor R9, a resistor R16, a capacitor C6, an inductor L1 and a first operational amplifier; one end of the resistor R16 is connected to the pin 29 of the main control chip U1, and the other end is connected to the pin 3 of the first operational amplifier to receive the voltage signal DA1 from the main control chip U1; one end of the resistor R8 is grounded, and the other end is simultaneously connected to one end of the resistor R9 and the pin 2 of the first operational amplifier; the other end of the resistor R9 is connected to the first operational amplifier. The output pin 6 of the amplifier is connected, one end of the inductor L1 is connected to the power module VDD, and the other end is connected to one end of the capacitor C6 and the pin 7 of the first operational amplifier, the other end of the capacitor C6 is grounded, and the pin 4 of the first operational amplifier is grounded; the second signal amplification circuit includes a resistor R10, a resistor R11, a resistor R17, a capacitor C7, an inductor L2 and a second operational amplifier; one end of the resistor R17 is connected to the pin 30 of the main control chip U1, and the other end is connected to the pin 3 of the second operational amplifier to receive the voltage signal DA2 from the main control chip U1, one end of the resistor R10 is grounded, and the other end is connected to the pin 3 of the second operational amplifier to receive the voltage signal DA2 from the main control chip U1, one end of the resistor R10 is grounded, and the other end is connected to the pin 4 of the first operational amplifier to receive the voltage signal DA2 from the main control chip U1 The third signal amplifying circuit comprises a resistor R12, a resistor R13, a resistor R18, a capacitor C9, an inductor L3 and a third operational amplifier; the resistor R18 has one end connected to the pin 33 of the main control chip U1, and the other end connected to the pin 4 of the third operational amplifier; the resistor R18 has one end connected to the pin 33 of the main control chip U1, and the other end connected to the pin 5 of the third operational amplifier; the resistor R18 has one end connected to the pin 33 of the main control chip U1, and the other end connected to the pin 6 of the third operational amplifier; the inductor L2 has one end connected to the power module VDD, and the other end connected to one end of the capacitor C7 and the pin 7 of the second operational amplifier; the other end of the capacitor C7 is grounded, and the pin 4 of the second operational amplifier is grounded; the third signal amplifying circuit comprises a resistor R12, a resistor R13, a resistor R18, a capacitor C9, an inductor L3 and a third operational amplifier; the resistor R18 has one end connected to the pin 33 of the main control chip U1, and the other end connected to the pin 5 of the third operational amplifier. Pin 3 is used to receive the voltage signal DA3 from the main control chip U1. One end of the resistor R12 is grounded, and the other end is connected to one end of the resistor R13 and the pin 2 of the third operational amplifier. The other end of the resistor R13 is connected to the output pin 6 of the third operational amplifier. One end of the inductor L3 is connected to the power module VDD, and the other end is connected to one end of the capacitor C9 and the pin 7 of the third operational amplifier. The other end of the capacitor C9 is grounded, and the pin 4 of the third operational amplifier is grounded. The fourth signal amplification circuit includes a resistor R14, a resistor R15, a resistor R19, a capacitor C10, an inductor L4 and a fourth operational amplifier.One end of the resistor R19 is connected to the pin 34 of the main control chip U1, and the other end is connected to the pin 3 of the fourth operational amplifier to receive the voltage signal DA4 from the main control chip U1. One end of the resistor R14 is grounded, and the other end is simultaneously connected to one end of the resistor R15 and the pin 2 of the fourth operational amplifier. The other end of the resistor R15 is connected to the output pin 6 of the fourth operational amplifier. One end of the inductor L4 is connected to the power module VDD, and the other end is simultaneously connected to one end of the capacitor C10 and the pin 7 of the fourth operational amplifier. The other end of the capacitor C10 is grounded, and the pin 4 of the fourth operational amplifier is grounded. The fourth signal amplification circuit is connected to the pin 34 of the main control chip U1 to receive the voltage signal DA4 from the main control chip U1. The above-mentioned multiple independent signal amplification circuits ensure that the multi-channel circuit can work simultaneously or independently. Preferably, the amplification factor can be 16 times, which can meet the further implementation of TES. ;

[0048] See also Figure 6 and Figure 7 , Figure 6 A circuit diagram of a first current detection circuit of a multi-channel cranial electrical stimulation circuit provided in an embodiment of the present application. Figure 7 A circuit diagram of a second current detection circuit of a multi-channel cranial electrical stimulation circuit provided in an embodiment of the present application.

[0049] In order to accurately detect the current flowing through each electrical stimulation channel, ensure that the current is within a safe range, and provide real-time current feedback data for the main control module to perform intelligent adjustments, in this embodiment, the first current detection circuit includes a current detection chip U2, a resistor R7 and a capacitor C8, and the end of the resistor R7 connected to the current detection chip U2 is also connected to the output pin 6 of the second signal amplifier; the pin 6 of the current detection chip U2 is simultaneously connected to the power module VDD and one end of the capacitor C8, the end of the capacitor C8 connected to the VS pin 6 is connected to the power module VDD, and the other end is grounded, the pin 7 of the current detection chip U2 is connected to the grounded end of the capacitor C8 to form a resistor voltage divider circuit, the pin 5 of the current detection chip U2 is connected to the pin 16 of the main control chip U1, one end of the resistor R7 is connected to the pin 1 of the current detection chip U2, and the other end is connected to the pin 8 of the current detection chip U2 and forms a resistor voltage divider circuit with the pin 7 of the current detection chip U2 connected to the power module VDD, and the current detection circuit is detected by measuring the current detection chip U2. The voltage drop on the resistor R7 is measured to detect the current; the second current detection circuit includes a current detection chip U3, a resistor R22 and a capacitor C11, and one end of the resistor R22 connected to the current detection chip U3 is also connected to the output pin 6 of the fourth signal amplifier; the VS pin 6 of the current detection chip U3 is simultaneously connected to the power module VDD and one end of the capacitor C22, the end of the capacitor C22 connected to the pin 6 is connected to the power module VDD, and the other end is grounded, the pin 7 of the current detection chip U3 is connected to the grounded end of the capacitor C22 to form a resistor voltage divider circuit, which is used for the current detection chip U3 to test the current flowing through the resistor R22, the pin 5 of the current detection chip U3 is connected to the pin 17 of the main control chip U1, one end of the resistor R22 is connected to the pin 1 of the current detection chip U3, and the other end is connected to the pin 8 of the current detection chip U3 and forms a resistor voltage divider circuit with the pin 7 of the current detection chip U3 connected to the power module VDD, and the current is detected by measuring the voltage drop on the resistor R22.

[0050] See also Figure 8 , Figure 8A circuit diagram of a first multi-channel current detection selection circuit of a multi-channel cranial electrical stimulation circuit provided in an embodiment of the present application is provided to realize intelligent selection of current paths flowing through different resistors in the present application, and optimize the current paths and parameters according to real-time current feedback data. In this embodiment, the first multi-channel current detection selection module includes a multi-channel current detection selection chip U4, a capacitor C12 and a capacitor C13, pins 4 and 5 of the multi-channel current detection selection chip U4 are connected and grounded, pin 12 is simultaneously connected to the power module VDD and one end of the capacitor C12, the other end of the capacitor C12 is grounded, pin 13 is simultaneously connected to the power module VDD and one end of the capacitor C13, the other end of the capacitor C13 is grounded, pins 2, 7, 10 and 15 of the multi-channel current detection selection chip U4 are connected to one end of the resistor R7, pin 14 of the multi-channel current detection selection chip U3 is connected to pin 51 of the main control chip U1, pin 3 is connected to pin 52 of the main control chip U1, pin 6 is connected to pin 55 of the main control chip U1, and pin 11 is connected to pin 56 of the main control chip U1.

[0051] See also Fig. 9 , Fig. 9 A circuit diagram of a second multi-channel current detection selection circuit of a multi-channel cranial electrical stimulation circuit provided in an embodiment of the present application. In order to further improve the accuracy and therapeutic effect of electrical stimulation, the current path flowing through different resistors is intelligently selected. In this embodiment, the multi-channel current detection selection module also includes a second multi-channel current detection selection circuit, and the second multi-channel current detection selection module includes a multi-channel current detection selection chip U5, a capacitor C14 and a capacitor C15. Pins 4 and 5 of the multi-channel current detection selection chip U3 are connected and grounded, pin 12 is simultaneously connected to the power module VDD and one end of the capacitor C14, and the other end of the capacitor C14 is grounded, pin 13 is simultaneously connected to the power module VDD and one end of the capacitor C15, and the other end of the capacitor C15 is grounded, pin 2 of the multi-channel current detection selection chip U5 is connected to one end of the resistor R7, pin 3 of the multi-channel current detection selection chip U5 is connected to pin 57 of the main control chip U1, pin 7 of the multi-channel current detection selection chip U5 is connected to one end of the resistor R22, and pin 6 of the multi-channel current detection selection chip U5 is connected to pin 57 of the main control chip U1.

[0052] See also Fig.10 , Fig.10A circuit diagram of a third multi-channel current detection selection circuit of a multi-channel cranial electrical stimulation circuit provided in an embodiment of the present application. In order to provide a more complex and sophisticated current path selection function, personalized adjustment is performed based on real-time current data and main control module signals. In this embodiment, the third multi-channel current detection selection module includes a multi-channel current detection selection chip U6, a capacitor C16 and a capacitor C17. Pins 4 and 5 of the multi-channel current detection selection chip U6 are connected and grounded, pin 12 is simultaneously connected to the power module VDD and one end of the capacitor C16, and the other end of the capacitor C16 is grounded, pin 13 is simultaneously connected to the power module VDD and one end of the capacitor C17, and the other end of the capacitor C17 is grounded, pin 2, pin 7, pin 10 and pin 15 of the multi-channel current detection selection chip U6 are connected to one end of the resistor R22, pin 14 of the multi-channel current detection selection chip U6 is connected to pin 58 of the main control chip U1, pin 3 is connected to pin 59 of the main control chip U1, pin 6 is connected to pin 60 of the main control chip U1, and pin 11 is connected to pin 61 of the main control chip U1.

[0053] See also Fig.11 , Fig.11 A circuit diagram of a signal output terminal of a multi-channel cranial electrical stimulation circuit provided in an embodiment of the present application. The driving module and the multi-channel current detection selection module can be selectively connected. In this embodiment, four signal output ports can be set to allow the amplified signal of the driving module to be further transmitted to the multi-channel current detection selection chip. Pin 1 of the first signal port J1 is connected to pin 1 of the multi-channel current detection selection chip U5, and pin 2 of the first signal port J1 is connected to output pin 6 of the first signal amplifier of the first signal amplification circuit; pin 1 of the second signal port J2 is connected to pin 9 of the multi-channel current detection selection chip U4, pin 2 is connected to pin 8 of the multi-channel current detection selection chip U4, pin 3 is connected to pin 1 of the multi-channel current detection selection chip U4, pin 4 is connected to pin 16 of the multi-channel current detection selection chip U4, and the second signal port J2 is connected to pin 1 of the multi-channel current detection selection chip U4. Pin 5 of port J2 is connected to output pin 6 of the first signal amplifier of the first signal amplifying circuit; pin 1 of the third signal port J3 is connected to pin 8 of the multi-channel current detection selection chip U5, and pin 2 of the third signal port J3 is connected to output pin 6 of the third signal amplifier of the third signal amplifying circuit; pin 1 of the fourth signal port J4 is connected to pin 9 of the multi-channel current detection selection chip U6, pin 2 is connected to pin 8 of the multi-channel current detection selection chip U6, pin 3 is connected to pin 1 of the multi-channel current detection selection chip U6, and pin 4 is connected to pin 16 of the multi-channel current detection selection chip U6, and pin 5 of the fourth signal port J4 is connected to output pin 6 of the third signal amplifier of the third signal amplifying circuit.

[0054] The above describes in detail the preferred implementation of this patent, but this patent is not limited to the above implementation. Various changes can be made within the knowledge scope of ordinary technicians in this field without departing from the purpose of this patent.

Claims

1. A multi-channel cranial electrical stimulation circuit, characterized in that: include: Main control module, drive module, current detection module, multi-channel current detection selection module; The main control module is connected to the driving module, the current detection module, and the multi-channel current detection selection module; the driving module is connected to the current detection module; and the current detection module is connected to the multi-channel current detection selection module; A current detection module, wherein the current detection circuit includes a first current detection circuit and a second current detection circuit, wherein the first current detection circuit includes a current detection chip U2 and a resistor R7, wherein the pin 5 of the current detection chip U2 is connected to the pin 16 of the main control chip U1, wherein one end of the resistor R7 is connected to the pin 1 of the current detection chip U2, and the other end is connected to the pin 8 of the current detection chip U2 and forms a resistor voltage divider circuit with the pin 7 of the current detection chip U2 connected to the power module VDD, and the current is detected by measuring the voltage drop across the resistor R7, wherein the second current detection circuit includes a current detection chip U3 and a resistor R22, wherein the pin 5 of the current detection chip U3 is connected to the pin 17 of the main control chip U1, wherein one end of the resistor R22 is connected to the pin 1 of the current detection chip U3, and the other end is connected to the pin 8 of the current detection chip U3 and forms a resistor voltage divider circuit with the pin 7 of the current detection chip U3 connected to the power module VDD, and the current is detected by measuring the voltage drop across the resistor R22; A multi-channel current detection selection module, wherein the multi-channel current detection selection module selects the current path flowing through the resistors R7 and R22 by switching the state of the EN pin, wherein the multi-channel current detection selection module includes a first multi-channel current detection selection circuit and a third multi-channel current detection selection circuit; pin 3 of the first multi-channel current detection selection circuit controls conduction between pin 1 and pin 2, and is connected to pin 52 of the main control module, and pin 3 of the third multi-channel current detection selection circuit controls conduction between pin 1 and pin 2, and is connected to pin 59 of the main control module.

2. A multi-channel cranial electrical stimulation circuit according to claim 1, characterized in that: The main control module includes a main control chip U1 and a crystal oscillator circuit, wherein the crystal oscillator circuit is connected to pins 12 and 13 of the main control chip U1, and pins 11, 19, 21, 22, 28, 50, 75 and 100 of the main control chip U1 are connected to the power supply module VDD; the crystal oscillator circuit includes a resistor R1, a resistor R3, a capacitor C1, a capacitor C3 and a crystal oscillator Y1, and pin 12 of the main control chip U1 is simultaneously connected to one end of the resistor R3, one end of the capacitor C1 and the crystal One end of the oscillator Y1, one end of the resistor R3, one end of the capacitor C1 and one end of the crystal oscillator Y1 are interconnected to form a path, and the other end of the capacitor C1 is grounded; the pin 13 of the main control chip U1 is connected to the resistor R1, and the resistor R1 is simultaneously connected to the other end of the resistor R3, one end of the capacitor C3 and the other end of the crystal oscillator Y1, the other end of the resistor R3, one end of the capacitor C3 and the other end of the crystal oscillator Y1 are interconnected to form a path, and the other end of the capacitor C3 is grounded; the crystal oscillator Y1 is grounded.

3. A multi-channel cranial electrical stimulation circuit according to claim 1, characterized in that: The main control module also includes a reset circuit, which includes a resistor R4, a capacitor C4 and a reset button RST1, wherein one end of the resistor R4 is connected to the power module VDD, and the other end is connected to the capacitor C4; one end of the capacitor C4 away from the resistor R4 is grounded, and the reset button RST1 and the capacitor C4 form a parallel circuit, one end of the reset button RST1 is simultaneously connected to the capacitor C4 and the resistor R4, and the other end is simultaneously connected to the capacitor C4 and the ground end.

4. A multi-channel cranial electrical stimulation circuit according to claim 1, characterized in that: The main control module also includes a debugging serial port, which includes a first debugging serial port and a second debugging serial port. The first debugging serial port includes a debugging element J5, a resistor R5 and a resistor R6. Pin 1 of the debugging element J5 is simultaneously connected to one end of the resistor R6 and pin 26 of the main control chip U1, the other end of the resistor R6 is connected to the power module VDD, pin 2 of the debugging element J5 is grounded, pin 3 of the debugging element J5 is simultaneously connected to one end of the resistor R5 and pin 25 of the main control chip U1, and the other end of the resistor R5 is connected to the power module VDD; the second debugging serial port includes a debugging element J6, a resistor R20 and a resistor R21. Pin 1 of the debugging element J6 is simultaneously connected to one end of the resistor R20 and pin 63 of the main control chip U1, the other end of the resistor R20 is connected to the power module VDD, pin 2 of the debugging element J6 is simultaneously connected to one end of the resistor R21 and pin 64 of the main control chip U1, the other end of the resistor R21 is connected to the power module VDD, and pins 3 to 6 of the debugging element J6 are grounded.

5. The multi-channel cranial electrical stimulation circuit according to claim 1, characterized in that: The driving module includes a first signal amplifying circuit, a second signal amplifying circuit, a third signal amplifying circuit, and a fourth signal amplifying circuit, wherein the first signal amplifying circuit is connected to pin 29 of the main control chip U1, and receives a voltage signal DA1 from the main control chip U1; the second signal amplifying circuit is connected to pin 30 of the main control chip U1, and receives a voltage signal DA2 from the main control chip U1; the third signal amplifying circuit is connected to pin 33 of the main control chip U1, and receives a voltage signal DA3 from the main control chip U1; the fourth signal amplifying circuit is connected to pin 34 of the main control chip U1, and receives a voltage signal DA4 from the main control chip U1.

6. A multi-channel cranial electrical stimulation circuit according to claim 5, characterized in that: The first signal amplifying circuit includes a resistor R8, a resistor R9, a resistor R16, a capacitor C6, an inductor L1 and a first operational amplifier; one end of the resistor R16 is connected to the pin 29 of the main control chip U1, and the other end is connected to the pin 3 of the first operational amplifier to receive the voltage signal DA1 from the main control chip U1; one end of the resistor R8 is grounded, and the other end is simultaneously connected to one end of the resistor R9 and the pin 2 of the first operational amplifier; the other end of the resistor R9 is connected to the output pin 6 of the first operational amplifier; one end of the inductor L1 is connected to the power module VDD, and the other end is simultaneously connected to The first operational amplifier is connected to one end of the capacitor C6 and the pin 7 of the first operational amplifier, the other end of the capacitor C6 is grounded, and the pin 4 of the first operational amplifier is grounded; the second signal amplifying circuit includes a resistor R10, a resistor R11, a resistor R17, a capacitor C7, an inductor L2 and a second operational amplifier; one end of the resistor R17 is connected to the pin 30 of the main control chip U1, and the other end is connected to the pin 3 of the second operational amplifier to receive the voltage signal DA2 from the main control chip U1, one end of the resistor R10 is grounded, and the other end is simultaneously connected to one end of the resistor R11 and the pin 2 of the second operational amplifier, the The other end of the resistor R11 is connected to the output pin 6 of the second operational amplifier, one end of the inductor L2 is connected to the power module VDD, and the other end is connected to one end of the capacitor C7 and the pin 7 of the second operational amplifier, the other end of the capacitor C7 is grounded, and the pin 4 of the second operational amplifier is grounded; the third signal amplification circuit includes a resistor R12, a resistor R13, a resistor R18, a capacitor C9, an inductor L3 and a third operational amplifier; one end of the resistor R18 is connected to the pin 33 of the main control chip U1, and the other end is connected to the pin 3 of the third operational amplifier to receive the signal from the main control chip U1. 1, one end of the resistor R12 is grounded, and the other end is connected to one end of the resistor R13 and the pin 2 of the third operational amplifier, the other end of the resistor R13 is connected to the output pin 6 of the third operational amplifier, one end of the inductor L3 is connected to the power module VDD, and the other end is connected to one end of the capacitor C9 and the pin 7 of the third operational amplifier, the other end of the capacitor C9 is grounded, and the pin 4 of the third operational amplifier is grounded; the fourth signal amplifying circuit includes a resistor R14, a resistor R15, a resistor R19, a capacitor C10, an inductor L4 and a fourth operational amplifier;One end of the resistor R19 is connected to the pin 34 of the main control chip U1, and the other end is connected to the pin 3 of the fourth operational amplifier to receive the voltage signal DA4 from the main control chip U1. One end of the resistor R14 is grounded, and the other end is simultaneously connected to one end of the resistor R15 and the pin 2 of the fourth operational amplifier. The other end of the resistor R15 is connected to the output pin 6 of the fourth operational amplifier. One end of the inductor L4 is connected to the power module VDD, and the other end is simultaneously connected to one end of the capacitor C10 and the pin 7 of the fourth operational amplifier. The other end of the capacitor C10 is grounded, and the pin 4 of the fourth operational amplifier is grounded. The fourth signal amplification circuit is connected to the pin 34 of the main control chip U1 to receive the voltage signal DA4 from the main control chip U1. ; 7. A multi-channel cranial electrical stimulation circuit according to claim 1, characterized in that: The first current detection circuit includes a current detection chip U2, a resistor R7 and a capacitor C8, one end of the resistor R7 connected to the current detection chip U2 is also connected to the output pin 6 of the second signal amplifier; the pin 6 of the current detection chip U2 is simultaneously connected to the power module VDD and one end of the capacitor C8, the end of the capacitor C8 connected to the VS pin 6 is connected to the power module VDD, and the other end is grounded, the pin 7 of the current detection chip U2 is connected to the grounded end of the capacitor C8 to form a resistor voltage divider circuit, the pin 5 of the current detection chip U2 is connected to the pin 16 of the main control chip U1, one end of the resistor R7 is connected to the pin 1 of the current detection chip U2, and the other end is connected to the pin 8 of the current detection chip U2 and forms a resistor voltage divider circuit with the pin 7 of the current detection chip U2 connected to the power module VDD, and the current is detected by measuring the voltage drop on the resistor R7; the second current detection circuit includes a current detection chip The VS pin 6 of the current detection chip U3 is simultaneously connected to the power module VDD and one end of the capacitor C22, the end of the capacitor C22 connected to the pin 6 is connected to the power module VDD, and the other end is grounded, the pin 7 of the current detection chip U3 is connected to the grounded end of the capacitor C22 to form a resistor voltage divider circuit, which is used for the current detection chip U3 to test the current flowing through the resistor R22, the pin 5 of the current detection chip U3 is connected to the pin 17 of the main control chip U1, one end of the resistor R22 is connected to the pin 1 of the current detection chip U3, and the other end is connected to the pin 8 of the current detection chip U3 and forms a resistor voltage divider circuit with the pin 7 of the current detection chip U3 connected to the power module VDD, and the current is detected by measuring the voltage drop on the resistor R22.

8. The multi-channel cranial electrical stimulation circuit according to claim 1, characterized in that: The first multi-channel current detection selection module includes a multi-channel current detection selection chip U4, a capacitor C12 and a capacitor C13. Pin 4 and pin 5 of the multi-channel current detection selection chip U4 are connected and grounded, pin 12 is simultaneously connected to the power module VDD and one end of the capacitor C12, and the other end of the capacitor C12 is grounded, pin 13 is simultaneously connected to the power module VDD and one end of the capacitor C13, and the other end of the capacitor C13 is grounded, pin 2, pin 7, pin 10 and pin 15 of the multi-channel current detection selection chip U4 are connected to one end of the resistor R7, pin 14 of the multi-channel current detection selection chip U3 is connected to pin 51 of the main control chip U1, pin 3 is connected to pin 52 of the main control chip U1, pin 6 is connected to pin 55 of the main control chip U1, and pin 11 is connected to pin 56 of the main control chip U1.

9. The multi-channel cranial electrical stimulation circuit according to claim 1, characterized in that: The multi-channel current detection selection module also includes a second multi-channel current detection selection circuit, which includes a multi-channel current detection selection chip U5, a capacitor C14 and a capacitor C15. Pins 4 and 5 of the multi-channel current detection selection chip U3 are connected and grounded, pin 12 is simultaneously connected to the power module VDD and one end of the capacitor C14, and the other end of the capacitor C14 is grounded, pin 13 is simultaneously connected to the power module VDD and one end of the capacitor C15, and the other end of the capacitor C15 is grounded, pin 2 of the multi-channel current detection selection chip U5 is connected to one end of the resistor R7, pin 3 of the multi-channel current detection selection chip U5 is connected to pin 57 of the main control chip U1, pin 7 of the multi-channel current detection selection chip U5 is connected to one end of the resistor R22, and pin 6 of the multi-channel current detection selection chip U5 is connected to pin 57 of the main control chip U1.

10. The multi-channel cranial electrical stimulation circuit according to claim 1, characterized in that: The third multi-channel current detection selection module includes a multi-channel current detection selection chip U6, a capacitor C16 and a capacitor C17, pins 4 and 5 of the multi-channel current detection selection chip U6 are connected and grounded, pin 12 is simultaneously connected to the power module VDD and one end of the capacitor C16, the other end of the capacitor C16 is grounded, pin 13 is simultaneously connected to the power module VDD and one end of the capacitor C17, the other end of the capacitor C17 is grounded, pin 2, pin 7, pin 10 and pin 15 of the multi-channel current detection selection chip U6 are connected to one end of the resistor R22, pin 14 of the multi-channel current detection selection chip U6 is connected to pin 58 of the main control chip U1, pin 3 is connected to pin 59 of the main control chip U1, pin 6 is connected to pin 60 of the main control chip U1, and pin 11 is connected to pin 61 of the main control chip U1.

Images