A package substrate structure and a method of manufacturing the same

Abstract

The application provides a packaging substrate structure and a preparation method thereof. The preparation method comprises the following steps: arranging a patterned conductive layer on the upper and lower surfaces of a core layer, arranging a dielectric build-up layer on the patterned conductive layer, arranging a silicon-based intermediate layer build-up layer on the dielectric build-up layer, and arranging a patterned solder mask layer on the upper and lower surfaces of the formed structure to lead out the conductive connection. The application sets the silicon-based intermediate layer on the dielectric build-up layer of the packaging substrate, utilizes the high flatness and low ductility of the silicon-based intermediate layer on the dielectric build-up layer, reduces the warping problem of the packaging substrate, and improves the flatness of the surface of the packaging substrate. Meanwhile, the silicon-based intermediate layer has a low dielectric constant and dielectric loss factor, and can improve the performance of the packaging substrate. In addition, the silicon-based intermediate layer can be used to make finer lines, and the packaging substrate structure with higher density integration can be realized. Finally, the two silicon-based intermediate layers wrap the intermediate conductive layer, and further improve the performance of the packaging substrate.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor integrated circuit manufacturing, and particularly relates to a packaging substrate structure and a preparation method thereof. BACKGROUND

[0002] With the rapid development of the semiconductor industry technology, the number of input and output pins (I / O) on the chip increases, and the packaging substrate, as a connecting bridge between the chip and the printed circuit board, requires higher and higher line fineness, which puts forward more stringent requirements for the preparation of the packaging substrate, and the traditional packaging substrate cannot meet the demand. In addition, heterogeneous integration applications are becoming more and more widespread, and multiple chips are embedded on the packaging substrate to form 2.5D or 3D multi-chip packaging, which also requires the packaging substrate to have smaller wiring density and higher integration. At the same time, the heterogeneous integration technology also further increases the manufacturing cost of the packaging substrate.

[0003] In the prior art, a silicon-based intermediate layer is usually embedded in the packaging substrate to improve the wiring density of the packaging substrate. However, the process of setting a groove to embed the silicon-based intermediate layer is prone to cause warping problems of the packaging substrate, and the process flow is also relatively complex and the cost is high.

[0004] Therefore, there is an urgent need for a packaging substrate structure and a preparation method which can realize high-precision lines while avoiding warping problems and reducing process costs.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of clearly and completely describing the technical solutions of the present application, and for the convenience of understanding by those skilled in the art, and cannot be considered as the prior art known by those skilled in the art only because these solutions are described in the background section of the present application. SUMMARY

[0006] In view of the above shortcomings of the prior art, the purpose of the present application is to provide a packaging substrate structure and a preparation method thereof, which are used to solve the warping problem of the packaging substrate in the prior art.

[0007] To achieve the above-mentioned purpose, the present application provides a preparation method of a packaging substrate structure, which comprises:

[0008] providing a core plate, the core plate comprising oppositely arranged upper and lower surfaces, the upper and lower surfaces each being provided with a first conductive layer, the core plate and the first conductive layer constituting a core plate layer;

[0009] providing a through groove in the core plate layer;

[0010] covering the surface exposed after the through groove is provided in the core plate layer with a first seed conductive layer, and covering the surface of the first seed conductive layer with a second conductive layer;

[0011] filling layer fills the gap of the second conductive layer in the through slot and covers the surface of the second conductive layer;

[0012] a third conductive layer is arranged on the surface of the filling layer;

[0013] a patterned first mask layer is arranged on the surface of the third conductive layer, exposing part of the third conductive layer below;

[0014] the exposed third conductive layer and the filling layer, the second conductive layer, the first seed conductive layer and the first conductive layer below the third conductive layer are etched, exposing part of the core board;

[0015] the first mask layer is removed, exposing the third conductive layer below, and the third conductive layer, the filling layer, the second conductive layer, the first seed conductive layer and the first conductive layer form a patterned conductive layer;

[0016] a substrate dielectric layer is arranged on the surface of the third conductive layer, which fills the gap of the patterned conductive layer after etching and covers its surface;

[0017] a dielectric layer is arranged on the surface of the substrate dielectric layer;

[0018] a silicon-based intermediate layer is arranged on the dielectric layer;

[0019] a patterned outer plating layer is arranged on the upper surface and the lower surface of the packaging substrate structure formed so far, and the outer plating layer forms a conductive connection part with the part of the packaging substrate structure formed so far which is pre-designed to be conductively connected;

[0020] a patterned solder resist layer is arranged on the outer plating layer, which fills the gap between the patterned outer plating layer and exposes the conductive connection part pre-designed to be led out.

[0021] Optionally, the preparation method of the dielectric layer comprises:

[0022] a first blind hole is arranged on the substrate dielectric layer, exposing the third conductive layer which is pre-designed to be conductively connected;

[0023] a second seed conductive layer is arranged on the substrate dielectric layer after the first blind hole, covering the substrate dielectric layer and exposing the third conductive layer;

[0024] a patterned second mask layer is arranged on the second seed conductive layer;

[0025] a conductive layer is filled in the gap between the patterned second mask layer;

[0026] removing the second mask layer and the second seed conductive layer exposed below the second mask layer to expose a portion of the substrate dielectric layer, thereby obtaining the patterned build-up conductive layer and the patterned second seed conductive layer;

[0027] A build-up dielectric layer is filled in the gap between the patterned build-up conductive layer and the second seed conductive layer, thereby obtaining the dielectric build-up layer.

[0028] Optionally, the method for preparing the silicon-based intermediate layer build-up layer includes:

[0029] Disposing a silicon-based intermediate layer on the surface of the dielectric build-up layer, and disposing a second blind hole penetrating the silicon-based intermediate layer and the uppermost build-up dielectric layer of the dielectric build-up layer to expose a portion of the dielectric build-up layer that is predetermined to be electrically conductively connected;

[0030] Disposing a third seed conductive layer on the surface of the silicon-based intermediate layer, wherein the third seed conductive layer covers the silicon-based intermediate layer and the surface exposed by the second blind hole;

[0031] Disposing a patterned third mask layer on the surface of the third conductive seed layer;

[0032] filling the gaps between the patterned third mask layers with an intermediate conductive layer;

[0033] removing the third mask layer and the third seed conductive layer exposed below the third mask layer to expose a portion of the silicon-based intermediate layer, thereby obtaining the patterned intermediate conductive layer and the patterned third seed conductive layer;

[0034] An intermediate dielectric layer is covered on the patterned intermediate conductive layer and the third seed conductive layer. The intermediate dielectric layer fills the gap between the patterned intermediate conductive layer and the third seed conductive layer, thereby obtaining a silicon-based intermediate layer build-up layer.

[0035] Optionally, after removing the third mask layer and the third seed conductive layer exposed below the third mask layer, a silicon-based intermediate layer is further covered on the exposed third seed conductive layer, the intermediate conductive layer and the silicon-based intermediate layer, and then the intermediate dielectric layer is covered.

[0036] Optionally, the dielectric build-up layer is repeatedly provided multiple times to form a multi-layer stack of the dielectric build-up layer; and / or the silicon-based intermediate layer build-up layer is repeatedly provided multiple times to form a multi-layer stack of the silicon-based intermediate layer build-up layer.

[0037] Optionally, the surface of the silicon-based intermediate layer is plasma bombarded with CF4 gas, and the surface of the silicon-based intermediate layer bombarded with plasma is brought into contact with the build-up dielectric layer of the uppermost dielectric build-up layer; or the surface of the silicon-based intermediate layer is chemically etched, and the surface of the silicon-based intermediate layer that is chemically etched is brought into contact with the build-up dielectric layer of the uppermost dielectric build-up layer.

[0038] Optionally, the silicon-based intermediate layer build-up layer is disposed on only one of the two oppositely disposed surfaces of the packaging substrate structure, or the silicon-based intermediate layer build-up layer is disposed on both oppositely disposed surfaces of the packaging substrate structure.

[0039] The present invention also provides a packaging substrate structure, which is obtained by any of the above-mentioned preparation methods, and comprises: a core board, a patterned conductive layer, a substrate dielectric layer, a dielectric build-up layer, a silicon-based intermediate layer build-up layer, an outer plating layer, and a patterned solder resist layer;

[0040] The graphic conductive layer is arranged on the upper surface and the lower surface of the core board and passes through the core board at a preset position. The substrate dielectric layer covers the graphic conductive layer and covers the gaps in the graphic conductive layer; the dielectric build-up layer is arranged on the substrate dielectric layer, and the silicon-based intermediate layer build-up layer is arranged on the dielectric build-up layer. The graphic outer plating layer is provided with a conductive connection at a portion preset for conductive connection with the surface of the packaging substrate structure. The solder resist layer covers the outer plating layer and fills the gaps between the outer plating layers. Conductive connection parts are formed in sequence among the core board, the graphic conductive layer, the dielectric build-up layer, the silicon-based intermediate layer build-up layer, and the outer plating layer. The conductive connection parts are led out to the surface of the packaging substrate structure through the outer plating layer.

[0041] Optionally, the silicon-based intermediate layer build-up layer is provided on only one of the two oppositely disposed surfaces of the packaging substrate structure, or the silicon-based intermediate layer build-up layer is provided on both of the oppositely disposed surfaces of the packaging substrate structure.

[0042] Optionally, the silicon-based intermediate layer build-up layer includes two silicon-based intermediate layers, a third seed conductive layer, an intermediate conductive layer and an intermediate dielectric layer. The third seed conductive layer and the intermediate conductive layer are arranged between the two silicon-based intermediate layers. The intermediate dielectric layer covers the silicon-based intermediate layer on the side of the silicon-based intermediate layer build-up layer away from the core plate layer, and the intermediate dielectric layer is in contact with the outer plating layer.

[0043] As described above, the package substrate structure and the preparation method thereof of the present invention have the following beneficial effects:

[0044] The application reduces the warping problem of the packaging substrate and improves the flatness of the packaging substrate by arranging the silicon-based intermediate layer on the dielectric build-up layer of the packaging substrate, using the high flatness and low ductility of the silicon-based intermediate layer on the dielectric build-up layer;

[0045] The silicon-based intermediate layer has low dielectric constant and low dielectric loss factor, and can improve the performance of the packaging substrate;

[0046] The silicon-based intermediate layer can be used to make finer lines, and the packaging substrate structure with higher integration density can be realized.

[0047] The two silicon-based intermediate layers can further improve the performance of the packaging substrate. BRIEF DESCRIPTION OF DRAWINGS

[0048] Figure 1 The structure diagram shown in step 1 of the embodiment one of the application.

[0049] Figure 2 The structure diagram shown in step 2 of the embodiment one of the application.

[0050] Figure 3 The structure diagram shown in step 3 of the embodiment one of the application.

[0051] Figure 4 The structure diagram shown in step 4 of the embodiment one of the application.

[0052] Figure 5 The structure diagram shown in step 5 of the embodiment one of the application.

[0053] Figure 6 The structure diagram shown in step 6 of the embodiment one of the application.

[0054] Figure 7 The structure diagram shown in step 7 of the embodiment one of the application.

[0055] Figure 8 The structure diagram shown in step 8 of the embodiment one of the application.

[0056] Figure 9 The structure diagram shown in step 9 of the embodiment one of the application and the optional example of step 10.

[0057] Figure 10The structure diagram shown in step 10 of the embodiment one of the present application is an optional example of setting the second seed conductive layer.

[0058] Figure 11 The structure diagram shown in step 10 of the embodiment one of the present application is an optional example of setting the second mask layer.

[0059] Figure 12 The structure diagram shown in step 10 of the embodiment one of the present application is an optional example of filling the conductive layer.

[0060] Figure 13 The structure diagram shown in step 10 of the embodiment one of the present application is an optional example of removing the second mask layer and the second seed conductive layer.

[0061] Figure 14 The structure diagram shown in step 10 of the embodiment one of the present application is an optional example of filling the dielectric layer.

[0062] Figure 15 The structure diagram shown in step 10 of the embodiment one of the present application is an optional example of setting the two dielectric layers.

[0063] Figure 16 The structure diagram shown in step 11 of the embodiment one of the present application is an optional example of setting the silicon-based intermediate layer and the second blind hole.

[0064] Figure 17 The structure diagram shown in step 11 of the embodiment one of the present application is an optional example of setting the third seed conductive layer.

[0065] Figure 18 The structure diagram shown in step 11 of the embodiment one of the present application is an optional example of setting the third mask layer.

[0066] Figure 19 The structure diagram shown in step 11 of the embodiment one of the present application is an optional example of filling the intermediate conductive layer.

[0067] Figure 20 The structure diagram shown in step 11 of the embodiment one of the present application is an optional example of removing the third mask layer and the third seed conductive layer.

[0068] Figure 21 The structure diagram shown in step 11 of the embodiment one of the present application is an optional example of covering the intermediate dielectric layer and setting the two silicon-based intermediate layer.

[0069] Figure 22 The structure diagram shown in step 12 of the embodiment one of the present application is an optional example of setting the outer plating layer.

[0070] Figure 23 The structure diagram of covering the solder resist layer in step 13 of the embodiment one of the present application.

[0071] Figure 24 The structure diagram of setting the silicon-based intermediate layer and the second blind hole in step 11 of the optional example of the embodiment two of the present application.

[0072] Figure 25 The structure diagram of setting the third seed conductive layer in step 11 of the optional example of the embodiment two of the present application.

[0073] Figure 26 The structure diagram of setting the third mask layer in step 11 of the optional example of the embodiment two of the present application.

[0074] Figure 27 The structure diagram of filling the intermediate conductive layer in step 11 of the optional example of the embodiment two of the present application.

[0075] Figure 28 The structure diagram of removing the third mask layer and the third seed conductive layer in step 11 of the optional example of the embodiment two of the present application.

[0076] Figure 29 The structure diagram of covering the intermediate dielectric layer and setting two layers of the silicon-based intermediate layer in step 11 of the optional example of the embodiment two of the present application.

[0077] Figure 30 The structure diagram of setting the outer plating layer in step 12 of the embodiment two of the present application.

[0078] Figure 31 The structure diagram of covering the solder resist layer in step 13 of the embodiment two of the present application.

[0079] Figure 32 The structure diagram of the two layers of the silicon-based intermediate layer wrapping the third seed conductive layer and the intermediate conductive layer in the package substrate structure of the embodiment five of the present application.

[0080] Explanation of element number

[0081] 11, core board; 12, first conductive layer; 13, through slot; 14, first seed conductive layer; 15, second conductive layer; 16, filling layer; 17, third conductive layer; 18, first mask layer; 19, substrate dielectric layer;

[0082] 21, first blind hole; 22, second seed conductive layer; 23, second mask layer; 24, build-up conductive layer; 25, build-up dielectric layer; 31, silicon-based intermediate layer; 32, second blind hole; 33, third seed conductive layer; 34, third mask layer; 35, intermediate conductive layer; 36, intermediate dielectric layer;

[0083] 41, fourth seed conductive layer; 42, outer plating conductive layer; 43, solder mask layer; 44, protective layer. DETAILED DESCRIPTION

[0084] Other advantages and effects of the present application will be easily understood by those skilled in the art from the above description. The present application can also be implemented or applied in other different embodiments, and the details in the description can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0085] In the detailed description of the embodiments of the present application, the schematic diagrams showing the structures of the devices are partially enlarged without the general scale for the convenience of description, and the schematic diagrams are only examples which should not limit the scope of protection of the present application. In addition, the three-dimensional spatial dimensions including length, width and depth should be included in the actual manufacture.

[0086] For the convenience of description, spatial relationship words such as "under", "below", "lower", "underneath", "above", "upper" and the like can be used herein to describe the relationship of one element or feature with other elements or features shown in the drawings. It will be understood that these spatial relationship words are intended to include other orientations of the device in use or operation in addition to the orientations depicted in the drawings.

[0087] In the context of the present application, the structure in which the first feature is "on" the second feature can include the embodiment in which the first and second features form direct contact, and can also include the embodiment in which additional features are formed between the first and second features, so that the first and second features can not be in direct contact.

[0088] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the present application, and only the components related to the present application are shown in the diagrams, not the number, shape and size of the components when actually implemented. The actual implementation of each component can be a random change, and the layout pattern of the components can be more complex.

[0089] Embodiment one:

[0090] As shown in Figures 1-23 The present application provides a preparation method of a packaging substrate structure, the preparation method comprising:

[0091] Step 1: providing a core plate 11, the core plate 11 comprising opposite upper and lower surfaces, both of which are provided with a first conductive layer 12, the core plate 11 and the first conductive layer 12 constituting a core plate layer;

[0092] Step 2: providing a through slot 13 in the core plate layer;

[0093] Step 3: covering the surface exposed after the through slot 13 is provided in the core plate layer with a first seed conductive layer 14, and covering the surface of the first seed conductive layer 14 with a second conductive layer 15;

[0094] Step 4: filling the through slot 13 with a filling layer 16, the filling layer 16 filling the gap of the second conductive layer 15 in the through slot 13 and covering the surface of the second conductive layer 15;

[0095] Step 5: providing a third conductive layer 17 on the surface of the filling layer 16;

[0096] Step 6: providing a patterned first mask layer 18 on the surface of the third conductive layer 17, and exposing part of the underlying third conductive layer 17;

[0097] Step 7: etching the exposed third conductive layer 17 and the filling layer 16, the second conductive layer 15, the first seed conductive layer 14 and the first conductive layer 12 underlying the third conductive layer 17, and exposing part of the core plate 11;

[0098] Step 8: removing the first mask layer 18, and exposing the underlying third conductive layer 17, the patterned conductive layer composed of the third conductive layer 17, the filling layer 16, the second conductive layer 15, the first seed conductive layer 14 and the first conductive layer 12, both of the upper and lower surfaces of the core plate 11 being provided with the patterned conductive layer;

[0099] Step 9: providing a substrate dielectric layer 19 on the surface of the third conductive layer 17 close to both the upper and lower surfaces of the core plate 11, the substrate dielectric layer 19 filling the gap of the patterned conductive layer after etching and covering the surface thereof;

[0100] Step 10: providing a dielectric layer on the surface of the substrate dielectric layer 19 close to both the upper and lower surfaces of the core plate 11;

[0101] Step 11: providing a silicon-based intermediate layer on the surface of the dielectric layer close to both the upper and lower surfaces of the core plate 11;

[0102] Step 12: forming conductive connection portions on the upper surface of the formed encapsulation substrate structure by patterning the outer plating layer and the portions of the silicon-based intermediate layer incrementally arranged near the upper surface of the core plate 11 to be conductively connected; and forming conductive connection portions on the lower surface of the formed encapsulation substrate structure by patterning the outer plating layer and the portions of the silicon-based intermediate layer incrementally arranged near the lower surface of the core plate 11 to be conductively connected;

[0103] Step 13: covering the outer plating layer with a patterned solder resist layer 43, which fills the gaps between the patterned outer plating layer and exposes the conductive connection portions of the outer plating layer.

[0104] The preparation method of the encapsulation substrate structure of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the preparation method of the encapsulation substrate structure of the present application, and those skilled in the art can change the actual preparation steps accordingly.

[0105] First, as shown in FIG. 1, step 1 is performed to provide a core plate 11, which includes oppositely arranged upper and lower surfaces, and each of the upper and lower surfaces is provided with a first conductive layer 12. The core plate 11 and the first conductive layer 12 constitute a core plate layer. Figure 1

[0106] In one embodiment, the material of the first conductive layer 12 is a copper layer.

[0107] In one embodiment, the first conductive layer 12 is thinned.

[0108] In one embodiment, the thickness of the first conductive layer 12 is 10-15 microns, and the thickness of the thinned first conductive layer 12 is 2.5-3.5 microns.

[0109] Then, as shown in FIG. 2, step 2 is performed to provide a through slot 13 in the core plate layer. Figure 2

[0110] In one embodiment, the through slot 13 is provided by mechanical drilling.

[0111] Next, as shown in FIG. 3, step 3 is performed to cover the exposed surface of the core plate layer after the through slot 13 is provided with a first seed conductive layer 14, and to cover the surface of the first seed conductive layer 14 with a second conductive layer 15. Figure 3

[0112] In one embodiment, the first seed conductive layer 14 is a chemical copper obtained by chemical copper plating.

[0113] In one embodiment, the second conductive layer 15 is provided by electroplating.

[0114] Next, as shown in FIG. 4, step 4 is performed to provide a silicon-based intermediate layer 16 on the core plate layer, which covers the first seed conductive layer 14 and the second conductive layer 15. Figure 4 ​​​As shown, step 4 is performed to fill the through-groove 13 with a filling layer 16 . The filling layer 16 fills the gaps of the second conductive layer 15 in the through-groove 13 and covers the surface of the second conductive layer 15 .

[0115] In one embodiment, the filling layer 16 is made of resin, or alternatively, a non-dielectric material such as a metal or metal compound, to fill the gaps in the through-slots 13 to prevent the gaps from causing reliability issues in the package substrate structure. Resin is preferably used as the filling material because it simplifies the process, is low-cost, and facilitates the production of the package substrate.

[0116] In one embodiment, after filling the filling layer 16 , the obtained package substrate structure is ground to remove the micro-etched portion of the surface of the filling layer 16 .

[0117] Then, if Figure 5 As shown, step 5 is performed to dispose a third conductive layer 17 on the surface of the filling layer 16 .

[0118] In one embodiment, the third conductive layer 17 is electroplated copper.

[0119] Then, if Figure 6 As shown, step 6 is performed to dispose a patterned first mask layer 18 on the surface of the third conductive layer 17 to expose a portion of the third conductive layer 17 underneath.

[0120] In one embodiment, the first mask layer 18 is a photosensitive material, and the first mask layer 18 can be patterned by exposure and development.

[0121] Then, if Figure 7 As shown, step 7 is performed to etch the exposed third conductive layer 17 and the filling layer 16 , the second conductive layer 15 , the first seed conductive layer 14 and the first conductive layer 12 below the third conductive layer 17 to expose a portion of the core board 11 .

[0122] Then, if Figure 8 As shown, step 8 is performed to remove the first mask layer 18 to reveal the third conductive layer 17 underneath. The third conductive layer 17, the filling layer 16, the second conductive layer 15, the first seed conductive layer 14 and the first conductive layer 12 constitute a graphic conductive layer, and the upper and lower surfaces of the core board 11 are both provided with a graphic conductive layer.

[0123] Then, if Figure 9 As shown, step 9 is performed to set a substrate dielectric layer 19 on the surface of the third conductive layer 17 close to the upper surface and the lower surface of the core board 11. The substrate dielectric layer 19 fills the gaps in the etched pattern conductive layer and covers its surface.

[0124] Then, step 10 is performed to form dielectric build-up layers on the surfaces of the substrate dielectric layer 19 close to the upper surface and the lower surface of the core board 11 .

[0125] In one embodiment, a method for providing a dielectric build-up layer includes:

[0126] like Figure 9 As shown, a first blind hole 21 is provided in the substrate dielectric layer 19 to expose a portion of the third conductive layer 17 that is pre-set for conductive connection;

[0127] like Figure 10 As shown, a second seed conductive layer 22 is disposed on the substrate dielectric layer 19 behind the first blind hole 21, and the second seed conductive layer 22 covers the substrate dielectric layer 19 and the exposed third conductive layer 17;

[0128] like Figure 11 As shown, a patterned second mask layer 23 is provided on the second seed conductive layer 22;

[0129] like Figure 12 As shown, the gaps between the patterned second mask layers 23 are filled with a build-up conductive layer 24;

[0130] like Figure 13 As shown, the second mask layer 23 and the second seed conductive layer 22 exposed below the second mask layer 23 are removed to expose a portion of the substrate dielectric layer 19, thereby obtaining a patterned build-up conductive layer 24 and a patterned second seed conductive layer 22;

[0131] like Figure 14 As shown, the gap between the patterned build-up conductive layer 24 and the second seed conductive layer 22 is filled with a build-up dielectric layer 25 , thereby obtaining a dielectric build-up layer.

[0132] In one embodiment, the dielectric build-up layer is repeatedly provided multiple times to form a multi-layer stack of dielectric build-up layers, such as Figures 14-15 The diagram shows a schematic diagram of two dielectric build-up layers. More than two dielectric build-up layers may also be provided.

[0133] In one embodiment, the first blind hole 21 is formed by UV laser (ultraviolet light), CO2 laser, Pico (picosecond) laser, etc., and a plasma etching method can also be used to etch the barrier layer to form a hole.

[0134] In one embodiment, the second seed conductive layer 22 is chemical copper obtained by chemical copper deposition.

[0135] In one embodiment, the second mask layer 23 is a photosensitive material, and the second mask layer 23 can be patterned by exposure and development.

[0136] In one embodiment, the second seed conductive layer 22 under the second mask layer 23 is removed by flash etching.

[0137] In one embodiment, the material of the build-up dielectric layer 25 can be one or any combination of epoxy resin-based polymer materials, nitrogen-containing polymer materials, Ajinomoto built-up film (ABF), polyimide material (PI), fluoropolymer materials, polymaleimide triazine resin polymers, and polyphenylene ether.

[0138] Next, step 11 is performed to form a silicon-based intermediate layer build-up layer on the surface of the dielectric build-up layer close to the upper surface and the lower surface of the core board 11 .

[0139] In one embodiment, a method for preparing a silicon-based intermediate layer build-up layer includes:

[0140] like Figure 16 As shown, a silicon-based intermediate layer 31 is provided on the surface of the dielectric build-up layer close to the upper surface and the lower surface of the core board 11, and a second blind hole 32 is provided to penetrate the two silicon-based intermediate layers 31 and the uppermost build-up dielectric layer 25 of the dielectric build-up layer respectively to expose the portion of the dielectric build-up layer where a conductive connection is to be performed;

[0141] like Figure 17 As shown, a third seed conductive layer 33 is respectively provided on the surface of the two silicon-based intermediate layers 31 , and the third seed conductive layer 33 covers the surface of the silicon-based intermediate layer 31 and the exposed surface of the second blind hole 32 ;

[0142] like Figure 18 As shown, a patterned third mask layer 34 is respectively provided on the surfaces of the two third conductive seed layers 33;

[0143] like Figure 19 As shown, the gaps between the two patterned third mask layers 34 are filled with an intermediate conductive layer 35 respectively;

[0144] like Figure 20 As shown, the third mask layer 34 and the third seed conductive layer 33 exposed below the third mask layer 34 are removed to expose a portion of the silicon-based intermediate layer 31, thereby obtaining a patterned intermediate conductive layer 35 and a patterned third seed conductive layer 33;

[0145] like Figure 21 As shown, an intermediate dielectric layer 36 is covered on the patterned intermediate conductive layer 35 and the third seed conductive layer 33, and the intermediate dielectric layer 36 fills the gap between the patterned intermediate conductive layer 35 and the third seed conductive layer 33, thereby obtaining two silicon-based intermediate layer build-up layers respectively close to the upper surface and lower surface of the core board 11.

[0146] In this embodiment, the silicon-based intermediate layer build-up layer is disposed on two opposite surfaces of the package substrate structure.

[0147] The application can further improve the integration of the packaging substrate structure by arranging the silicon-based intermediate layer increment on both sides of the packaging substrate structure, but the process complexity will be increased.

[0148] In one embodiment, the material of the silicon-based intermediate layer 31 includes silicon and silicon compounds.

[0149] In one embodiment, the silicon compound in the silicon-based intermediate layer 31 is silicon oxide and / or silicon nitride.

[0150] In one embodiment, the silicon-based intermediate layer increment is repeatedly arranged to form a multi-layer stacked silicon-based intermediate layer increment, as shown in Figure 21 The silicon-based intermediate layer increment is arranged in two layers, and more than two layers of silicon-based intermediate layer increment can also be arranged.

[0151] In the prior art, the silicon-based intermediate layer 31 is usually embedded in the packaging substrate to improve the exposure density. During the embedding process, a groove needs to be arranged on the packaging substrate, and the arrangement process is easy to cause the structure of the packaging substrate to be warped. At the same time, the step of arranging the groove is complex and high in cost. The application arranges the silicon-based intermediate layer 31 in the form of an increment on the dielectric increment of the packaging substrate, and the silicon-based intermediate layer 31 structure can be introduced without arranging a groove, thereby avoiding the problem of warping of the packaging substrate during preparation. At the same time, the preparation method is similar to the general line increment process, and there is no need to greatly change the process equipment and process, thereby greatly reducing the preparation cost required to improve the technical solution of the application, and the step of preparing the groove is saved, and the preparation process is simple. In addition, under the condition that the packaging substrate is not affected by the warping problem and the process efficiency is unchanged, the silicon-based intermediate layer 31 is used to realize a high-integration and high-performance packaging substrate structure by using the characteristics of low dielectric constant, low dielectric loss factor and high-precision line of the silicon-based intermediate layer 31.

[0152] In one embodiment, after the third mask layer 34 and the third seed conductive layer 33 exposed below the third mask layer 34 are removed, a layer of silicon-based intermediate layer 31 is covered on the exposed third seed conductive layer 33, intermediate conductive layer 35 and silicon-based intermediate layer 31, and then the intermediate dielectric layer 36 is covered.

[0153] The application further improves the signal transmission performance of the line by arranging two layers of silicon-based intermediate layer 31 to wrap the intermediate conductive layer 35 and the third seed conductive layer 33, and using the low dielectric constant and low dielectric loss factor of the two layers of silicon-based intermediate layer 31.

[0154] In one embodiment, an adhesive layer is arranged between the increment dielectric layer 25 and the silicon-based intermediate layer 31.

[0155] In one embodiment, CF 4 gas is used to perform plasma bombardment on the surface of the silicon-based intermediate layer 31 , so that the plasma-bombarded surface of the silicon-based intermediate layer 31 is in contact with the uppermost build-up dielectric layer 25 of the dielectric build-up layer.

[0156] In one embodiment, the surface of the silicon-based intermediate layer 31 is chemically etched, and the chemically etched surface of the silicon-based intermediate layer 31 is in contact with the uppermost build-up dielectric layer 25 of the dielectric build-up layer.

[0157] The present invention improves the bonding force between the silicon-based intermediate layer 31 and the dielectric build-up layer by plasma bombardment and / or chemical etching, thereby improving the structural reliability of the packaging substrate.

[0158] In one embodiment, the silicon-based intermediate layer 31 is disposed on the dielectric build-up layer by magnetron sputtering, physical vapor deposition, or atomic layer deposition.

[0159] The present invention provides a silicon-based interlayer 31 on the dielectric build-up layer of the package substrate. This can be directly deposited via magnetron sputtering, physical vapor deposition, or atomic layer deposition. Compared to the prior art method of providing a groove for the silicon-based interlayer 31, this method offers a simpler process and lowers costs. Preferably, magnetron sputtering is used to deposit the silicon-based interlayer 31, as it prevents damage to the dielectric layer material due to excessive temperatures, thereby improving structural reliability.

[0160] In one embodiment, the third conductive seed layer 33 is formed by atomic layer deposition, physical vapor deposition, or electroplating. Preferably, the third conductive seed layer 33 is formed by atomic layer deposition.

[0161] In one embodiment, the material of the third conductive seed layer 33 is one or more of copper, titanium, silver, and oxides thereof, and preferably copper is used as the material of the third conductive seed layer 33 .

[0162] In one embodiment, the third mask layer 34 is a photoresist, and a patterned third mask layer 34 can be obtained through photolithography and development.

[0163] In one embodiment, the third conductive seed layer 33 under the third mask layer 34 is removed by flash etching.

[0164] Then, if Figure 22 As shown, step 12 is performed, a graphic outer coating is set on the upper surface of the packaging substrate structure formed so far, and a conductive connection portion is formed with a portion of the silicon-based intermediate layer build-up layer that is preset to be conductively connected to the upper surface of the core board 11. A graphic outer coating is set on the lower surface of the packaging substrate structure formed so far, and a conductive connection portion is formed with a portion of the silicon-based intermediate layer build-up layer that is preset to be conductively connected to the lower surface of the core board 11.

[0165] In one embodiment, the outer plating layer is formed by first providing a fourth seed conductive layer 41 , and then providing an outer plating conductive layer 42 on the fourth seed conductive layer 41 . The fourth seed conductive layer 41 and the outer plating conductive layer 42 constitute the outer plating layer.

[0166] Finally, if Figure 23 As shown, step 13 is performed to cover the outer plating layer with a patterned solder resist layer 43 . The solder resist layer 43 fills the gaps between the patterned outer plating layers and exposes the conductive connection portions preset on the outer plating layers.

[0167] In one embodiment, the solder resist layer 43 is provided with photoresist, exposed, and developed to obtain a patterned solder resist layer 43 , thereby exposing the conductive connection portion.

[0168] In one embodiment, a protective layer 44 is disposed on the surface of the conductive connection portion of the patterned outer plating layer to protect the conductive connection on the surface and prevent oxidation of the portion of the circuit.

[0169] In one embodiment, the material of the protection layer 44 is chemical nickel palladium gold.

[0170] Example 2:

[0171] This embodiment provides a method for preparing a package substrate structure. Steps 1 to 10 of the preparation method are substantially the same as those in the first embodiment, except that:

[0172] Step 11: Figures 24-29 As shown, a silicon-based intermediate layer build-up layer is provided on the surface of the dielectric build-up layer close to the upper surface or lower surface of the core board 11;

[0173] Step 12: Figure 30 As shown, a patterned outer coating is provided on the surface of the package substrate structure formed so far with the silicon-based intermediate layer build-up layer, and a portion of the silicon-based intermediate layer build-up layer that is predetermined to be conductively connected is formed as a conductive connection portion; a patterned outer coating is provided on the surface of the package substrate structure formed so far without the silicon-based intermediate layer, and a portion of the dielectric build-up layer that is predetermined to be conductively connected is formed as a conductive connection portion;

[0174] Step 13: Figure 31 As shown, a patterned solder resist layer 43 is covered on the outer plating layer. The solder resist layer 43 fills the gaps between the patterned outer plating layers and exposes the conductive connection portions preset on the outer plating layers.

[0175] In one embodiment, in step 11, the method for preparing a silicon-based intermediate layer build-up layer includes:

[0176] like Figure 24As shown, a silicon-based intermediate layer 31 is provided on the surface of the dielectric build-up layer close to the upper surface or the lower surface of the core board 11, and a second blind hole 32 is provided through the silicon-based intermediate layer 31 and the uppermost build-up dielectric layer 25 of the dielectric build-up layer to expose a portion of the dielectric build-up layer for a predetermined conductive connection;

[0177] like Figure 25 As shown, a third seed conductive layer 33 is disposed on the surface of the silicon-based intermediate layer 31 , and the third seed conductive layer 33 covers the surface of the silicon-based intermediate layer 31 and the exposed surface of the second blind hole 32 ;

[0178] like Figure 26 As shown, a patterned third mask layer 34 is provided on the surface of the third conductive seed layer 33;

[0179] like Figure 27 As shown, the gaps between the patterned third mask layers 34 are filled with an intermediate conductive layer 35;

[0180] like Figure 28 As shown, the third mask layer 34 and the third seed conductive layer 33 exposed below the third mask layer 34 are removed to expose a portion of the silicon-based intermediate layer 31, thereby obtaining a patterned intermediate conductive layer 35 and a patterned third seed conductive layer 33;

[0181] like Figure 29 As shown, an intermediate dielectric layer 36 is covered on the patterned intermediate conductive layer 35 and the third seed conductive layer 33, and the intermediate dielectric layer 36 fills the gap between the patterned intermediate conductive layer 35 and the third seed conductive layer 33, thereby obtaining a silicon-based intermediate layer build-up layer close to the upper surface or lower surface of the core board 11.

[0182] Specifically, in this embodiment, a silicon-based intermediate layer build-up layer is provided on one side of the packaging substrate, which can realize a highly integrated packaging substrate structure in relatively simple process steps; in Example 1, a silicon-based intermediate layer build-up layer is provided on both sides of the packaging substrate structure, which can further improve the integration of the packaging substrate structure, but the process complexity will increase. Personnel in this field can make improvements according to needs, and its variations are all within the scope of protection of the present invention.

[0183] In one embodiment, a multi-layer silicon-based intermediate layer build-up layer may be provided on one side of the package substrate, such as Figure 29 The figure shows a schematic diagram of a structure in which two silicon-based intermediate layers are provided on one side of a packaging substrate.

[0184] In one embodiment, after removing the third mask layer 34 and the third seed conductive layer 33 exposed under the third mask layer 34, a silicon-based intermediate layer 31 is further covered on the exposed third seed conductive layer 33, the intermediate conductive layer 35 and the silicon-based intermediate layer 31, and then the intermediate dielectric layer 36 is covered.

[0185] The present invention uses two silicon-based intermediate layers 31 to wrap the intermediate conductive layer 35 and the third seed conductive layer 33 , and utilizes the low dielectric constant and low dielectric loss factor of the two silicon-based intermediate layers 31 to further improve the signal transmission performance of the line.

[0186] Example 3:

[0187] The present invention provides a package substrate structure, which is obtained by using any one of the preparation methods of the above-mentioned embodiment 1 or embodiment 2, and the package substrate structure includes: a core board 11, a patterned conductive layer, a substrate dielectric layer 19, a dielectric build-up layer, a silicon-based intermediate layer build-up layer, an outer plating layer and a patterned solder resist layer 43;

[0188] The graphic conductive layer is arranged on the upper and lower surfaces of the core board 11 and penetrates the core board 11 at a preset position. The substrate dielectric layer 19 covers the graphic conductive layer and covers the gaps in the graphic conductive layer; the dielectric build-up layer is arranged on the substrate dielectric layer 19, and the silicon-based intermediate layer build-up layer is arranged on the dielectric build-up layer. The graphic outer plating layer and the surface of the packaging substrate structure are preset to be conductively connected. The solder resist layer 43 covers the outer plating layer and fills the gaps between the outer plating layers. Conductive connection parts are formed in sequence between the core board 11, the graphic conductive layer, the dielectric build-up layer, the silicon-based intermediate layer build-up layer, and the outer plating layer, and the conductive connection parts are led out to the surface of the packaging substrate structure through the outer plating layer.

[0189] The invention in this embodiment arranges the silicon-based intermediate layer 31 on the dielectric build-up layer of the packaging substrate in a build-up manner, and utilizes the high flatness and low ductility of the silicon-based intermediate layer 31 material itself to suppress the warping deformation of the packaging substrate; at the same time, no grooves are required in the packaging substrate structure, and uneven structural distribution will not be generated, thereby further avoiding the warping problem of the packaging substrate structure and improving the structural reliability of the packaging substrate structure; in addition, the low dielectric constant, low dielectric loss factor, and high-precision circuit characteristics of the silicon-based intermediate layer 31 are utilized to improve the performance and integration of the packaging substrate structure, reduce the loss of the packaging substrate structure and the packaging size at the same integration.

[0190] In this embodiment, the silicon-based intermediate layer build-up layer is provided on two opposite surfaces of the package substrate structure.

[0191] The present invention can further improve the integration of the packaging substrate structure by arranging silicon-based intermediate layer build-up layers on both sides of the packaging substrate structure, but the process complexity will increase.

[0192] Example 4:

[0193] This embodiment provides a package substrate structure, which is obtained by using any one of the preparation methods of the first or second embodiment. The package substrate structure is substantially the same as that of the third embodiment, except that:

[0194] In this embodiment, the silicon-based intermediate layer build-up layer is disposed on only one of the two oppositely disposed surfaces of the package substrate structure.

[0195] Specifically, in this embodiment, a silicon-based intermediate layer build-up layer is provided on one side of the packaging substrate, which can realize a highly integrated packaging substrate structure in relatively simple process steps; in Example 3, a silicon-based intermediate layer build-up layer is provided on both sides of the packaging substrate structure, which can further improve the integration of the packaging substrate structure, but the process complexity will increase. Personnel in this field can make improvements according to needs, and its variations are all within the scope of protection of the present invention.

[0196] Embodiment 5:

[0197] This embodiment provides a package substrate structure, which is obtained by using any one of the preparation methods of the above-mentioned embodiment 1 or embodiment 2. The package substrate structure is basically the same as that of the embodiment 3 or embodiment 4, except that:

[0198] like Figure 32 As shown, the silicon-based intermediate layer buildup layer includes two silicon-based intermediate layers 31, a third seed conductive layer 33, an intermediate conductive layer 35 and an intermediate dielectric layer 36. The third seed conductive layer 33 and the intermediate conductive layer 35 are arranged between the two silicon-based intermediate layers 31. The intermediate dielectric layer 36 covers the silicon-based intermediate layer 31 on the side of the silicon-based intermediate layer buildup layer away from the core layer. The intermediate dielectric layer 36 is in contact with the outer plating layer.

[0199] In this embodiment, a silicon-based intermediate layer 31 is covered on both sides of the third seed conductive layer 33 and the intermediate conductive layer 35 , thereby utilizing the low dielectric constant and low dielectric loss factor of the two silicon-based intermediate layers 31 to further improve the signal transmission performance of the line.

[0200] In summary, the packaging substrate structure and preparation method thereof of the present invention can reduce the warping problem of the packaging substrate and improve the flatness of the board surface of the packaging substrate by setting a silicon-based intermediate layer on the dielectric build-up layer of the packaging substrate and utilizing the high flatness and low ductility of the silicon-based intermediate layer on the dielectric build-up layer; at the same time, the method of depositing the silicon-based intermediate layer on the packaging substrate avoids the warping problem caused by the process of setting grooves to embed the silicon-based intermediate layer; in addition, the dielectric constant and dielectric loss factor of the silicon-based intermediate layer are low, which can improve the performance of the packaging substrate; finally, the characteristic of the silicon-based intermediate layer that more sophisticated circuits can be produced, thereby realizing a higher-density integrated packaging substrate structure.

[0201] Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0202] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing a packaging substrate structure, characterized in that: The preparation method comprises: Providing a core board, the core board comprising an upper surface and a lower surface disposed opposite to each other, the upper surface and the lower surface both being provided with a first conductive layer, the core board and the first conductive layer forming a core board layer; providing a through groove in the core plate layer; The surface of the core plate layer exposed after the through grooves are provided is covered with a first seed conductive layer, and the surface of the first seed conductive layer is covered with a second conductive layer; Filling the through-groove with a filling layer, wherein the filling layer fills the gap of the second conductive layer in the through-groove and covers the surface of the second conductive layer; Disposing a third conductive layer on the surface of the filling layer; Disposing a patterned first mask layer on the surface of the third conductive layer to expose a portion of the third conductive layer below; Etching the exposed third conductive layer and the filling layer, the second conductive layer, the first seed conductive layer and the first conductive layer below the third conductive layer to expose a portion of the core board; removing the first mask layer to expose the third conductive layer thereunder, and exposing a patterned conductive layer consisting of the third conductive layer, the filling layer, the second conductive layer, the first seed conductive layer, and the first conductive layer; Disposing a substrate dielectric layer on the surface of the third conductive layer, wherein the substrate dielectric layer fills the gaps in the etched patterned conductive layer and covers the surface thereof; Disposing a dielectric build-up layer on the surface of the substrate dielectric layer; Disposing a silicon-based intermediate layer build-up layer on the dielectric build-up layer; A patterned outer plating layer is provided on both the upper surface and the lower surface of the package substrate structure thus formed, wherein the outer plating layer forms a conductive connection portion with a portion of the package substrate structure thus formed that is intended to be conductively connected; A patterned solder resist layer is covered on the outer plating layer, and the solder resist layer fills the gaps between the patterned outer plating layers and exposes the conductive connection parts preset from the outer plating layers.

2. The method for preparing a package substrate structure according to claim 1, wherein: The preparation method of providing the dielectric build-up layer comprises: A first blind hole is provided in the substrate dielectric layer to expose a portion of the third conductive layer that is predetermined to be electrically connected; a second seed conductive layer is provided on the substrate dielectric layer behind the first blind hole, the second seed conductive layer covering the substrate dielectric layer and the exposed third conductive layer; disposing a patterned second mask layer on the second conductive seed layer; filling the gaps between the patterned second mask layers with a build-up conductive layer; removing the second mask layer and the second seed conductive layer exposed below the second mask layer to expose a portion of the substrate dielectric layer, thereby obtaining the patterned build-up conductive layer and the patterned second seed conductive layer; A build-up dielectric layer is filled in the gap between the patterned build-up conductive layer and the second seed conductive layer, thereby obtaining the dielectric build-up layer.

3. The method for preparing a package substrate structure according to claim 1, wherein: The preparation method of providing the silicon-based intermediate layer build-up layer comprises: Disposing a silicon-based intermediate layer on the surface of the dielectric build-up layer, and disposing a second blind hole penetrating the silicon-based intermediate layer and the uppermost build-up dielectric layer of the dielectric build-up layer to expose a portion of the dielectric build-up layer that is predetermined to be electrically conductively connected; Disposing a third seed conductive layer on the surface of the silicon-based intermediate layer, wherein the third seed conductive layer covers the silicon-based intermediate layer and the surface exposed by the second blind hole; Disposing a patterned third mask layer on the surface of the third conductive seed layer; filling the gaps between the patterned third mask layers with an intermediate conductive layer; removing the third mask layer and the third seed conductive layer exposed below the third mask layer to expose a portion of the silicon-based intermediate layer, thereby obtaining the patterned intermediate conductive layer and the patterned third seed conductive layer; An intermediate dielectric layer is covered on the patterned intermediate conductive layer and the third seed conductive layer. The intermediate dielectric layer fills the gap between the patterned intermediate conductive layer and the third seed conductive layer, thereby obtaining a silicon-based intermediate layer build-up layer.

4. The method for preparing a package substrate structure according to claim 3, wherein: After removing the third mask layer and the third seed conductive layer exposed below the third mask layer, a silicon-based intermediate layer is further covered on the exposed third seed conductive layer, the intermediate conductive layer and the silicon-based intermediate layer, and then the intermediate dielectric layer is covered.

5. The method for preparing a package substrate structure according to any one of claims 1 to 4, wherein: The dielectric build-up layer is repeatedly provided multiple times to form a multi-layer stack of the dielectric build-up layer; and / or the silicon-based intermediate layer build-up layer is repeatedly provided multiple times to form a multi-layer stack of the silicon-based intermediate layer build-up layer.

6. The method for preparing a package substrate structure according to claim 1, wherein: The surface of the silicon-based intermediate layer is plasma bombarded with CF4 gas, and the surface of the silicon-based intermediate layer bombarded with plasma is brought into contact with the uppermost build-up dielectric layer of the dielectric build-up layer; or the surface of the silicon-based intermediate layer is chemically etched, and the surface of the silicon-based intermediate layer that is chemically etched is brought into contact with the uppermost build-up dielectric layer of the dielectric build-up layer.

7. The method for preparing a package substrate structure according to claim 1, wherein: The silicon-based intermediate layer build-up layer is disposed on only one of the two oppositely disposed surfaces of the package substrate structure, or the silicon-based intermediate layer build-up layer is disposed on both of the oppositely disposed surfaces of the package substrate structure.

8. A packaging substrate structure, characterized in that: The packaging substrate structure is obtained by the preparation method according to any one of claims 1 to 7, and the packaging substrate structure comprises: a core board, a patterned conductive layer, a substrate dielectric layer, a dielectric build-up layer, a silicon-based intermediate layer build-up layer, an outer plating layer, and a patterned solder resist layer; The graphic conductive layer is arranged on the upper surface and the lower surface of the core board and passes through the core board at a preset position. The substrate dielectric layer covers the graphic conductive layer and covers the gaps in the graphic conductive layer; the dielectric build-up layer is arranged on the substrate dielectric layer, and the silicon-based intermediate layer build-up layer is arranged on the dielectric build-up layer. The graphic outer plating layer is provided with a conductive connection at a portion preset for conductive connection with the surface of the packaging substrate structure. The solder resist layer covers the outer plating layer and fills the gaps between the outer plating layers. Conductive connection parts are formed in sequence among the core board, the graphic conductive layer, the dielectric build-up layer, the silicon-based intermediate layer build-up layer, and the outer plating layer. The conductive connection parts are led out to the surface of the packaging substrate structure through the outer plating layer.

9. The packaging substrate structure according to claim 8, wherein: The silicon-based intermediate layer build-up layer is disposed on only one of the two oppositely disposed surfaces of the packaging substrate structure, or the silicon-based intermediate layer build-up layer is disposed on both of the two oppositely disposed surfaces of the packaging substrate structure.

10. The packaging substrate structure according to claim 8, wherein: The silicon-based intermediate layer build-up layer includes two silicon-based intermediate layers, a third seed conductive layer, an intermediate conductive layer and an intermediate dielectric layer. The third seed conductive layer and the intermediate conductive layer are arranged between the two silicon-based intermediate layers. The intermediate dielectric layer covers the silicon-based intermediate layer on the side of the silicon-based intermediate layer build-up layer away from the core plate layer, and the intermediate dielectric layer is in contact with the outer plating layer.

Images