A PWM / PFM mode seamless switching circuit for Buck converters

Abstract

The present invention belongs to the technical field of integrated circuits and relates to a PWM / PFM mode seamless switching circuit for a Buck converter. The present invention comprises a seamless switching module, an oscillator module and a current limit module. The seamless switching module is used to switch the current limit according to the input signal V C The inverse signal of the clock signal is calculated to obtain the delay signal Delay and output it to the oscillator module; the current limit module is used to calculate the delay signal Delay according to the input signal V C , calculate the peak current limit signal and the valley current limit signal; the oscillator module is used to calculate the peak current limit signal and the valley current limit signal according to the delay signal Delay, the valley current limit signal and the input signal V L , generating a clock signal for controlling the power tube of the Buck converter. The PWM / PFM mode seamless switching circuit for the Buck converter proposed in the present invention does not require the design of multiple control loops or judgment circuits, and can achieve seamless switching of the Buck converter between PWM and PFM working modes, avoiding conflicts and gaps in mode switching. The present invention is suitable for low-power Buck converters operating in multiple modes.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a PWM / PFM mode seamless switching circuit for a Buck converter. Background Art

[0002] The power consumption of a buck converter is related to the operating frequency, load current, and power transistor size. When the load current decreases, lowering the circuit frequency helps the buck converter reduce power consumption and improve efficiency. Therefore, most current mainstream buck converters use PWM (Pulse Width Modulation) mode modulation under heavy loads and PFM (Pulse Frequency Modulation) mode modulation under light loads. Under varying load conditions, the buck converter needs to be able to automatically switch between PWM and PFM modes. Therefore, determining the switching point and implementing the mode switch are crucial.

[0003] Traditional PWM / PFM buck converters utilize two control loops: PWM modulation and PFM modulation. A selector circuit selectively controls the use of each loop. This not only increases design costs but also creates gaps and conflicts in the switching between the two modulation modes. When the circuit load is at the boundary between the two modes, the circuit may oscillate back and forth between PWM and PFM modes. This situation results in unstable operating frequency and large output voltage ripple, which should be avoided. Furthermore, traditional oscillator frequency reduction methods involve varying the charging current, which often fails to synchronize with the mode switching, leading to gaps in the switching. Summary of the Invention

[0004] The present invention aims to solve the above problem and proposes a PWM / PFM mode seamless switching circuit for a Buck converter.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] A PWM / PFM mode seamless switching circuit for a Buck converter, comprising a seamless switching module, an oscillator module and a current limit module;

[0007] The seamless switching module is used to switch between the input signal V C , clock signal CLK OSC The inverted signal is calculated to obtain the delayed signal Delay, where the signal V C The external error amplifier is based on the Buck converter output voltage V out Feedback voltage V FB and reference voltage Vref The error is generated, the delay signal Delay is output to the oscillator module, and the clock signal CLK OSC is the output signal of the oscillator module;

[0008] The current limit module is used to adjust the current according to the input signal V C , calculate the peak current limit signal V peak_limit With the valley current limit signal V valley_limit , where the valley current limit signal V valley_limit Output to the oscillator module, the peak current limit signal V peak_limit Output to the outside for comparison with the Buck converter inductor current;

[0009] The oscillator module is used to generate a current according to the delay signal Delay and the valley current limit signal V valley_limit and the input signal V L , generates the clock signal CLK used to control the Buck converter power tube OSC , where the input signal V L It is obtained by sampling the inductor current of the Buck converter;

[0010] When the input signal V C When the current changes, the peak current is limited by the current limit module. At the same time, under the control of the seamless switching module, the oscillator module generates a clock signal CLK corresponding to the required frequency. OSC , realizing seamless switching between PWM mode and PFM mode.

[0011] Furthermore, the seamless switching module includes a comparison circuit, a clamping circuit and a frequency reduction delay circuit;

[0012] The comparison circuit includes a first current source I1, a second current source I2, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, and a seventh MOS transistor M7; wherein the gate of the first MOS transistor M1 is connected to a fixed reference voltage V c_min Its source is connected to the first current source I1 and the source of the second MOS transistor M2. The drain of the first MOS transistor M1 is connected to the drain of the third MOS transistor M3, the gate and drain of the fifth MOS transistor M5, and the gate of the sixth MOS transistor M6. The gate of the second MOS transistor M2 is connected to the input signal V C The drain is connected to the drain and gate of the fourth MOS tube M4 and the gate of the third MOS tube; the source of the third MOS tube M3, the source of the fourth MOS tube M4, the source of the fifth MOS tube M5 and the source of the sixth MOS tube M6 are all connected to the ground power rail GND; the drain of the sixth MOS tube M6 and the gate and drain of the seventh MOS tube M7 are connected to the port V clampThe source of the seventh MOS transistor M7 is connected to the second current source I2;

[0013] The clamping circuit includes an eighth MOS transistor M8 and a ninth MOS transistor M9; wherein the gate of the eighth MOS transistor serves as the port V clamp , the drain is connected to the input signal V C The gate and drain of the ninth MOS tube M9 are used as the source and the port V Delay ; The source of the ninth MOS tube M9 is connected to the power rail V DD connect;

[0014] The frequency reduction delay circuit includes a third current source I3, a fourth current source I4, a first resistor R1, a second resistor R2, a capacitor C1, a first comparator COMP1, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, and a thirteenth MOS transistor M13; wherein the gate of the tenth MOS transistor M10 is connected to the port V Delay connected, with its source connected to the power rail V DD The drain of the 12th MOS tube M12 is connected to the third current source I3, the gate and drain of the 11th MOS tube M11, and the gate of the 12th MOS tube M12; the source of the 12th MOS tube M12 is connected to the power rail V DD The drain of the thirteenth MOS transistor M13 is connected to the upper end of the first resistor R1 and the positive input end of the first comparator COMP1; the gate of the thirteenth MOS transistor M13 is connected to the clock signal CLK OSC The inverted signal of the first comparator COMP1 is connected to the fourth current source I4 and the upper end of the second resistor R2; the lower end of the second resistor R2 is connected to the ground power rail GND; the output end of the first comparator COMP1 serves as the output end of the seamless switching module to output the delay signal Delay.

[0015] Furthermore, the current limit module includes a voltage-current conversion circuit and a current limit calculation circuit;

[0016] The voltage-current conversion circuit includes a clamping amplifier EA, a fourteenth MOS transistor M14, a third resistor R3, a fourth resistor R4, and a fifth resistor R5; wherein the positive input end of the clamping amplifier EA is connected to the input port voltage, and its negative input end is connected to the upper end of the third resistor R3 and the source of the fourteenth MOS transistor M14; the lower end of the third resistor R3 is connected to the ground power rail GND; the drain of the fourteenth MOS transistor M14 is connected to the output port, and outputs a current source signal;

[0017] The current limit calculation circuit includes a fifth current source I5, a sixth current source I6, a seventh current source I7, an eighth current source I8, a ninth current source I9, a tenth current source I 10, the eleventh current source I 11 , a fifteenth MOS transistor M15, a sixteenth MOS transistor M16, a seventeenth MOS transistor M17, and an eighteenth MOS transistor M18; wherein the lower end of the fifth current source I5 is connected to the lower end of the sixth current source I6, the upper end of the seventh current source I7, the drain and gate of the fifteenth MOS transistor M15, and the gate of the sixteenth MOS transistor M16; the drain of the sixteenth MOS transistor M16, the drain of the eighteenth MOS transistor M18, the upper end of the fourth resistor R4 and the peak current limit output port are connected to output a peak current limit current signal; the lower end of the eighth current source I8 is connected to the upper end of the ninth current source I9, the tenth current source I 10 The upper end, the gate and drain of the seventeenth MOS tube M17, and the gate of the eighteenth MOS tube M18 are connected; the eleventh current source I 11 The lower end is connected to the upper end of the fifth resistor R5 and the valley current limit output port, and is used to output a valley current limit signal.

[0018] Furthermore, the oscillator module includes a charge and discharge circuit, a first AND gate AND1, a second AND gate AND2, and a second comparator COMP2; wherein one input end of the first AND gate AND1 is connected to the fully charged output end of the charge and discharge circuit, and the other input end is connected to the output end of the second comparator COMP2; the output end of the first AND gate AND1 is connected to one input end of the second AND gate AND2, and serves as the output end of the oscillator module at the same time; the positive input end of the second comparator COMP2 is connected to the valley current limit signal V valley_limit Connect its negative input terminal to the input signal V L The other input terminal of the second AND gate AND2 is connected to the delay signal Delay, and its output terminal is connected to the discharge terminal of the charge and discharge circuit; the time required for the charge and discharge circuit to charge from 0 to full charge is T s . .

[0019] Compared with the prior art, the present invention has the following advantages: the present invention proposes a PWM / PFM mode seamless switching circuit for Buck converter. Through the clamping module, the error amplifier output voltage V C The minimum value of the peak current limit is achieved in the light-load PFM mode. At the same time, the clamped current is used to control the oscillator module to reduce the frequency, thereby achieving seamless switching between PWM mode and PFM mode, avoiding conflicts and gaps at the boundary between the two modes and reducing certain design costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is the overall block diagram of the PWM / PFM mode seamless switching circuit for Buck converter proposed by the present invention;

[0021] Figure 2 This is the circuit diagram of the seamless switching module;

[0022] Figure 3 This is the circuit diagram of the current limit module;

[0023] Figure 4 This is the circuit diagram of the oscillator module;

[0024] Figure 5 The peak current limit, valley current limit and frequency of the circuit in the present invention are related to the error amplifier output voltage V C Schematic diagram of the curve and key waveforms. DETAILED DESCRIPTION

[0025] The present invention provides a seamless PWM / PFM mode switching circuit for a Buck converter, comprising a seamless switching module, an oscillator module, and a current limit module. The circuit eliminates the need for multiple control loops and a judgment circuit. Instead, the circuit limits the minimum output voltage of the error amplifier and maintains a fixed peak current limit when the load decreases and the error amplifier output voltage drops. When the error amplifier output voltage is limited, a frequency reduction operation is simultaneously performed, thereby achieving seamless switching from PWM mode to PFM mode and reducing Buck converter power consumption.

[0026] The PWM / PFM seamless switching circuit for Buck converter is characterized in that the input signal is connected to the external error amplifier output signal V C , inductor current sampling circuit output signal V L , output signal V peak_limit Connect to the peak current comparison circuit input signal V peak_limit , output signal CLK OSC Connected to the Buck converter logic control circuit input signal CLK OSC .

[0027] The PWM / PFM seamless switching circuit for a Buck converter is used to seamlessly switch the working state and modulation mode of the Buck converter when the load current of the Buck converter changes; the error amplifier is used to amplify the output voltage V out Feedback voltage V FB With the reference voltage V ref The error, the output signal V C The error information of the Buck converter output voltage controls the seamless switching circuit to change or maintain the circuit working state; the inductor current sampling circuit is used to sample the inductor current signal of the Buck converter, and its output signal V L The amplitude information of the inductor current controls the seamless switching circuit to change or maintain the circuit working state; the peak current comparator circuit is used to compare the inductor current with the peak current limit, and its input signal Vpeak_limit Used to provide peak current limit; the logic control circuit is used to control the switching action of the Buck converter power tube, and its input signal CLK OSC A clock signal used as a reference for logic control circuits.

[0028] The PWM / PFM mode seamless switching circuit for Buck converter is characterized in that the seamless switching module input signal V C , Current limit mode input signal V C With the external error amplifier output signal V C seamless switching module output signal Delay is connected to the oscillator module input signal Delay; the current limit module output signal V valley_limit With the oscillator module input signal V valley_limit connection, its output signal V peak_limit Comparison circuit input signal V with peak current peak_limit Connection; oscillator module output signal CLK OSC AND logic control circuit input signal CLK OSC Connection, its input signal V L and the inductor current sampling signal V L connect.

[0029] The seamless switching module is used to output the error signal V according to the Buck converter C , clock signal CLK OSC The inverted signal calculation and generation of the delay signal Delay make the oscillator module generate a delay; the current limit module is used to output the error signal V according to the Buck converter C , calculate and generate the peak current limit signal V peak_limit With the valley current limit signal V valley_limit , which limits the maximum and minimum values ​​of the Buck converter inductor current; the oscillator module is used to generate a current according to the valley current limit signal V valley_limit , inductor current sampling signal V L and delay signal Delay, calculate and generate reference clock signals CLK of different frequencies OSC , so that the logic control circuit controls the Buck converter to perform different switching actions and realize different modulation modes

[0030] like Figure 1As shown, a PWM / PFM mode seamless switching circuit for a Buck converter includes a seamless switching module, an oscillator module, and a current limit module. This circuit eliminates the need for multiple control loops or a judgment circuit. Instead, it limits the minimum output voltage of the error amplifier and maintains a fixed peak current limit as the load decreases and the error amplifier output voltage drops. When the error amplifier output voltage is limited, the circuit simultaneously performs a frequency reduction operation, thereby achieving seamless switching from PWM mode to PFM mode and reducing Buck converter power consumption.

[0031] The seamless switching module includes a comparison circuit, a clamping circuit and a frequency reduction delay circuit. The comparison circuit includes a first current source I1, a second current source I2, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6 and a seventh MOS transistor M7. The gate of the first MOS transistor M1 is connected to a reference voltage V c_min Its source is connected to the first current source I1 and the source of the second MOS transistor M2, and its drain is connected to the drain of the third MOS transistor M3, the gate and drain of the fifth MOS transistor M5, and the gate of the sixth MOS transistor M6; the gate of the second MOS transistor M2 is connected to the output signal V C The drain is connected to the drain, gate, and gate of the fourth MOS tube M4 and the gate of the third MOS tube; the source of the third MOS tube M3, the source of the fourth MOS tube M4, the source of the fifth MOS tube M5, and the source of the sixth MOS tube M6 are all connected to the ground power rail GND; the drain of the sixth MOS tube M6 and the gate and drain of the seventh MOS tube M7 are connected to the port V clamp The source of the seventh MOS transistor M7 is connected to the second current source I2. The clamping circuit includes an eighth MOS transistor M8 and a ninth MOS transistor M9. The gate port V clamp , drain connection port V C , its source is connected to port V Delay , the gate and drain of the ninth MOS tube M9; the source of the ninth MOS tube M9 and the power rail V DD The frequency reduction delay circuit is composed of a third current source I3, a fourth current source I4, a first resistor R1, a second resistor R2, a capacitor C1, a first comparator COMP1, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, and a thirteenth MOS transistor M13. The gate of the tenth MOS transistor M10 is connected to the port V Delay connected, with its source connected to the power rail V DD The drain of the 12th MOS tube M12 is connected to the power rail V DDThe drain of the thirteenth MOS transistor M13 is connected to the upper end of the first resistor R1 and the positive input end of the first comparator COMP1; the gate of the thirteenth MOS transistor M13 is connected to the port CLK OSC The drain is connected to the lower end of the first resistor R1 and the upper plate of the capacitor C1, and the source is connected to the ground power rail GND; the lower plate of the capacitor C1 is connected to the ground power rail GND; the negative input terminal of the first comparator COMP1 is connected to the fourth current source I4 and the upper end of the second resistor R2; the lower end of the second resistor R2 is connected to the ground power rail GND; the output terminal of the first comparator COMP1 is connected to the output signal Delay, and the output Delay signal controls the delay of the oscillator module.

[0032] like Figure 2 As shown, the circuit of the seamless switching module is characterized in that: when the error amplifier output voltage drops to V c_min When the comparison circuit outputs V clamp decrease, increasing the clamping current I clamp , so that the current through the first resistor R1 during the frequency reduction delay is reduced, the voltage on the first resistor R1 is lowered, and the output signal Delay is lowered; when CLK OSC When it is 0, Dealy is low; when CLK OSC When it is 1, Delay passes a certain charging delay time T Delay Charge capacitor C1 until the output signal Delay of comparator COMP1 flips to 1. Figure 2 It can be seen that the charging delay time T Delay for:

[0033]

[0034] The current limit module includes a voltage conversion current circuit and a current limit calculation circuit. The voltage conversion current circuit includes a clamp amplifier EA, a fourteenth MOS tube M14, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The positive input end of the clamp amplifier EA is connected to the input port voltage, and its negative input end is connected to the upper end of the third resistor R3 and the source of the fourteenth MOS tube M14; the lower end of the third resistor R3 is connected to the ground power rail GND; the drain of the fourteenth MOS tube M14 is connected to the output port and outputs a current source signal. The current limit calculation circuit includes a fifth current source I5, a sixth current source I6, a seventh current source I7, an eighth current source I8, a ninth current source I9, a tenth current source I 10 , the eleventh current source I 11, the fifteenth MOS transistor M15, the sixteenth MOS transistor M16, the seventeenth MOS transistor M17, and the eighteenth MOS transistor M18. The lower end of the fifth current source I5 is connected to the lower end of the sixth current source I6, the upper end of the seventh current source I7, the drain and gate of the fifteenth MOS transistor M15, and the gate of the sixteenth MOS transistor M16; the drain of the sixteenth MOS transistor M16, the drain of the eighteenth MOS transistor M18, the upper end of the fourth resistor R4, and the peak current limit output port V peak_limit Connection for outputting peak current limit signal V peak_limit The lower end of the eighth current source I8 and the upper end of the ninth current source I9, the tenth current source I 10 The upper end, the gate and drain of the seventeenth MOS tube M17 and the gate of the eighteenth MOS tube M18; the eleventh current source I 11 The lower end is connected to the upper end of the fifth resistor R5 and the valley current limit output port V valley_limit Connection for outputting valley current limit signal V valley_limit .

[0035] like Figure 3 As shown, the current limit module includes a voltage conversion current circuit and a current limit calculation circuit. It is characterized in that: the eighth current source I8, the ninth current source I9, and the tenth current source I10 are used to perform calculations and then copied through the current mirror to obtain the current limit. Y , is about V C Piecewise function; I X with I Y Adding together, the total peak current limit I peak_limit It is also a piecewise function; the piecewise function is in V C Less than twice V c_min When V C Irrelevant constant; valley current limit V valley_limit In V C Equal to V c_min When it is 0, the peak current limit voltage and valley current limit voltage are:

[0036]

[0037] V valley_limit / R5=I vlley_limit =I C -I C_min

[0038] The oscillator module includes a charge and discharge circuit, a first AND gate AND1, a second AND gate AND2, and a second comparator COMP2. The input terminal A of the first AND gate AND1 is connected to the fully charged output terminal of the charge and discharge circuit, the input terminal B of the first AND gate AND1 is connected to the output terminal of the second comparator COMP2, and the output terminal of the first AND gate AND2 is connected to the input terminal A of the second AND gate AND2 and the oscillator module output signal CLK. OSCConnection; the positive input terminal of the second comparator COMP2 and the current limit module output signal V valley_limit Connect the negative input terminal to the inductor current sampling signal V L The second AND gate AND2 input terminal B is connected to the seamless switching module output signal Delay, and its output terminal is connected to the discharge terminal of the charge and discharge circuit; the time required for the charge and discharge circuit to charge from 0 to full charge is T s .

[0039] like Figure 4 As shown, the oscillator module includes a charge and discharge circuit, a first AND gate AND1, a second AND gate AND2, and a second comparator COMP2. After the charge and discharge circuit is fully charged and outputs 1, the signal needs to be transmitted to the discharge end of the charge and discharge circuit through the first AND gate AND1 and the second AND gate AND2; when the inductor current is greater than the valley current limit and the negative input end of the second comparator COMP2 is greater than the positive input end, its output end is 0, so that the output end of the first AND gate AND1 is 0, cutting off the transmission of the discharge signal; when the inductor current is less than the valley current limit and the output end of the second comparator COMP2 is 1, the discharge signal of the charge and discharge circuit is released, and CLK OSC Turn high to 1; at this time, if the Delay signal is 0, the frequency reduction delay circuit in the seamless switching circuit starts charging, and the T dealy After charging is completed, Delay turns high to 1, releasing the discharge signal of the charge and discharge circuit.

[0040] like Figure 5 As shown in the figure, when the load current is large, the circuit works in the PWM mode of peak current mode control; when the load current begins to decrease, the output voltage V C Starts to decrease when V C Drop to 2V c_min When the peak current limit is the minimum value; as V C drop, seamless switching module limits the V C The minimum value is V c_min , when V C Equal to V c_min When the oscillator module starts to generate additional delay T Delay , and at the same time the valley current limit drops to 0, ensuring that the inductor current operates in DCM mode; at this point, the circuit switches to PFM mode.

[0041] In summary, the present invention proposes a seamless PWM / PFM mode switching circuit for a Buck converter, comprising a seamless switching module, an oscillator module, and a current limit module. This circuit eliminates the need for multiple control loops or a judgment circuit. Instead, it limits the minimum output voltage of the error amplifier and maintains a fixed peak current limit as the error amplifier output voltage decreases due to load reduction. When the error amplifier output voltage is limited, the circuit simultaneously performs a frequency reduction operation, thereby achieving seamless switching from PWM mode to PFM mode and reducing Buck converter power consumption.

Claims

1. A PWM / PFM mode seamless switching circuit for a Buck converter, characterized in that: Includes seamless switching module, oscillator module and current limit module; The seamless switching module is used to switch between the input signal V C , clock signal CLK OSC The inverted signal is calculated to obtain the delayed signal Delay, where the signal V C The external error amplifier is based on the Buck converter output voltage V out Feedback voltage V FB and reference voltage V ref The error is generated, the delay signal Delay is output to the oscillator module, and the clock signal CLK OSC is the output signal of the oscillator module; the seamless switching module includes a comparison circuit, a clamping circuit and a frequency reduction delay circuit; The comparison circuit includes a first current source I1, a second current source I2, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, and a seventh MOS transistor M7; wherein the gate of the first MOS transistor M1 is connected to a fixed reference voltage V c_min Its source is connected to the first current source I1 and the source of the second MOS transistor M2. The drain of the first MOS transistor M1 is connected to the drain of the third MOS transistor M3, the gate and drain of the fifth MOS transistor M5, and the gate of the sixth MOS transistor M6. The gate of the second MOS transistor M2 is connected to the input signal V C The drain is connected to the drain and gate of the fourth MOS tube M4 and the gate of the third MOS tube; the source of the third MOS tube M3, the source of the fourth MOS tube M4, the source of the fifth MOS tube M5 and the source of the sixth MOS tube M6 are all connected to the ground power rail GND; the drain of the sixth MOS tube M6 and the gate and drain of the seventh MOS tube M7 are connected to the port V clamp The source of the seventh MOS transistor M7 is connected to the second current source I2; The clamping circuit includes an eighth MOS transistor M8 and a ninth MOS transistor M9; The gate of the eighth MOS tube serves as the port V clamp , the drain is connected to the input signal V C The gate and drain of the ninth MOS tube M9 are used as the source and the port V Delay ; The source of the ninth MOS tube M9 is connected to the power rail V DD connect; The frequency reduction delay circuit includes a third current source I3, a fourth current source I4, a first resistor R1, a second resistor R2, a capacitor C1, a first comparator COMP1, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, and a thirteenth MOS transistor M13; wherein the gate of the tenth MOS transistor M10 is connected to the port V Delay Connect its source to the power rail V DD The drain of the 12th MOS tube M12 is connected to the third current source I3, the gate and drain of the 11th MOS tube M11, and the gate of the 12th MOS tube M12; the source of the 12th MOS tube M12 is connected to the power rail V DD The drain of the thirteenth MOS transistor M13 is connected to the upper end of the first resistor R1 and the positive input end of the first comparator COMP1; the gate of the thirteenth MOS transistor M13 is connected to the clock signal CLK OSC The inverted signal of the first comparator COMP1 is connected to the lower end of the first resistor R1 and the upper plate of the capacitor C1, and the source is connected to the ground power rail GND; the lower plate of the capacitor C1 is connected to the ground power rail GND; the negative input terminal of the first comparator COMP1 is connected to the fourth current source I4 and the upper end of the second resistor R2; the lower end of the second resistor R2 is connected to the ground power rail GND; the output terminal of the first comparator COMP1 serves as the output terminal of the seamless switching module to output the delay signal Delay; The current limit module is used to adjust the current according to the input signal V C , calculate the peak current limit signal V peak_limit With the valley current limit signal V valley_limit , where the valley current limit signal V valley_limit Output to the oscillator module, the peak current limit signal V peak_limit Output to the outside for comparison with the Buck converter inductor current; The oscillator module is used to generate a current according to the delay signal Delay and the valley current limit signal V valley_limit and the input signal V L , generates the clock signal CLK used to control the Buck converter power tube OSC , where the input signal V L It is obtained by sampling the inductor current of the Buck converter; When the input signal V C When the current changes, the peak current is limited by the current limit module. At the same time, under the control of the seamless switching module, the oscillator module generates a clock signal CLK corresponding to the required frequency. OSC , realizing seamless switching between PWM mode and PFM mode.

2. A PWM / PFM mode seamless switching circuit for a Buck converter according to claim 1, characterized in that: The current limit module includes a voltage-current conversion circuit and a current limit calculation circuit; The voltage-current conversion circuit includes a clamping amplifier EA, a fourteenth MOS transistor M14, a third resistor R3, a fourth resistor R4, and a fifth resistor R5; wherein the positive input end of the clamping amplifier EA is connected to the input port voltage, and its negative input end is connected to the upper end of the third resistor R3 and the source of the fourteenth MOS transistor M14; the lower end of the third resistor R3 is connected to the ground power rail GND; the drain of the fourteenth MOS transistor M14 is connected to the output port, and outputs a current source signal; The current limit calculation circuit includes a fifth current source I5, a sixth current source I6, a seventh current source I7, an eighth current source I8, a ninth current source I9, a tenth current source I 10 , the eleventh current source I 11 , a fifteenth MOS transistor M15, a sixteenth MOS transistor M16, a seventeenth MOS transistor M17, and an eighteenth MOS transistor M18; wherein the lower end of the fifth current source I5 is connected to the lower end of the sixth current source I6, the upper end of the seventh current source I7, the drain and gate of the fifteenth MOS transistor M15, and the gate of the sixteenth MOS transistor M16; the drain of the sixteenth MOS transistor M16, the drain of the eighteenth MOS transistor M18, the upper end of the fourth resistor R4 and the peak current limit output port are connected to output a peak current limit current signal; the lower end of the eighth current source I8 is connected to the upper end of the ninth current source I9, the tenth current source I 10 The upper end, the gate and drain of the seventeenth MOS tube M17, and the gate of the eighteenth MOS tube M18 are connected; the eleventh current source I 11 The lower end is connected to the upper end of the fifth resistor R5 and the valley current limit output port, and is used to output a valley current limit signal.

3. A PWM / PFM mode seamless switching circuit for a Buck converter according to claim 1, characterized in that: The oscillator module includes a charge and discharge circuit, a first AND gate AND1, a second AND gate AND2, and a second comparator COMP2; wherein one input end of the first AND gate AND1 is connected to the full-charge output end of the charge and discharge circuit, and the other input end is connected to the output end of the second comparator COMP2; the output end of the first AND gate AND1 is connected to one input end of the second AND gate AND2, and serves as the output end of the oscillator module at the same time; the positive input end of the second comparator COMP2 is connected to the valley current limit signal V valley_limit Connect its negative input terminal to the input signal V L The other input terminal of the second AND gate AND2 is connected to the delay signal Delay, and its output terminal is connected to the discharge terminal of the charge and discharge circuit; the time required for the charge and discharge circuit to charge from 0 to full charge is T s .

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