A high-order configurable current-mode low-pass filter circuit

Abstract

The application discloses a high-order configurable current mode low-pass filter circuit, and belongs to the technical field of low-pass filters. The high-order configurable current mode low-pass filter circuit comprises a first-stage low-pass filter, a second-stage low-pass filter and a third-stage low-pass filter which are connected in sequence, the output current of the low-pass filter at a higher stage is poured into the input end of the low-pass filter at a lower stage through a current mirror between two adjacent low-pass filters; and a second-order current mode gm-C structure is adopted for each low-pass filter; a super source follower is arranged on one side of the first-stage low-pass filter, the output end of the super source follower is connected to the input end of the first-stage low-pass filter through two resistors, and a low-resistance connection to the ground is established. The gm-C filter of the three-stage current mode is utilized to realize a 6-order Butterworth filter, the bandwidth can be flexibly adjusted by controlling the sizes of the adjustable capacitors and gms, and thus the wireless communication system of multiple standards can be applied.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of low-pass filters, and particularly relates to a high-order configurable current-mode low-pass filter circuit. BACKGROUND

[0002] In recent years, with the development of wideband wifi and 5G technology, various standards of wireless communication systems have put forward higher requirements for reconfigurable baseband circuit technology. As an important module in the baseband circuit, the main function of the low-pass filter is to filter out interference signals and improve the signal-to-noise ratio of the overall output signal.

[0003] In order to meet the requirements of high-bandwidth standards such as 5G NR 200 / 400 / 800MHz and 802.11.ad wifi 2.16GHz, the baseband low-pass filter needs to have the function of configurable bandwidth. The traditional bandwidth adjustment scheme adopts a switch capacitor array scheme, which has the characteristics of simple structure and easy control, but in the case of large bandwidth adjustment range and high precision requirement, it has the problem of excessive area demand. The single gm tuning method will cause the problem of excessive gain variation. Therefore, a high-order configurable current-mode low-pass filter circuit is proposed. SUMMARY

[0004] In view of the deficiencies of the prior art, the purpose of the application is to provide a high-order configurable current-mode low-pass filter circuit to solve the problems in the prior art.

[0005] The purpose of the application can be achieved by the following technical solutions:

[0006] A high-order configurable current-mode low-pass filter circuit, comprising a first-stage low-pass filter, a second-stage low-pass filter and a third-stage low-pass filter connected in sequence, and the output current of the upper-stage low-pass filter is poured into the input end of the lower-stage low-pass filter through a current mirror between the two adjacent low-pass filters; and each low-pass filter adopts a second-order current-mode gm-C structure.

[0007] One side of the first-stage low-pass filter is provided with a super source follower, and the output end of the super source follower is connected to the input end of the first-stage low-pass filter through two resistors to establish a low-resistance connection to the ground.

[0008] Further, the first-stage low-pass filter comprises a transistor M 1A , a transistor M 1B , a transistor M 2A , a transistor M 2B , a transistor M 3A , a transistor M 3B , a transistor M 4A , a transistor M 4B , and a variable capacitor C 1A, variable capacitor C 1B , resistance R in1 , and resistance R in2 ;

[0009] The source of transistor M 2A is connected to ground GND, and the drain is connected to the source of transistor M 1A ; the drain of transistor M 1A is connected to the drain of transistor M 3A , and the source of transistor M 3A is connected to power supply VDD, and the drain and gate are connected; the source of transistor M 2B is connected to ground GND, and the drain is connected to the source of transistor M 1B ; the drain of transistor M 1B is connected to the drain of transistor M 3B , and the source of transistor M 3B is connected to power supply VDD, and the drain and gate are connected; one end of variable capacitor C 1A is connected to the source of transistor M 1A , and the other end is connected to the source of transistor M 1B ; one end of variable capacitor C 1B is connected to the drain of transistor M 3A , and the other end is connected to the drain of transistor M 3B ; the gate of transistor M 1A is connected to the drain of transistor M 1B , and the gate of transistor M 1B is connected to the drain of transistor M 1A ; one end of resistance R in1 is connected to the source of transistor M 1A , and the other end is connected to the positive pole I in1p of the current input end of the first-stage low-pass filter; one end of resistance R in2 is connected to the source of transistor M 1B , and the other end is connected to the negative pole I in1n of the current input end of the first-stage low-pass filter; the gate of transistor M 4A is connected to the gate of transistor M 3A , the source is connected to power supply VDD, the drain is connected to the negative pole I out1n of the output end of the first-stage low-pass filter, and the gate of transistor M 4B is connected to the gate of transistor M 3B , the source is connected to power supply VDD, and the drain is connected to the positive pole I out1p of the output end of the first-stage low-pass filter; transistor M 3A , transistor M 4A , transistor M 3B , transistor M 4Bwhich constitutes a current mirror, the output of which is connected to the input of a second low-pass filter.

[0010] Further, the second low-pass filter comprises a transistor M 5A , a transistor M 5B , a transistor M 6A , a transistor M 6B , a transistor M 7A , a transistor M 7B , a variable capacitor C 2A and a variable capacitor C 2A .

[0011] The source of a transistor M 5A is connected to the negative pole I in2n of the input of the second low-pass filter, the drain is connected to the drain of a transistor M 6A , the gate is connected to the source of a transistor M 5B , the source of a transistor M 6A is connected to ground GND, the drain is connected to the gate, the source of a transistor M 5B is connected to the positive pole I in2p of the input of the second low-pass filter, the drain is connected to the drain of a transistor M 6B , the gate is connected to the source of a transistor M 5A , the source of a transistor M 6B is connected to ground GND, the drain is connected to the gate, one end of a variable capacitor C 2A is connected to the source of a transistor M 5A , the other end is connected to the source of a transistor M 5B , one end of a variable capacitor C 2B is connected to the drain of a transistor M 5A , the other end is connected to the drain of a transistor M 5B , the gate of a transistor M 7A is connected to the gate of a transistor M 6A , the source is connected to ground GND, the drain is connected to the positive pole I out2p of the output of the second low-pass filter, the gate of a transistor M 7B is connected to the gate of a transistor M 6B , the source is connected to ground GND, the drain is connected to the negative pole I out2n of the output of the second low-pass filter, a transistor M 6A , a transistor M 7A , a transistor M 6B , a transistor M 7B which constitutes a current mirror, the output of which is connected to the input of a third low-pass filter.

[0012] Further, the third low-pass filter comprises a transistor M 8A , a transistor M8B , the source of transistor M 9A , the source of transistor M 9B , the source of transistor M 10A , the source of transistor M 10B , the source of transistor M 11A , the source of transistor M 11B , one end of variable capacitor C 3A , the other end of variable capacitor C 3B ;

[0013] , the source of transistor M 8A , the positive terminal of the third stage low pass filter input I in3p , the drain of transistor M 9A , the drain of transistor M 8B , the source of transistor M 9A , the drain of transistor M 8B , the negative terminal of the third stage low pass filter input I in3n , the drain of transistor M 9B , the drain of transistor M 8A , the source of transistor M 9B , the drain of transistor M 3A , one end of variable capacitor C 8A , the source of transistor M 8B , the source of transistor M 3B , the drain of transistor M 9A , the drain of transistor M 9B , the source of transistor M 10A , the gate of transistor M 9A , the drain of transistor M 11A , the source of transistor M 11A , the negative terminal of the third stage low pass filter output V outn , the source of transistor M 10B , the gate of transistor M 9B , the drain of transistor M 11B , the source of transistor M 11B , the positive terminal of the third stage low pass filter output V outp .

[0014] Further, the super source follower includes: transistor M 12A , transistor M 12B , transistor M 13A , transistor M 13B , transistor M14A , the transistor M 14B , the amplifier A, the resistor R 0A , and the resistor R 0B ;

[0015] the transistor M 14A has its source connected to the power supply VDD, its drain connected to the drain of the transistor M 12A , and its gate connected to the gate of the transistor M 14B ; the transistor M 12A has its source connected to the drain of the transistor M 13A , and its gate connected to the gate of the transistor M 12B ; the transistor M 13A has its source connected to the ground GND, and its drain connected to the output virtual voltage V virtual ; the transistor M 14B has its source connected to the power supply VDD, its drain connected to its gate, and its drain connected to the drain of the transistor M 12B ; the transistor M 12B has its gate connected to the gate of the transistor M 14B , and its source connected to the drain of the transistor M 13B ; the transistor M 13B has its source connected to the ground GND; the input of the amplifier A is connected to the drain of the transistor M 12A , and the output of the amplifier A is connected to the source of the transistor M 12A ; one end of the resistor R 0A is connected to the source of the transistor M 12A , and the other end of the resistor R in1p is connected to the positive pole I 0B of the input of the first-stage low-pass filter; one end of the resistor R 12A is connected to the source of the transistor M in1n , and the other end of the resistor R 1A is connected to the negative pole I 11A of the input of the first-stage low-pass filter.

[0016] Further, the transistors M 1B ~ M 11B have sizes that are equal one-to-one corresponding to the sizes of the transistors M 1A , M 1B , M 2A , M 2B , M 6A , M 6B , M 7A , M 7B , M 8A , M 8B , M 11A , M 11B are NMOS transistors, and the transistors M 3A , M 3B , M4A , M 4B , M 5A , M 5B , M 9A , M 9B , M 10A , M 10B is a PMOS transistor; transistor M 11A , M 11B The gate bias voltage of M

[0017] Further, the transistors M 12A ~M 14A The size of M 1A ~M 3A corresponds to the size of M 12B ~M 14B corresponds to the size of M 1B ~M 3B ; the transistors M 12A , M 12B , M 13A , M 13B are NMOS transistors, and the transistors M 14A , M 14B are PMOS transistors; the transistors M 2A , M 2B , M 13A , M 13B have equal gate bias voltages.

[0018] Further, the variable capacitors C 1A , C 1B , C 2A , C 2B , C 3A , C 3B each include a plurality of switched capacitor units and capacitors in parallel, and each switched capacitor unit includes a transistor M1, a transistor M2, a capacitor C1, and a capacitor C2; one end of the capacitor C1 is connected to the drain of the transistor M1, the other end is connected to the port P1 of the switched capacitor, and the source of the transistor M1 is connected to the ground GND; one end of the capacitor C2 is connected to the drain of the transistor M2, the other end is connected to the port P2 of the switched capacitor, and the source of the transistor M2 is connected to the ground GND; the gates of the transistors M1 and M2 are connected to a control voltage B0, and the control voltage B0 is set to high or low to adjust the capacitance value of the switched capacitor unit; and the transistors M1 and M2 are both NMOS transistors.

[0019] Further, the amplifier A includes a transistor M3 and a transistor M4, wherein the source of the transistor M3 is connected to the power supply VDD, the drain is connected to the drain of the transistor M4, and the gate is used as the input terminal IN of the amplifier A; the source of the transistor M4 is connected to the ground GND, and the gate is connected to a bias voltage VB The drain of the transistor M3 is connected to the output OUT of the amplifier A; the transistor M4 is an NMOS transistor.

[0020] A communication transceiver comprising the high-order configurable current-mode low-pass filter circuit.

[0021] The beneficial effects of the present application are:

[0022] 1. The present application uses a three-stage current-mode gm-C filter to realize a 6th-order Butterworth filter, and the bandwidth can be flexibly adjusted by controlling the sizes of the adjustable capacitors and gms, thereby being applicable to multi-standard wireless communication systems.

[0023] 2. The present application uses a super source follower, so that the filter circuit can be used in single-ended mode and differential mode. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below, and obviously, other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0025] Figure 1 is a schematic diagram of the low-pass filter circuit of the present application as a whole;

[0026] Figure 2 is a schematic diagram of the switch capacitor unit of the present application;

[0027] Figure 3 is a schematic diagram of the amplifier A of the present application;

[0028] Figure 4 is a schematic diagram of the equivalent circuit of the first-stage low-pass filter of the present application. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application, and obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0030] As Figure 1As shown, a high-order configurable current-mode low-pass filter circuit includes a first-stage low-pass filter, a second-stage low-pass filter, a third-stage low-pass filter, and a super source follower. The three-stage low-pass filters should be cascaded in turn, and the output current of the previous stage is directly poured into the input end of the next stage through a current mirror, avoiding the problem of inconsistent DC voltage between the front and rear stages when directly coupled, while reducing the number of current branches and reducing power consumption. Each low-pass filter adopts a second-order current-mode gm-C structure, which meets the large bandwidth while improving the signal linearity, wherein the capacitance of each stage adopts an adjustable switched capacitor, thereby realizing flexible adjustment of the bandwidth. The output end of the super source follower is connected to the input end of the first-stage low-pass filter through two resistors, which establishes a low-resistance connection to the ground, so that the filter circuit can be used in single-ended and differential modes.

[0031] The low-pass filter circuit further includes a ground GND and a power supply VDD.

[0032] The first-stage low-pass filter includes a transistor M 1A , a transistor M 1B , a transistor M 2A , a transistor M 2B , a transistor M 3A , a transistor M 3B , a transistor M 4A , a transistor M 4B , a variable capacitor C 1A , a variable capacitor C 1B , a resistor R in1 , and a resistor R in2 ; wherein the source of the transistor M 2A is connected to the ground GND, and the drain is connected to the source of the transistor M 1A ; the drain of the transistor M 1A is connected to the drain of the transistor M 3A , and the source of the transistor M 3A is connected to the power supply VDD, and the drain is connected to the gate; the source of the transistor M 2B is connected to the ground GND, and the drain is connected to the source of the transistor M 1B ; the drain of the transistor M 1B is connected to the drain of the transistor M 3B , and the source of the transistor M 3B is connected to the power supply VDD, and the drain is connected to the gate; one end of the variable capacitor C 1A is connected to the source of the transistor M 1A , and the other end is connected to the source of the transistor M 1B ; one end of the variable capacitor C 1B is connected to the drain of the transistor M 3A , and the other end is connected to the drain of the transistor M 3B ; the gate of the transistor M 1A is connected to the gate of the transistor M1B the drain of transistor M 1B the gate of transistor M 1A is connected to the drain of transistor M in1 one end of resistor R 1A the source of transistor M in1p the positive terminal of the current input of the first stage low pass filter I in2 one end of resistor R 1B the negative terminal of the current input of the first stage low pass filter I in1n the gate of transistor M 4A the gate of transistor M 3A the source of transistor M out1n the positive terminal of the output of the first stage low pass filter I 4B the gate of transistor M 3B the negative terminal of the output of the first stage low pass filter I out1p the gate of transistor M 3A the gate of transistor M 4A the gate of transistor M 3B the gate of transistor M 4B form a current mirror, the output of which is connected to the input of the second stage low pass filter.

[0033] The second stage low pass filter comprises: transistor M 5A transistor M 5B transistor M 6A transistor M 6B transistor M 7A transistor M 7B a variable capacitor C 2A and a variable capacitor C 2A ; wherein the source of transistor M 5A is connected to the negative terminal of the input of the second stage low pass filter I in2n the drain of transistor M 6A the source of transistor M 5B the source of transistor M 6A is connected to ground GND, the drain being connected to the gate; the source of transistor M 5B is connected to the positive terminal of the input of the second stage low pass filter I in2p the drain of transistor M 6B the source of transistor M 5A the source of transistor M 6B is connected to ground GND, the drain being connected to the gate; one end of variable capacitor C 2A transistor M 5Asource of transistor M 5B variable capacitor C 2B source of transistor M 5A source of transistor M 5B source of transistor M 7A gate of transistor M 6A source of transistor M out2p source of transistor M 7B source of transistor M 6B source of transistor M out2n source of transistor M 6A source of transistor M 7A source of transistor M 6B source of transistor M 7B source of transistor M

[0034] The third stage low-pass filter comprises: transistor M 8A , transistor M 8B , transistor M 9A , transistor M 9B , transistor M 10A , transistor M 10B , transistor M 11A , transistor M 11B , variable capacitor C 3A and variable capacitor C 3B ; wherein the source of transistor M 8A connects the positive pole I in3p of the third stage low-pass filter input end, the drain connects the drain of transistor M 9A , the gate connects the drain of transistor M 8B , the source of transistor M 9A connects the power supply VDD, and the drain and the gate are connected; the source of transistor M 8B connects the negative pole I in3n of the third stage low-pass filter input end, the drain connects the drain of transistor M 9B , the gate connects the drain of transistor M 8A , the source of transistor M 9B connects the power supply VDD, and the drain and the gate are connected; one end of variable capacitor C 3A connects the source of transistor M 8A , and the other end connects the source of transistor M 8B ; one end of variable capacitor C 3B connects the drain of transistor M 9A , and the other end connects the drain of transistor M9B The drains of transistors M are connected; 10A The source is connected to the power supply VDD, and the gate is connected to transistor M. 9A The gate is connected to the transistor M, and the drain is connected to the transistor M. 11A The drain of transistor M 11A The source is connected to ground (GND), and the drain is connected to the negative terminal V at the output of the third-stage low-pass filter. outn Transistor M 10B The source is connected to the power supply VDD, and the gate is connected to transistor M. 9B The gate is connected to the transistor M, and the drain is connected to the transistor M. 11B The drain of transistor M 11B The source is connected to ground (GND), and the drain is connected to the positive terminal V at the output of the third-stage low-pass filter. outp .

[0035] Super source follower includes: transistor M 12A Transistor M 12B Transistor M 13A Transistor M 13B Transistor M 14A Transistor M 14B Amplifier A, Resistor R 0A and resistance R 0B ; where transistor M 14A The source is connected to the power supply VDD, and the drain is connected to transistor M. 12A The drain is connected to the gate of transistor M. 14B The gate of transistor M is connected; 12A The source and transistor M 13A The drain is connected, and the gate and transistor M are connected. 12B The gate of transistor M is connected; 13A The source is connected to ground (GND), and the drain is connected to the output virtual voltage V. virtual Transistor M 14B The source is connected to the power supply VDD, the drain is connected to the gate, and the drain is connected to transistor M. 12B The drain of the transistor; transistor M 12B Gate and transistor M 14B The gate is connected to the transistor M, and the source is connected to the transistor M. 13B The drain of the transistor; transistor M 13B The source terminal of amplifier A is connected to ground (GND); the input terminal of amplifier A is connected to transistor M. 12A The drain of the transistor is connected to the output terminal of transistor M. 12A The source; resistor R 0A One end is connected to transistor M 12A The source of the filter is connected to the positive terminal I of the input of the first-stage low-pass filter. in1p Resistance R 0B One end is connected to transistor M12A source, the other end is connected to the negative pole I of the input end of the first-stage low-pass filter in1n .

[0036] Transistor M 1A ~M 11A corresponds to the size of transistor M 1B ~M 11B ; the size of transistor M 1A , M 1B , M 2A , M 2B , M 6A , M 6B , M 7A , M 7B , M 8A , M 8B , M 11A , M 11B is NMOS transistor, transistor M 3A , M 3B , M 4A , M 4B , M 5A , M 5B , M 9A , M 9B , M 10A , M 10B is PMOS transistor; the gate bias voltage of transistor M 11A , M 11B is equal, both V bias2 ;

[0037] Transistor M 12A ~M 14A corresponds to the size of transistor M 1A ~M 3A ; the size of transistor M 12B ~M 14B corresponds to the size of transistor M 1B ~M 3B ; the size of transistor M 12A , M 12B , M 13A , M 13B is NMOS transistor, transistor M 14A , M 14B is PMOS transistor; the gate bias voltage of transistor M 2A , M 2B , M 13A , M 13B is equal, both V bias1 .

[0038] As shown in Figure 2 , the variable capacitor C 1AC 1B C 2A C 2B C 3A C 3B Each capacitor includes several switched capacitor units connected in parallel. Each switched capacitor unit includes: transistor M1, transistor M2, capacitor C1, and capacitor C2. One end of capacitor C1 is connected to the drain of transistor M1, and the other end is connected to port P1 of the switched capacitor. The source of transistor M1 is connected to ground (GND). One end of capacitor C2 is connected to the drain of transistor M2, and the other end is connected to port P2 of the switched capacitor. The source of transistor M2 is connected to ground (GND). The gates of transistors M1 and M2 are connected to a control voltage B0. The capacitance value of the switched capacitor unit is adjusted by setting the control voltage B0 to a high or low level. Transistors M1 and M2 are both NMOS transistors.

[0039] like Figure 3 As shown, amplifier A includes transistors M3 and M4. The source of transistor M3 is connected to the power supply VDD, the drain of transistor M4 is connected to the drain of transistor M4, and the gate serves as the input terminal IN of amplifier A. The source of transistor M4 is connected to ground GND, and the gate is connected to the bias voltage V. B The drain is connected to the output terminal OUT of amplifier A; transistor M3 is a PMOS transistor and transistor M4 is an NMOS transistor.

[0040] like Figure 4 As shown, the first-stage low-pass filter can be equivalently represented by the LC second-order low-pass filter network shown in the figure, where C = C 1A transistor M 1A M 1B and capacitor C 1B Equivalent to an active inductor, L and C can be represented as:

[0041]

[0042] Among them, g m For transistor M 1A M 1B M 3A M 3B The transconductance of , where s is a complex frequency domain variable in the Laplace transform;

[0043] Therefore, the transfer function of the current can be obtained as follows:

[0044]

[0045] The Q value of the low-pass filter is:

[0046]

[0047] The cutoff frequency ω0 of the low-pass filter is:

[0048]

[0049] The current output in the above formula also needs to be multiplied by the amplification factor K of the output current mirror to obtain the gain of the first-order low-pass filter; the formula shows that the transfer function of the first-order low-pass filter has the characteristics of a second-order low-pass filter, and the bandwidth and Q value of the filter can be designed to the desired value by reasonably designing the values of the capacitance and the transistor g m The principle of the second-order low-pass filter and the third-order low-pass filter is similar to that of the first-order low-pass filter, the input transistor of the second-order low-pass filter is changed from an NMOS transistor to a PMOS transistor, and the second-order low-pass filter does not need a bias current source and is directly biased by the current mirror output of the first-order low-pass filter.

[0050] Working principle:

[0051] In the filter circuit, the first-order low-pass filter adopts a gm-C structure, which can be equivalent to a second-order LC filter network, and the desired bandwidth and Q value can be obtained by reasonably designing the values of the transconductance and the variable capacitance; the principle of the second-order low-pass filter and the third-order low-pass filter is basically the same as that of the first-order low-pass filter, the difference is that the input tube of the second-order low-pass filter is changed from an NMOS transistor to a PMOS transistor, and the second-order low-pass filter does not need a bias current source and is directly biased by the current mirror output of the first-order low-pass filter; the super source follower uses the same structure as the half circuit of the first-order low-pass filter and sets the same transistor size, thereby copying the direct current voltage of the first-order low-pass filter; the output end is connected to the input end of the first-order low-pass filter through a resistor, so that the single-ended impedance to ground of the filter is low, thereby supporting the application in single-ended and differential modes. The overall circuit is a 6th-order Butterworth filter, and the bandwidth can be accurately adjusted by controlling the value of the adjustable capacitance and adjusting the gm by changing the Vbias.

[0052] In addition, in some embodiments, the low-pass filter circuit of the application can be applied to a transceiver, a sensor readout and other high-speed circuits in a wireless communication system, and the wide bandwidth and current mode characteristics of the application can be used to filter out aliasing signals, interference signals and other effects, and improve the output signal-to-noise ratio; the application has a bandwidth configurable function, and can realize different bandwidth requirements, and in low bandwidth applications, the integral noise is further reduced and the signal-to-noise ratio is improved.

[0053] In the description of the specification, the description of the terms "one embodiment", "an example", "a specific example" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Also, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0054] The basic principles, main features and advantages of the present application are shown and described above. Those skilled in the art should understand that the present application is not limited by the above embodiments, and the above embodiments and descriptions in the specification are only to illustrate the principles of the present application. Without departing from the spirit and scope of the present application, various changes and improvements can be made to the present application, and these changes and improvements all fall within the scope of the claimed present application.

Claims

1. A high-order configurable current-mode low-pass filter circuit, characterized in that, It includes a first-stage low-pass filter, a second-stage low-pass filter, and a third-stage low-pass filter cascaded in sequence. The output current of the previous stage low-pass filter is fed into the input terminal of the next stage low-pass filter through a current mirror between adjacent stages. Each stage low-pass filter adopts a second-order current-mode gm-C structure. A super source follower is provided on one side of the first-stage low-pass filter. The output of the super source follower is connected to the input of the first-stage low-pass filter through two resistors to establish a low-impedance connection to ground. The first-stage low-pass filter includes: transistor M 1A Transistor M 1B Transistor M 2A Transistor M 2B Transistor M 3A Transistor M 3B Transistor M 4A Transistor M 4B Variable capacitor C 1A Variable capacitor C 1B Resistance R in1 and resistance R in2 ; transistor M 2A The source is connected to ground (GND), and the drain is connected to transistor M. 1A The source of the transistor; transistor M 1A The drain and transistor M 3A The drains of transistor M are connected. 3A The source of transistor M is connected to the power supply VDD, and the drain is connected to the gate; 2B The source is connected to ground (GND), and the drain is connected to transistor M. 1B The source of the transistor; transistor M 1B The drain and transistor M 3B The drains of transistor M are connected. 3B The source is connected to the power supply VDD, and the drain is connected to the gate; the variable capacitor C 1A One end is connected to transistor M 1A The source of the transistor is connected to transistor M at the other end. 1B The source; variable capacitor C 1B One end is connected to transistor M 3A The drain of one end is connected to transistor M. 3B The drain of the transistor; transistor M 1A Gate and transistor M 1B The drains of transistor M are connected. 1B Gate and transistor M 1A The drains are connected; resistor R in1 One end is connected to transistor M 1A The source terminal is connected to the positive terminal I of the current input terminal of the first-stage low-pass filter, and the other end is connected to it. in1p resistance R in2 One end is connected to transistor M 1B The source terminal is connected to the negative terminal I of the current input terminal of the first-stage low-pass filter. in1n Transistor M 4A Gate and transistor M 3A The gate is connected to the source, the source is connected to the power supply VDD, and the drain is connected to the negative terminal I of the output of the first-stage low-pass filter. out1n Connected, transistor M 4B Gate and transistor M 3B The gate is connected to the source, the source is connected to the power supply VDD, and the drain is connected to the positive terminal I of the first-stage low-pass filter output. out1p Connected; transistor M 3A Transistor M 4A Transistor M 3B Transistor M 4B This forms a current mirror, the output of which is connected to the input of the second-stage low-pass filter; The second-stage low-pass filter includes: transistor M 5A Transistor M 5B Transistor M 6A Transistor M 6B Transistor M 7A Transistor M 7B Variable capacitor C 2A and variable capacitor C 2A ; transistor M 5A The source is connected to the negative terminal I of the input of the second-stage low-pass filter. in2n The drain of transistor M is connected. 6A The drain and gate of transistor M are connected. 5B The source of the transistor M 6A The source of transistor M is connected to ground (GND), and the drain is connected to the gate. 5B The source is connected to the positive terminal I of the input of the second-stage low-pass filter. in2p The drain of transistor M is connected. 6B The drain and gate of transistor M are connected. 5A The source of the transistor M 6B The source is connected to ground (GND), and the drain is connected to the gate; the variable capacitor C 2A One end is connected to transistor M 5A The source of the transistor is connected to transistor M at the other end. 5B The source of the variable capacitor C 2B One end is connected to transistor M 5A The drain of one end is connected to transistor M. 5B The drain of the transistor; transistor M 7A Gate and transistor M 6A The gate is connected to the source, the source is connected to ground (GND), and the drain is connected to the positive terminal (I) of the output of the second-stage low-pass filter. out2p Connected; transistor M 7B Gate and transistor M 6B The gate is connected to the source, the source is connected to ground (GND), and the drain is connected to the negative terminal I of the output of the second-stage low-pass filter. out2n Connected; transistor M 6A Transistor M 7A Transistor M 6B Transistor M 7B This forms a current mirror, the output of which is connected to the input of the third-stage low-pass filter; The third-stage low-pass filter includes: transistor M 8A Transistor M 8B Transistor M 9A Transistor M 9B Transistor M 10A Transistor M 10B Transistor M 11A Transistor M 11B Variable capacitor C 3A and variable capacitor C 3B ; transistor M 8A The source is connected to the positive terminal I of the third-stage low-pass filter input. in3p The drain of transistor M is connected. 9A The drain and gate of transistor M are connected. 8B The drain of transistor M 9A The source of transistor M is connected to the power supply VDD, and the drain is connected to the gate; 8B The source is connected to the negative terminal I of the third-stage low-pass filter input. in3n The drain of transistor M is connected. 9B The drain and gate of transistor M are connected. 8A The drain of transistor M 9B The source is connected to the power supply VDD, and the drain is connected to the gate; the variable capacitor C 3A One end is connected to transistor M 8A The source of one is connected to the other end, and the other end is connected to transistor M. 8B The source is connected; the variable capacitor C 3B One end is connected to transistor M 9A The drain of one end is connected to the other end of the transistor M. 9B The drains of transistors M are connected; 10A The source is connected to the power supply VDD, and the gate is connected to transistor M. 9A The gate is connected to the transistor M, and the drain is connected to the transistor M. 11A The drain of transistor M 11A The source is connected to ground (GND), and the drain is connected to the negative terminal V at the output of the third-stage low-pass filter. outn Transistor M 10B The source is connected to the power supply VDD, and the gate is connected to transistor M. 9B The gate is connected to the transistor M, and the drain is connected to the transistor M. 11B The drain of transistor M 11B The source is connected to ground (GND), and the drain is connected to the positive terminal V at the output of the third-stage low-pass filter. outp .

2. The high-order configurable current-mode low-pass filter circuit according to claim 1, characterized in that, The super source follower includes: transistor M 12A Transistor M 12B Transistor M 13A Transistor M 13B Transistor M 14A Transistor M 14B Amplifier A, Resistor R 0A and resistance R 0B ; transistor M 14A The source is connected to the power supply VDD, and the drain is connected to transistor M. 12A The drain is connected to the gate of transistor M. 14B The gate of transistor M is connected; 12A The source and transistor M 13A The drain is connected, and the gate and transistor M are connected. 12B The gate of transistor M is connected; 13A The source is connected to ground (GND), and the drain is connected to the output virtual voltage V. virtual Transistor M 14B The source is connected to the power supply VDD, the drain is connected to the gate, and the drain is connected to transistor M. 12B The drain of the transistor; transistor M 12B Gate and transistor M 14B The gate is connected to the transistor M, and the source is connected to the transistor M. 13B The drain of the transistor; transistor M 13B The source terminal of amplifier A is connected to ground (GND); the input terminal of amplifier A is connected to transistor M. 12A The drain of the transistor is connected to the output terminal of transistor M. 12A The source; resistor R 0A One end is connected to transistor M 12A The source of the filter is connected to the positive terminal I of the input of the first-stage low-pass filter. in1p Resistance R 0B One end is connected to transistor M 12A The source of the filter is connected to the negative terminal I of the input of the first-stage low-pass filter. in1n .

3. The high-order configurable current-mode low-pass filter circuit according to claim 1, characterized in that, The transistor M 1A ~M 11A With transistor M 1B ~M 11B The dimensions are one-to-one equal; transistor M 1A M 1B M 2A M 2B M 6A M 6B M 7A M 7B M 8A M 8B M 11A M 11B It is an NMOS transistor, transistor M 3A M 3B M 4A M 4B M 5A M 5B M 9A M 9B M 10A M 10B It is a PMOS transistor; transistor M 11A M 11B The gate bias voltages are equal.

4. A high-order configurable current-mode low-pass filter circuit according to claim 2, characterized in that, The transistor M 12A ~M 14A With transistor M 1A ~M 3A The dimensions are one-to-one equal, transistor M 12B ~M 14B With transistor M 1B ~M 3B The dimensions are one-to-one equal; transistor M 12A M 12B M 13A M 13B For NMOS transistors, transistor M 14A M 14B It is a PMOS transistor; transistor M 2A M 2B M 13A M 13B The gate bias voltages are equal.

5. A high-order configurable current-mode low-pass filter circuit according to claim 1, characterized in that, The variable capacitor C 1A C 1B C 2A C 2B C 3A C 3B Each capacitor includes several switched capacitor units connected in parallel. Each switched capacitor unit includes: transistor M1, transistor M2, capacitor C1, and capacitor C2. One end of capacitor C1 is connected to the drain of transistor M1, and the other end is connected to port P1 of the switched capacitor. The source of transistor M1 is connected to ground (GND). One end of capacitor C2 is connected to the drain of transistor M2, and the other end is connected to port P2 of the switched capacitor. The source of transistor M2 is connected to ground (GND). The gates of transistors M1 and M2 are connected to a control voltage B0. The capacitance value of the switched capacitor unit is adjusted by setting the control voltage B0 to a high or low level. Transistors M1 and M2 are both NMOS transistors.

6. A high-order configurable current-mode low-pass filter circuit according to claim 2, characterized in that, The amplifier A includes transistor M3 and transistor M4, wherein the source of transistor M3 is connected to the power supply VDD, the drain of transistor M3 is connected to the drain of transistor M4, and the gate serves as the input terminal IN of amplifier A. The source of transistor M4 is connected to ground (GND), and the gate is connected to the bias voltage V. B The drain is connected to the output terminal OUT of amplifier A; transistor M3 is a PMOS transistor and transistor M4 is an NMOS transistor.

7. A communication transceiver, comprising: A high-order configurable current-mode low-pass filter circuit according to any one of claims 1-6.

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