A data selection circuit, method, apparatus, device and storage medium

Abstract

The application discloses a kind of data selection circuit, method, device, equipment and storage medium, it is related to data processing technical field, data selection circuit includes multiple data channels, the input end of each data channel is respectively connected different input data, output end is mutually connected, forms the structure of multiple inputs one output.When the input data of certain data channel is selected output, the first resistance variable device and the second resistance variable device in it will switch to low resistance state, and input data can be output after passing through the first resistance variable device of low resistance state and the second resistance variable device of low resistance state;When the input data of certain data channel is not selected output, the first resistance variable device and the second resistance variable device in it will be in high resistance state, and input data cannot be normally output by passing through the first resistance variable device of high resistance state and the second resistance variable device of high resistance state;Using resistance state change of resistance variable device realizes data selection function, compared with gate circuit, use few devices, circuit structure is simple, and scalability is strong.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to a data selection circuit, method, apparatus, device, and storage medium. Background Technology

[0002] A data selector is a circuit that selects and transmits multiple data points to a single channel to achieve data selection. It is a multi-input, single-output switch and the foundation for implementing other complex logic. Traditional CMOS (Complementary Metal Oxide Semiconductor) data selector circuits require one NOT gate, two AND gates, and one OR gate. The data selection process is achieved through the logic calculations of these gates. However, each gate consists of multiple transistors, resulting in a very high cost and a large footprint for the entire data selector. Especially when the amount of input data is large, the entire data selector circuit becomes extremely complex.

[0003] It is evident that how to implement a simpler data selector circuit is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a data selection circuit, method, apparatus, device, and storage medium that can solve the problems of high cost and large area occupation of data selection circuits.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a data selection circuit, comprising:

[0006] Several data channels are provided, with their outputs interconnected for outputting selected data; the inputs of each data channel are used to receive different input data.

[0007] For any given data channel, the data channel includes:

[0008] The first resistive switching device has a first terminal for receiving input data. The first resistive switching device is used to switch to a low resistance state when the input data it receives is within a preset valid range, and to switch to a high resistance state when the input data it receives is not within the preset valid range.

[0009] The second resistive switching device has a first end connected to the second end of the first resistive switching device, and the second end serves as the output end of the data channel. The second resistive switching device is used to switch to a low-resistance state when the input data connected to the corresponding first resistive switching device is selected for output, and to switch to a high-resistance state when the input data connected to the corresponding first resistive switching device is not selected for output.

[0010] In some embodiments, both the first resistive switching device and the second resistive switching device are resistive switching memories; the data selection circuit further includes:

[0011] A bias voltage output circuit, the bias voltage output circuit including a plurality of output terminals corresponding one-to-one with each of the data channels;

[0012] For any output terminal of the bias voltage output circuit, the output terminal is connected to the second terminal of the first resistive switching device in the corresponding data channel and the first terminal of the second resistive switching device in the corresponding data channel, respectively.

[0013] The bias voltage output circuit is used to output bias voltage to each of the data channels according to the selected output of the input data, so as to control the second resistive switching device to switch the resistive state.

[0014] In some embodiments, the second resistive switching device is a non-volatile resistive switching memory, and the first resistive switching device is a volatile resistive switching memory.

[0015] In some embodiments, the second resistive switching device is a bipolar resistive switching memory; the initial state of the second resistive switching device is a high-resistivity state.

[0016] The data selection circuit also includes:

[0017] The processor has its input terminal connected to the output terminal of the data selection circuit and its output terminal connected to the input terminal of the bias voltage output circuit. It is used to receive the output data of the data selection circuit and output a data selection completion command to the bias voltage output circuit when it receives the output data of the data selection circuit.

[0018] The bias voltage output circuit is specifically used to output a first preset bias voltage to the first terminal of the second resistive switching device in the target data channel when the input data of the target data channel is selected for output, so as to control the second resistive switching device in the target data channel to switch from a high resistance state to a low resistance state; when the data selection completion instruction is received, it outputs a second preset bias voltage to the first terminal of the second resistive switching device in the target data channel, so as to control the second resistive switching device in the target data channel to recover from a low resistance state to a high resistance state.

[0019] The first preset bias voltage and the second preset bias voltage have opposite voltage directions.

[0020] In some embodiments, the second resistive switching device is a unipolar resistive switching memory; the initial state of the second resistive switching device is a high-resistivity state;

[0021] The bias voltage output circuit is specifically used to output a third preset bias voltage to the first terminal of the second resistive switching device in the target data channel when the input data of the target data channel is selected for output, so as to control the second resistive switching device in the target data channel to switch from a high resistance state to a low resistance state; when a data selection completion command is received, the third preset bias voltage is output to the first terminal of the second resistive switching device in the target data channel again, so as to control the second resistive switching device in the target data channel to recover from a low resistance state to a high resistance state.

[0022] In some embodiments, the bias voltage output circuit is a controller, and several general-purpose input / output ports of the controller are connected one-to-one with each of the data channels;

[0023] The controller is used to configure the pin level state of each of the general-purpose input / output ports according to the selected output of the input data, so as to control the second resistive switching device to switch the resistive state.

[0024] To address the aforementioned technical problems, embodiments of the present invention also provide a data selection method, applied to the data selection circuit described above, the data selection method comprising:

[0025] Determine the target data channel corresponding to the target data to be output;

[0026] The first and second resistive switching devices in the target data channel are switched to a low-resistance state so that the target data can pass through the low-resistance first and second resistive switching devices.

[0027] Receive target data output from the target data channel.

[0028] To address the aforementioned technical problems, embodiments of the present invention also provide a data selection device, applied to the data selection circuit as described above, the data selection device comprising:

[0029] The target determination unit is used to determine the target data channel corresponding to the target data that needs to be output.

[0030] The control conduction unit is used to control the first resistive switching device and the second resistive switching device in the target data channel to switch to a low-resistance state so that the target data can pass through the first resistive switching device and the second resistive switching device in a low-resistance state.

[0031] A data receiving unit is used to receive target data output from the target data channel.

[0032] To address the aforementioned technical problems, embodiments of the present invention also provide an electronic device, comprising:

[0033] Memory, used to store computer programs;

[0034] A processor for executing the computer program to implement the steps of the data selection method as described above.

[0035] To address the aforementioned technical problems, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the data selection method as described above.

[0036] As can be seen from the above technical solution, the data selection circuit includes multiple data channels. The input terminals of each data channel are connected to different input data, and the output terminals are interconnected, forming a multiple-input, one-output structure. When the input data of a certain data channel is selected for output, the first and second resistive switching devices switch to a low-resistance state, allowing the input data to pass through these devices and be output. When the input data of a certain data channel is not selected for output, the first and second resistive switching devices are in a high-resistance state, preventing the input data from being output normally. The beneficial effect of this invention is that it utilizes the resistance changes of resistive switching devices to achieve the data selection function. Compared to gate circuits, it uses fewer components, has a simpler circuit structure, and is more scalable. Attached Figure Description

[0037] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of a data selection circuit provided in an embodiment of the present invention;

[0039] Figure 2 A schematic diagram of a data selection circuit including two data channels is provided in an embodiment of the present invention;

[0040] Figure 3 A schematic diagram of a data selection circuit including N data channels is provided in an embodiment of the present invention;

[0041] Figure 4 A schematic diagram illustrating the electrical characteristics of a bipolar non-volatile resistive random access memory (BRAM) provided in an embodiment of the present invention.

[0042] Figure 5 A schematic diagram illustrating the electrical characteristics of a volatile resistive random access memory (RRAM) provided in an embodiment of the present invention;

[0043] Figure 6 A schematic diagram illustrating the electrical characteristics of a unipolar non-volatile resistive random access memory (RRAM) provided in an embodiment of the present invention;

[0044] Figure 7 A flowchart illustrating a data selection method provided in an embodiment of the present invention;

[0045] Figure 8 This is a schematic diagram of the structure of a data selection device provided in an embodiment of the present invention;

[0046] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0048] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.

[0049] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0050] Since the invention of integrated circuits, their manufacturing technology has continuously advanced following Moore's Law. Today, the minimum linewidth has reached several nanometers, entering the realm of quantum and mesoscopic physics, resulting in physical phenomena such as Fermi pinning, Coulomb blocking, quantum tunneling, impurity fluctuations, and spin transport. These physical obstacles encountered by Moore's Law, which has lasted for over fifty years, pose significant challenges to silicon-based CMOS technology's reliance on simple size reduction to increase integration density, both in terms of physical principles and manufacturing processes. On the other hand, with the increase in transistor density, power consumption per unit area also increases significantly, generating enormous heat that severely impacts the high-frequency performance and reliability of integrated circuits. For example, from 1997 to 2010, the gate length of CMOS devices decreased by approximately 300 times, but the energy density increased by nearly 100,000 times, while the clock frequency only increased by about 2,000 times. Power consumption has become another challenge for the development of the microelectronics industry.

[0051] Against this backdrop, new technological breakthroughs are needed to maintain the continued growth of electronic device performance. Resistive random access memory (RRAM), as a novel non-volatile memory technology, has gradually become a research hotspot due to its advantages such as higher storage density, lower power consumption, and faster read / write speeds. RRAM utilizes the resistance changes of materials to store information, providing new possibilities for exceeding Moore's Law. The design of emerging circuit devices based on RRAM is beneficial for simplifying the current mainstream transistor-based CMOS circuits. Based on this, this invention utilizes RRAM to implement a data selection circuit.

[0052] Next, a data selection circuit provided by an embodiment of the present invention will be described in detail. See also Figure 1 As shown, Figure 1 This is a schematic diagram of a data selection circuit provided in an embodiment of the present invention. The data selection circuit includes:

[0053] Several data channels are provided, with their outputs interconnected for outputting selected data; the inputs of each data channel are used to receive different input data.

[0054] For any given data channel, the data channel includes:

[0055] The first resistive switching device has a first terminal for receiving input data. The first resistive switching device is used to switch to a low resistance state when the input data it receives is within a preset valid range, and to switch to a high resistance state when the input data it receives is not within the preset valid range.

[0056] The second resistive switching device has a first end connected to the second end of the first resistive switching device, and the second end serves as the output end of the data channel. The second resistive switching device is used to switch to a low-resistance state when the input data connected to the corresponding first resistive switching device is selected for output, and to switch to a high-resistance state when the input data connected to the corresponding first resistive switching device is not selected for output.

[0057] Understandably, the data selection circuit includes multiple data channels, each with independent input terminals used to receive different input data. The output terminals of all data channels are interconnected, forming a multi-input single-output data selection circuit structure. When a data channel has data input, the data selection circuit will only select one input data for output. The states of the first and second resistive switching devices in each data channel will switch according to their corresponding input data and whether it is selected for output. When a data channel receives valid data within a preset valid range, and the corresponding input data for that data channel is selected for output, both the first and second resistive switching devices will switch to a low-resistance state. The resistance of the low-resistance first and second resistive switching devices is very small, allowing the selected input data to be output normally without data loss. However, if the data received by a certain data channel is not valid data and / or the corresponding input data is not selected for output, the first and / or second resistive switching devices will be in a high-resistance state. The resistance values ​​of the first and second resistive switching devices in the high-resistance state are very large, and the corresponding input data cannot be output normally through that data channel. Thus, the selection and output of multiple input data is achieved by utilizing the resistance change process of the resistive switching devices.

[0058] It should be noted that the resistance state change of the second resistive switching device depends on whether its data channel is the target data channel corresponding to the selected output target data. The default initial state of the second resistive switching device is a high-resistance state. If a certain input data is selected as the target data output, the second resistive switching device in its corresponding data channel will receive a control signal and switch from a high-resistance state to a low-resistance state; the second resistive switching devices in other data channels will remain in a high-resistance state. The resistance state change of the first resistive switching device depends on the voltage of the input data connected to its first terminal. The default initial state of the first resistive switching device is a high-resistance state. When the voltage of the input data is greater than the first preset threshold corresponding to the first resistive switching device, the first resistive switching device will switch from a high-resistance state to a low-resistance state. Therefore, the first resistive switching device can only accept input data with a voltage greater than the preset value. When designing the data selection circuit, the type of the first resistive switching device will be adjusted according to the data type and voltage level used in the current application scenario. Therefore, when designing and applying data selection circuits, it is necessary to use the first preset threshold of the first resistive switching device to achieve the selection of target data. The preferred setting is to select a first resistive switching device with a very small first preset threshold in order to achieve a data selection circuit with a wider range of applications. The first preset threshold is also the opening threshold of the first resistive switching device.

[0059] It's easy to understand that valid data refers to data that, when input to the first terminal of the first resistive switching device, can support the device's transition to a low-impedance state. Generally, this means the voltage of the data itself can reach a first preset threshold that controls the first resistive switching device's configuration switching. Data being within a preset valid range means the data voltage is greater than the first preset threshold of the first resistive switching device. Taking digital signals as an example, digital signals include signal 0 and signal 1. Typically, multiple data channels will receive signal 1. A target data channel needs to be selected to output its corresponding signal 1. Therefore, the first resistive switching device needs to switch to a low-impedance state upon receiving signal 1. If signal 1 is a 3.3V voltage signal, then the first preset threshold of the first resistive switching device only needs to be less than 3.3V. Taking analog signals as an example, if an application requires analog signals above 0.5V, then the data selection circuit needs to support analog signal outputs of at least 0.5V. In this case, a first resistive switching device with a first preset threshold less than 0.5V needs to be selected.

[0060] It should be noted that this application does not impose any special restrictions on the specific types and implementation methods of the first and second resistive switching devices in each data channel. These requirements need to be set and adjusted according to the specific voltage level of the data in the actual application scenario. This application also does not impose any special restrictions on the number of data channels.

[0061] As one specific embodiment, see Figure 2 As shown, Figure 2 This invention provides a schematic diagram of a data selection circuit comprising two data channels, as shown in the embodiment of the invention. Taking a two-to-one data selector as an example, its structure is as follows: Figure 2 As shown, bit line X is the input, including two inputs X1 and X2; Y is the selection signal, which is the control signal set for the second resistive switching device. The process of selecting which input data to output is achieved by outputting different selection signals to each data channel, including Y1 corresponding to the first data channel and Y2 corresponding to the second data channel; Z is the output line. The first resistive switching device includes resistive switching memory B1 and resistive switching memory B2, and the second resistive switching device includes resistive switching memory A1 and resistive switching memory A2.

[0062] As one specific embodiment, see Figure 3 As shown, Figure 3 This is a schematic diagram of a data selection circuit including N data channels provided in an embodiment of the present invention. Based on a 2-to-1 data selector, 4-to-1, 8-to-1, and even more data selection functions can be achieved by linearly increasing the number of resistive switching devices. The specific structure of the N-to-1 data selector based on resistive switching memory is as follows... Figure 3As shown, there are n inputs X1, X2, up to Xn and n corresponding selection signals Y1, Y2, up to Yn, with Z being the output line. The first resistive switching device includes resistive switching memory B1, B2, up to Bn, and the second resistive switching device includes resistive switching memory A1, A2, up to An. A bias voltage is applied to the Ym corresponding to the line M to be selected. Subsequently, the corresponding second resistive switching device Am will become a low-impedance state under the action of the bias voltage. At the same time, due to the data input, the voltage division across the corresponding first resistive switching device Bm is greater than its opening threshold, and the first resistive switching device Bm becomes a low-impedance state. When Xm=1, regardless of the input values ​​of other lines X, Z=1 can be obtained. If the input data is a digital signal, multiple channels can be opened simultaneously. That is, when multiple input data are selected for output, the multiple signals are ORed. In other words, if the input data of any one of the selected multiple channels is 1, the output result will be 1.

[0063] The data selection circuit provided by this invention implements the data selection function based on resistive switching devices such as resistive switching memory. It achieves a multi-to-one data selector method with lower hardware complexity and lower power consumption, and has strong scalability. It has advantages such as fewer components, simpler circuit structure, and strong scalability, achieving the data selection function with lower hardware complexity.

[0064] In some embodiments, both the first resistive switching device and the second resistive switching device are resistive switching memories; the data selection circuit further includes:

[0065] A bias voltage output circuit, the bias voltage output circuit including a plurality of output terminals corresponding one-to-one with each of the data channels;

[0066] For any output terminal of the bias voltage output circuit, the output terminal is connected to the second terminal of the first resistive switching device in the corresponding data channel and the first terminal of the second resistive switching device in the corresponding data channel, respectively.

[0067] The bias voltage output circuit is used to output bias voltage to each of the data channels according to the selected output of the input data, so as to control the second resistive switching device to switch the resistive state.

[0068] It is easy to understand that the first and second resistive switching devices can be implemented using resistive switching memory. In this case, the resistance state changes of the first and second resistive switching devices are achieved by changing the bias voltage across the devices. Therefore, a bias voltage output can be set and connected to the first terminal of the second resistive switching device. By controlling whether the bias voltage output circuit outputs a bias voltage, the resistance state change of the second resistive switching device can be controlled, thereby realizing the process of selecting data output.

[0069] It should be noted that the specific electrical characteristics of the resistive switching memory A, which serves as the second resistive switching device, are as follows: Figure 4 As shown, the device is initially in a high-resistance state. When the bias voltage across the device exceeds its turn-on threshold, the device switches to a low-resistance state. Curve 1 represents the relationship between the voltage across the device and the current flowing through it when the resistive random access memory (RRAM) A is in a high-resistance state, and curve 2 represents the relationship between the voltage across the device and the current flowing through it when the RRAM A is in a low-resistance state. The electrical characteristics of the RRAM B, which serves as the first resistive device, are as follows: Figure 5 As shown, the device is initially in a high-resistance insulating state. When the bias voltage across the device is higher than its turn-on threshold Vth2, the device will switch to a low-resistance state. Curve 3 shows the relationship between the voltage across the device and the current flowing through it when the resistive random access memory B is in a high-resistance state, and curve 4 shows the relationship between the voltage across the device and the current flowing through it when the resistive random access memory B is in a low-resistance state.

[0070] It is understandable that when a specific input data needs to be selected for output, a bias voltage output circuit can be used to output a preset bias voltage to the second terminal of the first resistive switching device and the first terminal of the second resistive switching device in the corresponding data channel. The output terminal is in a zero-voltage state when there is no output. After the preset bias voltage is applied, the voltage across the second resistive switching device exceeds its turn-on threshold, causing the second resistive switching device to switch to a low-resistance state. Simultaneously, when the input data is connected to the corresponding first resistive switching device, the voltage of the data itself will also cause the voltage across the first resistive switching device to exceed its turn-on threshold, causing the first resistive switching device to switch to a low-resistance state, thus achieving data output. This application does not specifically limit the specific type and implementation method of the bias voltage output voltage. The specific value of the preset bias voltage can be selected and adjusted according to the turn-on threshold of the corresponding second resistive switching device.

[0071] As a specific embodiment, with Figure 2For example, the output terminals of the bias voltage output voltage output the selection signals Y1 and Y2 respectively. When there is no selection, neither selection signal Y1 nor Y2 applies bias to the corresponding data channel, and the resistive random access memory (RRAM) A1, RRAM A2, RRAM B1, and RRAM B2 are all in a high-impedance state. At this time, even if there are input signals on bit lines X1 and X2, no output can be detected because the high-impedance RRAMs A1 and A2 are connected in series on the lines. That is, when X1=0, X2=0, Y1=0, and Y2=0, Z=0. When the X1 line is turned on for data output, a bias voltage is applied at Y1, causing the RRAM A1 to become a low-impedance state. Since there is data input at X1, the voltage division across the RRAM B1 is greater than its turn-on threshold, and the RRAM B1 becomes a low-impedance state. Therefore, the input signal at X1 can be output from Z. At this time, X1=1. When X2=0 or X2=1, Z=1 can be obtained. Similarly, when line X2 is turned on, a bias voltage is applied to point Y2, causing the resistive variable resonator A2 to become a low-resistance state. At the same time, the voltage drop across resistive variable resonator B2 exceeds its turn-on threshold, causing B2 to become a low-resistance state. The output of line Z corresponds to the input of X2. At this time, X2=1. When X1=0 or X1=1, Z=1 can be obtained.

[0072] Specifically, both the first and second resistive switching devices can be directly implemented using resistive switching memory. In this case, the second resistive switching device can be controlled by setting a bias voltage output circuit. By controlling the resistance state change of each second resistive switching device by outputting a preset bias voltage, the data selection output process can be realized. This is simple, effective, and easy to implement.

[0073] See Figure 4 As shown, Figure 4 A schematic diagram illustrating the electrical characteristics of a bipolar non-volatile resistive random access memory (BRAM) provided in an embodiment of the present invention; see also Figure 5 As shown, Figure 5 This is a schematic diagram of the electrical characteristics of a volatile resistive switching memory provided in an embodiment of the present invention; in some embodiments, the second resistive switching device is a non-volatile resistive switching memory, and the first resistive switching device is a volatile resistive switching memory.

[0074] It is understandable that when the second resistive switching device switches to a low-resistance state, if there is still a bias voltage at the first terminal of the second resistive switching device, this bias voltage may affect the accuracy of the final output data. Therefore, a non-volatile resistive switching memory can be used to implement the second resistive switching device. The resistance state change of the first resistive switching device is determined by the voltage of the input data itself. As long as the input data is always at the first terminal of the first resistive switching device, the first resistive switching device can always receive the input data. Therefore, a volatile resistive switching memory can be used for the first resistive switching device.

[0075] like Figure 2 and Figure 3 As shown, resistive random access memory (RRAM) A exhibits non-volatile resistive switching characteristics. This means that RRAM A's low-resistance state, switched under a preset bias voltage, is non-volatile. At this point, a voltage needs to be applied again for RRAM A to return to the high-resistance state; otherwise, RRAM A will remain in the low-resistance state. Resistive random access memory (RRAM) B, on the other hand, exhibits volatile resistive switching characteristics. This means that RRAM B's low-resistance state, switched under input data, is volatile. When the bias voltage is removed or when the bias voltage across its terminals is less than the device's holding voltage Vth1, the device returns to its initial high-resistance insulating state. In other words, volatile RRAM requires continuous power to maintain the low-resistance state, while non-volatile RRAM only requires a momentary bias voltage to maintain the low-resistance state. Therefore, by using a non-volatile resistive switching memory to implement the second resistive switching device, the bias voltage output voltage only needs to be output at the moment the data path is selected to control the second resistive switching device to switch to a low resistance state. There is no need to continuously output the preset bias voltage to the second resistive switching device, thereby avoiding the impact of continuously applying the bias voltage on the output data.

[0076] Specifically, by combining volatile resistive switching memory and non-volatile resistive switching memory to implement the first resistive switching device and the second resistive switching device, the method of continuously outputting a preset bias voltage to maintain the low resistance state of the second resistive switching device is avoided. This ensures that the first and second resistive switching devices corresponding to the selected output data can remain in a low resistance state throughout the entire data output process, while improving the accuracy and reliability of the final output data.

[0077] In some embodiments, the second resistive switching device is a bipolar resistive switching memory; the initial state of the second resistive switching device is a high-resistivity state.

[0078] The data selection circuit also includes:

[0079] The processor has its input terminal connected to the output terminal of the data selection circuit and its output terminal connected to the input terminal of the bias voltage output circuit. It is used to receive the output data of the data selection circuit and output a data selection completion command to the bias voltage output circuit when it receives the output data of the data selection circuit.

[0080] The bias voltage output circuit is specifically used to output a first preset bias voltage to the first terminal of the second resistive switching device in the target data channel when the input data of the target data channel is selected for output, so as to control the second resistive switching device in the target data channel to switch from a high resistance state to a low resistance state; when the data selection completion instruction is received, it outputs a second preset bias voltage to the first terminal of the second resistive switching device in the target data channel, so as to control the second resistive switching device in the target data channel to recover from a low resistance state to a high resistance state.

[0081] The first preset bias voltage and the second preset bias voltage have opposite voltage directions.

[0082] It's easy to understand that non-volatile resistive random access memories (RRAMs) include two types: bipolar RRAMs and unipolar RRAMs. When the second resistive device is implemented using a bipolar RRAM, the device will only return to a high-impedance state when a reverse bias voltage is applied again. Therefore, the bias voltage output circuit controls the second resistive device to switch from a high-impedance state to a low-impedance state by outputting a first preset bias voltage when data output selection is needed. When the selected data output ends, the second resistive device in this low-impedance state needs to be switched back to a high-impedance state, that is, the previously selected data channel needs to be turned off. At this time, a reverse voltage needs to be applied to the first terminal of the second resistive device in the data channel to be turned off, thereby resetting the RRAM A in that data channel to its initial high-impedance state, thus turning off the data channel. The RRAM B will spontaneously return to its initial high-impedance state after the input voltage, that is, after the input data is removed, preparing for the next data selection. This application does not impose any special restrictions on the specific values ​​of the first preset bias voltage and the second preset bias voltage. The absolute values ​​of the first preset bias voltage and the second preset bias voltage do not necessarily have to be equal, as long as they can both trigger the resistance state switching of the second resistive switching device.

[0083] Furthermore, to facilitate the bias voltage output circuit in determining whether the selected data output has ended, a processor can be further configured in the data selection circuit to monitor the data output status in real time. The processor can be implemented by directly reusing the device receiving the output data, or the device receiving the output data and the device for issuing the data selection completion instruction can be set separately, with a pre-established communication connection between them. When the processor receives the output data, it indicates that the data output has ended, at which point it can instruct the bias voltage output voltage to control the second resistive switching device to return to a high-resistance state. This application does not specifically limit the specific type and implementation method of the processor and the data selection completion instruction.

[0084] Considering the relatively high speed of data transmission, a timer or delay circuit can be directly set in the bias voltage output circuit. After outputting the first preset bias voltage to the first terminal of the second resistive switching device in the target data channel, a second preset bias voltage can be output directly to the first terminal of the second resistive switching device in the target data channel after a preset delay. The specific value of the preset duration can be set according to the line length and data transmission speed.

[0085] Specifically, when the second resistive switching device is implemented using a bipolar resistive switching memory, the bias voltage output circuit needs to output a second preset bias voltage that is opposite to the first preset bias voltage at the end of the data output to control the second resistive switching device to return to a high-resistivity state so that the next data selection output process can proceed.

[0086] See Figure 6 As shown, Figure 6 This is a schematic diagram of the electrical characteristics of a unipolar non-volatile resistive switching memory provided in an embodiment of the present invention; in some embodiments, the second resistive switching device is a unipolar resistive switching memory; the initial state of the second resistive switching device is a high-resistivity state;

[0087] The bias voltage output circuit is specifically used to output a third preset bias voltage to the first terminal of the second resistive switching device in the target data channel when the input data of the target data channel is selected for output, so as to control the second resistive switching device in the target data channel to switch from a high resistance state to a low resistance state; when a data selection completion command is received, the third preset bias voltage is output to the first terminal of the second resistive switching device in the target data channel again, so as to control the second resistive switching device in the target data channel to recover from a low resistance state to a high resistance state.

[0088] It is understandable that resistive random access memory A can also be implemented using unipolar non-volatile resistive random access memory, and can also achieve the function of data selection. The specific electrical characteristics of unipolar non-volatile resistive random access memory are as follows: Figure 6As shown, curve 5 represents the relationship between the voltage across the device and the current flowing through it when the resistive variable memory (RMU) A is in a high-resistance state, and curve 6 represents the relationship between the voltage across the device and the current flowing through it when the RMU A is in a low-resistance state. The operation of controlling the second resistive variable device to return to a high-resistance state differs slightly. When the bias voltage applied to the unipolar RMU is greater than its turn-on threshold Vset, it changes from the initial high-resistance state to a low-resistance state, turning on the circuit and enabling data selection. When it is again subjected to a bias voltage higher than the turn-on threshold Vreset, the unipolar RMU returns from the low-resistance state to its initial high-resistance insulated state. At this time, the circuit it is on is closed, and data selection is impossible. Therefore, after the bias voltage output circuit outputs the third preset bias voltage to control the second resistive variable device to switch from a high-resistance state to a low-resistance state, if data output has ended, it can output the same third preset bias voltage again to control the second resistive variable device to return to a high-resistance state. This application does not impose any special limitations on the specific value of the third preset bias voltage. The bias voltage output when restoring the high impedance state does not necessarily have to be consistent with the third preset bias voltage, as long as it is greater than the opening threshold of the second resistive switching device. In this embodiment, for ease of implementation, the same bias voltage is used in both application processes. This application does not impose any special limitations on the specific method by which the bias voltage output circuit determines the end of data output, etc., and the implementation method in the previous embodiment can be referred to.

[0089] Specifically, when the second resistive switching device is implemented using a unipolar resistive switching memory, the bias voltage output circuit needs to output a third preset bias voltage again at the end of the data output to control the second resistive switching device to return to a high-resistivity state so that the next data selection output process can proceed. This method is simpler and easier to implement, and helps to further reduce the cost and size of the entire data selection circuit.

[0090] In some embodiments, the bias voltage output circuit is a controller, and several general-purpose input / output ports of the controller are connected one-to-one with each of the data channels;

[0091] The controller is used to configure the pin level state of each of the general-purpose input / output ports according to the selected output of the input data, so as to control the second resistive switching device to switch the resistive state.

[0092] It is easy to understand that the bias voltage output circuit can be directly implemented using a controller. The selection signal in the data selection circuit is implemented using address selection codes. A high-level signal is used to select the data output and apply the corresponding bias voltage. Therefore, the controller only needs to set several output ports that correspond one-to-one with each data channel. When a general-purpose input / output port is high, the input data of its corresponding connected data channel is selected and output. At this time, the high level is directly applied as the bias voltage to the first terminal of the second resistive switching device, controlling the second resistive switching device to switch to a low-impedance state. This application does not specifically limit the specific type and implementation method of the controller; it can be directly implemented using a processor.

[0093] It should be noted that the bias voltage output circuit can also be configured with bias voltage output sub-circuits corresponding to each data channel. Each bias voltage output sub-circuit includes a switching device with one end connected to a preset power supply, and the other end of the switching device connected to the first end of the second resistive switching device in the corresponding data channel. When a data channel is selected as the target data channel, its corresponding connected switching device is turned on, applying the preset power supply to the first end of the second resistive switching device, thereby controlling the state switching of the second resistive switching device. In this way, the voltage value of the preset power supply is more flexible and has a wider range of applications.

[0094] Specifically, the bias voltage output circuit can be implemented directly using a controller. The controller's own power supply generates a high-level signal to control the state switching of the second resistive switching device. This is simple, effective, and easy to implement. In particular, it can be multiplexed with a processor that receives and outputs data, further reducing the cost and size of the entire data selection circuit.

[0095] See Figure 7 As shown, Figure 7 This is a flowchart illustrating a data selection method provided in an embodiment of the present invention. To address the aforementioned technical problems, this embodiment of the present invention also provides a data selection method applied to the data selection circuit described above, the data selection method comprising:

[0096] S11: Determine the target data channel corresponding to the target data to be output;

[0097] S12: Control the first and second resistive switching devices in the target data channel to switch to a low-resistance state so that the target data can pass through the low-resistance first and second resistive switching devices.

[0098] S13: Receive target data output from the target data channel.

[0099] Understandably, when data output and selection are required, the input of each data to be selected can be controlled to the respective data channel, thereby controlling the state switching of the first resistive switching device corresponding to the valid data. Then, after determining the target data to be output and the target data channel, the second resistive switching device in the target data channel can be controlled to switch to a low-resistance state by applying a bias voltage or other means. At this time, the selected valid data can be output through the low-resistance first resistive switching device and the low-resistance second resistive switching device, thereby receiving the required target data.

[0100] For a description of the features in the data selection method provided in the embodiments of the present invention, please refer to the relevant description of the embodiments of the data selection circuit, which will not be repeated here.

[0101] See Figure 8 As shown, Figure 8 This is a schematic diagram of a data selection device provided in an embodiment of the present invention; to solve the above-mentioned technical problems, an embodiment of the present invention also provides a data selection device, applied to the data selection circuit as described above, the data selection device comprising:

[0102] Target determination unit 11 is used to determine the target data channel corresponding to the target data to be output;

[0103] The control conduction unit 12 is used to control the first resistive switching device and the second resistive switching device in the target data channel to switch to a low-resistance state so that the target data can pass through the first resistive switching device and the second resistive switching device in a low-resistance state.

[0104] The data receiving unit 13 is used to receive target data output from the target data channel.

[0105] For a description of the features in the data selection device provided in the embodiments of the present invention, please refer to the relevant descriptions of the embodiments of the data selection circuit and the data selection method, which will not be repeated here.

[0106] See Figure 9 As shown, Figure 9 This is a schematic diagram of an electronic device provided in an embodiment of the present invention. To solve the above-mentioned technical problems, an embodiment of the present invention also provides an electronic device, comprising:

[0107] Memory 60 is used to store computer programs;

[0108] Processor 61 is configured to execute the computer program to implement the steps of the data selection method as described above.

[0109] The electronic devices provided in this embodiment may include, but are not limited to, smartphones, tablets, laptops, or desktop computers.

[0110] The processor 61 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 61 may be implemented using at least one hardware form selected from Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 61 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 61 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 61 may also include an Artificial Intelligence (AI) processor, which handles computational operations related to machine learning.

[0111] The memory 60 may include one or more computer-readable storage media, which may be non-transitory. The memory 60 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 60 is used to store at least the following computer program 601, which, after being loaded and executed by the processor 61, is capable of implementing the relevant steps of the data selection method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 60 may also include an operating system 602 and data 603, etc., and the storage method may be temporary storage or permanent storage. The operating system 602 may include Windows, Unix, Linux, etc. The data 603 may include, but is not limited to, the data in the data selection method.

[0112] In some embodiments, the electronic device may further include a display screen 62, an input / output interface 63, a communication interface 64, a power supply 65, and a communication bus 66.

[0113] Those skilled in the art will understand that Figure 9 The structures shown do not constitute a limitation on electronic devices and may include more or fewer components than those shown.

[0114] For a description of the features in the electronic device provided in the embodiments of the present invention, please refer to the relevant descriptions of the embodiments of the data selection circuit and the data selection method, which will not be repeated here.

[0115] It is understood that if the data selection method in the above embodiments is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the current technology, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drive, mobile hard drive, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, magnetic disk, or optical disk, and other media capable of storing program code.

[0116] Based on this, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the data selection method described above.

[0117] For a description of the features in the computer-readable storage medium provided in the embodiments of the present invention, please refer to the relevant descriptions of the embodiments of the data selection circuit and the data selection method, which will not be repeated here.

[0118] This invention also provides a computer program product, including a computer program / instruction that, when executed by a processor, implements the steps of the data selection method described in the above embodiments.

[0119] For a description of the features in the computer program product provided in the embodiments of the present invention, please refer to the relevant descriptions of the embodiments of the data selection circuit and the data selection method, which will not be repeated here.

[0120] The foregoing has provided a detailed description of a data selection circuit, method, apparatus, device, and storage medium provided by embodiments of the present invention. The various embodiments are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0121] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0122] The data selection circuit, method, apparatus, device, and storage medium provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A data selection circuit, characterized in that, include: Several data channels, the output ends of which are interconnected to output selected data; The input terminals of each of the data channels are used to receive different input data; For any given data channel, the data channel includes: The first resistive switching device has a first terminal for receiving input data. The first resistive switching device is used to switch to a low resistance state when the input data it receives is within a preset valid range, and to switch to a high resistance state when the input data it receives is not within the preset valid range. The second resistive switching device has a first end connected to the second end of the first resistive switching device, and the second end serves as the output end of the data channel. The second resistive switching device is used to switch to a low-resistance state when the input data connected to the corresponding first resistive switching device is selected for output, and to switch to a high-resistance state when the input data connected to the corresponding first resistive switching device is not selected for output. Both the first and second resistive switching devices are resistive switching memories; the data selection circuit further includes: A bias voltage output circuit, the bias voltage output circuit including a plurality of output terminals corresponding one-to-one with each of the data channels; For any output terminal of the bias voltage output circuit, the output terminal is connected to the second terminal of the first resistive switching device in the corresponding data channel and the first terminal of the second resistive switching device in the corresponding data channel, respectively. The bias voltage output circuit is used to output bias voltage to each of the data channels according to the selected output of the input data, so as to control the second resistive switching device to switch the resistive state. If the second resistive switching device is a bipolar resistive switching memory, the bias voltage output circuit controls the resistive state switching of the second resistive switching device by outputting a first preset bias voltage and a second preset bias voltage opposite to the first preset bias voltage. If the second resistive switching device is a unipolar resistive switching memory, the bias voltage output circuit controls the resistive state switching of the second resistive switching device by outputting a third preset bias voltage and outputting the third preset bias voltage again.

2. The data selection circuit as described in claim 1, characterized in that, The second resistive switching device is a non-volatile resistive switching memory, and the first resistive switching device is a volatile resistive switching memory.

3. The data selection circuit as described in claim 1, characterized in that, The second resistive switching device is a bipolar resistive switching memory; the initial state of the second resistive switching device is a high-resistivity state; The data selection circuit also includes: The processor has its input terminal connected to the output terminal of the data selection circuit and its output terminal connected to the input terminal of the bias voltage output circuit. It is used to receive the output data of the data selection circuit and output a data selection completion command to the bias voltage output circuit when it receives the output data of the data selection circuit. The bias voltage output circuit is specifically used to output a first preset bias voltage to the first terminal of the second resistive switching device in the target data channel when the input data of the target data channel is selected for output, so as to control the second resistive switching device in the target data channel to switch from a high resistance state to a low resistance state; when the data selection completion instruction is received, it outputs a second preset bias voltage to the first terminal of the second resistive switching device in the target data channel, so as to control the second resistive switching device in the target data channel to recover from a low resistance state to a high resistance state. The first preset bias voltage and the second preset bias voltage have opposite voltage directions.

4. The data selection circuit as described in claim 1, characterized in that, The second resistive switching device is a unipolar resistive switching memory; the initial state of the second resistive switching device is a high-resistivity state; The bias voltage output circuit is specifically used to output a third preset bias voltage to the first terminal of the second resistive switching device in the target data channel when the input data of the target data channel is selected for output, so as to control the second resistive switching device in the target data channel to switch from a high resistance state to a low resistance state. When the data selection completion instruction is received, a third preset bias voltage is output again to the first terminal of the second resistive switching device in the target data channel to control the second resistive switching device in the target data channel to recover from a low resistance state to a high resistance state.

5. The data selection circuit as described in any one of claims 1 to 4, characterized in that, The bias voltage output circuit is a controller, and several general-purpose input / output ports of the controller are connected one-to-one with each of the data channels. The controller is used to configure the pin level state of each of the general-purpose input / output ports according to the selected output of the input data, so as to control the second resistive switching device to switch the resistive state.

6. A data selection method, characterized in that, The data selection method, applied to the data selection circuit as described in any one of claims 1 to 5, comprises: Determine the target data channel corresponding to the target data to be output; The first and second resistive switching devices in the target data channel are switched to a low-resistance state so that the target data can pass through the low-resistance first and second resistive switching devices. Receive target data output from the target data channel.

7. A data selection device, characterized in that, The data selection device is applied to the data selection circuit as described in any one of claims 1 to 5, the data selection device comprising: The target determination unit is used to determine the target data channel corresponding to the target data that needs to be output. The control conduction unit is used to control the first resistive switching device and the second resistive switching device in the target data channel to switch to a low-resistance state so that the target data can pass through the first resistive switching device and the second resistive switching device in a low-resistance state. A data receiving unit is used to receive target data output from the target data channel.

8. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the data selection method as described in claim 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the data selection method as described in claim 6.

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