Mismatches self-calibration circuit for dynamic comparators

Abstract

The disclosure provides a mismatch self-calibration circuit for a dynamic comparator, which can be applied to the technical field of analog integrated circuit design. The circuit comprises: a first transistor array comprising a first weight transistor group and a first default transistor, the first weight transistor group comprising first weight transistors with a multi-bit gate width increasing in a predetermined rule; a second transistor array comprising a second weight transistor group and a second default transistor, the second weight transistor group comprising second weight transistors with a multi-bit gate width increasing in a predetermined rule; a first calibration logic module connected with the first transistor array, used for providing a first control signal to the first transistor array to control the first effective transconductance in the case that the mismatch polarity of the dynamic comparator is positive; and a second calibration logic module connected with the second transistor array, used for providing a second control signal to the second transistor array in the case that the mismatch polarity of the dynamic comparator is negative.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of analog integrated circuit design, and more particularly, to a self-calibration circuit for a dynamic comparator. BACKGROUND

[0002] The dynamic comparator is widely used in an analog to digital converter (ADC) due to low power consumption of the dynamic working characteristics. The performance of the dynamic comparator, such as speed, noise and offset, affects the performance of the entire ADC.

[0003] The offset is a main non-ideal characteristic of the dynamic comparator, which is equivalent to an offset voltage existing at the input end, and causes the shift of the characteristic curve of the ADC. Meanwhile, the offset also causes the reduction of the dynamic range of the input signal. For a multi-channel ADC or a time-interleaved ADC, the offset of the comparator is one of the main reasons for the mismatch between channels. Therefore, it is of great significance to optimize the dynamic comparator.

[0004] In the process of implementing the present disclosure, the inventors have found that at least the following technical problems exist in the related art: the calibration of the offset of the dynamic comparator reduces the working speed and stability of the circuit, introduces a large area of the circuit to increase power consumption, and affects the conversion accuracy of the ADC. SUMMARY

[0005] Therefore, the present disclosure provides a self-calibration circuit for a dynamic comparator.

[0006] One aspect of the present disclosure provides a self-calibration circuit for a dynamic comparator, comprising:

[0007] The first transistor array comprises a first weight transistor group and a first default transistor, the first weight transistor group comprises first weight transistors with gate widths of multiple bits and increasing in a predetermined rule, and the first transistor array is configured to calibrate the dynamic comparator according to a first effective transconductance corresponding to the first weight transistors, wherein the first default transistor is connected to a first input transistor of the dynamic comparator; the second transistor array comprises a second weight transistor group and a second default transistor, the second weight transistor group comprises second weight transistors with gate widths of multiple bits and increasing in a predetermined rule, and the second transistor array is configured to calibrate the dynamic comparator according to a second effective transconductance corresponding to the second weight transistors, wherein the second default transistor is connected to a second input transistor of the dynamic comparator; the first calibration logic module is connected to the first transistor array and configured to provide a first control signal to the first transistor array to control the first effective transconductance when the dynamic comparator has a positive offset polarity; the second calibration logic module is connected to the second transistor array and configured to provide a second control signal to the second transistor array to control the second effective transconductance when the dynamic comparator has a negative offset polarity; and the delay chain module comprises a plurality of inverters, and the delay chain module is configured to provide a clear time length to the first calibration logic module and the second calibration logic module before an input level of the dynamic comparator is stabilized.

[0008] According to an embodiment of the present disclosure, the first transistor array further comprises a first switch transistor connected to each first weight transistor, and the calibration of the dynamic comparator according to the first effective transconductance corresponding to the first weight transistors comprises: the plurality of first switch transistors control access of the plurality of first weight transistors according to the first control signal to determine a first target weight transistor from the first weight transistor group; and the first effective transconductance is determined according to a number of the first target weight transistors to calibrate the dynamic comparator.

[0009] According to an embodiment of the present disclosure, the first calibration logic circuit comprises a first counter comprising a same number of first count output terminals as the first switch transistors, and the provision of the first control signal to the first transistor array to control the first effective transconductance when the dynamic comparator has a positive offset polarity comprises: the first calibration logic circuit is enabled when the dynamic comparator has a positive offset polarity, and generates the first control signal corresponding to the first counter according to a clock signal of the dynamic comparator; and the plurality of first count output terminals transmit the first control signal to the plurality of first switch transistors to control the first effective transconductance.

[0010] According to an embodiment of the present disclosure, in the case that the mismatch polarity of the dynamic comparator is positive, the first calibration logic circuit is enabled, and a first control signal corresponding to the first counter is generated according to the clock signal of the dynamic comparator, which comprises: in the case that the mismatch polarity of the dynamic comparator is positive, the first calibration logic circuit is enabled; the first counter counts up according to a period corresponding to the clock signal, and a first count control word is accumulated; and the first control signal corresponding to the first counter is generated according to the first count control word.

[0011] According to an embodiment of the present disclosure, the second transistor array further comprises a second switch transistor connected to each second weight transistor, and the mismatch of the dynamic comparator is calibrated according to the second effective transconductance corresponding to the second weight transistor, which comprises: the plurality of second switch transistors control the breaking of the plurality of second weight transistors according to the second control signal, and determine a second target weight transistor from the second weight transistor group; and the second effective transconductance is determined according to the second target weight transistor, so as to calibrate the mismatch of the dynamic comparator.

[0012] According to an embodiment of the present disclosure, the second calibration logic circuit comprises a second counter, and the second counter comprises a second count output end same in number as the second switch transistor, and in the case that the mismatch polarity of the dynamic comparator is positive, the second control signal is provided to the second transistor array to control the second effective transconductance, which comprises: in the case that the mismatch polarity of the dynamic comparator is negative, the second calibration logic circuit is enabled, and the second control signal corresponding to the second counter is determined according to the clock signal of the dynamic comparator; and the plurality of second count output ends transmit the second control signal to the plurality of second switch transistors to control the second effective transconductance.

[0013] According to an embodiment of the present disclosure, in the case that the mismatch polarity of the dynamic comparator is negative, the second calibration logic circuit is enabled, and a second control signal corresponding to the second counter is generated according to the clock signal of the dynamic comparator, which comprises: in the case that the mismatch polarity of the dynamic comparator is positive, the second calibration logic circuit is enabled; the second counter counts up according to a period corresponding to the clock signal, and a second count control word is accumulated; and the second control signal corresponding to the second counter is generated according to the second count control word.

[0014] According to an embodiment of the present disclosure, the predetermined rule comprises: 2 raised to the power of n, 0≤n.

[0015] According to an embodiment of the present disclosure, the first weight transistor comprises a plurality of first weight sub-transistors, and the second weight transistor comprises a plurality of second weight sub-transistors; a gate length of each first weight sub-transistor in each first weight transistor is equal to a gate length of the first default transistor, and a gate length of each second weight sub-transistor in each second weight transistor is equal to a gate length of the second default transistor; a number of the first weight sub-transistors is sequentially increased by 2 raised to the power of m, and a number of the second weight sub-transistors is sequentially increased by 2 raised to the power of m, where 0≤m.

[0016] According to an embodiment of the present disclosure, the first count output end and the second count output end are provided with latches.

[0017] According to an embodiment of the present disclosure, by splitting a tail current tube in a traditional dynamic comparator into the first default transistor and the second default transistor and connecting them to the first transistor array and the second transistor array respectively, the first calibration logic module is configured to provide a first control signal to the first transistor array to control a first effective transconductance corresponding to the first weight transistor when a mismatch polarity of the dynamic comparator is positive, and correspondingly, the second calibration logic module is configured to provide a second control signal to the first transistor array to control a second effective transconductance corresponding to the second weight transistor when the mismatch polarity of the dynamic comparator is negative, so that the mismatch of the dynamic comparator is calibrated according to the adjustment of the effective transconductances corresponding to the two input transistors in a high-speed scenario, and the gate width of the weight transistor is increased in a predetermined manner, so that the calibration range of the mismatch is kept linearly increasing. Meanwhile, the delay chain module provides a zero-clearing duration for the two calibration logic modules, further improving the stability and calibration accuracy of the circuit. BRIEF DESCRIPTION OF DRAWINGS

[0018] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 A circuit diagram of a traditional two-stage dynamic comparator is schematically shown.

[0020] Figure 2 A schematic diagram of a mismatch self-calibration circuit for a dynamic comparator is schematically shown.

[0021] Figure 3 A circuit diagram of a mismatch self-calibration circuit for a dynamic comparator is schematically shown. DETAILED DESCRIPTION

[0022] Embodiments of the present disclosure will be described below with reference to the accompanying drawings. It should be understood, however, that the description is merely exemplary and is not intended to limit the scope of the present disclosure. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent, however, that one or more embodiments can be practiced without these specific details. In other instances, well-known structures and functions have not been described in detail in order to avoid obscuring the concepts of the present disclosure.

[0023] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to be limiting of the present disclosure. As used herein, the term "includes" and tautological expressions thereof, such as "including," means the inclusion of but not limited to, and is not meant to be construed as a functionally limiting the scope of the embodiments.

[0024] All terms used herein, including technical and scientific terms, have the meanings commonly understood by one of ordinary skill in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning that is consistent with the context of the specification, and should not be interpreted in an idealized or overly formal way.

[0025] In the case of using expressions similar to "at least one of A, B, and C, etc.", it should generally be interpreted to include any of one, all, or a combination thereof. In other words, the expression "at least one of A, B, and C, etc." should be interpreted to include one of A, B, or C; a combination of at least two of A, B, and C; or all of A, B, and C, etc.

[0026] In embodiments of the present disclosure, the collection, updating, analysis, processing, use, transmission, provision, disclosure, storage, etc. of data (for example, including but not limited to user personal information) are in accordance with relevant laws and regulations, are used for legal purposes, and do not violate public order and good customs. In particular, necessary measures are taken to prevent illegal access to user personal information data, and to maintain user personal information security, network security, and national security.

[0027] In embodiments of the present disclosure, the authorization or consent of the user is obtained before the user's personal information is acquired or collected.

[0028] In order to reduce the offset of the dynamic comparator, the related art often uses self-zeroing technology or chopper technology, but the circuits of these two offset technologies are simple in structure, but not suitable for high-frequency applications.

[0029] In addition, there are some methods of directly calibrating the dynamic comparator itself. The basic idea is to introduce controllable imbalance on both sides of the dynamic comparator to offset the mismatch. For example, by adjusting the differential load capacitance of the pre-amplification stage, but this way will increase the power consumption and reduce the comparison speed; for example, by using the substrate bias effect, by adjusting the substrate bias of the input pair transistor to change its threshold to offset the mismatch, but a special digital-to-analog converter is needed to generate the corresponding substrate bias voltage; for example, by adding an additional current path at the output of the pre-amplification stage, but this also needs an additional digital-to-analog converter to generate the analog quantity to introduce imbalance, and the introduced parasitic will also reduce the comparison speed.

[0030] To solve the technical problems of the prior art for calibrating the dynamic comparator, the imbalance caused by changing the effective transconductance of the transistor pair on both sides of the comparator can be used to complete the mismatch calibration, such as adjusting the effective transconductance of the input pair transistor of the first stage or the second stage, which can achieve better calibration performance. For the comparator, the mismatch of the input pair transistor of the first stage is usually the largest source of comparator mismatch, and the mismatch of the second stage is equivalent to the input end when divided by the gain of the first stage, so adjusting the effective transconductance of the first stage usually can obtain a larger calibration range. However, when designing a comparator applied to an analog-to-digital converter, more factors need to be considered. If the total size of the transistor group of the input pair is too large, it will cause the input pair parasitic capacitance to increase and the kickback noise to increase, which will affect the accuracy of the analog-to-digital converter. For the commonly used transconductance control transistor group with binary weight, in the case that the total size is limited to avoid affecting the accuracy of the analog-to-digital converter, the calibration range and accuracy will depend on and be limited by the minimum gate length supported by the process. Therefore, the calibration performance of the method of adjusting the effective transconductance of the input pair of the first stage or the second stage also has certain limitations.

[0031] Figure 1 A circuit diagram of a conventional two-stage dynamic comparator is schematically shown.

[0032] As Figure 1 shown, the circuit 100 includes a two-stage latch 110, a load transistor 120, a first input transistor 130, a second input transistor 140, and a tail current transistor 150. The effective transconductance of the first input transistor 130 and the second input transistor 140 is usually adjusted in the prior art.

[0033] In view of this, embodiments of the present disclosure provide an offset self-calibration circuit for a dynamic comparator, comprising: a first transistor array including a first weighted transistor group and a first default transistor, the first weighted transistor group including multiple first weighted transistors with gate widths increasing according to a predetermined rule, the first transistor array being used to perform offset calibration of the dynamic comparator based on a first effective transconductance corresponding to the first weighted transistor, wherein the first default transistor is connected to a first input transistor of the dynamic comparator; and a second transistor array including a second weighted transistor group and a second default transistor, the second weighted transistor group including multiple second weighted transistors with gate widths increasing according to a predetermined rule, the second transistor array being used to perform offset calibration of the dynamic comparator based on a first effective transconductance corresponding to the second weighted transistor. Two effective transconductances are used to perform offset calibration on the dynamic comparator. A second default transistor is connected to the second input transistor of the dynamic comparator. A first calibration logic module, connected to the first transistor array, provides a first control signal to the first transistor array to control the first effective transconductance when the offset polarity of the dynamic comparator is positive. A second calibration logic module, connected to the second transistor array, provides a second control signal to the second transistor array to control the second effective transconductance when the offset polarity of the dynamic comparator is negative. A delay chain module, including multiple inverters, provides a reset time to the first and second calibration logic modules before the input level of the dynamic comparator stabilizes.

[0034] To better understand the offset self-calibration circuit for a dynamic comparator in the embodiments of this disclosure, a 5-bit weighted transistor will be used as an example below. Figure 2 The self-calibration circuit is described in detail.

[0035] Figure 2 A schematic diagram of an offset self-calibration circuit for a dynamic comparator according to an embodiment of the present disclosure is shown.

[0036] like Figure 2 As shown, this embodiment 200 includes a two-stage latch 110, a load transistor 120, a first input transistor 130, a second input transistor 140, a first transistor array 210, a second transistor array 220, a first calibration logic module 230, a second calibration logic module 240, a delay chain module 250, and an output NAND gate 260.

[0037] According to an embodiment of the present disclosure, the first transistor array 210 includes a first weight transistor group 211 including first weight transistors 211_1 of which gate widths are increased in a predetermined rule, and a first default transistor 151, and the first transistor array 210 is configured to calibrate the offset of the dynamic comparator according to a first effective transconductance corresponding to the first weight transistors, wherein the first default transistor 141 is connected to the first input transistor 130 of the dynamic comparator.

[0038] According to an embodiment of the present disclosure, the second transistor array 220 includes a second weight transistor group 221 including second weight transistors 221_1 of which gate widths are increased in a predetermined rule, and a second default transistor 152, and the second transistor array 220 is configured to calibrate the offset of the dynamic comparator according to a second effective transconductance corresponding to the second weight transistors, wherein the second default transistor 142 is connected to the second input transistor 140 of the dynamic comparator.

[0039] According to an embodiment of the present disclosure, the first calibration logic module 230 includes a pin CLD and a pin CAL, and is connected to the first transistor array, and is configured to provide a first control signal to the first transistor array to control the first effective transconductance when the offset polarity of the dynamic comparator is positive. The second calibration logic module 240 includes a pin CLD and a pin CAL, and is connected to the second transistor array, and is configured to provide a second control signal to the second transistor array to control the second effective transconductance when the offset polarity of the dynamic comparator is negative.

[0040] According to an embodiment of the present disclosure, the first default transistor and the second default transistor are always connected to the circuit, and the first weight transistors and the second weight transistors respectively adjust the number of connections according to the first control signal and the second control signal to change the first effective transconductance and the second effective transconductance, thereby calibrating the offset of the dynamic comparator.

[0041] According to an embodiment of the present disclosure, the delay chain module 250 includes a plurality of inverters 251, and the delay chain module 250 is connected to the pins CLD and CAL of the first calibration logic module and the second calibration logic module at the same time in order to reduce the circuit area.

[0042] According to an embodiment of the present disclosure, all the transistors in the first transistor array and the second transistor array are NMOS (N-Metal-Oxide-Semiconductor) transistors.

[0043] According to an embodiment of the present disclosure, compared with the above Figure 1Compared with the traditional two-stage dynamic comparator, the embodiment 200 splits the tail current tube 150 into a first default transistor and a second default transistor.

[0044] According to the embodiment of the present disclosure, to reduce the power consumption of the circuit, the first-stage pre-amplifier of the dynamic comparator adopts dynamic amplification, i.e., only works at the clock jump moment of the dynamic comparator, thus almost has no static power consumption at the rest time, and is suitable for application in low-power number / analog converters such as successive approximation register (SAR) analog-to-digital converters.

[0045] According to the embodiment of the present disclosure, the first default transistor and the second default transistor have the characteristic of cross-region operation when pre-amplifying, and the working region thereof is also affected by the gate voltage of the first input transistor and the second input transistor, i.e., the input voltage of the dynamic comparator. To make the calibration range of the offset cover the distribution condition of the larger offset of the dynamic comparator as much as possible, the standard deviation of the offset distribution of the dynamic comparator itself needs to be regulated, i.e., the first input transistor and the second input transistor with a proper size can be selected, and the length and width of the gate can be increased in proportion under the condition of keeping the width-length ratio unchanged.

[0046] According to the embodiment of the present disclosure, the calibration range of the offset depends on the maximum variation of the effective transconductance of the first transistor array and the second transistor array, thus the minimum calibration step depends on the gate width of the first weight transistor. To obtain higher calibration accuracy, the gate width of the first weight transistor can be set as the minimum gate width supported by the process.

[0047] According to the embodiment of the present disclosure, by splitting the tail current tube in the traditional dynamic comparator into the first default transistor and the second default transistor and connecting them to the first transistor array and the second transistor array respectively, the first calibration logic module is used to provide the first control signal to the first transistor array to control the first effective transconductance corresponding to the first weight transistor in the case that the offset polarity of the dynamic comparator is positive, and correspondingly, the second calibration logic module is used to provide the second control signal to the first transistor array to control the second effective transconductance corresponding to the second weight transistor in the case that the offset polarity of the dynamic comparator is negative, so as to realize the calibration of the offset of the dynamic comparator by adjusting the effective transconductance corresponding to the two input transistors in the high-speed scenario, and the gate width of the weight transistor is increased in a predetermined rule, so that the calibration range of the offset keeps linearly increasing. Meanwhile, the delay chain module provides the clear time length for the two calibration logic modules, further improving the stability of the circuit and the accuracy of the calibration.

[0048] According to the embodiment of the present disclosure, the predetermined rule includes: the n-th power of 2, 0≤n.

[0049] For example, taking a five-bit weight transistor as an example, the gate width of the first bit of the first weight transistor is W, the gate width of the second bit of the first weight transistor is 2W, the gate width of the third bit of the first weight transistor is 4W, the gate width of the fourth bit of the first weight transistor is 8W, and the gate width of the fifth bit of the first weight transistor is 16W; the gate width of the first bit of the second weight transistor is W, the gate width of the second bit of the second weight transistor is 2W, the gate width of the third bit of the second weight transistor is 4W, the gate width of the fourth bit of the second weight transistor is 8W, and the gate width of the fifth bit of the second weight transistor is 16W.

[0050] According to an embodiment of the present disclosure, the gate length of all bits of the first weight transistor is equal to the gate length of the first default transistor, and the gate length of all bits of the second weight transistor is equal to the gate length of the second default transistor.

[0051] According to an embodiment of the present disclosure, the first weight transistor includes a plurality of first weight sub-transistors, and the second weight transistor includes a plurality of second weight sub-transistors; the gate length of each first weight sub-transistor in each bit of the first weight transistor is equal to the gate length of the first default transistor, and the gate length of each second weight sub-transistor in each bit of the second weight transistor is equal to the gate length of the second default transistor; the number of the first weight sub-transistors is sequentially increased by 2 raised to the power of m, the number of the second weight sub-transistors is sequentially increased by 2 raised to the power of m, and 0≤m.

[0052] According to an embodiment of the present disclosure, each first weight sub-transistor is of the same size, and each bit of the first weight transistor can be formed by connecting a plurality of first weight sub-transistors in parallel; the number of the connected first weight sub-transistors is sequentially increased by 2 raised to the power of m to obtain each bit of the first weight transistor which is sequentially increased according to a predetermined rule.

[0053] According to an embodiment of the present disclosure, each second weight sub-transistor is of the same size, and each bit of the second weight transistor can be formed by connecting a plurality of second weight sub-transistors in parallel; the number of the connected first weight sub-transistors is sequentially increased by 2 raised to the power of m to obtain each bit of the first weight transistor which is sequentially increased according to a predetermined rule.

[0054] According to an embodiment of the present disclosure, by increasing the gate width of the first / second weight transistor at a constant ratio, the corresponding first / second effective transconductance changes linearly, the range of the offset calibration is effectively controlled, and the offset calibration accuracy of the dynamic comparator is improved.

[0055] According to an embodiment of the present disclosure, the first transistor array further comprises a first switch transistor connected to each first weight transistor, and the first effective transconductance is determined according to a first effective transconductance corresponding to the first weight transistor, so as to calibrate the offset of the dynamic comparator, which comprises: a plurality of first switch transistors control the access of the plurality of first weight transistors according to a first control signal, and determine a first target weight transistor from the first weight transistor group; and the first effective transconductance is determined according to the number of the first target weight transistor, so as to calibrate the offset of the dynamic comparator.

[0056] According to an embodiment of the present disclosure, the plurality of first switch transistors are turned on according to the first control signal, the first weight transistor corresponding to the turned-on first switch transistor is accessed to the circuit, and is determined as the first target weight transistor. The first effective transconductance is adjusted according to the number of the first target weight transistor accessed to the circuit, so as to calibrate the positive offset of the dynamic comparator.

[0057] According to an embodiment of the present disclosure, the second transistor array further comprises a second switch transistor connected to each second weight transistor, and the second effective transconductance is determined according to a second effective transconductance corresponding to the second weight transistor, so as to calibrate the offset of the dynamic comparator, which comprises: a plurality of second switch transistors control the disconnection of the plurality of second weight transistors according to a second control signal, and determine a second target weight transistor from the second weight transistor group; and the second effective transconductance is determined according to the second target weight transistor, so as to calibrate the offset of the dynamic comparator.

[0058] According to an embodiment of the present disclosure, the plurality of second switch transistors are turned on according to the second control signal, the second weight transistor corresponding to the turned-on second switch transistor is accessed to the circuit, and is determined as the second target weight transistor. The second effective transconductance is adjusted according to the number of the second target weight transistor accessed to the circuit, so as to calibrate the negative offset of the dynamic comparator.

[0059] According to an embodiment of the present disclosure, the number of weight transistors accessed through the first / second switch transistor can be accurately adjusted to adjust the first / second effective transconductance, so as to calibrate the offset of the dynamic comparator. In the high-speed ADC application scenario, the performance of the comparator is improved while the low power consumption is maintained.

[0060] According to an embodiment of the present disclosure, the first calibration logic circuit comprises a first counter, the first counter comprises a same number of first counting output terminals as the first switch transistors, and the first calibration logic circuit is enabled when the offset polarity of the dynamic comparator is positive, and generates a first control signal corresponding to the first counter according to a clock signal of the dynamic comparator, and the first control signal is transmitted to the first switch transistors through the first counting output terminals to control the first effective transconductance.

[0061] According to an embodiment of the present disclosure, the delay chain module is configured to provide a clear time length to the first counter in the first calibration logic module, so that the calibration is performed after the levels of the two input terminals of the dynamic comparator are stabilized.

[0062] According to an embodiment of the present disclosure, when the offset polarity of the dynamic comparator is positive, the first calibration logic circuit is enabled, the second calibration logic circuit cannot be enabled, the first counter generates the first control signal to control the switching state of the first switch transistor, and then controls the number of bits of the first weight transistor connected, and the first transistor array forms a source feedback for the first input transistor and the second input transistor, and with the increase of the first effective transconductance and the decrease of the on-resistance, the instantaneous discharge current of the parasitic capacitance of the first stage output node Vop of the dynamic comparator increases, and the Vop discharge speed gradually catches up with the Von discharge speed, and the offset calibration of the dynamic comparator is completed.

[0063] According to an embodiment of the present disclosure, when the offset polarity of the dynamic comparator is positive, the first calibration logic circuit is enabled, and a first control signal corresponding to the first counter is generated according to a clock signal of the dynamic comparator, and the first calibration logic circuit is enabled when the offset polarity of the dynamic comparator is positive, the first counter counts up according to a period corresponding to the clock signal, and a first counting control word is accumulated, and the first control signal corresponding to the first counter is generated according to the first counting control word.

[0064] According to an embodiment of the present disclosure, the flip-flop in the first counter can be designed in a falling edge trigger mode. When the calibration is completed, the first counter stops counting up.

[0065] According to an embodiment of the present disclosure, when the offset polarity of the dynamic comparator is positive, the output signal Von=0 and Vop=1, and the comparison result RDY is high.

[0066] According to an embodiment of the present disclosure, the second calibration logic circuit comprises a second counter, the second counter comprises a same number of second counting output terminals as the second switch transistors, and the second calibration logic circuit is enabled in the case that the offset polarity of the dynamic comparator is negative, and the second calibration logic circuit generates the second control signal corresponding to the second counter according to the clock signal of the dynamic comparator.

[0067] According to an embodiment of the present disclosure, the delay chain module is configured to provide a clear time length to the second counter in the second calibration logic module, so that the calibration is performed after the levels of the two input terminals of the dynamic comparator are stabilized.

[0068] According to an embodiment of the present disclosure, the second calibration logic circuit is enabled in the case that the offset polarity of the dynamic comparator is negative, the second calibration logic circuit cannot be enabled, the second counter generates the second control signal to control the switching state of the second switch transistor, thereby controlling the number of bits of the accessed second weight transistor, and the second transistor array forms a source feedback with the first input transistor and the second input transistor.

[0069] According to an embodiment of the present disclosure, the second calibration logic circuit is enabled in the case that the offset polarity of the dynamic comparator is negative, and the second calibration logic circuit generates the second control signal corresponding to the second counter according to the clock signal of the dynamic comparator, comprising: the second calibration logic circuit is enabled in the case that the offset polarity of the dynamic comparator is positive; the second counter counts up according to the period corresponding to the clock signal, and accumulates to obtain a second counting control word; and the second calibration logic circuit generates the second control signal corresponding to the second counter according to the second counting control word.

[0070] According to an embodiment of the present disclosure, the second counter counts up according to the period corresponding to the clock signal, and accumulates to obtain a second counting control word, and the working principle of the second counter is similar to that of the first counter, which is not described here.

[0071] According to an embodiment of the present disclosure, the delay chain module first generates a clear signal to provide a clear time length for the first calibration logic module and the second calibration logic module, so that the control words output by the first counter and the second counter are cleared, the first switch transistor and the second transistor are all turned off, and only the first default transistor and the second default transistor are accessed to the circuit. At this time, due to the influence of the mismatch between the two sides of the circuit, the input transistor with a larger gate voltage has a higher conduction degree and a larger current, and the discharge speed is faster, so that the output signal in the effective period is high on one end and low on the other end, indicating the offset polarity.

[0072] According to embodiments of this disclosure, latches are provided at the first and second count output terminals.

[0073] According to embodiments of this disclosure, when the triggers in the first or second counter are TSPC (TrueSingle Phase Clock) triggers, there is a possibility that the first / second control word cannot be maintained for a long time after calibration due to node leakage. Therefore, a latch can be added to each output node of the first or second counter to ensure that the first / second control word remains unchanged during the conversion of the analog-to-digital converter.

[0074] According to embodiments of this disclosure, the first calibration logic circuit and the second calibration logic circuit further include multiple logic gates, which will be described below. Figure 3 The offset self-calibration circuit used in the dynamic comparator is further explained.

[0075] Figure 3 A circuit diagram of an offset self-calibration circuit for a dynamic comparator according to an embodiment of the present disclosure is illustrated schematically.

[0076] like Figure 3 As shown, embodiment 300 includes a two-stage latch 110, a load transistor 120, a first input transistor 130, a second input transistor 140, a first transistor array 210, a second transistor array 220, a first calibration logic module 230, a second calibration logic module 240, a delay chain module 250, and an output NAND gate 260.

[0077] The first calibration logic module 230 includes a first counter 231, a first positive calibration logic gate 232, a second positive calibration logic gate 233, a third positive calibration logic gate 234, a fourth positive calibration logic gate 235, a fifth positive calibration logic gate 236, and a sixth positive calibration logic gate 237.

[0078] The second calibration logic module 240 includes a second counter 241, a first positive calibration logic gate 242, a second positive calibration logic gate 243, a third positive calibration logic gate 244, a fourth positive calibration logic gate 245, a fifth positive calibration logic gate 246, and a sixth positive calibration logic gate 247.

[0079] Taking the positive polarity as an example, when the enable signal CAL is changed from low to high, the circuit enters the calibration mode, the analog-digital converter stops the analog-digital conversion work, and the clock of the dynamic comparator continues to work, and the two input transistors are connected to the common-mode voltage Vcm. When the comparison result RDY is high, the output signal Von=0 and Vop=1, at this time, the count values of the first counter and the second counter are both 0, the CNTR and CNTL signals output by the first calibration logic module and the second calibration logic module are both high, and correspondingly, CAL, CNT, RDY and Vop are all high, so that the first counter is enabled, and the first counter counts up according to the period corresponding to the clock signal, and the control word is increased by 1 every clock period, and the second count control word is accumulated.

[0080] According to the embodiment of the present disclosure, after the first counter starts counting, the CNTR signal changes from 1 to 0, the second counter cannot be enabled, and the second control word is always kept as 0.

[0081] According to the embodiment of the present disclosure, when the discharge speed generated in the calibration process changes the output polarity of the dynamic comparator, at this time, the output signal is Von=1 and Vop=0, the first counter is no longer enabled in this calibration period, and the current first control word is kept, and the calibration is completed.

[0082] According to the embodiment of the present disclosure, after the calibration is completed, the enable signal is set to 0, the analog-digital converter starts conversion, the second control word of the second counter remains 0 unchanged, and the first control word after the counting is stopped is confirmed as the calibration value.

[0083] According to the embodiment of the present disclosure, the case that the offset polarity is negative is similar to the above process, and the second control word output by the first calibration logic module in the calibration period will be increased until the output signal of the dynamic comparator changes to Von=0 and Vop=1.

[0084] According to the embodiment of the present disclosure, in order to ensure that the calibration range is large enough, the effective period of the enable signal CAL needs to be greater than the maximum calibration period, and for the xth bit of the first counter, the effective period is the zero-clearing time provided by the delay module plus 2 x times of the clock period of the dynamic comparator.

[0085] The circuit diagrams and block diagrams in the drawings illustrate the architectural, functional, and operational aspects of possible implementations of circuits according to various embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams can represent a module or portion of a circuit that includes one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks noted in succession can, in fact, be executed substantially concurrently or in the reverse order, depending on the functionality involved. It will also be noted that each block in the flowchart or circuit diagram, and combinations of blocks in the flowchart or circuit diagram, can be implemented by dedicated hardware-based systems that perform the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions. Those skilled in the art will recognize that the features recited in the various embodiments of the present disclosure can be combined and / or integrated in a variety of ways, even if such combinations or integrations are not expressly contemplated in the present disclosure. In particular, the features recited in the various embodiments of the present disclosure can be combined and / or integrated in a variety of ways without departing from the spirit and teachings of the present disclosure. All such combinations and / or integrations are within the scope of the present disclosure.

[0086] The embodiments of the present disclosure have been described above. However, these embodiments are merely for illustrative purposes, and are not intended to limit the scope of the present disclosure. Although each of the embodiments is described above separately, this does not mean that the measures in each of the embodiments cannot be used advantageously in combination. Various alternatives and modifications can be made to the embodiments of the present disclosure by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications shall fall within the scope of the present disclosure.

Claims

1. An offset self-calibration circuit for a dynamic comparator, comprising: a first transistor array comprising a first weight transistor group and a first default transistor, the first weight transistor group comprising first weight transistors of which gate widths are increased in a predetermined rule, the first transistor array being configured to calibrate an offset of a dynamic comparator according to a first effective transconductance corresponding to the first weight transistors, wherein the first default transistor is connected to a first input transistor of the dynamic comparator; a second transistor array comprising a second weight transistor group and a second default transistor, the second weight transistor group comprising second weight transistors of which gate widths are increased in the predetermined rule, the second transistor array being configured to calibrate an offset of a dynamic comparator according to a second effective transconductance corresponding to the second weight transistors, wherein the second default transistor is connected to a second input transistor of the dynamic comparator; a first calibration logic module connected to the first transistor array, configured to provide a first control signal to the first transistor array to control the first effective transconductance when a polarity of the offset of the dynamic comparator is positive; a second calibration logic module connected to the second transistor array, configured to provide a second control signal to the second transistor array to control the second effective transconductance when the polarity of the offset of the dynamic comparator is negative; a delay chain module comprising a plurality of inverters, the delay chain module being configured to provide a clear time duration to the first calibration logic module and the second calibration logic module before input levels of the dynamic comparator are stable.

2. The circuit of claim 1, wherein, The first transistor array further comprises a first switch transistor connected to each of the first weight transistors, and the calibrating the offset of the dynamic comparator according to the first effective transconductance corresponding to the first weight transistors comprises: the plurality of the first switch transistors are configured to control access of the plurality of the first weight transistors to determine a first target weight transistor from the first weight transistor group according to the first control signal; the first effective transconductance is determined according to a number of the first target weight transistors to calibrate the offset of the dynamic comparator.

3. The circuit of claim 2, wherein, The first calibration logic module comprises a first counter comprising a same number of first count output terminals as the first switch transistors, and the providing the first control signal to the first transistor array to control the first effective transconductance when the polarity of the offset of the dynamic comparator is positive comprises: the first calibration logic module is enabled and generates the first control signal corresponding to the first counter according to a clock signal of the dynamic comparator when the polarity of the offset of the dynamic comparator is positive; the plurality of the first count output terminals transmit the first control signal to the plurality of the first switch transistors to control the first effective transconductance.

4. The circuit of claim 3, wherein, The first calibration logic module is enabled and generates a first control signal corresponding to the first counter according to a clock signal of the dynamic comparator when a positive polarity of the dynamic comparator is unbalanced. The first calibration logic module is enabled when a positive polarity of the dynamic comparator is unbalanced. The first counter counts up according to a period corresponding to the clock signal, and a first count control word is accumulated. A first control signal corresponding to the first counter is generated according to the first count control word.

5. The circuit of claim 3, wherein, The second transistor array further comprises a second switch transistor connected to each of the second weight transistors, and the second effective transconductance corresponding to the second weight transistors is used to calibrate the dynamic comparator. The second switch transistors control the opening of the second weight transistors according to the second control signal, and a second target weight transistor is determined from the second weight transistor group. The second effective transconductance is determined according to the second target weight transistor to calibrate the dynamic comparator.

6. The circuit of claim 5, wherein, The second calibration logic module comprises a second counter, and the second counter comprises a second count output end corresponding to the number of the second switch transistors. The second calibration logic module is enabled and generates a second control signal corresponding to the second counter according to a clock signal of the dynamic comparator when a negative polarity of the dynamic comparator is unbalanced. The second calibration logic module is enabled when a positive polarity of the dynamic comparator is unbalanced.

7. The circuit of claim 6, wherein, The second counter counts up according to a period corresponding to the clock signal, and a second count control word is accumulated. A first control signal corresponding to the first counter is generated according to the first count control word. The predetermined rule comprises: 2 raised to the power of n, 0≤n. The first weight transistor comprises a plurality of first weight sub-transistors, and the second weight transistor comprises a plurality of second weight sub-transistors; a gate length of each of the first weight sub-transistors in each first weight transistor is equal to a gate length of the first default transistor, and a gate length of each of the second weight sub-transistors in each second weight transistor is equal to a gate length of the second default transistor; the number of the first weight sub-transistors increases by 2 raised to the power of m in turn, and the number of the second weight sub-transistors increases by 2 raised to the power of m in turn, 0≤m.

8. The circuit of claim 1, wherein, ​ 9. The circuit of claim 1, wherein, ​ 10. The circuit of claim 6, wherein, The first count output and the second count output are provided with latches.

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