Low-delay PAC code Fano decoder design method and storage medium
By updating the decoding status and path update mechanism in the PAC code Fano decoder, the problem of high decoding delay of the PAC code Fano decoder in the prior art is solved, and a low-latency and efficient decoding effect is achieved.
Patent Information
- Application Number
- CN202411588835.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-08
- Publication Date
- 2025-03-14
AI Technical Summary
The existing PAC code Fano decoding is difficult to achieve low latency for decoding while improving the hardware implementation efficiency.
By receiving the LLR data of the channel and updating the decoding state, decoding the LLR data according to the updated decoding state, obtaining the internal polarization decoding results and external convolution results, and path updates are performed based on the current decoding type and external convolution results to determine whether forward decoding or node backtracking continues.
On the premise of ensuring low hardware complexity, the backtracking LLR data recovery process is optimized, the decoding delay is reduced, and the low-latency and efficient decoding of the PAC Fano decoder is realized.
Smart Images
Figure CN119628658A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of 5G mobile communications, and in particular to a low-latency PAC code Fano decoder design method and storage medium. Background Art
[0002] Since the concept of channel polarization was proposed, polarization code has received widespread attention as the only coding method that has been strictly mathematically proven to have a channel capacity that can reach the Shannon limit. In order to solve the problem that the current mainstream channel coding algorithm does not perform well under shorter code lengths, the existing technology proposes PAC code based on polarization code through external cascade convolutional code. This algorithm can use frozen bits as check codes to improve the decoding performance under short code lengths.
[0003] Currently, polarization codes have been used in control channel coding schemes in 5G enhanced mobile broadband (eMBB) application scenarios. Polarization-Adjusted Convolutional (PAC) codes have unique research value in the upcoming 6G communications.
[0004] Algorithmically, PAC code Fano decoding is an algorithm with variable complexity. It searches for the optimal path by moving on the decoding tree. When searching for the optimal path, node backtracking is required. This process will increase the decoding delay to a certain extent. Summary of the invention
[0005] The purpose of the present invention is to provide a low-latency PAC code Fano decoder design method in order to solve the problem that the existing PAC code Fano decoding is difficult to achieve low-latency decoding while improving the hardware implementation efficiency.
[0006] The above-mentioned purpose of the present application is achieved through the following technical solutions: S1: Receive the LLR data of the channel and update the decoding status; S2: Decode the LLR data according to the updated decoding state to obtain a decoded LLR; S3: Obtain the internal polarization decoding result and the external convolution result according to the decoded LLR; S4: Update the path according to the type of the current node to be decoded and the external convolution result, and determine whether to continue the forward decoding of the next node. The specific steps are as follows: If the forward decoding conditions are met, the forward decoding of the next node is continued according to the internal polarization decoding result; If the forward decoding condition is not met, the node is backtracked, the intermediate data is restored to the backtracking node, and the forward decoding of the next node is continued from the backtracking node; S5: Forward decoding to the last node of the decoding tree, end decoding and output the decoding result.
[0007] Optionally, the decoder includes: a control module, an LLR storage module, a data processing PE module, a partial sum calculation module and a path processing module; the LLR storage module includes: an LLR_RAM unit and a data splicing unit.
[0008] Optionally, step S1 includes: S11: the LLR storage module stores the received LLR data in a preset order; S12: After receiving a set of LLR data, the decoding state is updated through the control module; the decoding state includes: a decoding bit index and an LLR calculation index; The decoding bit index represents the natural order index of the current node to be decoded; the LLR calculation index includes: the starting position of the log-likelihood ratio calculation and the position information of the intermediate process of the calculation; S13: Determine the LLR calculation index by decoding the bit index; S14: Control the access of LLR data and the data splicing in the intermediate process of calculation according to the LLR calculation index.
[0009] Optionally, step S2 includes: S21: In the first decoding cycle CC0, according to the LLR calculation index, read the LLR data at the starting position and the LLR data at the second position in a group of LLR data; Input the LLR data at the starting position into the data processing PE module to obtain the first PE calculation result; The first PE calculation result is combined with the LLR calculation index through the data splicing unit to obtain a first splicing result; the first splicing result is stored in the cache register REG in the data splicing unit; S22: In the second decoding cycle CC1, the first splicing result in the cache register REG is stored in the LLR_RAM unit; Input the first splicing result into the data processing PE module to obtain the second PE calculation result; According to the updated LLR calculation index, read the LLR data of the third position; The second PE calculation result is spliced with the LLR data at the third position through the data splicing unit in combination with the updated LLR calculation index to obtain a second splicing result; the second splicing result is stored in the cache register REG; S23: Repeat step S22 until all calculations of a set of LLR data are completed to obtain decoded LLRs.
[0010] Optionally, step S3 includes: The path processing module includes: a decoding processing unit, a convolution transformation unit, a path information storage unit and a metric updating unit.
[0011] Optionally, step S3 further includes: The decoding LLR is processed by the decoding processing unit to obtain an internal polarization decoding result; The internal polar decoding results are transmitted to the part and calculation module, and the convolution transformation unit respectively; Updating the partial sum required for polar code decoding through the partial sum calculation module; The decoding result is processed by the convolution transformation module to obtain the external convolution result.
[0012] Optionally, step S4 includes: S41: The current node type to be decoded includes: frozen bit and information bit; If the type of the current node to be decoded is a frozen bit and the external convolution result is 0, the path metric value will not be changed; If the current node type to be decoded is a frozen bit and the external convolution result is 1, it means that the internal polarization decoding result does not match the frozen bit, then the path metric value is updated according to the decoded LLR; S42: If the type of the current node to be decoded is an information bit, calculate the path metric values of the two branch nodes under the current node to be decoded in the decoding tree: If any path metric value is greater than the preset threshold T, the decoding goes to the node with the largest path metric value; If any path metric value is not greater than the preset threshold T, the node will be backtracked as follows: When entering the node backtracking, determine whether the current node to be decoded meets the forward decoding conditions. If so, perform forward decoding of the next node. If not, update the preset threshold T and continue backtracking until the current node to be decoded meets the forward decoding conditions and continue forward decoding of the next node.
[0013] A computer-readable storage medium stores instructions. When the instructions are executed, a method for designing a low-latency PAC code Fano decoder is executed.
[0014] The beneficial effects of the technical solution provided by this application are: The control information necessary for decoding is provided by the control module to control the normal operation of each module. All LLR data to be calculated are stored in the LLR storage module. The LLR data is subjected to two operations, F and G, through the data processing module, and the output decoding results are stored in the LLR storage module, and the decoded LLR in the decoding stage is output to the path processing module. The partial sum calculation module updates the partial sum network according to the internal polarization decoding result or the backtracking result provided by the path processing module to provide the partial sum required for the G operation, and stores the updated partial sum in the path processing module. The path processing module determines whether backtracking is required according to the current internal polarization decoding result, and saves the key data necessary for backtracking. The present invention optimizes the LLR data recovery process during backtracking to reduce the decoding delay by changing the data storage and update mode of the PAC code Fano decoder while ensuring low hardware complexity, thereby realizing low-latency and efficient decoding of the PAC code Fano decoder and solving the problem of high decoding delay of the polarization adjustment convolutional code Fano decoder. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The present application will be further described below with reference to the accompanying drawings and embodiments, in which: Figure 1 is a structural block diagram of a PAC code Fano decoder in an embodiment of the present application; Figure 2 is a block diagram of the internal structure of the LLR storage module in an embodiment of the present application; Figure 3 is a block diagram of the internal structure of the data processing PE module in the embodiment of the present application; Figure 4 is a block diagram of the internal structure of the path processing module in the embodiment of the present application; Figure 5 It is a block diagram of the internal structure of the part and the calculation module in the embodiment of the present application; Figure 6 It is an internal structure diagram of a single PE in an embodiment of the present application; Figure 7 It is a schematic diagram of LLR_RAM internal data storage in an embodiment of the present application; Figure 8 Schematic diagram of the LLR calculation data reading and writing process in an embodiment of the present application; Fig. 9 is a logic flow chart of the Fano decoding node search in the embodiment of the present application; Fig.10 This is a Fano decoding node search example in the embodiment of the present application. DETAILED DESCRIPTION
[0016] In order to have a clearer understanding of the technical features, purposes and effects of the present application, the specific implementation methods of the present application are now described in detail with reference to the accompanying drawings.
[0017] Embodiments of the present application provide a low-latency PAC code Fano decoder design method and storage medium.
[0018] Please refer to Figure 1 , Figure 1 : is a structural block diagram of a low-latency PAC code Fano decoder design method in an embodiment of the present application, including: S1: Receive the LLR data of the channel and update the decoding status; Specifically, LLR data (Log-Likelihood Ratio).
[0019] S2: Decode the LLR data according to the updated decoding state to obtain a decoded LLR; S3: Obtain the internal polarization decoding result and the external convolution result according to the decoded LLR; S4: Update the path according to the type of the current node to be decoded and the external convolution result, and determine whether to continue the forward decoding of the next node. The specific steps are as follows: If the forward decoding conditions are met, the forward decoding of the next node is continued according to the internal polarization decoding result; If the forward decoding condition is not met, the node is backtracked, the intermediate data is restored to the backtracking node, and the forward decoding of the next node is continued from the backtracking node; S5: Forward decoding to the last node of the decoding tree, end decoding and output the decoding result.
[0020] The decoder comprises: a control module, an LLR storage module, a data processing PE module, a partial sum calculation module and a path processing module; the LLR storage module comprises: an LLR_RAM unit and a data splicing unit.
[0021] Step S1 includes: S11: the LLR storage module stores the received LLR data in a preset order; As an exemplary embodiment, the LLR (LLR data) transmitted by the channel is stored in Figure 2 In the LLR_RAM of the LLR storage module, N represents the decoding sequence code length, Q represents the number of quantization bits of LLR, and LLR_RAM is a true dual-port RAM. The storage method of its internal data is as follows: Figure 7 , the shaded part is an example when N = 8. After completing the reception of the LLR data of all channels, the decoder's decoding enable signal is pulled high.
[0022] S12: After receiving a set of LLR data, the decoding state is updated through the control module; the decoding state includes: a decoding bit index and an LLR calculation index; The decoding bit index represents the natural order index of the current node to be decoded; the LLR calculation index includes: the starting position of the log-likelihood ratio calculation and the position information of the intermediate process of the calculation; S13: Determine the LLR calculation index by decoding the bit index; S14: Control the access of LLR data and the data splicing in the intermediate process of calculation according to the LLR calculation index.
[0023] Specifically, the starting position calculation function of LLR data as follows:
[0024] in is the decoding index, The binary representation of ; express Each bit represented by a binary digit; for The subscript indicates the index of the bit; A decimal number representing the natural order of the current decoding node; Expressing satisfaction =1 condition minimum value among all indexes j; express If the decoding length is 128, x is .
[0025] Step S2 includes: S21: In the first decoding cycle CC0, according to the LLR calculation index, read the LLR data at the starting position and the LLR data at the second position in a group of LLR data; Input the LLR data at the starting position into the data processing PE module to obtain the first PE calculation result; The first PE calculation result is combined with the LLR calculation index through the data splicing unit to obtain a first splicing result; the first splicing result is stored in the cache register REG in the data splicing unit; As an exemplary embodiment, decoding begins after the channel transmission LLR is received, such as Figure 8 As shown, in the decoding cycle CC0, two sets of data at the starting and second positions are read according to the LLR calculation index, the data at the starting position is used as the calculation input of PE, and after obtaining the first PE calculation result, it is spliced with the data at the second position, and the spliced result is stored in the cache register REG.
[0026] As an exemplary embodiment, the data processing (PEs) module is responsible for performing operations on the LLR data, such as Figure 3 As shown, the module consists of N / 2 PE units, each of which inputs two LLRs and a partial sum. Figure 6 It is the internal logic diagram of PE. PE processes LLR data by separating sign and amplitude. The input L1_in and L2_in are the input LLR, and PS_in is the input partial sum. The numerical processing module has the functions of full adder and full subtractor. Bi is the borrow of the full subtractor, diff is the result of the full subtractor, and sum is the result of the full adder. TtoS can realize the data conversion from binary complement to sign plus amplitude form. Finally, the sign and amplitude are combined to obtain the results of f_out and g_out operations to meet the requirements of F and G operations.
[0027] S22: In the second decoding cycle CC1, the first splicing result in the cache register REG is stored in the LLR_RAM unit; Input the first splicing result into the data processing PE module to obtain the second PE calculation result; According to the updated LLR calculation index, read the LLR data of the third position; The second PE calculation result is spliced with the LLR data at the third position through the data splicing unit in combination with the updated LLR calculation index to obtain a second splicing result; the second splicing result is stored in the cache register REG; As an exemplary embodiment, during the decoding cycle CC1, the first splicing result in the cache REG is stored in the LLR_RAM, and at the same time, it is passed as input to the data processing PE module, the LLR data at the next position (LLR data at the third position) is read and spliced with the calculation result of the data processing PE module, and the second splicing result is stored in the cache REG.
[0028] S23: Repeat step S22 until all calculations of a set of LLR data are completed to obtain decoded LLRs.
[0029] Step S3 includes: The path processing module includes: a decoding processing unit, a convolution transformation unit, a path information storage unit and a metric updating unit.
[0030] Step S3 also includes: The decoding LLR is processed by the decoding processing unit to obtain an internal polarization decoding result; The internal polar decoding results are transmitted to the part and calculation module, and the convolution transformation unit respectively; Updating the partial sum required for polar code decoding through the partial sum calculation module; The decoding result is processed by the convolution transformation module to obtain the external convolution result.
[0031] As an exemplary embodiment, after a set of LLR calculations are completed, the decoded LLRs are obtained and transmitted to Figure 4 The path processing module in the path processing module obtains the decoding result of the internal polar code according to the decoded LLR; the internal polarization decoding result is passed to the external partial sum calculation module and the internal convolution transformation module respectively, the former is used to update the partial sum required for polar code decoding, and the latter is used to obtain the external convolution result for metric value update.
[0032] Step S4 includes: S41: The current node type to be decoded includes: frozen bit and information bit; If the type of the current node to be decoded is a frozen bit and the external convolution result is 0, the path metric value will not be changed; If the current node type to be decoded is a frozen bit and the external convolution result is 1, it means that the internal polarization decoding result does not match the frozen bit, then the path metric value is updated according to the decoded LLR; Specifically, the path metric value is updated according to the decoded LLR to indicate that the credibility of the path is reduced.
[0033] S42: If the type of the current node to be decoded is an information bit, calculate the path metric values of the two branch nodes under the current node to be decoded in the decoding tree: If any path metric value is greater than the preset threshold T, the decoding goes to the node with the largest path metric value; If any path metric value is not greater than the preset threshold T, the node will be backtracked as follows: When entering the node backtracking, determine whether the current node to be decoded meets the forward decoding conditions. If so, perform forward decoding of the next node. If not, update the preset threshold T and continue backtracking until the current node to be decoded meets the forward decoding conditions and continue forward decoding of the next node.
[0034] Specifically, Fig.10Schematic diagram of the decoding tree when Δ=3. The figure gives a simple example of the Fano decoding process. The child node corresponds to two decoding results of the parent node. Next to the node is the path metric value PM of the node. Starting from the node with a metric of 0 at the beginning, the threshold T is updated to -3. Step 1 moves to the node with a larger path metric value. The metrics of the two child nodes of this node are both less than T. At this time, step 2 performs node backtracking; at this time, the node with a PM of -2.57 has been traversed, and the node with a PM of -2.81 meets the conditions. Step 3 is performed to move the node. It is determined that both nodes of the node do not meet the conditions. Step 4 is performed and the threshold T=-6 is updated. According to the new threshold, it moves to the node with a larger PM value to complete steps 5, 6 and 7; when the node backtracking is completed, the decoding node information is updated to the control module. According to the control information, Figure 4 The path processing module reads the path data and updates the parts and networks. Fig. 9 As shown, the path is updated according to the current node type to be decoded and the external convolution result.
[0035] The present application also discloses a computer-readable storage medium storing a plurality of instructions, wherein the instructions are suitable for a processor to load to execute the above-mentioned method for designing a low-latency PAC code Fano decoder.
[0036] The above are only exemplary embodiments of the present disclosure and cannot be used to limit the scope of the present disclosure. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the disclosure of the specification and the truth of practice, those skilled in the art will easily think of other embodiments of the present disclosure.
[0037] This application is intended to cover any variation, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the art not described in the present disclosure. The description and examples are to be regarded as exemplary only, and the scope and spirit of the present disclosure are defined by the claims.
Claims
1. A low-latency PAC code Fano decoder design method, characterized in that: Methods include: S1: Receive the LLR data of the channel and update the decoding status; S2: Decode the LLR data according to the updated decoding state to obtain a decoded LLR; S3: Obtain the internal polarization decoding result and the external convolution result according to the decoded LLR; S4: Update the path according to the type of the current node to be decoded and the external convolution result, and determine whether to continue the forward decoding of the next node. The specific steps are as follows: If the forward decoding conditions are met, the forward decoding of the next node is continued according to the internal polarization decoding result; If the forward decoding condition is not met, the node is backtracked, the intermediate data is restored to the backtracking node, and the forward decoding of the next node is continued from the backtracking node; S5: Forward decoding to the last node of the decoding tree, end decoding and output the decoding result.
2. A low-latency PAC code Fano decoder design method as claimed in claim 1, characterized in that: The decoder comprises: a control module, an LLR storage module, a data processing PE module, a partial sum calculation module and a path processing module; the LLR storage module comprises: an LLR_RAM unit and a data splicing unit.
3. A low-latency PAC code Fano decoder design method as claimed in claim 2, characterized in that: Step S1 includes: S11: the LLR storage module stores the received LLR data in a preset order; S12: After receiving a set of LLR data, the decoding state is updated through the control module; the decoding state includes: a decoding bit index and an LLR calculation index; The decoding bit index represents the natural order index of the current node to be decoded; the LLR calculation index includes: the starting position of the log-likelihood ratio calculation and the position information of the intermediate process of the calculation; S13: Determine the LLR calculation index by decoding the bit index; S14: Control the access of LLR data and the data splicing in the intermediate process of calculation according to the LLR calculation index.
4. A method for designing a low-latency PAC code Fano decoder as claimed in claim 3, characterized in that: Step S2 includes: S21: In the first decoding cycle CC0, according to the LLR calculation index, read the LLR data at the starting position and the LLR data at the second position in a group of LLR data; Input the LLR data at the starting position into the data processing PE module to obtain the first PE calculation result; The first PE calculation result is combined with the LLR calculation index through the data splicing unit to obtain a first splicing result; the first splicing result is stored in the cache register REG in the data splicing unit; S22: In the second decoding cycle CC1, the first splicing result in the cache register REG is stored in the LLR_RAM unit; Input the first splicing result into the data processing PE module to obtain the second PE calculation result; According to the updated LLR calculation index, read the LLR data of the third position; The second PE calculation result is spliced with the LLR data at the third position through the data splicing unit in combination with the updated LLR calculation index to obtain a second splicing result; the second splicing result is stored in the cache register REG; S23: Repeat step S22 until all calculations of a set of LLR data are completed to obtain decoded LLRs.
5. A low-latency PAC code Fano decoder design method as claimed in claim 4, characterized in that: Step S3 includes: The path processing module includes: a decoding processing unit, a convolution transformation unit, a path information storage unit and a metric updating unit.
6. A method for designing a low-latency PAC code Fano decoder as claimed in claim 5, characterized in that: Step S3 also includes: The decoding LLR is processed by the decoding processing unit to obtain an internal polarization decoding result; The internal polar decoding results are transmitted to the part and calculation module, and the convolution transformation unit respectively; Updating the partial sum required for polar code decoding through the partial sum calculation module; The decoding result is processed by the convolution transformation module to obtain the external convolution result.
7. A method for designing a low-latency PAC code Fano decoder as claimed in claim 6, characterized in that: Step S4 includes: S41: The current node type to be decoded includes: frozen bit and information bit; If the type of the current node to be decoded is a frozen bit and the external convolution result is 0, the path metric value will not be changed; If the current node type to be decoded is a frozen bit and the external convolution result is 1, it means that the internal polarization decoding result does not match the frozen bit, then the path metric value is updated according to the decoded LLR; S42: If the type of the current node to be decoded is an information bit, calculate the path metric values of the two branch nodes under the current node to be decoded in the decoding tree: If any path metric value is greater than the preset threshold T, the decoding goes to the node with the largest path metric value; If any path metric value is not greater than the preset threshold T, the node will be backtracked as follows: When entering the node backtracking, determine whether the current node to be decoded meets the forward decoding conditions. If so, perform forward decoding of the next node. If not, update the preset threshold T and continue backtracking until the current node to be decoded meets the forward decoding conditions and continue forward decoding of the next node.
8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores instructions, and when the instructions are executed by a computer, the method according to any one of claims 1 to 7 is executed.