A method for generating digital chrip sequence for power grid centralized data collection

Abstract

The present application discloses a method for generating a digital CHrip sequence for power grid collection, which relates to the field of technical signal processing. The method includes: obtaining data to be modulated; calculating a virtual address corresponding to the address of the data to be modulated; calculating a data access address corresponding to the virtual address in the wave table according to the virtual address and the address length of the wave table; obtaining a value corresponding to the data to be modulated from the wave table according to the data access address to obtain a modulation sequence. The virtual address is converted into a data access address, and the size change of the spread spectrum coefficient can be adaptively adjusted without changing and reloading the I / Q waveform of the CSS sequence, thereby improving the efficiency of linear frequency modulation spread spectrum.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to a method for generating a digital chrip sequence for power grid metering. Background Art

[0002] At present, the main communication methods for related power grid technologies to collect electricity consumption information are dual-mode communication methods of HPLC (high-speed power line carrier communication) and HRF (high-speed wireless communication). The modulation technology used in both methods is OFDM technology. From the current usage effect, the above communication technology meets the needs of most collection scenarios, but there are still a small number of scenarios where the modulation technology of this communication method cannot meet the needs. For example, for isolated points with long communication distances, HPLC and HRF are both high-speed communications with relatively low communication sensitivity, and cannot communicate with isolated points, resulting in final collection failure.

[0003] Therefore, in order to solve the problem of isolated points in power grid communication, it is recommended to adopt a low-speed modulation technology, namely linear frequency modulation spread spectrum technology (CSS, CSS is the abbreviation of Chirp Spread Spectrum). In the digital CSS modulation process, CSS sequence is generally used. The method for generating CSS sequence is usually to store the I / Q waveform of the CSS sequence in the system, that is, the in-phase component waveform / orthogonal component waveform. During the modulation and demodulation process, the data to be modulated needs to perform certain operations with the CSS sequence I / Q path and conjugate waveform data. However, when the spread spectrum factor changes, the I / Q waveform of the CSS sequence needs to be changed accordingly and reloaded into the system, which is inefficient. Summary of the invention

[0004] The main purpose of the embodiments of the present application is to propose a method for generating a digital chrip sequence for power grid data collection to improve the efficiency of linear frequency modulation spread spectrum.

[0005] To achieve the above object, an embodiment of the present application provides a method for generating a digital chrip sequence for power grid data collection, the method comprising the following steps:

[0006] Obtaining data to be modulated;

[0007] Calculating a virtual address corresponding to the address of the data to be modulated;

[0008] Calculate the data access address corresponding to the virtual address in the wave table according to the virtual address and the address length of the wave table;

[0009] According to the data acquisition address, the value corresponding to the data to be modulated is obtained from the wave table to obtain a modulation sequence.

[0010] In some embodiments, the calculating the virtual address corresponding to the address of the data to be modulated comprises the following steps:

[0011] The address of the data to be modulated is first squared and then modulo-ed to obtain the corresponding virtual address; wherein the length of the modulo is the address length of the wave table.

[0012] In some embodiments, the step of calculating the access address corresponding to the virtual address in the wave table according to the virtual address and the address length of the wave table comprises the following steps:

[0013] If the length of the virtual address is the same as the address length of the wave table, the virtual address is determined as the data access address;

[0014] If the length of the virtual address is smaller than the address length of the wave table, the lower bits of the virtual address are padded with 0 until they are the same as the address length of the wave table, and the address obtained after the virtual address is padded with 0 is used as the access address;

[0015] If the length of the virtual address is greater than the address length of the wave table, a high-order address in the virtual address is taken as the data access address; wherein the length of the high-order address is the same as the address length of the wave table.

[0016] In some embodiments, the step of acquiring a value corresponding to the data to be modulated from the wave table according to the data acquisition address to obtain a modulation sequence includes the following steps:

[0017] Acquire the values ​​corresponding to the in-phase component and the orthogonal component of the data to be modulated from the wave table according to the data acquisition address;

[0018] The expression of the in-phase component is:

[0019] ;

[0020] The expression of the orthogonal component is:

[0021] ;

[0022] in, represents the in-phase component, represents the orthogonal components, represents the data access address, m is the virtual address, M is the address length of the wave table;

[0023] The modulation sequence is determined according to the in-phase component and the quadrature component.

[0024] In some embodiments, the method further comprises the following steps:

[0025] Calculate a corresponding conjugate sequence according to the modulation sequence;

[0026] Alternatively, if the length of the virtual address is greater than the address length of the wave table, interpolation processing is performed on the values ​​corresponding to the in-phase component and the orthogonal component to obtain the interpolated modulation sequence.

[0027] In some embodiments, before calculating the access address corresponding to the virtual address in the wave table according to the virtual address and the address length of the wave table, the method further includes the following steps:

[0028] Obtaining the wave table for a complete cycle;

[0029] Alternatively, obtain the wave table of a quarter period, and extend the wave table of a quarter period to a full period.

[0030] In some embodiments, the step of extending the wavetable of a quarter period to a full period comprises the following steps:

[0031] Synthesize a full-cycle sine function as the wave table based on the wave table of a quarter cycle and the virtual address;

[0032] Alternatively, the first address of the virtual address is set to a quarter of the address length of the wave table, and a cosine function of a complete period is synthesized based on the wave table of a quarter period and the virtual address as the wave table;

[0033] Alternatively, the first address of the virtual address is set to half the address length of the wave table, and a negative sine function of a complete period is synthesized based on the wave table of a quarter period and the virtual address as the wave table.

[0034] To achieve the above-mentioned purpose, another aspect of the embodiment of the present application provides a device for generating a digital chrip sequence for power grid centralized meter reading, the device comprising:

[0035] A data acquisition unit for obtaining data to be modulated, used for obtaining data to be modulated;

[0036] A virtual address calculation unit, used for calculating a virtual address corresponding to the address of the data to be modulated;

[0037] An access address calculation unit, used for calculating the access address corresponding to the virtual address in the wave table according to the virtual address and the address length of the wave table;

[0038] The modulation data acquisition unit is used to obtain the numerical value corresponding to the data to be modulated from the wave table according to the data acquisition address to obtain a modulation sequence.

[0039] To achieve the above objective, another aspect of an embodiment of the present application provides an electronic device, the electronic device comprising a memory and a processor, the memory storing a computer program, and the processor implementing the above method when executing the computer program.

[0040] To achieve the above objective, another aspect of an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and the computer program implements the above method when executed by a processor.

[0041] The embodiments of the present application include at least the following beneficial effects:

[0042] The present application can obtain the data to be modulated; calculate the virtual address corresponding to the address of the data to be modulated; calculate the access address corresponding to the virtual address in the wave table according to the virtual address and the address length of the wave table; obtain the value corresponding to the data to be modulated from the wave table according to the access address to obtain the modulation sequence. The virtual address is converted into the access address, and the size change of the spread spectrum coefficient can be adaptively changed without changing and reloading the I / Q path waveform of the CSS sequence, thereby improving the efficiency of linear frequency modulation spread spectrum. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 A schematic diagram of a flow chart of a method for generating a digital chrip sequence for power grid data collection provided in an embodiment of the present application;

[0045] Figure 2 A schematic diagram of synthesizing chirp sequences in the prior art;

[0046] Figure 3 An example flow chart of a method for generating a digital chrip sequence for power grid data collection provided in an embodiment of the present application;

[0047] Figure 4 A more specific example flowchart of synthesizing chirp sequences;

[0048] Figure 5 An example diagram of a synthesized full-period wave table provided in an embodiment of the present application;

[0049] Figure 6 A schematic diagram of the change of wave table data symbols provided in an embodiment of the present application;

[0050] Figure 7 A sequence diagram for synthesizing a full-period sine wave from a 1 / 4-period wave table;

[0051] Figure 8 1 is a sample diagram of each synthesized waveform;

[0052] Fig. 9 A diagram showing the relationship between the sine wave table address and the chirp sequence address provided in the embodiment of the present application;

[0053] Fig.10 Another relationship diagram between a sine wave table address and a chirp sequence address provided in an embodiment of the present application;

[0054] Fig.11 An example diagram of a synthetic chirp sequence provided in an embodiment of the present application;

[0055] Fig.12 A schematic diagram of the structure of a device for generating a digital chrip sequence for power grid metering provided in an embodiment of the present application;

[0056] Fig.13 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.

[0058] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0059] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0061] Before describing the embodiments of the present application in detail, some related technologies involved in the embodiments of the present application are first described as follows:

[0062] CSS technology is the abbreviation of Chirp Spread Spectrum, which is linear frequency modulation spread spectrum technology. In the digital CSS modulation process, CSS sequence is generally used. The method of generating CSS sequence is usually to store the I / Q waveform of CSS sequence in the system. In the modulation and demodulation process, the modulated data needs to perform certain operations with the waveform data of CSS sequence I / Q path and conjugate.

[0063] The expression of the modulation data after CSS modulation is:

[0064] ;

[0065] Wherein, n is the data to be modulated; , .

[0066] When the related technology performs digital CSS modulation, the method used is as follows:

[0067] 1) Direct calculation method requires hardware to calculate trigonometric functions in real time, which has high hardware overhead and high latency;

[0068] 2) The system directly stores the CSS sequence, pre-calculates the values ​​of the CSS sequence at different phases, and stores them in the system. When used, a table lookup method is used instead of real-time calculation.

[0069] First calculate the CSS sequence css0 when n=0. The expression is as follows:

[0070] ;

[0071] ;

[0072] in and They are the I and Q paths of css0 respectively.

[0073] In the communication system, I path and Q path are two important parts of signal processing. They represent the real part and imaginary part of the signal respectively, and realize signal transmission and processing through orthogonal modulation technology.

[0074] I-path (In-phase Component): Also known as the in-phase component or real part. In a communication system, the I-path signal represents the signal component that is in phase with the carrier. In the orthogonal modulation process, the I-path signal is usually multiplied with a sine signal (or a cosine signal, depending on the specific implementation method) to achieve signal modulation.

[0075] Q-path (Quadrature Component): Also known as the orthogonal component or imaginary part. Unlike the I-path signal, the Q-path signal is 90 degrees out of phase with the carrier, so in the orthogonal modulation process, the Q-path signal is usually multiplied with a cosine signal (or a sine signal, which is 90 degrees out of phase with the I-path multiplied signal).

[0076] The principle of Chirp modulation:

[0077] According to the input data to be modulated n, css0 is divided into two parts according to the size of n: css1, css2. Among them, css1 is the 1-n-1th item of css0, and css2 is the nMth item of css0. Then the data is sent out in the order of css2-css1. In the specific implementation, data can be read starting from address n, then n+1, n+2, …n+i, and a total of M data outputs are read. Note: When n+i>M, the highest bit of the address is discarded, that is, reading continues from the first address of the storage unit. In the above case, it is necessary to implement the storage of the css0 sequence (I / Q).

[0078] The I / Q data storage space requires a total of 2*M units. For a system with a SF (spreading factor) of 6 to 12, 128 to 8192 storage spaces are required (I / Q storage is separate).

[0079] When the spreading factor SF changes, the corresponding css sequence stored in the system must also be changed and reloaded. In a system where the spreading factor changes dynamically, more time is required, affecting the flexibility of the system.

[0080] CSS demodulation process:

[0081] 1) Modulated data sequence:

[0082] ;

[0083] 2) CSS0 conjugated sequence for demodulation:

[0084] ;

[0085] 3) Demodulated sequence:

[0086] ;

[0087] It can be seen that the demodulated sequence is a single-tone signal that is only related to the modulation signal n.

[0088] By performing fast Fourier transform on this single tone signal, the modulation signal n can be restored.

[0089] When performing CSS demodulation, it is necessary to perform complex multiplication on the received data sequence and the conjugate sequence of CSS0, and a memory is also used to store the corresponding wave table.

[0090] In summary, the related technology has the problem that the wave table occupies a large storage space and the switching of the spreading coefficient is inflexible.

[0091] Therefore, the embodiment of the present application provides a method for generating a digital CHrip sequence for power grid data collection. The technical solution of the present application includes: obtaining the data to be modulated; calculating the virtual address corresponding to the address of the data to be modulated; calculating the data access address corresponding to the virtual address in the wave table according to the virtual address and the address length of the wave table; obtaining the numerical value corresponding to the data to be modulated from the wave table according to the data access address to obtain the modulation sequence. The virtual address is converted into a data access address, and the size change of the spread spectrum coefficient can be adaptively changed without changing and reloading the I / Q waveform of the CSS sequence, thereby improving the efficiency of linear frequency modulation spread spectrum.

[0092] The embodiment of the present application provides a method for generating a digital chrip sequence for power grid collection, and relates to the field of signal processing technology. The method for generating a digital chrip sequence for power grid collection provided in the embodiment of the present application can be applied to a terminal, can be applied to a server, or can be software running in a terminal or a server. In some embodiments, the terminal can be a smart phone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, and a vehicle-mounted terminal, etc., but is not limited to this; the server side can be configured as an independent physical server, or can be configured as a server cluster or a distributed system composed of multiple physical servers, and can also be configured as a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms. The server can also be a node server in a blockchain network; the software can be an application that implements a method for generating a digital chrip sequence for power grid collection, etc., but is not limited to the above forms.

[0093] The present application can be used in many general or special computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, etc. The present application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application can also be practiced in distributed computing environments, in which tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.

[0094] Reference Figure 1 The embodiment of the present application provides a method for generating a digital chrip sequence for power grid centralized metering. The method may include but is not limited to S100 to S130, which are as follows:

[0095] S100: Acquire data to be modulated.

[0096] Specifically, the data to be modulated in this embodiment may include n items of data, and each item of data may include 0, 1 or more data.

[0097] S110: Calculate the virtual address corresponding to the address of the data to be modulated.

[0098] Specifically, the data number of each data item can be used as the address of the data to be modulated. For example, the data numbers of the first three data items to be modulated are 1, 2, and 3 respectively, and the first three addresses of the data to be modulated can be 1, 2, and 3 respectively.

[0099] Furthermore, S110 may include:

[0100] The address of the data to be modulated is first squared and then modulo-ed to obtain the corresponding virtual address; wherein the length of the modulo is the address length of the wave table.

[0101] Specifically, the spreading factor is used as the length of the virtual address. For example, if the spreading factor is 8, the length of the address of the data to be modulated is also 8. For example, the first three addresses of the data to be modulated are 00000001, 00000010, and 00000011, respectively. Moreover, the length of the virtual address is also the same as the spreading factor.

[0102] S120: Calculate the data access address corresponding to the virtual address in the wave table according to the virtual address and the address length of the wave table.

[0103] Specifically, the length of the virtual address and the length of the wave table address may be different. For example, the length of the wave table address is 10, while the length of the virtual address is 8. If the lengths are different, it is necessary to calculate the corresponding access address of the virtual address in the wave table.

[0104] Furthermore, S120 may include S121 to S123:

[0105] S121: If the length of the virtual address is the same as the address length of the wave table, determining the virtual address as the data access address;

[0106] S122: If the length of the virtual address is smaller than the address length of the wave table, the lower bits of the virtual address are padded with 0 until the virtual address becomes the same as the address length of the wave table, and the address obtained after the virtual address is padded with 0 is used as the access address;

[0107] S123: If the length of the virtual address is greater than the address length of the wave table, a high-order address in the virtual address is taken as the data access address; wherein the length of the high-order address is the same as the address length of the wave table.

[0108] Exemplarily, if the length of the virtual address and the address length of the wave table are both 10, the virtual address is used as the data access address; if the length of the virtual address is 8, which is less than the address length of the wave table 10, two zeros are added to the virtual address to make the length of the 0-padded virtual address the same as the address length of the wave table; if the length of the virtual address is 12, which is greater than the address length of the wave table 10, the first 10 high bits of the virtual address are taken as the data access address.

[0109] S130: Obtain the value corresponding to the data to be modulated from the wave table according to the data acquisition address to obtain a modulation sequence.

[0110] Specifically, the wave table may include multiple data access addresses, each data access address corresponds to a numerical value, and the numerical values ​​corresponding to different data access addresses may be the same or may be different.

[0111] Further, S130 may include S131-S132:

[0112] S131: Acquire values ​​corresponding to the in-phase component and the orthogonal component of the data to be modulated from the wave table according to the data acquisition address;

[0113] The expression of the in-phase component is:

[0114] ;

[0115] The expression of the orthogonal component is:

[0116] ;

[0117] in, represents the in-phase component, represents the orthogonal components, represents the data access address, m is the virtual address, M is the address length of the wave table;

[0118] S132: Determine the modulation sequence according to the in-phase component and the orthogonal component.

[0119] Furthermore, the embodiments of the present application can also calculate the corresponding conjugate sequence according to the modulation sequence based on the phase relationship of the trigonometric function.

[0120] In addition, to improve the accuracy of the modulation sequence, the embodiment of the present application may further include the following steps:

[0121] If the length of the virtual address is greater than the address length of the wave table, interpolation processing is performed on the values ​​corresponding to the in-phase component and the orthogonal component to obtain the interpolated modulation sequence.

[0122] Exemplarily, the algorithm of the interpolation processing may include linear interpolation, quadratic function interpolation, bidirectional quadratic interpolation and other interpolations.

[0123] Furthermore, before S120, the embodiment of the present application may further include a step of obtaining a wave table, specifically including:

[0124] Obtaining the wave table for a complete cycle;

[0125] Alternatively, obtain the wave table of a quarter period, and extend the wave table of a quarter period to a full period.

[0126] It can be understood that, in this embodiment, a wave table of a complete period can be directly obtained, or a wave table of a quarter period or a half period can be first obtained, and then the wave table with an incomplete period can be expanded to a complete period.

[0127] Furthermore, the step of extending the wave table of a quarter period to a full period specifically includes:

[0128] Synthesize a full-cycle sine function as the wave table based on the wave table of a quarter cycle and the virtual address;

[0129] Alternatively, the first address of the virtual address is set to a quarter of the address length of the wave table, and a cosine function of a complete period is synthesized based on the wave table of a quarter period and the virtual address as the wave table;

[0130] Alternatively, the first address of the virtual address is set to half the address length of the wave table, and a negative sine function of a complete period is synthesized based on the wave table of a quarter period and the virtual address as the wave table.

[0131] It can be understood that the specific implementation method of expanding the wave table based on a half period can be adaptively set and implemented with reference to the above implementation method.

[0132] Next, the solution of the embodiment of the present application will be introduced and explained in detail with reference to specific application examples.

[0133] In order to more clearly describe the problems existing in the prior art, a comparison is first made between the prior art and the general scheme of the embodiments of the present application.

[0134] Reference Figure 2 , Figure 2 The schematic diagram of synthesizing chirp sequence (i.e. modulation sequence) in the prior art is that the modulated data passes through two chirp wave tables, I wave table 1 and Q wave table 2, to synthesize the chirp sequence. It occupies a large space and is not flexible to use, and can only be used to send chirp sequences.

[0135] Reference Figure 3 This embodiment provides an example flow chart of a method for generating a digital chrip sequence for power grid data collection, wherein the modulated data is synthesized into the I path and Q path of the chirp sequence, as well as the conjugate sequence, through the address operation unit 1 and the sine / cosine wave table 2. Compared with the existing transceiver system that needs to store the I / Q of the chrip separately, this embodiment reduces the space occupied by the wave table, and combined with the symmetry algorithm of the sine / cosine waveform, it can be reduced to 1 / 8 of the total capacity of the original chirp I / Q wave table at most.

[0136] As an optional implementation, Figure 4 An example flow chart of synthesizing chirp sequences provided for this embodiment.

[0137] about Figure 4 Step 1 in the description of chirp wave table address calculation:

[0138] The I-path and Q-path synthesis expressions of the known chirp sequence are:

[0139] ;

[0140] ;

[0141] The I path and Q path of the chirp sequence are sequences formed by taking out data from a sine / cosine wave table according to the square of the linear address.

[0142] When the square of the address exceeds the length of the wave table, the square of the address is modulo the wave table length and used as the new address to continue to fetch numbers from the sine / cosine wave table.

[0143] Therefore, the calculation of the above step 1 is to use the data to be modulated as the address starting point and perform square and modulo operations on a series of continuous addresses with a length of M (the length of the chirp sequence).

[0144] Next, refer to Figure 5 , the implementation process of synthesizing a full-cycle wavetable is explained:

[0145] Generate a 1 / 4 period sine table using the following formula:

[0146] ;

[0147] Where, m=1, 2, 3…M / 4, and amp is the waveform amplitude.

[0148] Use the address conversion algorithm to map the full cycle address to the 1 / 4 cycle;

[0149] Let M be the length of the synthetic sequence, and M is generally set to an integer power of 2.

[0150] A complete period of sine waves formed by a series of operations and combinations of a 1 / 4 period wave table is used as a synthetic data series. It should be noted that the wave table of this embodiment can also be a complete period wave table and can be used without synthesis.

[0151] The implementation method using a 1 / 4 period wave table is as follows:

[0152] The synthetic data sequence is divided into 4 intervals, as shown in Table 1:

[0153]

[0154] Table 1

[0155] For example, the following will take a target and waveform sequence of 1024 length as an example to explain the synthetic waveform address (phase) range and wave table The corresponding relationship between address (phase) is shown in Table 2:

[0156]

[0157] Table 2

[0158] Reference Figure 6 , according to the corresponding relationship, add appropriate symbols to the output data, and get the relationship shown in Table 3:

[0159]

[0160] Table 3

[0161] This is equivalent to obtaining a sine wave table with a complete cycle. When the input address (the address of the data to be modulated) increases linearly, a complete sine waveform is synthesized;

[0162] use (addr) represents the storage content corresponding to the wave table address addr, that is, the 1 / 4 cycle of the sine wave data, and the full cycle sine sequence is shown in Table 4:

[0163]

[0164] Table 4

[0165] Using the above relationship, a full-period sine wave sequence can be synthesized from a 1 / 4 period wave table, such as Figure 7 shown.

[0166] In addition, this embodiment can also use the phase relationship between the sine function and the cosine function:

[0167] ;

[0168] By setting the input first address to M / 4, we can get the cosine function sequence;

[0169] Let addr be the synthetic wave table address, and the cosine sequence be , the sinusoidal sequence is , then:

[0170] ;

[0171] Similarly, D(addr) is used to represent the storage content corresponding to the wave table address addr, so the output data of the full-period cosine sequence is As shown in Table 5:

[0172]

[0173] Table 5

[0174] Similarly, by setting the input first address to M / 2, we can get a negative sine function sequence for conjugate sequence synthesis. The synthesized waveforms are as follows: Figure 8 shown.

[0175] Summary of the above waveform synthesis:

[0176] 1) Mirror the wave table curve to the left and right to get the first quadrant of the cosine waveform;

[0177] 2) Mirror the wavetable curve up and down with the x-axis as the axis, and then translate it to get the second quadrant of the cosine curve;

[0178] 3) Mirror the wavetable curve horizontally and then vertically to obtain the third quadrant of the cosine curve.

[0179] 4) Translate the wavetable curve directly to obtain the fourth quadrant of the cosine curve.

[0180] Based on the above methods of synthesizing sine, cosine, and negative sine sequences, square the wavetable address and take the modulus of M to generate a chirp sequence.

[0181] According to the definitions of the I-channel and Q-channel of the chirp sequence:

[0182] ;

[0183] ;

[0184] Obviously, the I-channel and Q-channel of the chirp sequence are sequences synthesized by taking numbers from the sine / cosine wavetable after squaring the address:

[0185] ;

[0186] According to the principle of the aforementioned Chirp modulation, the sequence generated above is equivalent to a sequence with modulation data of 0.

[0187] If the data to be modulated is n (n < M), divide css0 into two parts according to the size of n: css1 and css2. Among them:

[0188] css1 is the 1 - n - 1th item of css0;

[0189] css2 is the n - Mth item of css0;

[0190] The modulated sequence: {css2, css1}.

[0191] Therefore, if the data to be modulated is n, starting from n, to M, then from 0 to n - 1, a total of M numbers, perform square and modulus operations, and use the M results as addresses to extract corresponding data from the synthesized virtual sine / cosine wavetable, which is the modulated chirp sequence.

[0192] The above process of symmetrically expanding the wavetable is an optional implementation method. In the specific implementation process, a complete cycle of sine / cosine wavetable can also be directly used to omit the above process.

[0193] Exemplarily, the relationship between the sine wave wavetable address and the chirp sequence address is as Fig. 9As shown, a linearly changing number series starting from 0, i.e. a straight line, 0-1023, represents the address of the sine wave. After squaring and modulo (modulus is M), a curve is obtained as the data acquisition address of the chirp sequence.

[0194] Fig. 9 In the figure, the horizontal axis is the number of data to be modulated, and the vertical axis is the address.

[0195] In another example, refer to Fig.10 , when the number of data to be modulated is 349, when the address changes linearly, a linearly changing sequence starting from 349, that is Fig.10 The address change process of the broken line in the figure is: {(349:1023), (0:348)}. After squaring and taking the modulus (the modulus is M), we get Fig.10 The curve is the address of the chirp sequence.

[0196] Taking the chirp modulation I channel as an example, the broken line is a linear sequence of {(349:1024), (0, 348)}, which means the modulation data at this time is 349. Fig.10 The curve is the curve obtained by square operation and modulo operation of the broken line.

[0197] The Q path of chirp modulation uses the above curve as the address to get data from the cosine wave table. Since there is only one sine wave table, according to the relationship between the sine curve and the cosine curve, the address is added by 1 / 4 address period. This is equivalent to getting data from the cosine wave table.

[0198] If the chirp sequence length is 1024, the address curve of the I path + 256 forms the address curve of the Q path.

[0199] Fig.10 In the figure, the horizontal axis is the number of data to be modulated, and the vertical axis is the address.

[0200] When used Fig.10 The curve sequence is used as the address to get the number from the sine wave table. Input the above synthetic sine wave table to synthesize the chirp sequence, such as Fig.11 shown.

[0201] Optionally, in actual implementation, the synthesized full wave table can be generated in real time without prior synthesis and storage, that is, the final is input to the original On the wave table.

[0202] The phase relationship of the sine / cosine trigonometric functions can be used to synthesize the I / Q waveform of the chirp sequence.

[0203] By using the property of complex conjugation, that is, the opposite sign of the imaginary part, the conjugate sequence of the chirp sequence can also be obtained: , whose conjugate is:

[0204] ;

[0205] The conjugate imaginary waveform sequence can be obtained by It is obtained by inverting the sign of the sequence, or by using the odd function characteristics of the sin function from the original wave table.

[0206] When the spreading factor SF changes, if (wave table address length), you can fill 0 in the low bit of the generated address; if , a more accurate synthetic sequence value can be obtained through interpolation operation; the generated address refers to the address after the linear address is squared and modulo operated.

[0207] Note: Assume that the current full-cycle sine wave table contains 1024 data, that is, the address is 10 bits. If the spread factor is relatively small, such as SF=8, then That is, the required CSS sequence only needs a length of 256, while the existing wave table is 1024 in length. In this case, the address generated as described above is 8 bits. At this time, two bits of 0 need to be added to the last bit, and the address becomes 10 bits. The number can be taken from the 10-bit wave table.

[0208] If the spreading factor is larger, such as SF=12, , that is, the required css sequence needs to be 4096 in length, while the existing wavetable is 1024 in length. The address calculated according to the above process is 12 bits. At this time, the high 10 bits of the 12-bit address are connected to the wavetable, and there will be two more bits. At this time, the extracted value needs to be interpolated based on the two extra bits.

[0209] The interpolation process is to perform a certain interpolation operation based on the two values ​​before and after the upper 10 bits, combined with the values ​​of the extra two bits, to obtain a more accurate waveform amplitude value. For example, a simple 0-order hold method, a linear interpolation algorithm, or a quadratic interpolation algorithm with smaller errors and more complex structures can be used according to system performance requirements.

[0210] This embodiment can not only be used to generate chirp sequences, but also can be used to generate sine / cosine waveform data of different frequencies in real time if the address is not squared, and can then be used as FM / FSK modulation. Combined with interpolation, it can be used as a precision sine wave generator, a sine wave table, to achieve multiple uses.

[0211] It should be noted that this embodiment can also be implemented in the following ways:

[0212] 1) This embodiment can be implemented by hardware / FPGA, MCU / DSP, or software / hardware. Wave tables, address calculations, interpolation algorithms, etc. can be implemented by software / hardware respectively.

[0213] 2) The wave table can be a full-period wave table, a quarter-period wave table, or a half-period wave table;

[0214] 3) In addition to linear interpolation and quadratic function interpolation, the interpolation algorithm also includes bidirectional quadratic interpolation and other interpolations, including non-interpolation. That is, when sf is large, the required wave table address width is smaller than the current wave table address width, and the generated address low bit can be truncated (but the truncation noise caused by this is high);

[0215] 4) This embodiment can be used not only to generate the CSS sequence required for CSS modulation and demodulation, but also to generate sine and cosine waveforms of different frequencies, and to generate other waveforms through other operations on addresses.

[0216] In addition, the solution provided in this embodiment can be applied to the three-mode transceiver system of the power grid and the photovoltaic circuit breaker control chip.

[0217] In summary, the beneficial effects of this embodiment include:

[0218] 1) Use a one-cycle sine / cosine wave table to synthesize a full-cycle I / Q two-way chirp sequence, reducing the space occupied by the wave table to 1 / 2 of the original;

[0219] 2) Using the symmetry of the sine / cosine function, a 1 / 4 period sine / cosine wave table is used to synthesize a full period I / Q two-way chirp sequence, reducing the space occupied by the wave table to 1 / 8 of the original space;

[0220] 3) When the spread spectrum coefficient changes, the process of replacing the css0 wave table is eliminated, thereby improving the switching speed.

[0221] 4) In addition to generating chirp signals, it can also be used to generate single tone signals of different frequencies and other signals.

[0222] 5) Since the space occupied by the wave table is reduced, if necessary, two or even more sets of the solutions of this embodiment can be used to achieve fast parallel output of chirp sequences with multiple waveforms and multiple spreading coefficients.

[0223] Reference Fig.12 The embodiment of the present application also provides a device for generating a digital chrip sequence for power grid centralized metering, which can implement the above-mentioned method for generating a digital chrip sequence for power grid centralized metering, and the device includes:

[0224] A data acquisition unit for obtaining data to be modulated, used for obtaining data to be modulated;

[0225] A virtual address calculation unit, used for calculating a virtual address corresponding to the address of the data to be modulated;

[0226] An access address calculation unit, used for calculating the access address corresponding to the virtual address in the wave table according to the virtual address and the address length of the wave table;

[0227] The modulation data acquisition unit is used to obtain the numerical value corresponding to the data to be modulated from the wave table according to the data acquisition address to obtain a modulation sequence.

[0228] It can be understood that the contents of the above method embodiments are all applicable to the present device embodiments, the functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0229] The embodiment of the present application also provides an electronic device, the electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the above-mentioned method for generating a digital chrip sequence for power grid centralized meter reading when executing the computer program. The electronic device can be any intelligent terminal including a tablet computer, a car computer, etc.

[0230] It can be understood that the contents of the above method embodiments are all applicable to the present device embodiments, the functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0231] See also Fig.13 , Fig.13 The hardware structure of an electronic device of another embodiment is illustrated, and the electronic device includes:

[0232] The processor 1301 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0233] The memory 1302 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 1302 can store an operating system and other application programs. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 1302, and the processor 1301 calls and executes the method for generating a digital chrip sequence for power grid collection in the embodiment of this application;

[0234] Input / output interface 1303, used to implement information input and output;

[0235] The communication interface 1304 is used to realize the communication interaction between the device and other devices. The communication can be realized through a wired manner (such as USB, network cable, etc.) or a wireless manner (such as mobile network, WIFI, Bluetooth, etc.);

[0236] A bus 1305 that transmits information between various components of the device (e.g., the processor 1301, the memory 1302, the input / output interface 1303, and the communication interface 1304);

[0237] The processor 1301 , the memory 1302 , the input / output interface 1303 and the communication interface 1304 are connected to each other in communication within the device via a bus 1305 .

[0238] An embodiment of the present application also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the above-mentioned method for generating a digital chrip sequence for power grid metering.

[0239] It can be understood that the contents of the above method embodiments are all applicable to the present storage medium embodiments, the functions specifically implemented by the present storage medium embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0240] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0241] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0242] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0243] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0244] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0245] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0246] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0247] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0248] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0249] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0250] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0251] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A method for generating a digital chrip sequence for power grid data collection, characterized in that: The method comprises the following steps: Obtaining data to be modulated; Calculating a virtual address corresponding to the address of the data to be modulated; Calculate the data access address corresponding to the virtual address in the wave table according to the virtual address and the address length of the wave table; According to the data acquisition address, the value corresponding to the data to be modulated is obtained from the wave table to obtain a modulation sequence.

2. A method for generating a digital chrip sequence for power grid data collection according to claim 1, characterized in that: The step of calculating the virtual address corresponding to the address of the data to be modulated comprises the following steps: The address of the data to be modulated is first squared and then modulo-ed to obtain the corresponding virtual address; wherein the length of the modulo is the address length of the wave table.

3. A method for generating a digital chrip sequence for power grid data collection according to claim 1, characterized in that: The step of calculating the data access address corresponding to the virtual address in the wave table according to the virtual address and the address length of the wave table comprises the following steps: If the length of the virtual address is the same as the address length of the wave table, the virtual address is determined as the data access address; If the length of the virtual address is smaller than the address length of the wave table, the lower bits of the virtual address are padded with 0 until they are the same as the address length of the wave table, and the address obtained after the virtual address is padded with 0 is used as the access address; If the length of the virtual address is greater than the address length of the wave table, a high-order address in the virtual address is taken as the data access address; wherein the length of the high-order address is the same as the address length of the wave table.

4. A method for generating a digital chrip sequence for power grid data collection according to claim 2, characterized in that: The step of acquiring a value corresponding to the data to be modulated from the wave table according to the data acquisition address to obtain a modulation sequence comprises the following steps: Acquire the values ​​corresponding to the in-phase component and the orthogonal component of the data to be modulated from the wave table according to the data acquisition address; The expression of the in-phase component is: ； The expression of the orthogonal component is: ； in, represents the in-phase component, represents the orthogonal components, represents the data access address, m is the virtual address, M is the address length of the wave table; The modulation sequence is determined according to the in-phase component and the quadrature component.

5. A method for generating a digital chrip sequence for power grid data collection according to claim 4, characterized in that: The method further comprises the following steps: Calculate a corresponding conjugate sequence according to the modulation sequence; Alternatively, if the length of the virtual address is greater than the address length of the wave table, interpolation processing is performed on the values ​​corresponding to the in-phase component and the orthogonal component to obtain the interpolated modulation sequence.

6. A method for generating a digital chrip sequence for power grid data collection according to any one of claims 1 to 5, characterized in that: Before calculating the data access address corresponding to the virtual address in the wave table according to the virtual address and the address length of the wave table, the method further includes the following steps: Obtaining the wave table for a complete cycle; Alternatively, obtain the wave table of a quarter period, and extend the wave table of a quarter period to a full period.

7. A method for generating a digital chrip sequence for power grid data collection according to claim 6, characterized in that: The step of extending the wave table of a quarter period to a full period comprises the following steps: Synthesize a full-cycle sine function as the wave table based on the wave table of a quarter cycle and the virtual address; Alternatively, the first address of the virtual address is set to a quarter of the address length of the wave table, and a cosine function of a complete period is synthesized based on the wave table of a quarter period and the virtual address as the wave table; Alternatively, the first address of the virtual address is set to half the address length of the wave table, and a negative sine function of a complete period is synthesized based on the wave table of a quarter period and the virtual address as the wave table.

8. A device for generating a digital chrip sequence for power grid data collection, characterized in that: The device comprises: A data acquisition unit for obtaining data to be modulated, used for obtaining data to be modulated; A virtual address calculation unit, used for calculating a virtual address corresponding to the address of the data to be modulated; An access address calculation unit, used for calculating the access address corresponding to the virtual address in the wave table according to the virtual address and the address length of the wave table; The modulation data acquisition unit is used to obtain the numerical value corresponding to the data to be modulated from the wave table according to the data acquisition address to obtain a modulation sequence.

9. An electronic device, characterized in that: The electronic device comprises a memory and a processor, the memory stores a computer program, and the processor implements the method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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