Anti-overflow method and system for data transmission between FPGA (Field Programmable Gate Array) and CPU (Central Processing Unit) through Ethernet
By using custom flow control packets to transmit the space size of the CPU application layer BUF in the Ethernet data transmission of FPGA and CPU, the data loss problem caused by the lack of effective flow control mechanism in FPGA and CPU data transmission is solved, and reliable cache of data packets and end-to-end flow control mechanism are realized.
Patent Information
- Application Number
- CN202411734725.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-29
- Publication Date
- 2025-03-14
AI Technical Summary
In the process of FPGA and CPU transmitting data through Ethernet, there is a lack of an effective flow control mechanism, which leads to the inability to reliably control the data flow between the CPU application layer BUF and the driving layer BUF, which is prone to data loss, affecting the reliability of data transmission.
By using a custom flow control packet in the FPGA packetization control logic, the current space size of the CPU application layer BUF is sent to the FPGA packetization control logic, and data transmission is controlled according to the space size to ensure that the data packet checks the space size before sending to avoid overflow.
The FPGA is implemented to obtain the current space size of the CPU application layer BUF in real time, ensuring that all data packets are cached reliably and will not overflow, ensuring an end-to-end flow control mechanism, and preventing data overflow from the CPU Ethernet driver layer BUF to the application layer BUF.
Smart Images
Figure CN119629139A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of data transmission between FPGA and CPU, and in particular to an anti-overflow method and system for data transmission between FPGA and CPU via Ethernet. Background Art
[0002] FPGA user logic sends data packets to Ethernet on the CPU side through Ethernet. The CPU Ethernet caches the received data in the driver layer BUF and controls the packet sending speed of the FPGA user logic by sending pause frames to the FPGA according to the water level of the driver layer BUF to prevent the driver layer BUF from overflowing and losing data. However, there is no reliable flow control method between the driver layer BUF of the CPU Ethernet and the BUF of the application software, and the FPGA packet control logic cannot know whether the CPU application layer BUF can cache the sent data, and cannot control the flow at the data source. In actual use, data loss often occurs, affecting the reliability of data transmission. Summary of the invention
[0003] The present invention aims to provide an overflow prevention method and system for data transmission between FPGA and CPU via Ethernet, so as to solve the above-mentioned problems.
[0004] In a first aspect, the present invention provides an overflow prevention method for transmitting data between an FPGA and a CPU via Ethernet, comprising:
[0005] The CPU sends the current space size of the application layer BUF to the FPGA packet control logic;
[0006] The FPGA packet sending control logic controls data transmission according to the current space size.
[0007] In some embodiments, the CPU sends the current space size of the application layer BUF to the FPGA packet control logic through a custom flow control packet.
[0008] In some embodiments, the custom flow control packet carries the following information:
[0009] In the initial stage, the custom flow control packet carries the space size of the CPU application layer BUF;
[0010] During the data transmission phase, the custom flow control packet carries the size of the newly released space of the CPU application layer BUF.
[0011] In some embodiments, the FPGA packet control logic controls data transmission according to the current space size, including:
[0012] Obtain the current space size of the CPU application layer BUF from the custom flow control packet;
[0013] Determine the current data packet and the current space size, if the current data packet is less than or equal to the current space size, send the current data packet to the CPU, otherwise pause sending and wait for a new space size.
[0014] In some embodiments, obtaining the current space size of the CPU application layer BUF from the custom flow control packet includes:
[0015] In the initial stage, the current space size is the space size of the CPU application layer BUF;
[0016] During the data transmission phase, the current space size is updated according to the following method:
[0017] If the current data packet is sent successfully, the current space size is updated to: current space size - current data packet size;
[0018] If a new custom flow control packet is received, the newly released space size of the CPU application layer BUF is parsed from the new custom flow control packet, and the current space size is updated to: the current space size + the newly released space size;
[0019] If the current data packet is successfully sent and a new custom flow control packet is received at the same time, the current space size is updated to: current space size - size of current data packet + newly released space size.
[0020] In a second aspect, the present invention provides an anti-overflow system for transmitting data between an FPGA and a CPU via Ethernet, comprising an FPGA and a CPU, wherein the FPGA is provided with an FPGA packet sending control logic;
[0021] The CPU is used to send the current space size of the application layer BUF to the FPGA packet control logic;
[0022] The FPGA packet sending control logic is used to control data transmission according to the current space size.
[0023] In some embodiments, the CPU is specifically configured to send the current space size of the application layer BUF to the FPGA packet control logic via a custom flow control packet.
[0024] In some embodiments, the custom flow control packet carries the following information:
[0025] In the initial stage, the custom flow control packet carries the space size of the CPU application layer BUF;
[0026] During the data transmission phase, the custom flow control packet carries the size of the newly released space of the CPU application layer BUF.
[0027] In some embodiments, the FPGA packet sending control logic is specifically used to:
[0028] Obtain the current space size of the CPU application layer BUF from the custom flow control packet;
[0029] Determine the current data packet and the current space size, if the current data packet is less than or equal to the current space size, send the current data packet to the CPU, otherwise pause sending and wait for a new space size.
[0030] In some embodiments, obtaining the current space size of the CPU application layer BUF from the custom flow control packet includes:
[0031] In the initial stage, the current space size is the space size of the CPU application layer BUF;
[0032] During the data transmission phase, the current space size is updated according to the following method:
[0033] If the current data packet is sent successfully, the current space size is updated to: current space size - current data packet size;
[0034] If a new custom flow control packet is received, the newly released space size of the CPU application layer BUF is parsed from the new custom flow control packet, and the current space size is updated to: the current space size + the newly released space size;
[0035] If the current data packet is successfully sent and a new custom flow control packet is received at the same time, the current space size is updated to: current space size - size of current data packet + newly released space size.
[0036] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:
[0037] In the present invention, the FPGA can obtain the current space size (i.e., free space size) of the CPU application layer BUF in real time, ensuring that all data packets sent to the CPU can be reliably cached without overflow. Such an end-to-end flow control mechanism can also ensure that data overflow does not occur from the CPU Ethernet driver layer BUF to the application layer BUF. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Figure 1 This is a schematic diagram of the current FPGA sending data to the CPU.
[0039] Figure 2 Schematic diagram of data overflow prevention when transmitting data between FPGA and CPU via Ethernet in an embodiment of the present invention. DETAILED DESCRIPTION
[0040] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.
[0041] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0042] In the link where FPGA sends data to CPU, data can be reliably transmitted between FPGA user logic and FPGA Ethernet through the valid+ready handshake mechanism and the pause frame mechanism; data can be reliably flow controlled through the pause frame between FPGA Ethernet and CPU Ethernet; therefore, the key to the technical problem is that there is no reliable flow control measure between the CPU application layer BUF and the driver layer BUF. In view of this, an embodiment of the present invention provides an anti-overflow method for transmitting data between FPGA and CPU through Ethernet to solve the technical problem.
[0043] The communication scheme between Ethernet and application software on the CPU side is generally provided by Ethernet card manufacturers or third-party companies. The schemes provided by various parties are varied, and it is difficult for users to make effective modifications. Moreover, rashly modifying the third-party program will also cause adaptability problems, which will cause troubles for later support and maintenance. The design idea of an anti-overflow method for transmitting data between FPGA and CPU via Ethernet provided by an embodiment of the present invention is to enable the FPGA packet control logic to obtain the cache status of the CPU application layer BUF, control data transmission according to the cache status of the CPU application layer BUF, and ensure that all data packets sent by the FPGA can be safely and reliably cached in the CPU application layer BUF, ensuring that the CPU application layer BUF does not overflow. This method does not directly add a flow control mechanism between the CPU application layer BUF and the driver layer BUF, but ensures that even if there is no reliable flow control mechanism between the application layer BUF and the driver layer BUF, it will not cause data overflow problems.
[0044] In some embodiments, Figure 2 As shown, the method for preventing overflow of data transmitted between the FPGA and the CPU via Ethernet is characterized by comprising:
[0045] The CPU sends the current space size of the application layer BUF to the FPGA packet control logic;
[0046] The FPGA packet sending control logic controls data transmission according to the current space size.
[0047] In some embodiments, the CPU sends the current space size of the application layer BUF to the FPGA packet control logic through a custom flow control packet. Thus, the FPGA packet control logic controls data transmission according to the current space size, including:
[0048] Obtain the current space size of the CPU application layer BUF from the custom flow control packet;
[0049] Determine the current data packet and the current space size, if the current data packet is less than or equal to the current space size, send the current data packet to the CPU, otherwise pause sending and wait for a new space size.
[0050] Specifically, the CPU-side application software constructs the space size of the application layer BUF into a custom flow control packet in the initial stage and sends it to the FPGA packet control logic via Ethernet. After the CPU application software reads the application layer BUF, it also constructs the newly released space size into a custom flow control packet and sends it to the FPGA packet control logic. The FPGA packet control logic can obtain the current space size based on the space size of the CPU application layer BUF and the newly released space size. The FPGA packet control logic determines whether data can be sent based on the received space size. If the current space size is sufficient, data is sent, otherwise wait for the newly released space. Therefore, in order to enable the FPGA packet control logic to obtain the current space size of the application layer BUF, the custom flow control packet carries the following information:
[0051] In the initial stage, the custom flow control packet carries the space size of the CPU application layer BUF;
[0052] In the data transmission phase, the custom flow control packet carries the newly released space size of the CPU application layer BUF. One implementation method is that the CPU reads the cache data of the application layer BUF, and after the read amount accumulates to a set threshold, the newly released space size is configured to the custom flow control packet.
[0053] An example of the structure of a custom flow control packet is shown in Table 1. The custom flow control packet is a carrier for transmitting space size parameters between the FPGA and the CPU. Its structure includes a frame header, a frame tail, length information, space size, etc.
[0054] Table 1, the structure of a custom flow control package:
[0055]
[0056] It can be seen from the structure of the above custom flow control packet that the current space size of the CPU application layer BUF is not carried in the custom flow control packet. It is necessary to obtain the current space size of the CPU application layer BUF from the custom flow control packet according to the space size parameter carried by the custom flow control packet, as follows:
[0057] In the initial stage, the CPU application layer BUF is empty and the entire application layer BUF can be used. Therefore, the current space size is the space size of the CPU application layer BUF.
[0058] During the data transmission phase, the data packet sent by the FPGA will update the space size of the application layer BUF. At the same time, the CPU application software can obtain the newly released space size of the application layer BUF after reading the application layer BUF. Therefore, the current space size is updated according to the following method:
[0059] If the current data packet is sent successfully, the current space size is updated to: current space size - current data packet size;
[0060] If a new custom flow control packet is received, the newly released space size of the CPU application layer BUF is parsed from the new custom flow control packet, and the current space size is updated to: the current space size + the newly released space size;
[0061] If the current data packet is successfully sent and a new custom flow control packet is received at the same time, the current space size is updated to: current space size - size of current data packet + newly released space size.
[0062] According to the above process, FPGA can obtain the current space size (i.e. free space size) of CPU application layer BUF in real time, ensuring that all data packets sent to CPU can be reliably cached without overflow. Such end-to-end flow control mechanism can also ensure that data overflow does not occur from CPU Ethernet driver layer BUF to application layer BUF.
[0063] Based on the same technical concept, an embodiment of the present invention also provides an anti-overflow system for transmitting data between an FPGA and a CPU via Ethernet, comprising an FPGA and a CPU, wherein the FPGA is provided with an FPGA packet sending control logic;
[0064] The CPU is used to send the current space size of the application layer BUF to the FPGA packet control logic;
[0065] The FPGA packet sending control logic is used to control data transmission according to the current space size.
[0066] The specific working principle of the overflow prevention system can be referred to the description of the aforementioned overflow prevention method, which will not be repeated here.
[0067] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A method for preventing overflow of data transmitted between FPGA and CPU via Ethernet, characterized in that: include: The CPU sends the current space size of the application layer BUF to the FPGA packet control logic; The FPGA packet sending control logic controls data transmission according to the current space size.
2. The method for preventing overflow of data transmitted between FPGA and CPU via Ethernet according to claim 1, characterized in that: The CPU sends the current space size of the application layer BUF to the FPGA packet control logic through a custom flow control packet.
3. The method for preventing overflow of data transmitted between FPGA and CPU via Ethernet according to claim 2, characterized in that: The custom flow control packet carries the following information: In the initial stage, the custom flow control packet carries the space size of the CPU application layer BUF; During the data transmission phase, the custom flow control packet carries the size of the newly released space of the CPU application layer BUF.
4. The method for preventing overflow of data transmitted between FPGA and CPU via Ethernet according to claim 3, characterized in that: The FPGA packet control logic controls data transmission according to the current space size, including: Obtain the current space size of the CPU application layer BUF from the custom flow control packet; Determine the current data packet and the current space size, if the current data packet is less than or equal to the current space size, send the current data packet to the CPU, otherwise pause sending and wait for a new space size.
5. The method for preventing overflow of data transmitted between FPGA and CPU via Ethernet according to claim 4, characterized in that: The obtaining the current space size of the CPU application layer BUF from the custom flow control packet includes: In the initial stage, the current space size is the space size of the CPU application layer BUF; During the data transmission phase, the current space size is updated according to the following method: If the current data packet is sent successfully, the current space size is updated to: current space size - current data packet size; If a new custom flow control packet is received, the newly released space size of the CPU application layer BUF is parsed from the new custom flow control packet, and the current space size is updated to: the current space size + the newly released space size; If the current data packet is successfully sent and a new custom flow control packet is received at the same time, the current space size is updated to: current space size - size of current data packet + newly released space size.
6. An anti-overflow system for transmitting data between FPGA and CPU via Ethernet, characterized in that: It includes an FPGA and a CPU, wherein the FPGA is provided with an FPGA packet sending control logic; The CPU is used to send the current space size of the application layer BUF to the FPGA packet control logic; The FPGA packet sending control logic is used to control data transmission according to the current space size.
7. The anti-overflow system for transmitting data between FPGA and CPU via Ethernet according to claim 6, characterized in that: The CPU is specifically used to send the current space size of the application layer BUF to the FPGA packet control logic through a custom flow control packet.
8. The anti-overflow system for transmitting data between FPGA and CPU via Ethernet according to claim 7, characterized in that: The custom flow control packet carries the following information: In the initial stage, the custom flow control packet carries the space size of the CPU application layer BUF; During the data transmission phase, the custom flow control packet carries the size of the newly released space of the CPU application layer BUF.
9. The anti-overflow system for transmitting data between FPGA and CPU via Ethernet according to claim 8, characterized in that: The FPGA packet sending control logic is specifically used for: Obtain the current space size of the CPU application layer BUF from the custom flow control packet; Determine the current data packet and the current space size, if the current data packet is less than or equal to the current space size, send the current data packet to the CPU, otherwise pause sending and wait for a new space size.
10. The anti-overflow system for transmitting data between FPGA and CPU via Ethernet according to claim 8, characterized in that: The obtaining the current space size of the CPU application layer BUF from the custom flow control packet includes: In the initial stage, the current space size is the space size of the CPU application layer BUF; During the data transmission phase, the current space size is updated according to the following method: If the current data packet is sent successfully, the current space size is updated to: current space size - current data packet size; If a new custom flow control packet is received, the newly released space size of the CPU application layer BUF is parsed from the new custom flow control packet, and the current space size is updated to: the current space size + the newly released space size; If the current data packet is successfully sent and a new custom flow control packet is received at the same time, the current space size is updated to: current space size - size of current data packet + newly released space size.