High electron mobility field effect transistor with crystallographic aligned electrode region structure

Abstract

Disclosed is a high electron mobility field effect transistor having a crystal aligned electrode region structure. The high electron mobility transistor includes: a semiconductor body including a barrier region, a channel region, and a two-dimensional charge carrier gas channel; a first electrode and a second electrode both in electrical contact with the two-dimensional charge carrier gas channel; and a gate structure laterally between the first electrode and the second electrode and configured to control a conduction state of the two-dimensional charge carrier gas channel, where the gate structure includes a gate electrode and a first region of group III-V doped semiconductor material between the gate electrode and the two-dimensional charge carrier gas channel, wherein the first region of the III-V doped semiconductor material comprises a plurality of sides defining a plan view geometry of the first region, and wherein in the plan view geometry of the first region, at least two lateral boundaries of the first region that intersect one another extend along a crystallographically equivalent plane of the III-V doped semiconductor material.

Description

Background Art

[0001] Semiconductor transistors, in particular field effect controlled switching devices, such as MISFET (Metal Insulator Semiconductor Field Effect Transistor), also referred to below as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and HEMT (High Electron Mobility Field Effect Transistor), also known as Heterostructure FET (HFET) and Modulation Doped FET (MODFET) are used in various applications. HEMTs are formed of III-V semiconductor materials (e.g., Gallium Nitride (GaN), Gallium Arsenide (GaAs), etc.). HEMTs include a two-dimensional charge carrier gas created by a heterojunction between two layers of III-V semiconductor materials having different band gaps. This two-dimensional charge carrier gas provides an active device channel that accommodates the load current of the device. Due to the high mobility of carriers within the two-dimensional charge carrier gas, these devices offer very low on-resistance compared to other device technologies. For this reason, HEMTs are well suited for power switching applications and / or high frequency applications. HEMTs can be used to control voltages on the order of 5 V, 10 V, 50 V, 100 V, 250 V, 500 V, 1000 V, etc., or more, and / or control currents exceeding 1 A, 5 A, 10 A, or more. HEMTs can operate at switching frequencies on the order of 10 KHz to 50 GHz.

[0002] It is desirable to improve the steady-state conduction characteristics of a HEMT without deleteriously affecting other parameters including threshold voltage, gate current, and linear region characteristics. Summary of the invention

[0003] A high electron mobility transistor comprises: a semiconductor body comprising a barrier region of a III-V semiconductor material and a channel region of a III-V semiconductor material forming a heterojunction with the barrier region, thereby forming a two-dimensional charge carrier gas channel in the channel region; a first electrode and a second electrode, both of which are in low-ohmic contact with the two-dimensional charge carrier gas channel; and a gate structure, which is disposed laterally on an upper surface of the semiconductor body between the first electrode and the second electrode and is configured to control a conduction state of the two-dimensional charge carrier gas channel, wherein the gate structure comprises a gate electrode and a first region of a III-V doped semiconductor material between the gate electrode and the two-dimensional charge carrier gas channel, wherein the first region of the III-V doped semiconductor material comprises a plurality of side surfaces, which define a plan view geometry of the first region, and wherein in the plan view geometry of the first region, at least two mutually intersecting lateral boundaries of the first region extend along a crystallographic equivalent plane of the III-V doped semiconductor material.

[0004] A high electron mobility transistor comprises: a semiconductor body comprising a barrier region of a III-V semiconductor material and a channel region of a III-V semiconductor material forming a heterojunction with the barrier region, thereby forming a two-dimensional charge carrier gas channel in the channel region; a plurality of transistor cells formed in the semiconductor body, each of the transistor cells comprising: a first electrode and a second electrode, both of which are in electrical contact with the two-dimensional charge carrier gas channel; and a gate structure comprising a gate electrode and a first region of a III-V doped semiconductor material between the gate electrode and the two-dimensional charge carrier gas channel; and one or more regions of a III-V doped semiconductor material enclosing one of the first electrode or the second electrode and providing a first region of a III-V doped semiconductor material for each of the transistor cells, wherein the one or more regions of the III-V doped semiconductor material comprise a plurality of side surfaces defining a plan view geometry of the one or more regions, and

[0005] Wherein at least two intersecting lateral boundaries in the plan view geometry of the one or more regions extend along crystallographically equivalent planes of the III-V doped semiconductor material.

[0006] A high electron mobility transistor comprises: a semiconductor body comprising a barrier region of a III-V semiconductor material and a channel region of a III-V semiconductor material forming a heterojunction with the barrier region, thereby forming a two-dimensional charge carrier gas channel in the channel region; a first electrode and a second electrode, both of which are in electrical contact with the two-dimensional charge carrier gas channel; and a gate structure, which is disposed laterally on the upper surface of the semiconductor body between the first electrode and the second electrode and is configured to control the conduction state of the two-dimensional charge carrier gas channel, wherein the gate structure comprises a gate electrode and a first region of a III-V doped semiconductor material between the gate electrode and the two-dimensional charge carrier gas channel, wherein the first region of the III-V doped semiconductor material has a wurtzite crystal structure, and wherein from the perspective of a planar view of the first region, side surfaces of the first region intersect each other at integer multiples of 60°. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The elements in the drawings are not necessarily to scale with respect to each other. Similar reference numerals designate corresponding similar parts. The features of the various illustrated embodiments may be combined unless they are mutually exclusive. The embodiments are depicted in the drawings and are detailed in the subsequent description.

[0008] include Figure 1A and Figure 1B FIG. 1 illustrates a high electron mobility field effect transistor according to an embodiment. Figure 1A illustrates a high electron mobility field effect transistor from a cross-sectional view; and Figure 1BA high electron mobility field effect transistor is illustrated from a plan view perspective.

[0009] include Figure 2A and Figure 2B FIG. 2 illustrates a high electron mobility field effect transistor according to an embodiment. Figure 2A illustrates a high electron mobility field effect transistor from a cross-sectional view; and Figure 2B A high electron mobility field effect transistor is illustrated from a plan view perspective.

[0010] Figure 3 A high electron mobility field effect transistor from a plan view perspective according to an embodiment is illustrated.

[0011] Figure 4 A high electron mobility field effect transistor from a plan view perspective according to an embodiment is illustrated.

[0012] include Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E FIG. 5 illustrates a transistor cell layout of a high electron mobility field effect transistor according to various embodiments.

[0013] Figure 6 A high electron mobility field effect transistor from a plan view perspective according to an embodiment is illustrated.

[0014] Figure 7 A high electron mobility field effect transistor from a plan view perspective according to an embodiment is illustrated.

[0015] Figure 8 A high electron mobility field effect transistor from a plan view perspective according to an embodiment is illustrated.

[0016] Fig. 9 A high electron mobility field effect transistor from a plan view perspective according to an embodiment is illustrated. DETAILED DESCRIPTION

[0017] Embodiments of high electron mobility transistors having electrode structures including regions of III-V doped semiconductor material with favorable geometries are described herein. These electrode structures may include gate structures having doped regions of III-V semiconductor material used to adjust the threshold voltage of the device. These electrode structures may also include gate structures having regions of III-V doped semiconductor material used to reduce dynamic RDS. ONDrain structures of doped regions of III-V semiconductor materials with reduced (drain-source on-resistance). In either case, the III-V doped semiconductor material is structured so that the intersecting sides of the regions extend along crystallographically equivalent planes of the semiconductor material. This alignment of the sides is achieved by setting the intersection angles between intersecting pairs of III-V doped semiconductor materials to correspond to the natural orientation of the same axial crystallographic planes from the materials. This technique and the corresponding structure create a homogenous surface in the III-V doped semiconductor material, which results in uniform behavior and mitigates leakage.

[0018] Reference Figure 1A , a high electron mobility transistor 100 according to an embodiment is shown. The high electron mobility transistor 100 includes a semiconductor body 102. The semiconductor body 102 includes a barrier region 104 of a III-V semiconductor material, which is disposed on a channel region 106 of a III-V semiconductor material. Due to the band gap difference in the materials forming the barrier region 104 and the channel region 106, a two-dimensional charge carrier gas channel 111 is formed near the heterojunction interface between the barrier region 104 and the channel region 106. The band gap difference may arise from the difference in metal alloy concentration between the barrier region 104 and the channel region 106. Exemplary III-V semiconductor materials that can be used for barrier region 104 and channel region 106 include gallium nitride (GaN), gallium arsenide (GaAs), aluminum arsenide (AlAs), indium nitride (InN), indium arsenide (InAs), etc., and ternary or quaternary III-V materials such as aluminum gallium nitride (AlGaN), aluminum gallium arsenide (AlGaAs), indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), etc. In general, the two-dimensional charge carrier gas channel 111 can be a 2DEG (two-dimensional electron gas) or a 2DHG (two-dimensional hole gas). According to an embodiment, barrier region 104 is a region of AlGaN, channel region 106 is a region of GaN or AlGaN having a lower aluminum content than barrier region 104, and two-dimensional charge carrier gas channel 111 is a 2DEG.

[0019] The semiconductor body 102 further includes a base substrate 108. The base substrate 108 is a lower portion of the semiconductor body 102, which is below an active region formed by the barrier region 104 and the channel region 106. The base substrate 108 may correspond to a semiconductor region used for epitaxial growth of a III-type nitride semiconductor material thereon. The base substrate 108 may include a variety of semiconductor materials, such as silicon (Si), sapphire, silicon carbide (SiC), or silicon germanium (SiGe), etc. The base substrate 108 may be provided by a commercially available semiconductor wafer, such as a bulk silicon wafer or a SOI (silicon on insulator) wafer.

[0020] The semiconductor body 102 may additionally include an intermediate region 110 disposed between the base substrate 108 and the active region. The intermediate region 110 may include a plurality of different regions or layers not specifically identified in the figure. For example, the intermediate region 110 may include a lattice transition region configured to relieve mechanical stress attributable to a crystal lattice mismatch between the base substrate 108 and the active region formed by the barrier region 104 and the channel region 106. For example, the lattice transition region may include different layers of III-V semiconductor materials, such as GaN / AlGaN / AlN layers with varying alloy contents. Separately or in combination, the intermediate region 110 may include a back barrier region that is adjacent to the lower side of the channel region 106 and is configured to increase carrier confinement in the channel region 106 and prevent leakage through the lower portion of the semiconductor body 102. For example, the back barrier region 104 may include AlGaN having a higher aluminum content than the channel region 106 , and may be optionally doped with C and / or Fe.

[0021] The high electron mobility transistor 100 includes a source electrode 112 and a drain electrode 114, which are disposed on an upper surface 116 of the semiconductor body 102. The source electrode 112 and the drain electrode 114 are spaced apart from each other laterally in the current flow direction D1 of the device. The source electrode 112 and the drain electrode 114 are both in electrical contact with the two-dimensional charge carrier gas channel 111. This electrical contact can be effected by a trench that extends into the upper surface 116 (not shown in FIG. 1) of the semiconductor body 102 and is filled with a conductive metal or a doped semiconductor. The connection between the source electrode 112 and the drain electrode 114 can be a low-ohmic (i.e., non-rectifying) connection, or can have a rectifying (i.e., Schottky) behavior.

[0022] The high electron mobility transistor 100 includes a gate structure 118 disposed laterally on an upper surface 116 of the semiconductor body 102 between a source electrode 112 and a drain electrode 114. The gate structure 118 includes: a gate electrode 120; and a first region 122 of a III-V doped semiconductor material, which is between the gate electrode 120 and the two-dimensional charge carrier gas channel 111. The gate electrode 120 may be formed of a conductive material, such as tungsten, aluminum, titanium, titanium nitride, a highly doped single crystal or polycrystalline semiconductor, etc. The first region 122 of the III-V doped semiconductor material is configured to locally deplete the two-dimensional charge carrier gas channel 111 in the absence of a gate bias, thereby configuring the high electron mobility transistor 100 as a normally closed device. According to an embodiment, the first region 122 of the III-V doped semiconductor material includes p-type GaN or an alloy thereof, such as p-type AlGaN. Such a structure may be used to generate an electric field that depletes the two-dimensional charge carrier gas channel 111 as a 2DEG. Device parameters including the thickness of the first region 122 of the III-V doped semiconductor material, the dopant concentration of the first region 122 of the III-V doped semiconductor material, and the distance between the first region 122 of the III-V doped semiconductor material and the two-dimensional charge carrier gas channel 111 can be tailored so that the two-dimensional charge carrier gas channel 111 under the gate structure 118 is depleted at zero gate-source bias, thereby configuring the high electron mobility transistor 100 as a normally-off device. In the depicted embodiment, the barrier region 104 has a uniform thickness under and outside the gate structure 118. In other embodiments, the thickness of the barrier region 104 can be modulated to locally increase or decrease the separation distance between the gate structure 118 and the two-dimensional charge carrier gas channel 111.

[0023] The high electron mobility transistor 100 may include additional layers and / or structures, which are not shown for the sake of simplicity, on the upper surface 116 of the semiconductor body 102. These additional layers and / or structures may include further semiconductor layers, such as capping layers, electrically insulating layers and / or protective layers (e.g. passivation layers, interlayer dielectrics, etc.), metallization layers (e.g. metal contact pads, bonding pads, etc.).

[0024] The working principle of the high electron mobility transistor 100 is as follows. The gate structure 118 is configured to control the conductive connection between the source electrode 112 and the drain electrode 114 by controlling the conductive state of the two-dimensional charge carrier gas channel 111. The gate structure 118 provides on / off control by electrical modulation of the two-dimensional charge carrier gas channel 111 that depletes the carriers under the gate structure 118 or repopulates it. In the case of a normally closed device, the two-dimensional charge carrier gas channel 111 is depleted under the two-dimensional charge carrier gas channel 111 at zero gate-source bias. The device is turned on by applying a gate-source bias that changes the electric field under the gate structure 118, thereby populating the two-dimensional charge carrier gas channel 111 under the gate structure 118 and completing the electrical connection between the source electrode 112 and the drain electrode 114. The normally-on device operates similarly, except that a negative gate bias is applied to the gate structure 118 to deplete the two-dimensional charge carrier gas channel 111 beneath the gate structure 118 and turn off the device.

[0025] The first region 122 of the III-V doped semiconductor material is a structured material region formed on the upper surface 116 of the semiconductor body 102. According to one technique, a blanket layer of the III-V doped semiconductor material having the desired thickness and doping concentration for the first region 122 is epitaxially grown on the upper surface 116 of the semiconductor body 100, and the blanket layer is subsequently structured, for example, using a masked etching process. The first region 122 of the III-V doped semiconductor material includes side faces 124 created by the structuring process. These side faces 124 are oriented transversely to the upper surface 116 of the semiconductor body 102. For example, the side faces 124 may be perpendicular to the upper surface 116 of the semiconductor body 102.

[0026] Reference Figure 1B , the side surface 124 defines the geometry of the first region 122 from a plan view perspective. That is, when viewed from above, the side surface 124 forms a lateral boundary of the first region 122. Figure 2B , the gate electrode 120 is omitted for ease of illustration. The plan view geometry of the gate electrode 120 may mimic the plan view geometry of the first region 122. For example, the gate electrode 120 portion of the gate structure 118 may be created from a blanket layer of conductive material formed on top of a blanket layer of III-V type semiconductor material forming the first region 122, wherein the two blanket layers are structured simultaneously by a common mask or lithographic alignment mask.

[0027] The high electron mobility transistor 100 is configured such that at least two of the side surfaces 124 from the first region 122 of the III-V doped semiconductor material that intersect each other extend along crystallographically equivalent planes of the III-V semiconductor material. That is, at least one pair of side surfaces 124 that form an angled intersection with each other are arranged such that the two side surfaces 124 from the pair extend along crystallographically equivalent planes of the III-V semiconductor material. As used herein, the term "crystallographically equivalent plane" refers to a two-dimensional lattice plane that passes through a common lattice point in an underlying crystal structure.

[0028] Configuring the high electron mobility transistor 100 so that each of the intersecting pairs of side surfaces 124 extends along a crystallographically equivalent plane of the III-V semiconductor material requires that the intersection angle α between the intersecting side surfaces 124 be appropriately selected. 1 FIG. 1 shows the intersection angle α between a pair of side surfaces 124. 1 , but the following discussion is equally applicable to any pair of side surfaces 124 that intersect each other. 1 Must correspond to the angle existing between the crystallographically equivalent planes of the semiconductor material determined by the unit crystal structure below the semiconductor material. A common type of crystal in power devices is the wurtzite crystal structure. Examples of semiconductor materials with a wurtzite crystal structure include gallium nitride, aluminum nitride, boron nitride, and so-called α-SiC (silicon carbide). Therefore, in the case where the first region 122 of the III-V group doped semiconductor material is a region of p-type GaN or its alloy, it has a wurtzite crystal structure. The wurtzite crystal structure includes 6 crystallographically equivalent planes, which form a hexagon in a plane running perpendicular to the c-axis. Therefore, each intersecting pair of these crystallographically equivalent planes is oriented at 60° relative to another, and each crystallographically equivalent plane running parallel to the c-axis is oriented at an integer multiple of 60° relative to another. Thus, forming the side surfaces 124 to intersect each other and extend along a crystallographically equivalent plane of the first region 122 of the III-V doped semiconductor material may be achieved by orienting the side surfaces 124 to extend along a common axis of the material and have an intersection angle α with each other of 60° or a multiple thereof (e.g., 120°, 240°, or 300°). 1. A mask used to structure the first region 122 of the III-V doped semiconductor material can be created according to a design rule requiring each sidewall of the mask to be oriented at an integer multiple of 60°. Further, the mask can be formed so that the sidewalls of the mask are aligned with the underlying lattice planes of the semiconductor material, for example using optically detectable features. In this way, each sidewall in the III-V doped semiconductor material formed by masked etching will be aligned with a crystallographically equivalent plane. Similar considerations can be used to structure semiconductor materials having other crystal types (e.g., cubic, orthorhombic, etc.).

[0029] By configuring the high electron mobility transistor 100 so that the intersecting paired sides 124 from the first region 122 of the III-V doped semiconductor material extend along the crystallographic equivalent plane of the III-V semiconductor material, the rough surface of the III-V doped semiconductor material is eliminated from the gate structure 118. The rough surface refers to the surface of the semiconductor material including a step-shaped transition between multiple lattice planes. The rough surface may be generated by cutting or otherwise forming the semiconductor surface at an angle that deviates from the crystallographic equivalent plane of the semiconductor material, such as forming an angle that is not an integer multiple of 60° in the above wurtzite crystal structure example. The rough surface may also be generated by forming non-sharp transitions in the semiconductor material, such as rounded corners. In either case, the structuring of the material creates discrete steps and transitions at the microscopic level corresponding to the transitions between the underlying lattice planes. These rough surfaces may increase the gate-source or gate-drain leakage current by providing a path for carrier flow. The technology described herein can be used to at least reduce the presence of rough surfaces and thereby improve the leakage characteristics of the device.

[0030] According to an embodiment, each of the side surfaces 124 from the first region 122 extends along one of the crystallographically equivalent planes of the III-V doped semiconductor material. FIG. 1 may represent an example of this embodiment, wherein the first region 122 of the III-V doped semiconductor material forms a simple closed shape having a plurality of side surfaces 124 defining the geometry of the closed shape. Each of these side surfaces 124 may be arranged to extend along one of the crystallographically equivalent planes of the III-V doped semiconductor material. In particular, the first region 122 may be structured such that each intersection angle α between two side surfaces 124 is 1 In other embodiments, the intersection angle α 1 One or more of may be a multiple of 60°, such as 120°, 240° or 300°.

[0031] Reference Figure 2A, a high electron mobility transistor 100 according to another embodiment is shown. The high electron mobility transistor 100 is the same as the transistor in FIG. 1 , except that the device has a modified drain structure. The drain structure includes a second region 126 of a III-V doped semiconductor material, which is disposed on an upper surface 116 of a semiconductor body 102, and the upper surface 116 of the semiconductor body 102 is bound to a drain potential by an auxiliary electrode 117. The drain structure additionally includes a drain electrode 114, which is laterally spaced apart from the second region 126 of the III-V doped semiconductor material and is disposed on the upper surface 116 of the semiconductor body 102. The drain structure including the second region 126 of the III-V doped semiconductor material is configured to reduce the dynamic RDS of the device ON The second region 126 of III-V doped semiconductor material may be formed according to techniques similar or identical to the first region 122 of III-V doped semiconductor material described above. In an embodiment, the second region 126 of III-V doped semiconductor material is a region of p-type GaN, wherein the two-dimensional charge carrier gas channel 111 is a 2DEG channel. The second region 126 of III-V doped semiconductor material includes side surfaces 124 that define the geometry of the second region 126 from a plan view perspective in a manner similar to that described above.

[0032] Reference Figure 2B According to an embodiment, the high electron mobility transistor 100 is configured such that at least two of the side surfaces 124 of the second region 126 of the III-V doped semiconductor material that intersect each other extend along crystallographically equivalent planes of the III-V doped semiconductor material. In a similar manner as described above, this avoids the formation of a rough surface in the second region 126 of the III-V doped semiconductor material, thereby improving the leakage characteristics of the device. As shown, the second region 126 of the III-V doped semiconductor material can be formed to have the same geometry as the first region 122 of the III-V doped semiconductor material. Separately or in combination, the second region 126 of the III-V doped semiconductor material can be configured such that each of its side surfaces 124 extends along one of the crystallographically equivalent planes of the III-V doped semiconductor material.

[0033] Reference Figure 3, shows a layout of a high electron mobility transistor 100 according to another embodiment. In this embodiment, the high electron mobility transistor 100 includes two drain electrodes 114, which are arranged on opposite sides of a source electrode 122. The high electron mobility transistor 100 is configured to conduct in a first current flow direction D1 between one of the source electrode 112 and the drain electrode 114, and conduct in a second current flow direction D2 between the other of the source electrode 112 and the drain electrode 114, wherein the second current flow direction D2 is antiparallel to the first current flow direction D1.

[0034] exist Figure 3 In the device of , a gate structure 118 including a first region 122 is provided from a closed ring 129 of III-V doped semiconductor material. The closed ring 129 of III-V doped semiconductor material surrounds the source electrode 112. This provides a gate structure 118 that controls current flowing in both the first current flow direction D1 and the second current flow direction D1. Similar concepts can be used to create a device having a closed ring 129 surrounding one of the drain electrodes 114 between two of the source electrodes 114, for example, as described below with reference to Figure 4 As shown in the picture.

[0035] The closed loop 129 of the III-V doped semiconductor material can be structured so that at least two of the mutually intersecting side faces 124 from the closed loop 129 extend along a crystallographically equivalent plane of the III-V doped semiconductor material in a manner similar to that described above. In particular, the closed loop 129 forms a first closed shape 128, which faces and surrounds an inner region 130, wherein the source electrode 112 is arranged within the inner region 130. According to an embodiment, at least two of the mutually intersecting side faces 124 forming the first closed shape 128 extend along a crystallographically equivalent plane of the III-V doped semiconductor material. In a specific embodiment of this case, each of the side faces 128 forming the first closed shape 128 extends along a crystallographically equivalent plane of the III-V doped semiconductor material. The closed loop 129 additionally forms a second closed shape 128, which forms a second closed shape 132 defining the outer perimeter of the closed loop 129. According to an embodiment, at least two of the side faces 124 that form the second closed shape 132 and intersect each other extend along a crystallographically equivalent plane of the III-V doped semiconductor material. In a specific embodiment of this case, each of the side faces 124 that form the second closed shape 132 extends along a crystallographically equivalent plane of the III-V doped semiconductor material.

[0036] Reference Figure 4, shows a high electron mobility transistor 100 according to another embodiment. The high electron mobility transistor 100 includes a plurality of transistor cells 200 formed in a semiconductor body 100. Each transistor cell 200 includes: a source electrode 112 and a drain electrode 114, both of which are in electrical contact with a two-dimensional charge carrier gas channel 111 (e.g., as seen in FIG. 1 ); a gate electrode 120 (e.g., as seen in FIG. 1 ); a first region 122 of a III-V doped semiconductor material, between the gate electrode 120 and the two-dimensional charge carrier gas channel 111; and a gate via 123 for electrically connecting the first region 122 of the III-V doped semiconductor material to an upper level gate metallization. This multi-cell configuration can be used to increase current carrying capacity by parallelization.

[0037] The first region 122 of III-V doped semiconductor material for each of the transistor cells 200 is provided by a plurality of closed loops of III-V doped semiconductor material. These closed loops may have a shape similar to that from reference Figure 4 The closed ring 129 of the device described is similar in geometry to the closed ring 129 of the device described. Therefore, the region 122 of the III-V doped semiconductor material forming the first region 122 of the III-V doped semiconductor material for each of the transistor cells 200 may comply with the requirement that the side surface 124 extends along a crystallographically equivalent plane of the III-V doped semiconductor material as described above. In the depicted embodiment, the closed ring is configured to surround one drain electrode 114 for each of the transistor cells 200, wherein the source electrode 112 for each of the transistor cells 200 is arranged outside the closed ring. In principle, either arrangement is possible, i.e., for each of the transistor cells 200, the closed ring may surround the drain electrode 114 or the source electrode 112.

[0038] The high electron mobility transistor 100 includes: a first row 132 of transistor cells 200; and a second row 134 of transistor cells 200, which is adjacent to the first row 132. In the depicted embodiment, each of the transistor cells 200 from the first row 132 is aligned with each of the transistor cells 200 from the second row 134 in a lateral direction LD1 parallel to the current flow direction of the transistor cells 200. That is, the source electrodes 112 and the drain electrodes 114 of the transistor cells 200 from the first row 132 are aligned with the source electrodes 112 and the drain electrodes 114 of the transistor cells 200 from the first row 132 in the lateral direction LD1. In practice, the number of transistor cells 200 per row and / or the number of rows per device may vary from what is shown.

[0039] The high electron mobility transistor 100 may include an edge termination electrode 125 disposed between the transistor cells 200 from the first row 132 and the second row 134 and the outer edge side 134 of the semiconductor body. The edge termination electrode 125 may be configured to reduce the electric field strength at the edge of the device. The edge termination electrode 125 may be connected to a fixed potential, such as a source potential. In this case, the edge termination electrode 125 is a continuous electrode structure extending adjacent to each of the transistor cells 200 from the first row 132 and the second row 134.

[0040] 5, various layouts are shown for a high electron mobility transistor 100 including a plurality of transistor cells 200. These figures show only partial views of the device to illustrate the layout of the transistor cells 200 relative to each other and the edge termination electrodes 125 are omitted.

[0041] Reference Figure 5A In this embodiment, the transistor cells 200 from the first row 132 are offset in the lateral direction LD1 from the transistor cells 200 from the second row 134. That is, the source electrodes 112 and the drain electrodes 114 of the transistor cells 200 from the first row 132 are not aligned in the lateral direction LD1 with the source electrodes 112 and the drain electrodes 114 of the transistor cells 200 from the first row 132. Furthermore, the closed loop of the III-V doped semiconductor material providing the first region 122 of the III-V doped semiconductor material for the transistor cells 200 from the first row 132 overlaps in the central region 133 of the high electron mobility transistor 100 with the closed loop of the III-V doped semiconductor material providing the first region 122 of the III-V doped semiconductor material for the transistor cells 200 from the second row 134. Due to the angled orientation of the side faces 124 of the III-V doped semiconductor dictated by the design rules, it is possible to provide a closed-loop dovetail arrangement for these partially overlapping first and second rows 132 , 134 , thereby increasing space efficiency.

[0042] Reference Figure 5B , the high electron mobility transistor 100 includes a continuous region of III-V doped semiconductor material that provides a first region 122 of III-V doped semiconductor material for each of the transistor cells 200. The continuous region includes a gate bus 136 that is connected to the first region 122 of III-V doped semiconductor material for each of the transistor cells 200. This layout may substantially correspond to Figure 5A, except that the transistor cells 200 from the first row 132 and the second row 134 are merged together. The continuous region of III-V doping can therefore meet the design requirements of the III-V doped semiconductor material 122 in each of the embodiments described above. In particular, any or all of the intersecting side surfaces 124 from the continuous region of III-V doped semiconductor material are oriented along a crystallographic equivalent plane of the III-V doped semiconductor material.

[0043] Reference Figure 5C , Figure 5D and Figure 5E , shows a further layout of the high electron mobility transistor 100. Figure 5A and Figure 5B One disadvantage of the shifted geometry of the described embodiments is that it creates areas of unused space and may require shifting of edge terminals. Figure 5C , Figure 5D and Figure 5E The embodiment of avoids this arrangement and provides a first row 132 and a second row 134 equidistant from the edge terminations. Figure 5C and Figure 5D In the embodiment of the present invention, the outermost transistor cell of transistor cells 200 from first row 132 is configured differently than each other transistor cell of transistor cells 200 from first row 132 and second row 134. As a result, first row 132 and second row 134 of transistor cells 200 terminate along the same plane. Figure 5C and Figure 5D The embodiments differ from one another only with regard to the geometry of the openings in the continuous region. Figure 5C and Figure 5D In an embodiment, the opening is adapted to eliminate sharp angles. By configuring the III-V doped semiconductor material so that each intersection between the side surfaces 134 forms an oblique angle, local high electric fields can be avoided. Figure 5E In the embodiment of the present invention, each of the transistor cells 200 from the first row 132 is aligned with each of the transistor cells 200 from the second row 134 in the lateral direction LD1 of the transistor cells 200, for example in a manner similar to that described above. However, the transistor cells 200 are merged together so that the high electron mobility transistor 100 includes a continuous region of III-V doped semiconductor material that provides a first doped region of a gate structure for each of the transistor cells 200, and includes a gate bus 136 that is connected to the first doped region of the gate structure for each of the transistor cells 200, for example in a manner similar to that described above.

[0044] Reference Figure 6, shows a layout of a high electron mobility transistor 100 according to another embodiment. In this example, the high electron mobility transistor 100 includes a gate structure 118 having a closed loop 129 of a III-V doped semiconductor material, wherein the closed loop 129 can be structured so that at least two of the sides 124 from the closed loop 129 that intersect each other extend along a crystallographic equivalent plane of the III-V semiconductor material in a manner similar to that described above. Additionally, the high electron mobility transistor 100 is configured with a drain structure that includes a second region 126 of a III-V doped semiconductor material. In this case, the second region 126 of the III-V doped semiconductor material is structured so that at least two of the sides 124 from the second region 126 of the III-V doped semiconductor material that intersect each other extend along a crystallographic equivalent plane of the III-V semiconductor material in a manner similar to that described above. In this case, the second region 126 of the III-V doped semiconductor material is configured as an elongated strip within the confines of the drain electrode 114.

[0045] Reference Figure 7 , shows a layout of a high electron mobility transistor 100 according to another embodiment. Figure 7 The high electron mobility transistor 100 and Figure 6 The high electron mobility transistor 100 of FIG. 1 is different in that the drain structure is configured with a plurality of second regions 126 of III-V doped semiconductor material around the perimeter of the drain electrode 114. On the right side of the figure, two possible variations are shown. In each case, the second region 126 is disposed at the terminating end of the elongated drain electrode 114. These second regions 126 may be provided in addition to or in place of the plurality of second regions 126 of III-V doped semiconductor material shown on the left side of the figure.

[0046] Reference Figure 8 , shows a layout of a high electron mobility transistor 100 according to another embodiment. In this case, the high electron mobility transistor 100 is configured as a bidirectional switch, wherein the device is configured to conduct in either direction between two source electrodes 112 depending on the bias polarity between these source electrodes 112. In this device, the high electron mobility transistor 100 includes a gate structure 118 having a closed loop 129 of a III-V doped semiconductor material, which can be structured so that at least two of the sides 124 from the closed loop 129 that intersect each other extend along a crystallographic equivalent plane of the III-V semiconductor material in a similar manner as described above.

[0047] Reference Fig. 9, shows a layout of a high electron mobility transistor 100 according to another embodiment. Fig. 9 The high electron mobility transistor 100 is Figure 8 The device is configured in a similar manner as a bidirectional switch. Fig. 9 The high electron mobility transistor 100 and Figure 8 The HEMT 100 of FIG. 1 differs in that the closed loops 129 of the gate structure 118 are merged together to form a single continuous structure.

[0048] Although the present disclosure is not so limited, the following numbered examples demonstrate one or more aspects of the present disclosure.

[0049] Example 1. A high electron mobility transistor, comprising: a semiconductor body, which includes a barrier region of a III-V semiconductor material and a channel region of a III-V semiconductor material forming a heterojunction with the barrier region, thereby forming a two-dimensional charge carrier gas channel in the channel region; a first electrode and a second electrode, both of which are in electrical contact with the two-dimensional charge carrier gas channel; and a gate structure, which is laterally disposed on the upper surface of the semiconductor body between the first electrode and the second electrode, and is configured to control the conduction state of the two-dimensional charge carrier gas channel, wherein the gate structure includes a gate electrode and a first region of a III-V doped semiconductor material between the gate electrode and the two-dimensional charge carrier gas channel, wherein the first region of the III-V doped semiconductor material includes a plurality of side surfaces, which define a plan view geometry of the first region, and wherein at least two mutually intersecting lateral boundaries of the first region in the plan view geometry of the first region extend along a crystallographic equivalent plane of the III-V doped semiconductor material.

[0050] Example 2. The high electron mobility transistor of Example 1, wherein the first region of the III-V doped semiconductor material has a wurtzite crystal structure, and wherein at least two mutually intersecting lateral boundaries of the first region are oriented at an integer multiple of 60° relative to each other.

[0051] Example 3. The high electron mobility transistor of Example 2, wherein the first region of the III-V doped semiconductor material is configured to deplete the two-dimensional charge carrier gas channel under zero gate bias.

[0052] Example 4. The high electron mobility transistor of Example 3, wherein the two-dimensional charge carrier gas channel is a two-dimensional electron gas, and wherein the first region of group III-V doped semiconductor material is a region of p-type GaN or an alloy thereof.

[0053] Example 5. The high electron mobility transistor of Example 1, further comprising: a second region of III-V doped semiconductor material, which is disposed on the upper surface of the semiconductor body and is electrically connected to the second electrode, wherein the second region of III-V doped semiconductor material includes a second plurality of side surfaces that define a plan view geometry of the second region, wherein at least two mutually intersecting lateral boundaries of the second region in the plan view geometry of the second region extend along a crystallographically equivalent plane of the III-V doped semiconductor material.

[0054] Example 6. The high electron mobility transistor of Example 5, wherein the second region of group III-V doped semiconductor material is a region of p-type GaN or an alloy thereof.

[0055] Example 7. The high electron mobility transistor of Example 1, wherein each of the lateral boundaries of the first region extends along one of the crystallographically equivalent planes of the III-V doped semiconductor material.

[0056] Example 8. The high electron mobility transistor of Example 1, wherein the high electron mobility transistor comprises a closed ring of a III-V doped semiconductor material providing a first region, and wherein a side of the closed ring forms a first closed shape facing and enclosing an inner region in a plan view geometry of the first region, wherein a first electrode or a second electrode is arranged within the inner region, and wherein each lateral boundary from the first closed shape extends along a crystallographically equivalent plane of the III-V doped semiconductor material.

[0057] Example 9. The high electron mobility transistor of Example 8, wherein the side surfaces of the closed loop form a second closed shape in the plan view geometry of the first region, the second closed shape forms an outer perimeter of the closed loop, and wherein each lateral boundary from the second closed shape extends along one of the crystallographically equivalent planes of the III-V doped semiconductor material.

[0058] Example 10. A high electron mobility transistor, comprising: a semiconductor body comprising a barrier region of a III-V semiconductor material and a channel region of a III-V semiconductor material forming a heterojunction with the barrier region, thereby forming a two-dimensional charge carrier gas channel in the channel region; a plurality of transistor units formed in the semiconductor body, each of the transistor units comprising: a first electrode and a second electrode, both of which are in electrical contact with the two-dimensional charge carrier gas channel; and a gate structure comprising a gate electrode and a first region of a III-V doped semiconductor material between the gate electrode and the two-dimensional charge carrier gas channel; and one or more regions of a III-V doped semiconductor material enclosing one of the first electrode or the second electrode and providing a first region of a III-V doped semiconductor material for each of the transistor units, wherein the one or more regions of the III-V doped semiconductor material include a plurality of side surfaces defining a plan view geometry of the one or more regions, and wherein at least two intersecting lateral boundaries in the plan view geometry of the one or more regions extend along a crystallographically equivalent plane of the III-V doped semiconductor material.

[0059] Example 11. A high electron mobility transistor of Example 10, wherein the plurality of transistor cells include: a first row of transistor cells; and a second row of transistor cells adjacent to the first row, and wherein at least some of the transistor cells from the first row are aligned with transistor cells from the second row in a current flow direction of the transistor cells.

[0060] Example 12. A high electron mobility transistor of Example 10, wherein the plurality of transistor cells comprises: a first row of transistor cells; and a second row of transistor cells adjacent to the first row, and wherein transistor cells from the first row are offset from transistor cells from the second row in a direction of current flow of the transistor cells.

[0061] Example 13. The high electron mobility transistor of Example 12, wherein the one or more regions of III-V doped semiconductor material include multiple closed loops of III-V doped semiconductor material, and wherein the closed loops of the first regions of III-V doped semiconductor material provided for transistor cells from a first row overlap with the closed loops of the first regions of III-V doped semiconductor material provided for transistor cells from a second row in a central region of the high electron mobility transistor.

[0062] Example 14. The high electron mobility transistor of Example 13, wherein at least two intersecting lateral boundaries of the lateral boundaries from each of the closed loops extend along a crystallographically equivalent plane of the III-V doped semiconductor material.

[0063] Example 15. The high electron mobility transistor of Example 12, wherein the one or more regions of III-V doped semiconductor material include a continuous region of III-V doped semiconductor material that provides a first region of a gate structure for each of the transistor cells, and wherein the continuous region includes a gate bus that is connected to the first region of the gate structure for each of the transistor cells.

[0064] Example 16. The high electron mobility transistor of Example 15, wherein each of the lateral boundaries from the continuous region extends along one of the crystallographically equivalent planes of the III-V doped semiconductor material.

[0065] Example 17. The high electron mobility transistor of Example 10, wherein the multiple transistor cells include: a first row of transistor cells; and a second row of transistor cells adjacent to the first row, wherein the high electron mobility transistor also includes a continuous edge termination electrode disposed between the outermost transistor cell from the first row and the second row of transistor cells and the outer edge side of the semiconductor body.

[0066] Example 18. The high electron mobility transistor of Example 17, wherein transistor cells from a first row are offset from transistor cells from a second row in a direction of current flow in the transistor cells, and wherein an outermost transistor cell from the first row is configured differently from each other transistor cell from the first row and the second row.

[0067] Example 19. The high electron mobility transistor of Example 10, wherein the III-V doped semiconductor material has a wurtzite crystal structure, and wherein at least two intersecting lateral boundaries of the side surfaces are oriented at an integer multiple of 60° relative to each other.

[0068] Example 20. A high electron mobility transistor, comprising: a semiconductor body, which includes a barrier region of a III-V semiconductor material and a channel region of a III-V semiconductor material forming a heterojunction with the barrier region, thereby forming a two-dimensional charge carrier gas channel in the channel region; a first electrode and a second electrode, both of which are in electrical contact with the two-dimensional charge carrier gas channel; and a gate structure, which is laterally disposed on the upper surface of the semiconductor body between the first electrode and the second electrode, and is configured to control the conduction state of the two-dimensional charge carrier gas channel, wherein the gate structure includes a gate electrode and a first region of a III-V doped semiconductor material between the gate electrode and the two-dimensional charge carrier gas channel, wherein the first region of the III-V doped semiconductor material has a wurtzite crystal structure, and wherein from a planar view perspective of the first region, the side faces of the first region intersect with each other at integer multiples of 60°.

[0069] As used herein, for example, the term "III-V semiconductor material" refers to a compound material that includes: at least one III-group element, such as aluminum (Al), gallium (Ga), indium (In), and boron (B); and at least one V-group element, such as nitrogen (N), phosphorus (P), and arsenic (As), and includes but is not limited to any alloys thereof, such as aluminum gallium nitride (AlxGa(1-x)N), indium gallium nitride (InyGa(1-y)N), aluminum indium gallium nitride (AlxInyGa(1-xy)N), gallium arsenic nitride phosphide (GaAsaPbN(1-ab)), and aluminum indium gallium arsenic phosphide nitride (AlxInyGa(1-xy)AsaPbN(1-ab)). Aluminum gallium nitride and AlGaN refer to alloys described by the molecular formula AlxGa(1-x)N, where 0 <x<1。

[0070] The term HEMT is also commonly referred to as HFET (heterostructure field effect transistor), MODFET (modulation doped FET), and MESFET (metal semiconductor field effect transistor). The terms HEMT, HFET, MESFET, and MODFET are used interchangeably herein to refer to any III-V compound-based semiconductor transistor that incorporates a junction between two materials with different band gaps (i.e., a heterojunction) as a channel.

[0071] Spatially relative terms such as "under," "below," "down," "above," and "upper" are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the device in addition to different orientations that are different from the orientations depicted in the figures. Further, terms such as "first," "second," and the like are also used to describe various elements, regions, sections, and the like, and are also not intended to be limiting. Similar terms are used throughout the description to refer to similar elements.

[0072] As used herein, the terms "having," "comprising," "including," and "comprising," etc. are open-ended terms indicating the presence of stated elements or features, but do not exclude additional elements or features. The quantifiers "a," "an," and the pronoun "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0073] With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description nor by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.

Claims

1. A high electron mobility transistor, comprising: A semiconductor body comprising a barrier region of a III-V semiconductor material and a channel region of a III-V semiconductor material forming a heterojunction with the barrier region, thereby forming a two-dimensional charge carrier gas channel in the channel region; a first electrode and a second electrode, both of which are in electrical contact with the two-dimensional charge carrier gas channel; as well as a gate structure disposed laterally on an upper surface of the semiconductor body between the first electrode and the second electrode and configured to control a conduction state of the two-dimensional charge carrier gas channel, wherein the gate structure comprises a gate electrode and a first region of III-V doped semiconductor material between the gate electrode and the two-dimensional charge carrier gas channel, wherein the first region of the III-V doped semiconductor material includes a plurality of sides defining a plan view geometry of the first region, and Wherein in the plan view geometry of the first region, at least two mutually intersecting lateral boundaries of the first region extend along crystallographically equivalent planes of the III-V doped semiconductor material.

2. The high electron mobility transistor of claim 1, wherein the first region of III-V doped semiconductor material has a wurtzite crystal structure, and wherein at least two mutually intersecting lateral boundaries of the first region are oriented at an integer multiple of 60° relative to each other. 3 . The high electron mobility transistor of claim 2 , wherein the first region of III-V doped semiconductor material is configured to deplete the two-dimensional charge carrier gas channel under zero gate bias.

4. A high electron mobility transistor as claimed in claim 3, wherein the two-dimensional charge carrier gas channel is a two-dimensional electron gas, and wherein the first region of group III-V doped semiconductor material is a region of p-type GaN or an alloy thereof.

5. The high electron mobility transistor according to claim 1, further comprising: a second region of III-V doped semiconductor material disposed on the upper surface of the semiconductor body and electrically connected to the second electrode, wherein the second region of the III-V doped semiconductor material includes a second plurality of sides defining a plan view geometry of the second region, Wherein in the plan view geometry of the second region, at least two mutually intersecting lateral boundaries of the second region extend along crystallographically equivalent planes of the III-V doped semiconductor material. 6 . The high electron mobility transistor of claim 5 , wherein the second region of III-V doped semiconductor material is a region of p-type GaN or an alloy thereof. 7 . The high electron mobility transistor of claim 1 , wherein each of the lateral boundaries of the first region extends along one of the crystallographically equivalent planes of the III-V doped semiconductor material.

8. A high electron mobility transistor as described in claim 1, wherein the high electron mobility transistor comprises a closed ring of a III-V doped semiconductor material, which provides a first region, and wherein the side surfaces of the closed ring form a first closed shape facing and surrounding an inner region in a plan view geometry of the first region, wherein the first electrode or the second electrode is arranged within the inner region, and wherein each lateral boundary from the first closed shape extends along a crystallographically equivalent plane of the III-V doped semiconductor material.

9. A high electron mobility transistor as described in claim 8, wherein the side of the closed loop forms a second closed shape in the plan view geometry of the first region, the second closed shape forms an outer perimeter of the closed loop, and wherein each lateral boundary from the second closed shape extends along one of the crystallographically equivalent planes of the III-V doped semiconductor material.

10. A high electron mobility transistor, comprising: A semiconductor body comprising a barrier region of a III-V semiconductor material and a channel region of a III-V semiconductor material forming a heterojunction with the barrier region, thereby forming a two-dimensional charge carrier gas channel in the channel region; A plurality of transistor cells formed in a semiconductor body, each of the transistor cells comprising: a first electrode and a second electrode, both of which are in electrical contact with the two-dimensional charge carrier gas channel; and a gate structure comprising a gate electrode and a first region of a III-V doped semiconductor material between the gate electrode and the two-dimensional charge carrier gas channel; and one or more regions of III-V doped semiconductor material enclosing one of the first electrode or the second electrode and providing a first region of III-V doped semiconductor material for each of the transistor cells, wherein the one or more regions of Group III-V doped semiconductor material include a plurality of sides defining a plan view geometry of the one or more regions, and Wherein at least two intersecting lateral boundaries in the plan-view geometry of the one or more regions extend along crystallographically equivalent planes of the III-V doped semiconductor material.

11. The high electron mobility transistor of claim 10, wherein the plurality of transistor units comprises: The first row of transistor cells; and a second row of transistor cells adjacent to the first row and wherein at least some of the transistor cells from the first row are aligned with transistor cells from the second row in a current flow direction of the transistor cells.

12. The high electron mobility transistor of claim 10, wherein the plurality of transistor cells comprises: The first row of transistor cells; and a second row of transistor cells adjacent to the first row and wherein the transistor cells from the first row are offset from the transistor cells from the second row in a current flow direction of the transistor cells.

13. A high electron mobility transistor as described in claim 12, wherein the one or more regions of III-V doped semiconductor material include multiple closed loops of III-V doped semiconductor material, and wherein the closed loop of the first region of III-V doped semiconductor material provided for transistor cells from a first row overlaps with the closed loop of the first region of III-V doped semiconductor material provided for transistor cells from a second row in a central region of the high electron mobility transistor.

14. The high electron mobility transistor of claim 13, wherein at least two intersecting lateral boundaries from each of the closed loops extend along a crystallographically equivalent plane of the III-V doped semiconductor material.

15. A high electron mobility transistor as described in claim 12, wherein the one or more regions of III-V doped semiconductor material include a continuous region of III-V doped semiconductor material that provides a first region of a gate structure for each of the transistor cells, and wherein the continuous region includes a gate bus that is connected to the first region of the gate structure for each of the transistor cells.

16. A high electron mobility transistor as claimed in claim 15, wherein each of the lateral boundaries from the continuous region extends along one of the crystallographically equivalent planes of the III-V doped semiconductor material.

17. The high electron mobility transistor of claim 10, wherein the plurality of transistor cells comprises: The first row of transistor cells; and a second row of transistor cells adjacent to the first row, wherein the high electron mobility transistor further comprises a continuous edge termination electrode disposed between an outermost transistor cell from the first and second rows of transistor cells and an outer edge side of the semiconductor body.

18. A high electron mobility transistor as described in claim 17, wherein the transistor cells from the first row are offset from the transistor cells from the second row in a current flow direction of the transistor cells, and wherein the outermost transistor cell from the transistor cells from the first row is configured differently from each other transistor cell from the first row and the second row.

19. The high electron mobility transistor of claim 10, wherein the III-V doped semiconductor material has a wurtzite crystal structure, and wherein at least two intersecting lateral boundaries of the side surfaces are oriented at an integer multiple of 60° relative to each other.

20. A high electron mobility transistor, comprising: A semiconductor body comprising a barrier region of a III-V semiconductor material and a channel region of a III-V semiconductor material forming a heterojunction with the barrier region, thereby forming a two-dimensional charge carrier gas channel in the channel region; a first electrode and a second electrode, both of which are in electrical contact with the two-dimensional charge carrier gas channel; as well as a gate structure disposed laterally on an upper surface of the semiconductor body between the first electrode and the second electrode and configured to control a conduction state of the two-dimensional charge carrier gas channel, wherein the gate structure comprises a gate electrode and a first region of III-V doped semiconductor material between the gate electrode and the two-dimensional charge carrier gas channel, wherein the first region of the III-V group doped semiconductor material has a wurtzite crystal structure, and From the perspective of a plan view of the first region, side surfaces of the first region intersect each other at an integral multiple of 60°.

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