Semiconductor structure, distance measuring sensor chip and working method and device

Abstract

The embodiment of the invention provides a semiconductor structure, a distance measuring sensor chip, a working method and equipment, relates to the technical field of electronics, and is used for optimizing the performance of the distance measuring sensor chip. By utilizing the characteristics of in-chip integration and non-volatility of a nonvolatile memory, a scheme of integrating the nonvolatile memory in a distance measuring sensor chip is adopted to replace a scheme of adding a plug-in nonvolatile memory to an in-chip volatile memory in a traditional distance measuring sensor chip; a nonvolatile memory is used for providing storage requirements for a processor and a functional circuit in the distance measuring sensor chip. A plurality of beneficial functions of simplifying the architecture, saving the area, reducing the time delay, simplifying the hardware single board solution and the like are realized.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a semiconductor structure, a ranging sensor chip, and a working method and device. Background Art

[0002] A distance sensor can measure the distance between an object and the distance sensor. For example, a time of flight (ToF) sensor is a sensor that uses the principle of optics to measure distance. A ToF sensor uses a tiny laser to emit infrared light, where the light generated bounces off any object and returns to the ToF sensor. Based on the time difference between the emission of light and the time it reflects off the object and returns to the ToF sensor, the ToF sensor can measure the distance between the object and the ToF sensor.

[0003] ToF sensors can be widely used in devices that need to detect distance, and the performance of ToF sensors directly affects the performance of the devices. Summary of the invention

[0004] The embodiments of the present application provide a semiconductor structure, a ranging sensor chip, and a working method and device for optimizing the performance of the ranging sensor chip.

[0005] In order to achieve the above objectives, this application adopts the following technical solutions:

[0006] In a first aspect of an embodiment of the present application, a semiconductor structure is provided, which is applied to a distance measuring sensor chip including a photoelectric conversion module. The semiconductor structure can be a bare chip or a packaged chip. The semiconductor structure includes a non-volatile memory, an analog front end, and a processor. The non-volatile memory is used to store software code; the analog front end is used to couple with the photoelectric conversion module, receive the electrical signal output by the photoelectric conversion module, and process the electrical signal and output it; the processor is coupled with the non-volatile memory and the analog front end, and is used to read the software code to process the signal output by the analog front end to generate distance data.

[0007] The semiconductor structure provided in the embodiment of the present application has a non-volatile memory integrated inside, and the software code required for the semiconductor structure to perform processing operations is directly stored in the non-volatile memory inside the semiconductor structure, and is no longer stored in an external non-volatile memory. In this way, when the semiconductor structure performs processing operations, the processor can directly retrieve the software code from the non-volatile memory without having to go through the process of loading from the external non-volatile memory to the internal volatile memory, so that the startup speed of the semiconductor structure is fast, the workflow is simple, and the delay of the semiconductor structure can be reduced. Moreover, by utilizing the characteristics of the non-volatile memory being integrated on-chip and non-volatile, instead of the external non-volatile memory required by the traditional semiconductor structure, the architecture of the semiconductor structure can be streamlined, area can be saved, and the hardware single-board solution can be simplified.

[0008] In a possible implementation, the volatile memory is further used to store curing parameters representing the identity information of the semiconductor structure; and the processor is further used to read and / or write the curing parameters.

[0009] Using non-volatile memory to implement the function of one-time programmable memory can reduce the possibility of memory data being deduced through reverse observation under a microscope, and increase the safety of the semiconductor structure. In addition, by using non-volatile memory instead of one-time programmable memory, there is no need to set up one-time programmable memory in the semiconductor structure, and the types of memory in the semiconductor structure are reduced, which can simplify the preparation process and layout difficulty of the semiconductor structure.

[0010] In one possible implementation, the semiconductor structure further includes a statistical analysis circuit, which is used to perform statistical analysis on the signal output by the analog front end and output the processing result to the processor. By performing preliminary statistical analysis on the signal output by the analog front end through the hardware statistical analysis circuit and then transmitting the result to the processor for processing, the accuracy and efficiency of the processor can be improved.

[0011] In a possible implementation, the semiconductor structure further includes a statistical analysis circuit, which is coupled between the analog front end and the processor. The hardware statistical analysis circuit performs preliminary statistical analysis on the signal output by the analog front end, and then transmits the result to the processor for processing, which can improve the accuracy and efficiency of the processor.

[0012] In a possible implementation, the statistical analysis circuit includes a statistical circuit, a compensation circuit, a low-pass filter circuit, a noise calculation circuit, an echo detection circuit, and an echo analysis circuit; the statistical circuit is used to perform statistical processing on the signal output by the analog front end and then output it; the compensation circuit is used to perform compensation processing on the received signal and then output it; the low-pass filter circuit is used to filter out the noise signal in the received signal and then output it; the noise calculation circuit is used to calculate the noise signal in the received signal and output it; the echo detection circuit is used to detect the peak information of the received signal and output it; the echo analysis circuit is used to analyze the received signal and output the analysis result to the processor. This statistical analysis circuit has a simple structure and high accuracy.

[0013] In a possible implementation, the statistical analysis circuit includes a statistical circuit, a compensation circuit, a low-pass filter circuit, a noise calculation circuit, an echo detection circuit, and an echo analysis circuit; the statistical circuit is coupled to the analog front end; the compensation circuit is coupled to the statistical circuit; the low-pass filter circuit is coupled to the compensation circuit; the noise calculation circuit is coupled to the low-pass filter circuit; the echo detection circuit is coupled to the noise calculation circuit; and the echo analysis circuit is coupled to the echo detection circuit and the processor. This statistical analysis circuit has a simple structure and high accuracy.

[0014] In a possible implementation, at least one of the statistical circuit, the low-pass filter circuit, and the echo detection circuit is also coupled to a non-volatile memory. By using a non-volatile memory to provide a storage function for the statistical analysis circuit, there is no need to set up a static random access memory in the semiconductor structure, and the types of memories in the semiconductor structure are reduced, which can simplify the preparation process and layout difficulty of the semiconductor structure and reduce the area and power consumption of the semiconductor structure.

[0015] In a possible implementation, the semiconductor structure further includes a volatile memory; at least one of the statistical circuit, the low-pass filter circuit, the echo detection circuit, and the processor is also coupled to the volatile memory. The volatile memory is used to provide a storage function for the statistical analysis circuit, which can improve the access speed of the statistical analysis circuit.

[0016] In one possible implementation, the semiconductor structure further includes an input / output interface, which is coupled to the non-volatile memory and is used to write or read data from the outside of the semiconductor structure. In this way, data stored in the external memory can be transferred to the non-volatile memory via the input / output interface to meet different needs.

[0017] In a possible implementation, the non-volatile memory includes one or more of a flash memory, a magnetoresistive random access memory, a resistive random access memory, a phase change random access memory, and a ferroelectric memory. This is an implementation with a simple structure.

[0018] According to a second aspect of an embodiment of the present application, a ranging sensor chip is provided, comprising a semiconductor structure and a photoelectric conversion module; the semiconductor structure is coupled to the photoelectric conversion module; and the semiconductor structure comprises any semiconductor structure of the first aspect.

[0019] The ranging sensor chip provided in the second aspect of the embodiment of the present application includes the semiconductor structure in the first aspect, and its beneficial effects are the same as those of the semiconductor structure, which will not be described in detail here.

[0020] According to a third aspect of the embodiments of the present application, a device is provided, including a ranging sensor chip and a controller, wherein the ranging sensor chip is coupled to the controller; the ranging sensor chip includes the ranging sensor chip according to the second aspect.

[0021] The device provided in the third aspect of the embodiment of the present application includes the semiconductor structure of the first aspect, and its beneficial effects are the same as those of the semiconductor structure, which will not be repeated here.

[0022] According to a fourth aspect of an embodiment of the present application, a working method of a ranging sensor chip is provided, wherein the ranging sensor chip comprises a semiconductor structure and a photoelectric conversion module; the semiconductor structure comprises a non-volatile memory, an analog front end and a processor; the working method comprises: the analog front end receives an electrical signal output by the photoelectric conversion module, processes the electrical signal and outputs the signal; the processor directly reads a software code from the non-volatile memory to process the signal output by the analog front end and generates distance data.

[0023] In the working method of the ranging sensor chip provided in the embodiment of the present application, the software code required by the processor for processing operations is directly stored in the non-volatile memory inside the semiconductor structure, and is no longer stored in the external non-volatile memory. In this way, when the semiconductor structure performs processing operations, the processor can directly retrieve the software code from the non-volatile memory without going through the process of loading from the external non-volatile memory to the internal volatile memory. The ranging sensor chip has a fast startup speed and a simple workflow, which can reduce the delay of the semiconductor structure.

[0024] In a possible implementation, the working method further includes: at the power-on startup moment, the processor directly reads the solidification parameters representing the identity information of the semiconductor structure from the non-volatile memory.

[0025] The fixed parameters required for the startup of the ranging sensor chip are directly stored in the non-volatile memory inside the semiconductor structure, rather than in the external non-volatile memory. In this way, during the power-on startup process, the ranging sensor chip can directly retrieve the fixed parameters from its internal non-volatile memory, without having to go through the process of loading the fixed parameters from the external non-volatile memory to the internal volatile memory. The startup speed of the ranging sensor chip is fast, the workflow is simple, and the delay of the ranging sensor chip can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 An appearance diagram of a device provided in an embodiment of the present application;

[0027] Figure 2 A schematic diagram of the structure of a distance measuring sensor chip according to an embodiment of the present application;

[0028] Figure 3A-3C A topological schematic diagram of a semiconductor structure provided in an embodiment of the present application;

[0029] Figure 4 A diagram showing the relationship between a circuit in a semiconductor structure and a non-volatile memory provided in an embodiment of the present application;

[0030] Figure 5 A diagram showing the relationship between a circuit in another semiconductor structure and a non-volatile memory provided in an embodiment of the present application;

[0031] Figure 6 A diagram showing the relationship between a circuit in another semiconductor structure and a non-volatile memory provided in an embodiment of the present application;

[0032] Figure 7 A diagram showing the relationship between a circuit in another semiconductor structure and a non-volatile memory provided in an embodiment of the present application;

[0033] Figure 8 A diagram showing the relationship between a circuit in another semiconductor structure and a non-volatile memory provided in an embodiment of the present application;

[0034] Fig. 9 A diagram showing the relationship between a circuit in another semiconductor structure and a non-volatile memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0036] In the following, the terms "second", "first", etc. are used only for convenience of description and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "second", "first", etc. may explicitly or implicitly include one or more of the feature. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0037] In addition, in the embodiments of the present application, directional terms such as "up", "down", "left" and "right" may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.

[0038] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. In addition, the term "coupled" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be a direct contact or an indirect contact through an intermediate medium.

[0039] In the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B may be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0040] The embodiment of the present application provides a device, which is, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, etc. with a range finding requirement. Among them, consumer electronic products are such as mobile phones, tablet computers (pads), laptop computers, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop displays, smart wearable products (e.g., smart watches, smart bracelets), virtual reality (VR) devices, augmented reality (AR) devices, drones, etc. Home electronic products are such as smart door locks, rechargeable small household appliances (e.g., sweeping robots), etc. Vehicle-mounted electronic products are such as vehicle-mounted navigators, cars, etc. The embodiment of the present application does not impose any special restrictions on the specific forms of the above-mentioned devices.

[0041] Figure 1This is an appearance diagram of a device provided in an embodiment of the present application.

[0042] In some embodiments, Figure 1 As shown, the embodiment of the present application is illustrated by taking the device 1 as a vehicle as an example. Of course, the embodiment of the present application does not limit the device 1 to a vehicle, and the device 1 can be any device with a distance measurement requirement, and the device 1 includes the distance measurement sensor chip provided in the embodiment of the present application.

[0043] For example, a vehicle may include a ranging sensor chip 10 and a controller 40. The ranging sensor chip 10 is used to generate distance data and transmit the distance data to the controller 40 for corresponding control processing. For example, the ranging sensor chip 10 detects the distance data, and the controller 40 performs control processing, and combines with other components in the vehicle to realize automatic driving of the vehicle.

[0044] Of course, the vehicle can be a fuel vehicle, a new energy vehicle, or a hybrid vehicle.

[0045] The distance sensor chip 10 includes, for example, a time of flight (ToF) sensor, which uses a light pulse emitted by a laser, which is reflected by an object and then received by the distance sensor chip 10, and the distance between the object and the distance sensor chip 10 is determined by calculating the flight time of the light. The controller 40 includes, for example, a microcontroller unit (MCU) of the device 1.

[0046] The ranging sensor chip 10 can measure the distance between an object and the ranging sensor. Through the ranging sensor chip 10, the mobile phone can realize functions such as facial payment and electronic banking, and the drone, VR, AR, sweeping robot, and car can realize functions such as obstacle avoidance.

[0047] Figure 2 This is a schematic diagram of the structure of a distance measuring sensor chip according to an embodiment of the present application.

[0048] In some embodiments, Figure 2 As shown, the distance sensor chip 10 includes a pixel photosensitive area and a circuit logic area, wherein the pixel photosensitive area includes a pixel die, and the circuit logic area includes a logic die. The pixel die can convert optical signals into electrical signals, and the logic die processes and calculates the electrical signals to obtain corresponding distance data, and can transmit the distance data to the next level chip (such as a microcontroller MCU coupled thereto).

[0049] The logic wafer includes an analog front end (AFE), a histogram statistics circuit 21′, a differential nonlinearity (DNL) compensation circuit 22′, a low-pass filter circuit 23, an echo detection circuit 24, an echo analysis circuit 25, a noise calculation circuit 27, a processor 26, a first static random access memory (SRAM) SRAM1, a second static random access memory SRAM2, a third static random access memory SRAM3, a fourth static random access memory SRAM4 and a one-time programmable memory (OTP).

[0050] The analog front end AFE receives the electrical signal output by the pixel wafer, and the signal flow sequentially flows through the AFE, the histogram statistics circuit 21', the DNL compensation circuit 22', the low-pass filter circuit 23, the noise calculation circuit 27, the echo detection circuit 24, the echo analysis circuit 25 and the processor 26, and the processor 26 outputs the distance data. For example, the processor 26 transmits the distance output to the microcontroller MCU.

[0051] The histogram statistics circuit 21′ is also coupled to the first static random access memory SRAM1, and the first static random access memory SRAM1 is used to store the signal output by the histogram statistics circuit 21′. The low-pass filter circuit 23 and the echo detection circuit 24 are also coupled to the second static random access memory SRAM2, and the second static random access memory SRAM2 is used to store the signal output by the low-pass filter circuit 23, and the echo detection circuit 24 is used to read the signal from the second static random access memory SRAM2.

[0052] The processor 26 is also coupled to the third static random access memory SRAM3, the fourth static random access memory SRAM4, and the one-time programmable memory OTP. The third static random access memory SRAM3 is used to store the software code required for the processor 26 to perform processing operations. The third static random access memory SRAM3 is also connected to the non-volatile memory (NVM) outside the ranging sensor chip 10. After the ranging sensor chip 10 is powered on, the non-volatile memory transfers the software code to the third static random access memory SRAM3. The fourth static random access memory SRAM4 is used to store the signal output by the processor 26, and the one-time programmable memory OTP is used to store the fixed parameters that characterize the identity information of the ranging sensor chip 10.

[0053] by Figure 2 Taking the distance measuring sensor chip shown in the figure as an example, the distance measuring sensor chip can be roughly divided into three parts.

[0054] The first part is the process of powering on the ranging sensor chip, during which the processor 26 reads the software code to put the ranging sensor chip into working state.

[0055] The second part is that the ranging sensor chip receives the electrical signal output by the pixel wafer, and after a series of data processing, outputs it to the microcontroller MCU.

[0056] The third part stores some information about fixed parameters that characterize the identity information of the ranging sensor chip.

[0057] From the perspective of data storage, the storage function involved in the ranging sensor chip is provided by the volatile memory inside the ranging sensor chip and the non-volatile memory outside the ranging sensor chip.

[0058] Among them, according to whether the stored signal in the memory still exists after the external power supply of the chip is removed, the memory can be divided into volatile memory and non-volatile memory.

[0059] Volatile memory, for example, may include static random access memory (SRAM) or dynamic random access memory (DRAM). The storage of information in volatile memory requires continuous external power supply. When the external power supply is low, the stored information will no longer exist. Figure 2 In the figure, the volatile memory included in the distance measuring sensor chip 10 is taken as an example to illustrate.

[0060] Non-volatile memory: Information stored in non-volatile memory will not be lost when external power is cut off. Figure 2 The non-volatile memory included in the ranging sensor chip 10 is a serial peripheral interface flash (SPI flash) as an example for illustration.

[0061] That is to say, from the perspective of data storage, the ranging sensor chip 10 involves two parts of data storage. One part is the external serial peripheral interface flash memory SPI flash outside the ranging sensor chip 10, which is a non-volatile memory used to store data that needs to be saved when the power is off. The other part is the SRAM and one-time programmable memory OTP inside the ranging sensor chip 10, which is a volatile memory. The SRAM is responsible for reading data from the serial peripheral interface flash memory SPI flash and participating in data processing, as well as serving as a cache. The one-time programmable memory OTP is used to store solidified parameters. The one-time programmable memory OTP can be, for example, an electronic fuse (eFuse) or an anti-electronic fuse (antifuse).

[0062] Figure 2 Although the distance measuring sensor chip 10 shown can measure the distance of an object, the distance measuring sensor chip 10 needs to be additionally connected to an external non-volatile memory (such as a serial peripheral interface flash memory SPI flash) to store data when the distance measuring sensor chip 10 is powered off (such as software codes required for starting the distance measuring sensor chip 10, software codes required for processing data by the distance measuring sensor chip 10, etc.), which increases the number of pads of the distance measuring sensor chip 10 and increases the complexity of the single-board solution. Moreover, since the software codes required for starting the distance measuring sensor chip 10 and the operation of the processor 26 are stored in the external non-volatile memory, when the distance measuring sensor chip 10 is working, it is necessary to first load the startup data and the processing data from the external non-volatile memory into the internal volatile memory, and then transmit them to the processor 26 before starting the processing to complete the power-on startup work. The startup time of the distance measuring sensor chip 10 is long and the workflow is complicated. In addition, the ranging sensor chip 10 is integrated with multiple volatile memories (for example, a first static random access memory SRAM1, a second static random access memory SRAM2, a third static random access memory SRAM3, and a fourth static random access memory SRAM4). The large-capacity static random access memory SRAM for on-chip storage will increase the area of ​​the ranging sensor chip 10. Furthermore, the volatile memory needs continuous power supply to save data, resulting in high power consumption of the ranging sensor chip 10. In addition, the one-time programmable memory OTP completes data writing by breaking down transistors, which can be cracked under a microscope, resulting in low security of the ranging sensor chip 10. Optimizing any of the above problems can improve the performance of the ranging sensor chip 10.

[0063] Based on this, an embodiment of the present application provides a distance measuring sensor chip 10 , removing the serial peripheral interface flash memory SPI flash coupled to the third static random access memory SRAM3 , so as to optimize the performance of the distance measuring sensor chip 10 .

[0064] Figure 3A A topological schematic diagram of a semiconductor structure provided in an embodiment of the present application.

[0065] An embodiment of the present application provides a semiconductor structure. The semiconductor structure can be applied to the ranging sensor chip 10 provided in the embodiment of the present application. The semiconductor structure is coupled to the photoelectric conversion module in the ranging sensor chip 10.

[0066] like Figure 3A As shown, the semiconductor structure 20 includes a non-volatile memory NVM, an analog front end AFE, and a processor 26 .

[0067] The analog front end AFE is used to couple with the photoelectric conversion module 30 , receive the electrical signal output by the photoelectric conversion module 30 , and process the electrical signal before outputting it.

[0068] The analog front end AFE processes the electrical signal, including converting the electrical signal (analog signal) into a digital signal and adding a time stamp to the digital signal, which is referred to as a time stamp digital signal in the embodiment of the present application.

[0069] The non-volatile memory NVM is used to store software codes, including, for example, software codes required for the processor 26 to process calculations.

[0070] The processor 26 is coupled to the analog front end AFE and the non-volatile memory NVM, and is used to read the software code in the non-volatile memory NVM, receive the timestamp digital signal output by the analog front end AFE, process the timestamp digital signal according to the software code, and generate distance data.

[0071] The processor 26 includes, for example, one or more of a central processing unit (CPU), an arithmetic and logic unit (ALU), or a microcontroller MCU.

[0072] That is to say, the software codes required for the semiconductor structure 20 to perform calculation processing are no longer stored in an external non-volatile memory coupled to the semiconductor structure 20 , but are directly stored in the non-volatile memory NVM inside the semiconductor structure 20 .

[0073] It should be noted that the embodiment of the present application does not limit the semiconductor structure 20 to not integrating any volatile memory. The structure of the semiconductor structure 20 may be that only the non-volatile memory NVM is integrated inside, the structure of the semiconductor structure 20 may be that the non-volatile memory NVM and other non-volatile memories are integrated inside, and the structure of the semiconductor structure 20 may be that the non-volatile memory NVM and volatile memory are integrated inside. As long as the semiconductor structure 20 has the non-volatile memory NVM integrated inside, it falls within the protection scope of the semiconductor structure 20 provided by the embodiment of the present application.

[0074] The semiconductor structure 20 provided in the embodiment of the present application has a non-volatile memory NVM integrated inside. The software code required for the semiconductor structure 20 to perform processing operations is directly stored in the non-volatile memory NVM inside the semiconductor structure 20, and is no longer stored in an external non-volatile memory. In this way, when the semiconductor structure 20 performs processing operations, the processor 26 can directly retrieve the software code from the non-volatile memory NVM without having to go through the process of loading from the external non-volatile memory to the internal volatile memory. The semiconductor structure 20 has a fast startup speed and a simple workflow, which can reduce the delay of the semiconductor structure 20. Moreover, by utilizing the characteristics of the non-volatile memory NVM being integrated on-chip and non-volatile, instead of the external non-volatile memory required by the traditional semiconductor structure 20, the architecture of the semiconductor structure 20 can be streamlined, area can be saved, and the hardware single-board solution can be simplified.

[0075] In some embodiments, the volatile memory NVM is further used to store curing parameters representing identity information of the semiconductor structure 20 , and the processor 26 is further used to read and / or write the curing parameters.

[0076] That is to say, the curing parameters are no longer stored in the one-time programmable memory OTP, but directly stored in the volatile memory NVM. By performing a special curing process on the non-volatile memory NVM, the non-volatile memory NVM can have a one-time programmable function.

[0077] In this way, the use of non-volatile memory NVM to implement the function of one-time programmable memory OTP can reduce the possibility of memory data being deduced through reverse observation by microscopes such as scanning electron microscope (SEM) and transmission electron microscope (TEM), thereby increasing the security of semiconductor structure 20. In addition, by using non-volatile memory NVM to replace one-time programmable memory OTP, there is no need to set one-time programmable memory OTP in semiconductor structure 20, and the types of memory in semiconductor structure 20 are reduced, which can simplify the preparation process and layout difficulty of semiconductor structure 20.

[0078] In some embodiments, please refer to Figure 3A As shown, the semiconductor structure 20 includes a processor 26, a non-volatile memory NMV, and an analog front end AFE, and also includes a statistical analysis circuit 28. The statistical analysis circuit 28 is used to perform statistical analysis on the signal output by the analog front end AFE and output the processing result to the processor 26.

[0079] For example, the statistical analysis circuit 28 is coupled between the analog front end AFE and the processor 26. The structure of the statistical analysis circuit 28 is constituted by a hardware circuit structure, for example.

[0080] It should be noted that in the embodiment of the present application, A is coupled between B and C, which means that A is located between B and C along the transmission direction of the data flow. For example, the data line is transmitted to B, then transmitted to A, and then transmitted to C. It is not limited to A being located between B and C on the layout of the semiconductor structure 20, and the three circuits of A, B, and C can be arranged in any layout manner.

[0081] The hardware statistical analysis circuit 28 performs preliminary statistical analysis on the signal output by the analog front end AFE, and then transmits the result to the processor 26 for processing, which can improve the accuracy and efficiency of the processor 26.

[0082] Figure 3B and Figure 3C A topological schematic diagram of a semiconductor structure provided in an embodiment of the present application.

[0083] In some embodiments, the statistical analysis circuit 28 needs a storage function when performing preliminary statistical analysis on the signal output by the analog front end AFE.

[0084] For example, Figure 3B As shown, the statistical analysis circuit 28 is coupled to the non-volatile memory NVM, and the non-volatile memory NVM provides a temporary buffer function required by the statistical analysis circuit 28 .

[0085] Or, for example, Figure 3C As shown, the statistical analysis circuit 28 is coupled to a volatile memory (eg, a static random access memory SRAM), and the volatile memory provides a temporary cache function required by the statistical analysis circuit 28 .

[0086] In some embodiments, the statistical analysis circuit 28 includes a statistical circuit 21, a compensation circuit 22, a low-pass filter circuit 23, a noise calculation circuit 27, an echo detection circuit 24, and an echo analysis circuit 25. Of course, the statistical analysis circuit 28 is not limited to including the above-mentioned circuit modules, and other circuit modules may be added, or one or more of the above-mentioned circuit modules may be reduced. The embodiment of the present application is only an illustration, and the statistical analysis circuit 28 applicable to the ToF sensor in the related art is applicable to the embodiment of the present application.

[0087] The statistical circuit 21 is coupled to the analog front end AFE, and is used for performing statistical processing on the received signal and transmitting the statistical processing result to the compensation circuit 22 .

[0088] For example, the statistical circuit 21 includes a histogram statistical circuit 21'. Since the photons received by the photoelectric conversion module 30 are not received at the same time, the timestamp digital signal output by the analog front end AFE has a time distribution. The histogram statistical circuit 21' will perform histogram statistics on the timestamp digital signal according to the time distribution of the received photons. Of course, the statistical circuit 21 can also expose other statistical circuits, and the histogram statistical circuit 21' is only a schematic.

[0089] At the same time, the statistical circuit 21 also needs to store the statistical results.

[0090] In some embodiments, Figure 3B As shown, the statistical circuit 21 is used to store the statistical results in the non-volatile memory NVM.

[0091] For example, Figure 3A As shown, the statistical circuit 21 is coupled to the analog front end AFE and the non-volatile memory NVM.

[0092] Non-volatile memory NVM is used to implement the function of static random access memory SRAM. Static random access memory SRAM is no longer needed in the semiconductor structure 20. The types of memory in the semiconductor structure 20 are reduced, which can simplify the preparation process and layout difficulty of the semiconductor structure 20 and reduce the area and power consumption of the semiconductor structure 20.

[0093] In other embodiments, Figure 3CAs shown, the semiconductor structure 20 also includes a volatile memory (such as a static random access memory SRAM), which is used as a cache to temporarily store the statistical results output by the statistical circuit 21 or store some data in the statistical process. The use of a volatile memory to provide a storage function for the statistical circuit 21 can improve the access speed of the statistical circuit 21.

[0094] In some embodiments, the compensation circuit 22 is used to perform compensation processing on the received signal and then output it.

[0095] Since the analog signal is inconsistent during differentiation, after being counted by the histogram counting circuit 21 ′, the data needs to be compensated before being output, so as to improve the accuracy of signal processing.

[0096] For example, the compensation circuit 22 includes a DNL compensation circuit 22'. The DNL compensation circuit 22' reduces the error of histogram statistics through a differential algorithm.

[0097] In some embodiments, the compensation circuit 22 is coupled to an output terminal of the statistical circuit 21 for receiving data output by the statistical circuit 21 .

[0098] Of course, the semiconductor structure 20 may not include the compensation circuit 22, or the compensation circuit 22 may be disposed at other locations. Figure 3B The figure is for illustration only.

[0099] In some embodiments, the low-pass filter circuit 23 is used to filter out the noise signal in the received signal and then output it. For example, the low-pass filter circuit 23 filters out the high-frequency signal in the received signal to remove the noise signal in the signal. The embodiment of the present application does not limit the specific frequency of the high-frequency signal filtered out, and the frequency band of the noise signal filtered out can be set in combination with the specific application scenario.

[0100] For example, the low-pass filter circuit 23 is coupled to the compensation circuit 22 and receives the signal output by the compensation circuit 22 .

[0101] In some embodiments, the low-pass filter circuit 23 is also used to filter out noise signals in the received signals and then store them.

[0102] For example, Figure 3B As shown, the low-pass filter circuit 23 is used to filter out the noise signal in the received signal and store it in the non-volatile memory NVM.

[0103] For example, the low pass filter circuit 23 is coupled to the compensation circuit 22 and the non-volatile memory NVM. In the case where the semiconductor structure 20 does not include the compensation circuit 22, the low pass filter circuit 23 is coupled to the statistical circuit 21 and the non-volatile memory NVM.

[0104] Non-volatile memory NVM is used to implement the function of static random access memory SRAM. Static random access memory SRAM is no longer needed in the semiconductor structure 20. The types of memory in the semiconductor structure 20 are reduced, which can simplify the preparation process and layout difficulty of the semiconductor structure 20 and reduce the area and power consumption of the semiconductor structure 20.

[0105] Or, for example, Figure 3C As shown, the semiconductor structure 20 further includes a volatile memory (eg, a static random access memory SRAM), and the volatile memory is used as a cache to temporarily store the signal output by the low-pass filter circuit 23.

[0106] For example, the low pass filter circuit 23 is coupled to the compensation circuit 22 and the static random access memory SRAM. In the case where the semiconductor structure 20 does not include the compensation circuit 22, the low pass filter circuit 23 is coupled to the statistical circuit 21 and the static random access memory SRAM.

[0107] The volatile memory is used to provide a storage function for the low-pass filter circuit 23 , which can improve the access speed of the low-pass filter circuit 23 .

[0108] In some embodiments, the noise calculation circuit 27 is used to calculate the noise signal in the received signal and output it.

[0109] Illustratively, the noise calculation circuit 27 is coupled to the low-pass filter circuit 23 for calculating the noise signal.

[0110] In some embodiments, the echo detection circuit 24 is used to detect and output peak information of the received signal.

[0111] If there are multiple obvious peaks and troughs in the histogram, we will extract the histogram near the peak. The extracted peak information includes the location of the peak value, the half-height width of the peak, the slope of the peak rising and falling edges, the confidence of the peak relative to the noise floor (signal-to-noise ratio) and other information.

[0112] For example, the echo detection circuit 24 is coupled to the noise calculation circuit 27. In the case where the semiconductor structure 20 does not include the noise calculation circuit 27, the echo detection circuit 24 may be coupled to the low-pass filter circuit 23, for example.

[0113] In some embodiments, the echo detection circuit 24 also needs to retrieve cache data from the memory.

[0114] For example, Figure 3B As shown, the low-pass filter circuit 23 is coupled to the non-volatile memory NVM.

[0115] Or, for example, Figure 3C As shown, the low-pass filter circuit 23 is coupled to the volatile memory NVM.

[0116] In some embodiments, the echo analysis circuit 25 is used to analyze the received signal and output the analysis result to the processor 26. For example, the echo analysis circuit 25 calculates the centroid position information (also referred to as the center position information) of the peak according to the peak information.

[0117] For example, the echo analysis circuit 25 is coupled between the echo detection circuit 24 and the processor 26 , and transmits the analysis result to the processor 26 .

[0118] After receiving the analysis result (eg, centroid position information), the processor 26 reads the software code and fixed parameters required for the calculation stored in the non-volatile memory NVM, and processes the centroid position information to generate distance data.

[0119] In some embodiments, Figure 3B and Figure 3C As shown, when the processor 26 generates distance data, it also needs to directly receive the signal output by the compensation circuit 22. For example, the compensation circuit 22 is also coupled to the processor 26.

[0120] Of course, the various circuit modules in the semiconductor structure 20 are not limited to the coupling relationship illustrated in the embodiment of the present application, and may also be other coupling relationships, which is only an illustration in the embodiment of the present application.

[0121] In some embodiments, the processor 26 needs to use a storage function when processing the centroid position information to generate distance data.

[0122] For example, Figure 3B As shown, the non-volatile memory NVM provides the processor 26 with a temporary cache function required when generating distance data. The processor 26 is used to write data to the non-volatile memory NVM. When the processor 26 needs to temporarily cache the data, the data can be written to the non-volatile memory NVM. And / or, the processor 26 is also used to read data from the non-volatile memory NVM. The processor 26 can retrieve the temporarily cached data from the non-volatile memory NVM to complete the processing function.

[0123] For example, the processor 26 is coupled to a non-volatile memory NVM.

[0124] Non-volatile memory NVM is used to implement the function of static random access memory SRAM. Static random access memory SRAM is no longer needed in the semiconductor structure 20. The types of memory in the semiconductor structure 20 are reduced, which can simplify the preparation process and layout difficulty of the semiconductor structure 20 and reduce the area and power consumption of the semiconductor structure 20.

[0125] Or, for example, Figure 3CAs shown, the semiconductor structure 20 further includes a volatile memory (eg, a static random access memory SRAM), which acts as a cache to provide temporary storage for the processor 26.

[0126] For example, processor 26 is coupled to volatile memory.

[0127] The distance data generated by the processor 26 may be transmitted to a next-level chip, such as a controller 40 (eg, MCU) of the device 1 , so that the device 1 can respond.

[0128] It can be seen from the above description that the software code storage, fixed parameter storage, and data cache functions required by the processor 26 can all be provided by the on-chip non-volatile memory NVM.

[0129] The semiconductor structure 20 provided in the embodiment of the present application can be a bare chip (die) or a packaged chip (chip), which is not limited in the embodiment of the present application. In addition, the order of the circuit modules in the semiconductor structure 20 can be swapped. The core of the embodiment of the present application lies in the interactive structure of the circuit modules and the non-volatile memory NVM in the semiconductor structure 20. The order between the circuit modules can be adjusted based on the difference between the algorithm and the actual application scenario, and whether the circuit modules are included can also be increased or decreased based on the difference between the algorithm and the actual application scenario. Of course, the semiconductor structure 20 is not limited to only including the above-mentioned circuit modules illustrated in the embodiment of the present application, but can also include other circuit modules, and the structures in the relevant technology are all applicable to the embodiment of the present application. Moreover, when other circuit modules need storage functions, they can be coupled with the non-volatile memory NVM or volatile memory in the semiconductor structure 20.

[0130] In some embodiments, the semiconductor structure 20 further includes a photoelectric conversion module 30. That is, the photoelectric conversion module 30 and the semiconductor structure 20 are integrated on the same substrate, and the semiconductor structure 20 is packaged to form the ranging sensor chip 10 provided in the embodiment of the present application.

[0131] In some other embodiments, the semiconductor structure 20 does not include the photoelectric conversion module 30 , and the semiconductor structure 20 and the photoelectric conversion module 30 are packaged together in the same package chip to constitute the ranging sensor chip 10 provided in the embodiment of the present application.

[0132] The photoelectric conversion module 30 includes, for example, a plurality of photodiodes arranged in an array, and converts optical signals into electrical signals through the photodiodes.

[0133] The embodiment of the present application further provides a working method of a ranging sensor chip 10 , where the ranging sensor chip 10 , for example, includes any of the above-mentioned ranging sensor chips 10 .

[0134] Working methods, including:

[0135] At the power-on startup moment, the processor 26 directly reads the curing parameters representing the identity information of the semiconductor structure 20 (or the ranging sensor chip 10 ) from the non-volatile memory NVM.

[0136] In the working method of the ranging sensor chip 10 provided in the embodiment of the present application, the fixed parameters required for starting the ranging sensor chip 10 are directly stored in the non-volatile memory NVM inside the semiconductor structure 20, and are no longer stored in the external non-volatile memory. In this way, during the power-on startup process, the ranging sensor chip 10 can directly retrieve the fixed parameters from its internal non-volatile memory NVM, without having to go through the process of loading the fixed parameters from the external non-volatile memory to the internal volatile memory. The ranging sensor chip 10 has a fast startup speed and a simple workflow, which can reduce the delay of the ranging sensor chip 10.

[0137] In some embodiments, the working method further comprises:

[0138] The analog front end AFE receives the electrical signal output by the photoelectric conversion module 30 , processes the electrical signal and then outputs it.

[0139] The processor 26 directly reads the software code from the non-volatile memory NVM to process the signal output by the analog front end AFE to generate distance data.

[0140] In the working method of the ranging sensor chip 10 provided in the embodiment of the present application, the software code required for the processor 26 to perform processing operations is directly stored in the non-volatile memory NVM inside the semiconductor structure 20, and is no longer stored in the external non-volatile memory. In this way, when the semiconductor structure 20 performs processing operations, the processor 26 can directly retrieve the software code from the non-volatile memory NVM without going through the process of loading from the external non-volatile memory to the internal volatile memory. The ranging sensor chip 10 has a fast startup speed and a simple workflow, which can reduce the delay of the semiconductor structure 20.

[0141] In some embodiments, the processor 26 directly reads the software code from the non-volatile memory NVM to process the signal output by the analog front end AFE to generate distance data, including:

[0142] The statistical circuit 21 receives the signal output by the analog front end AFE, performs statistical processing on the signal and then outputs it. The compensation circuit 22 receives the signal output by the statistical circuit 21, performs statistical processing on the signal and then outputs it. The low-pass filter circuit 23 receives the signal output by the compensation circuit 22, filters out the noise in the signal and then outputs it. The echo detection circuit 24 receives the signal output by the low-pass filter circuit 23, detects the peak information of the signal and then outputs it. The echo analysis circuit 25 receives the peak information in the echo detection circuit 24, generates the centroid position information and then outputs it. The processor 26 receives the centroid position information output by the echo analysis circuit 25, processes the centroid position information and then outputs the distance data.

[0143] During the operation of the ranging sensor chip 10 , the storage functions required by the ranging sensor chip 10 may all be provided by the non-volatile memory NVM, and the storage functions required by the ranging sensor chip 10 may also be partially provided by the volatile memory.

[0144] In some embodiments, after the processor 26 performs calculations, the data stored in the non-volatile memory NVM will be updated or rewritten.

[0145] Regarding the structure of the non-volatile memory NVM in the semiconductor structure 20, in some embodiments, the non-volatile memory NVM includes a control circuit and a storage array, and the control circuit is coupled to the storage array to control the reading of the storage array. The storage array includes a plurality of storage cells.

[0146] Regarding the manner in which the non-volatile memory NVM provides storage functions for each circuit in the semiconductor structure 20:

[0147] In some embodiments, the non-volatile memory NVM is physically divided into a plurality of memory modules, and the circuit coupled to the non-volatile memory NVM in the semiconductor structure 20 is coupled to one or more memory modules accordingly.

[0148] For example, the control circuit includes a plurality of control branches, and the storage array includes a plurality of array modules. The non-volatile memory NVM includes a plurality of storage modules, and each storage module includes a control branch and an array module.

[0149] Then, the circuit coupled to the nonvolatile memory NVM is called an X circuit. Figure 3B As an example of the semiconductor structure 20 shown in FIG. 1 , the X circuit may be Figure 3B The semiconductor structure 20 shown includes a processor 26 , a statistical circuit 21 , a low-pass filter circuit 23 , and an echo detection circuit 24 .

[0150] Figure 4-Figure 9 A diagram showing the relationship between a circuit in a semiconductor structure and a non-volatile memory provided in an embodiment of the present application.

[0151] like Figure 4 As shown, each X circuit is coupled to one or more storage modules. When the X circuit is an intermediate transmission circuit, the X circuit is also coupled to an upstream X circuit and a downstream X circuit. An input end of the X circuit obtains a signal from the upstream X circuit, processes the received signal, and transmits it to the downstream X circuit.

[0152] In some embodiments, Figure 5 As shown, the storage module can be integrated in the X circuit, or the storage module can be located outside the X circuit, and can be reasonably arranged according to needs.

[0153] In some embodiments, transistors included in the logic portion of part or all of the circuits in the semiconductor structure 20 and transistors in the non-volatile memory NVM are integrated on the same chip.

[0154] In some other embodiments, the non-volatile memory NVM is divided into a plurality of storage regions by addresses, and the circuit coupled to the non-volatile memory NVM in the semiconductor structure 20 corresponds to one or more storage regions.

[0155] For example, Figure 6 As shown, each X circuit is coupled to a control circuit. When the X circuit is an intermediate transmission circuit, the X circuit is also coupled to an upstream X circuit and a downstream X circuit. An input end of the X circuit obtains a signal from the upstream X circuit, processes the received signal, and transmits it to the downstream X circuit.

[0156] In some embodiments, the semiconductor structure 20 further includes an input / output interface I / O, which is coupled to the non-volatile memory NVM for writing or reading with the outside of the semiconductor structure 20 .

[0157] In some embodiments, part of the X circuits in the semiconductor structure 20 only reads data from the non-volatile memory NVM, and part of the X circuits in the semiconductor structure 20 not only reads data from the non-volatile memory NVM, but also writes the data processed by its own operation into the non-volatile memory NVM. The non-volatile memory NVM stores the written data and updates or does not update the previous data as needed.

[0158] The input / output interface I / O is directly coupled to the non-volatile memory NVM, and the non-volatile memory NVM is externally connected to other structures via the input / output interface I / O.

[0159] For example, the non-volatile memory NVM is connected to an external device 1 through an input / output interface I / O to obtain a system chip.

[0160] Or, for example, the non-volatile memory NVM is externally connected to other non-volatile memories via an input / output interface I / O.

[0161] In some embodiments, Figure 7 As shown, the input / output interface I / O exists independently, and the X circuit is coupled to the input / output interface I / O via the non-volatile memory NVM.

[0162] In other embodiments, Figure 8 As shown, the input / output interface I / O is integrated in the X circuit, and the X circuit can be directly coupled to the input / output interface I / O.

[0163] In some other embodiments, Fig. 9 As shown, some input / output interfaces I / O exist independently, and some input / output interfaces I / O are integrated in the X circuit.

[0164] Of course, the logic part of the X circuit may be integrated with the control branch of the non-volatile memory NVM, or may not be integrated with the control branch of the non-volatile memory NVM. The drawings of the embodiments of the present application are only for illustration and are not intended to limit the present invention in any way.

[0165] Regarding the type of non-volatile memory NVM, in some embodiments, the non-volatile memory NVM includes one or more of read-only memory (ROM) and flash memory, ferroelectric random-access memory (FeRAM, ferroelectric field effect transistor, FeFET), magnetoresistive random access memory (MRAM), resistive random access memory (RRAM) and phase-change random access memory (PCRAM).

[0166] The characteristic of flash memory is that a floating gate, oxide-nitride-oxide-silicon oxygen nitride oxide silicon (ONO-SONOS) or nano crystal is added to the gate of the transistor to store electrons for reading and writing data.

[0167] The characteristic of magnetoresistive random access memory (MRAM) is that it combines transistors with magnetic tunneling junctions (MTJs) by using toggle, spin transfer torque (STT), spin orbit torque (SOT), or voltage control magnetic anisotropy (VCMA) to store information in the relative magnetic moments of the two layers of magnetic materials in the magnetic tunneling junction.

[0168] The characteristic of resistive random access memory (RRAM) is that it is a memory composed of a transistor and a variable resistor. The variable resistor is that a conductive path can be created or disappeared in the middle of the resistor layer by applying an external voltage. Examples of RRAM include oxygen vacancy memories (OxRAM) and conductive bridge memories (CBRAM).

[0169] Phase-change random access memory (PCRAM) is characterized by combining transistors with phase-change materials, where the resistance of the phase-change material changes as the crystal phase changes.

[0170] Ferroelectric memories are divided into two categories, one is FeRAM and the other is FeFET. The characteristic of FeRAM is that the drain of the transistor is combined with ferroelectric materials, and the characteristic of FeFET is that a layer of ferroelectric material is added to the gate of the transistor, and information is stored in the polarity of the ferroelectric. FeRAM can be, for example, a 1T-1C (1transistor+1capacitor) structure ferroelectric memory, and FeFET can be, for example, a 1T-1G (1transistor+1gate) structure ferroelectric memory.

[0171] The manner in which the volatile memory provides storage functions for each circuit in the semiconductor structure 20 may be the same as the manner in which the non-volatile memory NVM provides storage functions for each circuit in the semiconductor structure 20 .

[0172] In some embodiments, the volatile memory is physically divided into a plurality of memory modules, and the circuit coupled to the volatile memory in the semiconductor structure 20 is coupled to one or more memory modules accordingly.

[0173] For example, the control circuit includes a plurality of control branches, the storage array includes a plurality of array modules, and the volatile memory includes a plurality of storage modules, each storage module includes a control branch and an array module.

[0174] Then, the circuit coupled to the volatile memory is called an X circuit. Figure 3C As an example of the semiconductor structure 20 shown in FIG. 1 , the X circuit may be Figure 3C The processor 26, the statistical circuit 21, the low-pass filter circuit 23, and the echo detection circuit 24 in the semiconductor structure 20 are shown. Then, the connection relationship between the circuit in the semiconductor structure 20 and the volatile memory can be referred to. Figure 4-Figure 9 The connection relationship between the circuit in the semiconductor structure 20 and the non-volatile memory NVM is shown.

[0175] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: Applicable to a distance measuring sensor chip including a photoelectric conversion module; The semiconductor structure comprises: Non-volatile memory; used to store software code; An analog front end, used to couple with the photoelectric conversion module, receive the electrical signal output by the photoelectric conversion module, and process the electrical signal before outputting it; The processor is coupled to the non-volatile memory and is used to read the software code and process the signal output by the analog front end to generate distance data.

2. The semiconductor structure according to claim 1, characterized in that: The volatile memory is further used to store curing parameters representing the identity information of the semiconductor structure; and the processor is further used to read and / or write the curing parameters.

3. The semiconductor structure according to claim 1 or 2, characterized in that: The semiconductor structure also includes a statistical analysis circuit, which is used to perform statistical analysis processing on the signal output by the analog front end and output the processing result to the processor.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The semiconductor structure further includes a statistical analysis circuit coupled between the analog front end and the processor.

5. The semiconductor structure according to claim 3 or 4, characterized in that: The statistical analysis circuit includes a statistical circuit, a compensation circuit, a low-pass filter circuit, a noise calculation circuit, an echo detection circuit and an echo analysis circuit; The statistical circuit is used for performing statistical processing on the signal output by the analog front end and then outputting the signal; The compensation circuit is used to perform compensation processing on the received signal and then output it; The low-pass filter circuit is used to filter out the noise signal in the received signal and then output it; The noise calculation circuit is used to calculate the noise signal in the received signal and output it; The echo detection circuit is used to detect the peak information of the received signal and output it; The echo analysis circuit is used to analyze the received signal and output the analysis result to the processor.

6. The semiconductor structure according to any one of claims 3 to 5, characterized in that: The statistical analysis circuit includes a statistical circuit, a compensation circuit, a low-pass filter circuit, a noise calculation circuit, an echo detection circuit and an echo analysis circuit; The statistical circuit is coupled to the analog front end; The compensation circuit is coupled to the statistical circuit; The low-pass filter circuit is coupled to the compensation circuit; The noise calculation circuit is coupled to the low-pass filter circuit; The echo detection circuit is coupled to the noise calculation circuit; The echo analysis circuit is coupled to the echo detection circuit and the processor.

7. The semiconductor structure according to claim 5 or 6, characterized in that: At least one of the statistical circuit, the low-pass filtering circuit, and the echo detection circuit is also coupled to the non-volatile memory.

8. The semiconductor structure according to claim 5 or 6, characterized in that: The semiconductor structure further includes a volatile memory; at least one of the statistical circuit, the low-pass filter circuit, the echo detection circuit and the processor is also coupled to the volatile memory.

9. The semiconductor structure according to any one of claims 1 to 8, characterized in that: The semiconductor structure further includes an input / output interface coupled to the non-volatile memory.

10. A distance measuring sensor chip, characterized in that: It comprises a semiconductor structure and a photoelectric conversion module; the semiconductor structure is coupled to the photoelectric conversion module; the semiconductor structure comprises the semiconductor structure according to any one of claims 1 to 9.

11. A device, characterized in that: It comprises a distance measuring sensor chip and a controller, wherein the distance measuring sensor chip is coupled to the controller; the distance measuring sensor chip comprises the distance measuring sensor chip according to claim 10.

12. A method for operating a ranging sensor chip, characterized in that: The distance measuring sensor chip includes a semiconductor structure and a photoelectric conversion module; the semiconductor structure includes a non-volatile memory, an analog front end and a processor; The working method comprises: The analog front end receives the electrical signal output by the photoelectric conversion module, processes the electrical signal and then outputs it; The processor directly reads the software code from the non-volatile memory to process the signal output by the analog front end to generate distance data.

13. The working method according to claim 12, characterized in that: The working method also includes: At the power-on startup moment, the processor directly reads the curing parameters representing the identity information of the semiconductor structure from the non-volatile memory.

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