A method for improving the uniformity of square resistance of solar cells

Abstract

The present invention discloses a method for improving the uniformity of square resistance of solar cell chips, including quartz boat preparation, precise positioning and placement after cleaning and baking at a specific temperature and time; silicon wafer loading, placing the chips in a PE-like forward direction at a specific tilt angle (10°-30°) and spacing (2mm-5mm) to control operating accuracy; quartz boat entering the furnace, pushing and monitoring smoothly; boron expansion process, selecting different parameter combinations according to silicon chip placement parameters and monitoring; subsequent process treatment, involving etching, cleaning, passivation, electrode preparation and sintering, etc. The present invention significantly improves the uniformity of square resistance, enhances the consistency and stability of battery performance, and improves photoelectric conversion efficiency by optimizing the chip placement method and related process parameters. The process is flexible and optimizable and can adapt to a variety of production conditions. It is cost-effective at the same time, helps to reduce production costs, and promotes large-scale production and application of solar cells.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cell manufacturing, and in particular to a method for improving the square resistance uniformity of solar cell sheets by optimizing a sheet placement method and related process parameters. Background Art

[0002] In the booming solar cell manufacturing sector, topcon solar cells, with their unique structural and performance advantages, have become a key area of ​​research and production. The boron diffusion process is undoubtedly a key factor in determining the performance of topcon solar cells, fundamentally shaping the uniformity of the cell's sheet resistance. The boron diffusion process aims to precisely control the diffusion of impurity atoms (boron atoms) to create a specific doping profile on the silicon wafer surface, laying the foundation for subsequent electrical performance enhancement. However, traditional wafer placement methods, such as the widely used horizontal and vertical placement modes, have exposed numerous insurmountable drawbacks in practice. While horizontal placement allows for relatively smooth airflow from the furnace entrance to the rear, the temperature distribution of the heating filaments gradually decreases from the furnace walls to the center. This uneven temperature distribution directly leads to relatively low sheet resistance deposition and advancement temperatures in the center of the furnace, inevitably resulting in high sheet resistance areas. Furthermore, the significant temperature differences experienced by different locations across the entire wafer plane cause large fluctuations in sheet resistance in the horizontal direction, severely disrupting sheet resistance uniformity. The vertical placement method faces a significant challenge due to obstructed airflow. When the first silicon wafer is placed on the quartz boat, it acts as a barrier, significantly hindering the uniform flow of subsequent airflow within the tube. This results in uneven concentrations of reactant gases across the wafer surfaces, leading to far less-than-ideal sheet resistance uniformity within the tube. Even if the temperature distribution can be relatively uniform vertically, airflow non-uniformity remains a key factor hindering improved sheet resistance uniformity. This poor sheet resistance uniformity has a ripple effect on solar cell performance. Differences in sheet resistance within different regions of the cell cause localized resistance non-uniformity during current flow, leading to inconsistent cell performance. Specifically, during the photoelectric conversion process, the transmission of electrons and holes is disrupted by this non-uniform sheet resistance, increasing the carrier recombination rate in certain areas and significantly reducing the cell's photoelectric conversion efficiency. As a core performance metric for solar cells, a decrease in photoelectric conversion efficiency directly impairs the cell's ability to convert solar energy into electricity. From the perspective of the entire solar cell module, inconsistent performance of individual cells can create a "barrel effect" within the module. Poorly performing cells can limit the output power of the entire module, reducing its reliability and stability. During long-term outdoor use, the module may experience premature failure due to the degradation of local cell performance, shortening its service life and increasing maintenance costs. This severely restricts the widespread application and promotion of solar cell modules in photovoltaic power generation systems.In summary, as solar cell manufacturing technology continues to pursue high efficiency, stability and reliability, developing a method that can effectively improve the uniformity of square resistance has become the key to breaking through the current technical bottleneck and improving the quality and performance of solar cells. It has far-reaching strategic significance and urgent practical needs for promoting the sustainable development of the solar cell industry. Summary of the Invention

[0003] In order to overcome the above problems or at least partially solve the above problems, the core of the present invention is to provide a method for improving the uniformity of the square resistance of a solar cell.

[0004] A method for improving the uniformity of square resistance of a solar cell, characterized by comprising the following steps:

[0005] Quartz boat preparation

[0006] Choose a quartz boat made of high-purity quartz material, whose specifications should match the furnace tube and silicon wafer size used. Ensure that the quartz boat's surface flatness is within ±0.1mm and free of visible scratches and impurities. Place the quartz boat in a dedicated cleaning machine and first rinse it with deionized water for 3-5 minutes to remove loose surface particles. Then soak it in a cleaning solution composed of hydrofluoric acid and nitric acid in a specific ratio (e.g., 1:5-1:10) for 10-15 minutes to remove any metal impurities and other contaminants that may have adhered to the surface. After soaking, rinse it again with deionized water for 5-10 minutes to ensure that the cleaning solution is completely removed. Finally, place the quartz boat in a high-temperature oven for drying. Set the oven temperature to 800°C-1000°C at a controlled heating rate of 5°C / min-10°C / min. Once at the set temperature, hold it for 30-60 minutes to thoroughly dry the boat and remove any surface impurities such as moisture.

[0007] The optimal placement of the quartz boat inside the furnace is precisely calculated based on the inner diameter and length of the furnace tube, as well as the size of the silicon wafer. Using a laser positioning device to assist in positioning, the quartz boat is placed near the center axis of the furnace tube, with a deviation controlled within ±5mm to ensure relatively uniform heating and airflow distribution within the furnace tube.

[0008] Wafer loading

[0009] Place the cleaned and dried silicon wafers on the quartz boat in a PE-like forward placement method. The long side of the silicon wafer is placed at an inclination angle of 10°-30° to the long side of the quartz boat. Different angles such as 15°, 20°, and 25° can be selected for testing, and a high-precision protractor is used to ensure that the inclination angle error of each silicon wafer does not exceed ±0.2°. Before loading the silicon wafer, a thin layer of inert gas (such as argon) is evenly applied to the surface of the quartz boat. The gas film is about 0.1μm-0.5μm thick to reduce the friction between the silicon wafer and the quartz boat and facilitate the placement of the silicon wafer. Maintain a spacing of 2mm-5mm between the silicon wafers, such as different spacing settings of 2mm, 3mm, 4mm or 5mm, and use precision spacing measurement tools (such as micrometers) to ensure that the spacing error does not exceed ±0.05mm. During the loading process, automated loading equipment or manual operation with soft tweezers is used. The loading time of each silicon wafer is controlled within 5 seconds to 10 seconds to ensure that the silicon wafer is placed stably, avoid collisions and scratches, ensure the neatness of arrangement, and the lateral deviation of adjacent silicon wafers does not exceed ±0.3mm.

[0010] Quartz boat into the furnace

[0011] Place the quartz boat loaded with silicon wafers on the furnace entry track. The track should be kept level, with a flatness deviation of no more than ±0.5mm. Use an electric pusher to slowly and steadily feed the quartz boat into the furnace tube at a pushing speed of 5cm / s-10cm / s. For example, speeds of 6cm / s, 7cm / s, 8cm / s, 9cm / s, or 10cm / s can be selected. During the pushing process, a laser rangefinder monitors the distance between the front end of the quartz boat and the furnace tube entrance in real time to ensure that the distance deviation does not exceed ±2cm. At the same time, a high-definition camera is installed at the furnace tube entrance to monitor the status of the silicon wafers in real time during the furnace entry process. If any displacement or shaking of the silicon wafers is detected, the push is immediately stopped and adjustments are made. When the quartz boat is completely in the furnace tube, the entry time is recorded to the second, providing a time reference for accurate control of subsequent process steps.

[0012] Boron diffusion process

[0013] Different boron diffusion process parameters were selected for experiments according to the tilt angle and spacing of the silicon wafers.

[0014] When the angle of inclination is 10 ° and the wafer spacing is 2 mm, the BCl gas flow rate is set to 80 sccm, the furnace tube pressure is 200 Pa, the boron expansion temperature is 900 ℃, and the boron expansion time is 60 minutes. Simultaneously, during the boron expansion process, the gas atmosphere in the furnace tube is controlled so that the oxygen content remains at 1%-3% (volume fraction) to promote the diffusion and doping reaction of the boron atoms. When the angle of inclination is 20 ° and the wafer spacing is 3 mm, the BCl gas flow rate is 120 sccm, the furnace tube pressure is 300 Pa, the boron expansion temperature is 950 ℃, and the boron expansion time is 90 minutes. In addition, before the boron expansion, the furnace tube is pre-evacuated to a vacuum degree of 10-2 Pa-10-3 Pa to reduce the interference of impurity gases in the boron expansion process. When the tilt angle is 30° and the wafer spacing is 4mm, the BCl3 gas flow rate is 150sccm, the furnace pressure is 400Pa, the boron diffusion temperature is 980°C, and the boron diffusion time is 100 minutes. During this process, a small amount of nitrogen (flow rate of 10sccm-20sccm) is introduced into the furnace tube as a protective gas to prevent oxidation of the silicon wafer surface. When the tilt angle is 15° and the wafer spacing is 5mm, the BCl3 gas flow rate is 180sccm, the furnace pressure is 500Pa, the boron diffusion temperature is 1000°C, and the boron diffusion time is 120 minutes. In the later stages of the boron diffusion process, the furnace pressure is gradually reduced to 100Pa-200Pa to optimize the diffusion depth and distribution of boron atoms. (Different parameter combinations can be supplemented according to actual conditions.) During the boron diffusion process, parameters such as furnace temperature, pressure, and gas flow rate are continuously monitored, and data is recorded every 5 minutes. The temperature distribution on the silicon wafer surface is also monitored to ensure temperature uniformity within ±5°C.

[0015] Cooling and subsequent processing

[0016] After the boron expansion process, the furnace tube is cooled using a graded cooling method. The temperature is first lowered to 500-600°C at a cooling rate of 5-10°C / min, and then naturally cooled to room temperature to prevent stress on the silicon wafer caused by sudden temperature changes. During the cooling process, a pure inert gas (such as argon) is introduced into the furnace tube at a flow rate of 50-100 sccm to protect the silicon wafer surface from oxidation.

[0017] After cooling, the silicon wafer is removed from the furnace and then subjected to subsequent processing. For example, etching to remove the phosphosilicate glass (PSG) layer can be performed using either wet etching (e.g., hydrofluoric acid solution at a concentration of 5%-10%) or dry etching. The etching time is determined by the thickness of the PSG layer on the silicon wafer surface, typically 30-60 seconds. After etching, the wafer is rinsed with deionized water 3-5 times, followed by ultrasonic cleaning at a frequency of 20kHz-40kHz for 5-10 minutes to ensure removal of any residues generated during the etching process. Passivation treatment is then performed, such as using plasma-enhanced chemical vapor deposition (PECVD) to deposit a 50nm-100nm thick silicon nitride (SiNx) film on the wafer surface. During deposition, the plasma power is controlled at 100W-200W, and the reaction gas flow ratio (silane:ammonia) is 1:5-1:10. Finally, the electrodes are prepared by screen printing technology, and silver paste or aluminum paste is printed as the front and back electrode materials with a printing thickness of 80μm-120μm. Then, sintering treatment is carried out at a sintering temperature of 800℃-900℃ and a sintering time of 30 seconds-60 seconds to form a good ohmic contact between the electrode and the silicon wafer, completing the manufacturing of the solar cell.

[0018] The embodiments of the present invention have at least the following advantages or beneficial effects:

[0019] 1. The present invention significantly improves the uniformity of square resistance. Through a carefully designed PE-like forward wafer placement method, combined with precisely controlled different tilt angles, silicon wafer spacing, and optimized boron diffusion process parameters, including gas flow, pressure, temperature, time, and gas atmosphere, the thermal radiation and airflow transmission conditions of the silicon wafer in the furnace tube can be greatly improved. After a large number of experimental tests and comparisons, the method of the present invention has made a qualitative leap in the uniformity of square resistance compared to the traditional wafer placement method. For example, the uniformity of the furnace mouth-upper wafer of the traditional horizontal wafer placement may reach 4.71%, while under the optimized parameter combination of the present invention, the uniformity within the wafer can be reduced to less than 1%, such as 0.8%, 0.6%, etc., which significantly improves the consistency and stability of the battery performance, thereby improving the photoelectric conversion efficiency of solar cells.

[0020] 2. The process involved in the present invention is highly flexible and optimizable. The present invention provides a rich variety of tilt angles and silicon wafer spacing options, as well as a comprehensive and detailed combination of boron diffusion process parameters corresponding thereto. This allows for flexible adjustment and in-depth optimization in the actual production process based on different equipment conditions (such as furnace tube size, heating system performance, etc.), silicon wafer characteristics (such as silicon wafer size, crystal structure, etc.) and product requirements (such as solar cells of different power levels). Enterprises can find the process solution that best suits their own production environment through simple experiments, which not only improves production efficiency but also ensures the stability and reliability of product quality.

[0021] 3. The method involved in the present invention achieves a significant improvement in square resistance uniformity, without introducing expensive new equipment or complex additional process steps, simply through innovative improvements to the wafer placement method and fine optimization of process parameters. This helps to significantly reduce production costs, including reduced raw material consumption (due to good square resistance uniformity, the number of silicon wafers scrapped due to poor performance can be reduced), reduced energy consumption (optimized process parameters make processes such as heating and gas supply more efficient), and shortened production cycles (rapidly finding the optimal process parameters can reduce debugging time). Ultimately, the market competitiveness of solar cells is improved, which is conducive to large-scale production applications and promotes the development of the solar cell industry. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 This is a schematic diagram of the film placing step of the present invention;

[0024] Figure 2 Schematic diagram of the principles of different film placement methods in the present invention;

[0025] Figure 3 This is a test data diagram of the corresponding square resistance of different chip placement methods in the present invention. DETAILED DESCRIPTION

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0027] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0028] Example 1

[0029] Quartz boat preparation

[0030] Select a quartz boat with a surface roughness of less than 0.1 μm. Rinse it with deionized water for 5 minutes, then soak it in a cleaning solution consisting of a 1:8 volume ratio of hydrofluoric acid and nitric acid for 12 minutes. Rinse it again with deionized water for 8 minutes, and bake it in a 900°C oven for 45 minutes at a heating rate of 8°C / min. Place the quartz boat so that the center axis of the furnace tube deflects within ±3 mm.

[0031] An argon film with a thickness of 0.3 μm was evenly applied on the surface of the quartz boat.

[0032] Wafer loading

[0033] Silicon wafers are placed on a quartz boat using a PE-like forward loading method, with the long edge of the wafer tilted at a 15° angle relative to the boat's length. A high-precision protractor is used to ensure an angular error of ±0.3°. The wafers are spaced 3mm apart, and a micrometer is used to ensure a spacing error of ±0.08mm. Automated loading equipment is used, with each wafer loading time of 8 seconds, and lateral deviation between adjacent wafers does not exceed ±0.4mm.

[0034] Quartz boat into the furnace

[0035] The flatness deviation of the furnace entry track is ±0.3mm. The quartz boat is pushed at a speed of 8cm / s by an electric pushing device. The high-definition camera monitoring at the furnace tube entrance shows that the silicon wafer has no displacement or shaking, and the furnace entry time is accurately recorded as 10:0:0.

[0036] Boron diffusion process

[0037] The BCl3 gas flow rate was 120 sccm, the furnace pressure was 300 Pa, the boron expansion temperature was 950°C, and the boron expansion time was 90 minutes. The furnace was pre-evacuated to 10-2.5 Pa before the boron expansion. Data recorded every 5 minutes during the boron expansion process showed that the temperature fluctuation was within ±3°C, the pressure fluctuation was within ±10 Pa, and the gas flow fluctuation was within ±5 sccm.

[0038] Cooling and subsequent processing

[0039] The temperature was cooled in stages, first decreasing to 550°C at a rate of 8°C / min, followed by natural cooling. During cooling, argon gas was introduced at a flow rate of 80 sccm. Etching was performed using a 5% hydrofluoric acid solution wet etch for 45 seconds, followed by four deionized water rinses and ultrasonic cleaning for 8 minutes. Passivation was performed by depositing a 70nm thick SiNx film using PECVD at a plasma power of 150W and a silane:ammonia flow ratio of 1:8. The screen-printed electrodes were 100μm thick and sintered at 850°C for 45 seconds.

[0040] After testing, the square resistance uniformity of the solar cell prepared in this embodiment is significantly improved, and the uniformity within the cell reaches 1.2%, which is a significant improvement compared to the traditional cell placement method (such as horizontal or vertical cell placement in the comparative example). The photoelectric conversion efficiency of the cell is increased by about 0.8%, and the fill factor is also improved to a certain extent, indicating that the performance of the cell is effectively enhanced.

[0041] Example 2

[0042] Quartz boat preparation

[0043] The quartz boat preparation steps are the same as those in Example 1, but the baking temperature is 950° C. and the baking time is 50 minutes.

[0044] Wafer loading

[0045] The wafer tilt angle is 20°, with an angular error of ±0.2°, and the spacing is 4mm, with a spacing error of ±0.06mm. Manual loading with soft tweezers takes 6 seconds per wafer, and the lateral deviation between adjacent wafers does not exceed ±0.3mm.

[0046] Quartz boat into the furnace

[0047] The flatness deviation of the furnace entry track is ±0.2mm, the pushing speed is 9cm / s, and the furnace entry time is 10 hours, 10 minutes and 0 seconds.

[0048] Boron diffusion process

[0049] The BCl3 gas flow rate was 150 sccm, the furnace pressure was 400 Pa, the boron diffusion temperature was 980°C, and the boron diffusion time was 100 minutes. During the boron diffusion process, nitrogen was introduced at a flow rate of 15 sccm. The temperature fluctuation was ±2°C, the pressure fluctuation was ±8 Pa, and the gas flow fluctuation was ±3 sccm.

[0050] Cooling and subsequent processing

[0051] The cooling method is the same as that in Example 1, the etching adopts dry etching, and the passivation, screen printing and sintering parameters are the same as those in Example 1.

[0052] Test results show that the cell sheet resistance uniformity of this embodiment is excellent, with an intra-cell uniformity of 1.0%, which is significantly superior to the traditional cell placement method. The cell's photoelectric conversion efficiency is increased by approximately 1.0%, and the fill factor is also optimized, thanks to the improved sheet resistance uniformity and the synergistic effect of various process steps.

[0053] Example 3

[0054] Quartz boat preparation

[0055] Same as Example 1, except that the cleaning solution immersion time is 10 minutes, the baking temperature is 850° C., and the baking time is 35 minutes.

[0056] Wafer loading

[0057] The wafer tilt angle is 25°, with an angle error of ±0.4°, and the spacing is 2mm, with a spacing error of ±0.05mm. Automatic loading takes 7 seconds per wafer, and the lateral deviation between adjacent wafers does not exceed ±0.35mm.

[0058] Quartz boat into the furnace

[0059] The flatness deviation of the furnace entry track is ±0.4mm, the pushing speed is 7cm / s, and the furnace entry time is 10 hours, 20 minutes and 0 seconds.

[0060] Boron diffusion process

[0061] The BCl3 gas flow rate was 100 sccm, the furnace pressure was 250 Pa, the boron diffusion temperature was 920°C, the boron diffusion time was 70 minutes, and the oxygen content was controlled at 2% during the boron diffusion process. The temperature fluctuation was ±4°C, the pressure fluctuation was ±12 Pa, and the gas flow rate fluctuation was ±6 sccm.

[0062] Cooling and subsequent processing

[0063] The cooling method is the same as that in Example 1. The etching adopts wet etching (hydrofluoric acid concentration 8%, etching time 50 seconds). The passivation, screen printing and sintering parameters are the same as those in Example 1.

[0064] The cell sheet resistance uniformity of this embodiment reached 1.3%, a significant improvement over the traditional placement method. The cell's photoelectric conversion efficiency increased by approximately 0.7%, and the fill factor was also improved, further demonstrating the effectiveness of the method of the present invention.

[0065] 2. Comparative Example

[0066] Comparative Example 1 (Traditional horizontal film placement method)

[0067] Quartz boat preparation

[0068] After briefly cleaning the quartz boat, it was baked at 800°C for 30 minutes and randomly placed in the furnace tube (the position was not precisely controlled).

[0069] Wafer loading

[0070] The silicon wafers are placed horizontally on the quartz boat without any tilt angle, and the silicon wafers are closely arranged (the spacing is less than 1mm).

[0071] Quartz boat into the furnace

[0072] The quartz boat was pushed into the furnace tube manually and quickly at a speed of about 15 cm / s. The time of entry into the furnace was not recorded.

[0073] Boron diffusion process

[0074] The BCl3 gas flow rate was 100 sccm, the furnace pressure was 200 Pa, the boron diffusion temperature was 900°C, and the boron diffusion time was 60 minutes. No special atmosphere control or other optimization was performed.

[0075] Cooling and subsequent processing

[0076] Natural cooling, etching, passivation, screen printing and sintering use conventional but unoptimized process parameters (poor etching effect, uneven electrode thickness, etc.).

[0077] Tests show that its square resistance uniformity is poor, with the intra-chip uniformity reaching 4.5%, the photoelectric conversion efficiency is relatively low, and the fill factor is not ideal. This is caused by the uneven distribution of airflow and thermal radiation when the chip is placed horizontally.

[0078] Comparative Example 2 (Traditional vertical film placement method)

[0079] Quartz boat preparation

[0080] The quartz boat preparation steps are the same as those in Comparative Example 1.

[0081] Wafer loading

[0082] The silicon wafers were placed vertically on a quartz boat, with a spacing of approximately 0.5 mm between the wafers.

[0083] Quartz boat into the furnace

[0084] The same furnace feeding method as Comparative Example 1.

[0085] Boron diffusion process

[0086] The boron diffusion process parameters are the same as those in Comparative Example 1.

[0087] Cooling and subsequent processing

[0088] The cooling and subsequent treatment methods are the same as those of Comparative Example 1.

[0089] The square resistance uniformity of the cell in this comparative example is also poor, with an intra-cell uniformity of 5.0%. The photoelectric conversion efficiency and fill factor are poor. The main reason is that the airflow transmission is blocked when the cell is placed vertically, which affects the boron diffusion effect and square resistance uniformity.

[0090] By comparing the examples and comparative examples, it can be clearly seen that the method of the present invention has significant advantages in improving the uniformity of the square resistance of solar cell wafers and enhancing the overall performance of the cell (photoelectric conversion efficiency, fill factor, etc.), providing a strong basis for improving the solar cell manufacturing process.

[0091] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above and that the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the present application is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

Claims

1. A method for improving the uniformity of square resistance of solar cells, characterized in that: The following steps are involved: Step 1. Quartz boat preparation: Select a quartz boat of appropriate specifications with a smooth surface, free of scratches and impurities. After cleaning, dry it by high-temperature baking at 800-1000°C for 30-60 minutes. Depending on the size of the furnace tube and the size of the silicon wafer, place the quartz boat near the center axis of the furnace tube, with a deviation of no more than ±5mm. Step 2. Wafer Loading: Place the cleaned and dried silicon wafers on a quartz boat in a PE-like forward loading method, with the long side of the wafer tilted at a 10°-30° angle to the long side of the quartz boat. Use a high-precision protractor to ensure that the tilt angle error of each wafer does not exceed ±0.5°. Maintain a spacing of 2mm-5mm between the wafers, and use a precision spacing measurement tool to ensure that the spacing error does not exceed ±0.1mm. During the loading process, use automated loading equipment or manual operation with soft tweezers. The loading time for each wafer is controlled within 5-10 seconds. Ensure that the wafers are placed stably, avoid collisions and scratches, and ensure that they are arranged neatly. The lateral deviation of adjacent wafers does not exceed ±0.5mm. Step 3. Place the quartz boat in the furnace: Slowly and steadily place the loaded quartz boat into the furnace tube at a speed of 5cm / s-10cm / s, ensuring that the distance between the front end of the quartz boat and the furnace tube entrance does not exceed ±2cm. During the placement process, closely observe whether the silicon wafers are displaced or shaken. If any abnormality is found, make timely adjustments. At the same time, accurately record the time the quartz boat enters the furnace, accurate to the second. Step 4. Boron diffusion process: Boron diffusion is performed using different process parameters based on the wafer tilt angle and spacing. Parameters such as temperature, pressure, and gas flow rate in the furnace tube are continuously monitored during the process, with data recorded every 5 minutes. After the Boron diffusion is completed, the furnace tube is cooled and the wafers are removed from the furnace tube for subsequent processing. Step 5. Subsequent processing: including etching to remove the phosphosilicate glass (PSG) layer, cleaning to remove residues after etching, passivation treatment, and finally preparing electrodes through screen printing technology. Sintering treatment is performed to form a good ohmic contact between the electrodes and the silicon wafer to complete the solar cell manufacturing.

2. The method for improving the uniformity of square resistance of a solar cell according to claim 1, characterized in that: In the quartz boat preparation step, the quartz boat is first rinsed with deionized water for 3-5 minutes, then immersed in a cleaning solution prepared by mixing hydrofluoric acid and nitric acid in a ratio of 1:5-1:10 for 10-15 minutes, and then rinsed again with deionized water for 5-10 minutes.

3. The method for improving the uniformity of square resistance of a solar cell according to claim 1, wherein: In the silicon wafer loading step, a layer of inert gas film with a thickness of 0.1 μm-0.5 μm is evenly applied on the surface of the quartz boat before loading the silicon wafer.

4. The method for improving the uniformity of square resistance of a solar cell according to claim 1, wherein: During the quartz boat entering the furnace step, the flatness deviation of the furnace track does not exceed ±0.5mm. An electric pushing device is used to push the quartz boat, and a high-definition camera is set at the entrance of the furnace tube to monitor the silicon wafer entering the furnace in real time.

5. The method for improving the uniformity of square resistance of a solar cell according to claim 1, wherein: When the silicon wafer tilt angle is 10° and the silicon wafer spacing is 2 mm, the boron diffusion process parameters are BCl3 gas flow rate 80 sccm, furnace tube pressure 200 Pa, boron diffusion temperature 900°C, and boron diffusion time 60 minutes. During the boron diffusion process, the oxygen content in the furnace tube is controlled to be maintained at 1%-3% (volume fraction).

6. The method for improving the uniformity of square resistance of a solar cell according to claim 1, characterized in that: When the silicon wafer tilt angle is 20° and the silicon wafer spacing is 3mm, the boron expansion process parameters are BCl3 gas flow rate 120sccm, furnace tube pressure 300Pa, boron expansion temperature 950℃, boron expansion time 90 minutes, and the furnace tube is pre-vacuumed before boron expansion, and the vacuum degree reaches 10-2Pa-10-3Pa.

7. The method for improving the uniformity of square resistance of a solar cell according to claim 1, characterized in that: When the silicon wafer tilt angle is 30° and the silicon wafer spacing is 4mm, the boron expansion process parameters are BCl3 gas flow rate 150sccm, furnace tube pressure 400Pa, boron expansion temperature 980℃, and boron expansion time 100 minutes. During the boron expansion process, nitrogen with a flow rate of 10sccm-20sccm is introduced into the furnace tube as a protective gas.

8. The method for improving the uniformity of square resistance of a solar cell according to claim 1, wherein: When the silicon wafer tilt angle is 15° and the silicon wafer spacing is 5mm, the boron diffusion process parameters are BCl3 gas flow rate 180sccm, furnace tube pressure 500Pa, boron diffusion temperature 1000℃, and boron diffusion time 120 minutes, and the pressure in the furnace tube is gradually reduced to 100Pa-200Pa in the later stage of boron diffusion.

9. The method for improving the uniformity of square resistance of a solar cell according to claim 1, wherein: In the cooling and subsequent processing steps, a graded cooling method is adopted after the boron expansion process is completed. The furnace tube temperature is first reduced to 500℃-600℃ at a cooling rate of 5℃ / min-10℃ / min, and then naturally cooled to room temperature. During the cooling process, an inert gas with a flow rate of 50sccm-100sccm is introduced into the furnace tube.

10. The method for improving the uniformity of square resistance of a solar cell according to claim 1, characterized in that: In the subsequent process steps, the etching process adopts wet etching using a hydrofluoric acid solution with a concentration of 5%-10%, and the etching time is 30 seconds-60 seconds; the passivation treatment adopts plasma enhanced chemical vapor deposition (PECVD) technology, and the thickness of the deposited silicon nitride (SiNx) film is 50nm-100nm. During the deposition process, the plasma power is controlled to 100W-200W, and the reaction gas flow ratio (silane: ammonia) is 1:5-1:10; the thickness of the screen-printed electrode is 80μm-120μm, the sintering temperature is 800℃-900℃, and the sintering time is 30 seconds-60 seconds.

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